From 944537dcc1ff73d78ba6415dcddb8ba95659113e Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Tue, 3 Feb 2026 12:23:09 -0800
Subject: [PATCH 01/59] deprecate Arduino IDE, Visual Studio builds. VSCode/PIO
 only going forwards

---
 arduino/1.6.15/boards.local.txt               |   62 -
 arduino/1.6.15/programmers.txt                |   78 -
 arduino/1.6.15/readme.txt                     |    2 -
 arduino/boards.local.txt                      |   39 -
 arduino/boards.txt                            |   24 -
 arduino/boards.txt.arduino0022                |  383 ----
 arduino/boards.txt.arduino1.6.9               |  866 -------
 arduino/boards.txt.arduino1.6.x               |  834 -------
 arduino/boards.txt.arduino106                 |  580 -----
 firmware/open_evse/open_evse.ino              |    1 -
 ...open_evse.ino.with_bootloader.standard.hex | 2004 -----------------
 firmware/open_evse/open_evse.sln              |   44 -
 firmware/open_evse/open_evse.vcxproj          |  180 --
 firmware/open_evse/open_evse.vcxproj.filters  |  156 --
 14 files changed, 5253 deletions(-)
 delete mode 100644 arduino/1.6.15/boards.local.txt
 delete mode 100644 arduino/1.6.15/programmers.txt
 delete mode 100644 arduino/1.6.15/readme.txt
 delete mode 100644 arduino/boards.local.txt
 delete mode 100644 arduino/boards.txt
 delete mode 100644 arduino/boards.txt.arduino0022
 delete mode 100644 arduino/boards.txt.arduino1.6.9
 delete mode 100644 arduino/boards.txt.arduino1.6.x
 delete mode 100644 arduino/boards.txt.arduino106
 delete mode 100644 firmware/open_evse/open_evse.ino
 delete mode 100644 firmware/open_evse/open_evse.ino.with_bootloader.standard.hex
 delete mode 100644 firmware/open_evse/open_evse.sln
 delete mode 100644 firmware/open_evse/open_evse.vcxproj
 delete mode 100644 firmware/open_evse/open_evse.vcxproj.filters

diff --git a/arduino/1.6.15/boards.local.txt b/arduino/1.6.15/boards.local.txt
deleted file mode 100644
index 586837fa..00000000
--- a/arduino/1.6.15/boards.local.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-#####
-# OpenEVSE with hardware programmer
-#####
-openevse.name=[Programmer]OpenEVSE
-openevse.upload.tool=avrdude
-openevse.upload.maximum_size=32768
-openevse.upload.maximum_data_size=2048
-openevse.build.mcu=atmega328p
-openevse.build.f_cpu=16000000L
-openevse.build.board=AVR_DUEMILANOVE
-openevse.build.core=arduino
-openevse.build.variant=standard
-openevse.menu.cpu.atmega328=ATmega328
-
-#####
-# OpenEVSE with optiboot
-#####
-openevsebl.name=[optiboot]OpenEVSE
-
-openevsebl.upload.tool=avrdude
-openevsebl.upload.protocol=arduino
-openevsebl.upload.maximum_size=32256
-openevsebl.upload.maximum_data_size=2048
-openevsebl.upload.speed=115200
-
-openevsebl.bootloader.tool=avrdude
-openevsebl.bootloader.low_fuses=0xFF
-openevsebl.bootloader.high_fuses=0xDE
-openevsebl.bootloader.extended_fuses=0x04
-openevsebl.bootloader.unlock_bits=0x3F
-openevsebl.bootloader.lock_bits=0x0F
-openevsebl.bootloader.file=optiboot/optiboot_atmega328.hex
-
-openevsebl.build.mcu=atmega328p
-openevsebl.build.f_cpu=16000000L
-openevsebl.build.board=AVR_DUEMILANOVE
-openevsebl.build.core=arduino
-openevsebl.build.variant=standard
-
-atm328.name=[Programmer]ATmega328
-atm328.upload.tool=avrdude
-atm328.upload.maximum_size=32768
-atm328.upload.maximum_data_size=2048
-atm328.build.mcu=atmega328p
-atm328.build.f_cpu=16000000L
-atm328.build.board=AVR_DUEMILANOVE
-atm328.build.core=arduino
-atm328.build.variant=standard
-atm328.menu.cpu.atmega328=ATmega328
-
-atm168.name=[Programmer]ATmega168
-atm168.upload.tool=avrdude
-atm168.upload.maximum_size=16384
-atm168.upload.maximum_data_size=1024
-atm168.build.mcu=atmega168
-atm168.build.f_cpu=16000000L
-atm168.build.board=AVR_DUEMILANOVE
-atm168.build.core=arduino
-atm168.build.variant=standard
-atm168.menu.cpu.atmega168=ATmega168
-
-
diff --git a/arduino/1.6.15/programmers.txt b/arduino/1.6.15/programmers.txt
deleted file mode 100644
index 4d716524..00000000
--- a/arduino/1.6.15/programmers.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-avrisp.name=AVR ISP
-avrisp.communication=serial
-avrisp.protocol=stk500v1
-avrisp.program.protocol=stk500v1
-avrisp.program.tool=avrdude
-avrisp.program.extra_params=-P{serial.port}
-
-avrispmkii.name=AVRISP mkII
-avrispmkii.communication=usb
-avrispmkii.protocol=stk500v2
-avrispmkii.program.protocol=stk500v2
-avrispmkii.program.tool=avrdude
-avrispmkii.program.extra_params=-Pusb
-
-usbtinyisp.name=USBtinyISP
-usbtinyisp.protocol=usbtiny
-usbtinyisp.program.tool=avrdude
-usbtinyisp.program.extra_params=-B1
-
-arduinoisp.name=ArduinoISP
-arduinoisp.protocol=arduinoisp
-arduinoisp.program.tool=avrdude
-arduinoisp.program.extra_params=
-
-usbasp.name=USBasp
-usbasp.communication=usb
-usbasp.protocol=usbasp
-usbasp.program.protocol=usbasp
-usbasp.program.tool=avrdude
-usbasp.program.extra_params=-Pusb -B0.5
-
-parallel.name=Parallel Programmer
-parallel.protocol=dapa
-parallel.force=true
-# parallel.delay=200
-parallel.program.tool=avrdude
-parallel.program.extra_params=-F
-
-arduinoasisp.name=Arduino as ISP
-arduinoasisp.communication=serial
-arduinoasisp.protocol=stk500v1
-arduinoasisp.speed=19200
-arduinoasisp.program.protocol=stk500v1
-arduinoasisp.program.speed=19200
-arduinoasisp.program.tool=avrdude
-arduinoasisp.program.extra_params=-P{serial.port} -b{program.speed}
-
-usbGemma.name=Arduino Gemma
-usbGemma.protocol=arduinogemma
-usbGemma.program.tool=avrdude
-usbGemma.program.extra_params=
-usbGemma.config.path={runtime.platform.path}/bootloaders/gemma/avrdude.conf
-
-# STK500 firmware version v1 and v2 use different serial protocols.
-# Using the 'stk500' protocol tells avrdude to try and autodetect the
-# firmware version. If this leads to problems, we might need to add
-# stk500v1 and stk500v2 entries to allow explicitely selecting the
-# firmware version.
-stk500.name=Atmel STK500 development board
-stk500.communication=serial
-stk500.protocol=stk500
-stk500.program.protocol=stk500
-stk500.program.tool=avrdude
-stk500.program.extra_params=-P{serial.port}
-
-## Notes about Dangerous Prototypes Bus Pirate as ISP
-## Bus Pirate V3 need Firmware v5.10 or later
-## Bus Pirate V4 need Firmware v6.3-r2151 or later
-## Could happen that BP does not have enough current to power an Arduino board 
-## through the ICSP connector. In this case disconnect the +Vcc from ICSP connector
-## and power Arduino board in the normal way.
-buspirate.name=BusPirate as ISP
-buspirate.communication=serial
-buspirate.protocol=buspirate
-buspirate.program.protocol=buspirate
-buspirate.program.tool=avrdude
-buspirate.program.extra_params=-P{serial.port}
-
diff --git a/arduino/1.6.15/readme.txt b/arduino/1.6.15/readme.txt
deleted file mode 100644
index cb0a05d1..00000000
--- a/arduino/1.6.15/readme.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-drop boards.local.txt and programmers.txt into <user>/AppData/Local/Arduino15/packages/hardware/avr/1.6.15.
--> overwrites existing programmers.txt
diff --git a/arduino/boards.local.txt b/arduino/boards.local.txt
deleted file mode 100644
index 598e4757..00000000
--- a/arduino/boards.local.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-#####
-# OpenEVSE with hardware programmer
-#####
-openevse.name=[Programmer]OpenEVSE
-openevse.upload.tool=avrdude
-openevse.upload.maximum_size=32768
-openevse.upload.maximum_data_size=2048
-openevse.build.mcu=atmega328p
-openevse.build.f_cpu=16000000L
-openevse.build.board=AVR_DUEMILANOVE
-openevse.build.core=arduino
-openevse.build.variant=standard
-openevse.menu.cpu.atmega328=ATmega328
-
-#####
-# OpenEVSE with optiboot
-#####
-openevsebl.name=[optiboot]OpenEVSE
-
-openevsebl.upload.tool=avrdude
-openevsebl.upload.protocol=arduino
-openevsebl.upload.maximum_size=32256
-openevsebl.upload.maximum_data_size=2048
-openevsebl.upload.speed=115200
-
-openevsebl.bootloader.tool=avrdude
-openevsebl.bootloader.low_fuses=0xFF
-openevsebl.bootloader.high_fuses=0xDE
-openevsebl.bootloader.extended_fuses=0x04
-openevsebl.bootloader.unlock_bits=0x3F
-openevsebl.bootloader.lock_bits=0x0F
-openevsebl.bootloader.file=optiboot/optiboot_atmega328.hex
-
-openevsebl.build.mcu=atmega328p
-openevsebl.build.f_cpu=16000000L
-openevsebl.build.board=AVR_DUEMILANOVE
-openevsebl.build.core=arduino
-openevsebl.build.variant=standard
-
diff --git a/arduino/boards.txt b/arduino/boards.txt
deleted file mode 100644
index 79c2b70c..00000000
--- a/arduino/boards.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-
-##############################################################
-## OpenEVSE with Programmer selected from Tools->Programmer
-## ---------------------------------------------
-openevse.name=[Programmer]OpenEVSE
-openevse.upload.tool=arduino:avrdude
-openevse.upload.protocol=arduino
-openevse.upload.maximum_size=32768
-openevse.upload.maximum_data_size=2048
-
-openevse.bootloader.tool=avrdude
-openevse.bootloader.low_fuses=0xFF
-openevse.bootloader.high_fuses=0xDF
-openevse.bootloader.extended_fuses=0x05
-openevse.bootloader.unlock_bits=0x3F
-openevse.bootloader.lock_bits=0x0F
-openevse.bootloader.file=optiboot/optiboot_atmega328.hex
-
-openevse.build.mcu=atmega328p
-openevse.build.f_cpu=16000000L
-openevse.build.board=AVR_DUEMILANOVE
-openevse.build.core=arduino:arduino
-openevse.build.variant=arduino:standard
-openevse.menu.cpu.atmega328=ATmega328
diff --git a/arduino/boards.txt.arduino0022 b/arduino/boards.txt.arduino0022
deleted file mode 100644
index 842a81ef..00000000
--- a/arduino/boards.txt.arduino0022
+++ /dev/null
@@ -1,383 +0,0 @@
-############################################################
-evse.name=[USBasp]OpenEVSE
-evse.upload.using=usbasp
-evse.upload.maximum_size=32768
-evse.bootloader.low_fuses=0xff
-evse.bootloader.high_fuses=0xdf
-evse.bootloader.extended_fuses=0x04
-evse.bootloader.unlock_bits=0x3F
-evse.bootloader.lock_bits=0x0F
-evse.build.mcu=atmega328p
-evse.build.f_cpu=16000000L
-evse.build.core=arduino
-##############################################################
-
-usbtiny168.name=[usbtinyisp]ATmega168
-
-usbtiny168.upload.using=usbtinyisp
-usbtiny168.upload.maximum_size=16384
-
-usbtiny168.build.mcu=atmega168
-usbtiny168.build.f_cpu=16000000L
-usbtiny168.build.core=arduino
-
-##############################################################
-
-usbtiny328.name=[usbtinyisp]ATmega328
-
-usbtiny328.upload.using=usbtinyisp
-usbtiny328.upload.maximum_size=32768
-
-usbtiny328.build.mcu=atmega328p
-usbtiny328.build.f_cpu=16000000L
-usbtiny328.build.core=arduino
-
-##############################################################
-
-USBasp328.name=[USBasp]ATmega328
-
-USBasp328.upload.using=usbasp
-USBasp328.upload.maximum_size=32768
-
-USBasp328.build.mcu=atmega328p
-USBasp328.build.f_cpu=16000000L
-USBasp328.build.core=arduino
-
-##############################################################
-
-uno.name=Arduino Uno
-uno.upload.protocol=stk500
-uno.upload.maximum_size=32256
-uno.upload.speed=115200
-uno.bootloader.low_fuses=0xff
-uno.bootloader.high_fuses=0xde
-uno.bootloader.extended_fuses=0x05
-uno.bootloader.path=optiboot
-uno.bootloader.file=optiboot_atmega328.hex
-uno.bootloader.unlock_bits=0x3F
-uno.bootloader.lock_bits=0x0F
-uno.build.mcu=atmega328p
-uno.build.f_cpu=16000000L
-uno.build.core=arduino
-
-##############################################################
-
-atmega328.name=Arduino Duemilanove or Nano w/ ATmega328
-
-atmega328.upload.protocol=stk500
-atmega328.upload.maximum_size=30720
-atmega328.upload.speed=57600
-
-atmega328.bootloader.low_fuses=0xFF
-atmega328.bootloader.high_fuses=0xDA
-atmega328.bootloader.extended_fuses=0x05
-atmega328.bootloader.path=atmega
-atmega328.bootloader.file=ATmegaBOOT_168_atmega328.hex
-atmega328.bootloader.unlock_bits=0x3F
-atmega328.bootloader.lock_bits=0x0F
-
-atmega328.build.mcu=atmega328p
-atmega328.build.f_cpu=16000000L
-atmega328.build.core=arduino
-
-##############################################################
-
-diecimila.name=Arduino Diecimila, Duemilanove, or Nano w/ ATmega168
-
-diecimila.upload.protocol=stk500
-diecimila.upload.maximum_size=14336
-diecimila.upload.speed=19200
-
-diecimila.bootloader.low_fuses=0xff
-diecimila.bootloader.high_fuses=0xdd
-diecimila.bootloader.extended_fuses=0x00
-diecimila.bootloader.path=atmega
-diecimila.bootloader.file=ATmegaBOOT_168_diecimila.hex
-diecimila.bootloader.unlock_bits=0x3F
-diecimila.bootloader.lock_bits=0x0F
-
-diecimila.build.mcu=atmega168
-diecimila.build.f_cpu=16000000L
-diecimila.build.core=arduino
-
-##############################################################
-
-mega2560.name=Arduino Mega 2560
-
-mega2560.upload.protocol=stk500v2
-mega2560.upload.maximum_size=258048
-mega2560.upload.speed=115200
-
-mega2560.bootloader.low_fuses=0xFF
-mega2560.bootloader.high_fuses=0xD8
-mega2560.bootloader.extended_fuses=0xFD
-mega2560.bootloader.path=stk500v2
-mega2560.bootloader.file=stk500boot_v2_mega2560.hex
-mega2560.bootloader.unlock_bits=0x3F
-mega2560.bootloader.lock_bits=0x0F
-
-mega2560.build.mcu=atmega2560
-mega2560.build.f_cpu=16000000L
-mega2560.build.core=arduino
-
-##############################################################
-
-mega.name=Arduino Mega (ATmega1280)
-
-mega.upload.protocol=stk500
-mega.upload.maximum_size=126976
-mega.upload.speed=57600
-
-mega.bootloader.low_fuses=0xFF
-mega.bootloader.high_fuses=0xDA
-mega.bootloader.extended_fuses=0xF5
-mega.bootloader.path=atmega
-mega.bootloader.file=ATmegaBOOT_168_atmega1280.hex
-mega.bootloader.unlock_bits=0x3F
-mega.bootloader.lock_bits=0x0F
-
-mega.build.mcu=atmega1280
-mega.build.f_cpu=16000000L
-mega.build.core=arduino
-
-##############################################################
-
-mini.name=Arduino Mini
-
-mini.upload.protocol=stk500
-mini.upload.maximum_size=14336
-mini.upload.speed=19200
-
-mini.bootloader.low_fuses=0xff
-mini.bootloader.high_fuses=0xdd
-mini.bootloader.extended_fuses=0x00
-mini.bootloader.path=atmega
-mini.bootloader.file=ATmegaBOOT_168_ng.hex
-mini.bootloader.unlock_bits=0x3F
-mini.bootloader.lock_bits=0x0F
-
-mini.build.mcu=atmega168
-mini.build.f_cpu=16000000L
-mini.build.core=arduino
-
-##############################################################
-
-fio.name=Arduino Fio
-
-fio.upload.protocol=stk500
-fio.upload.maximum_size=30720
-fio.upload.speed=57600
-
-fio.bootloader.low_fuses=0xFF
-fio.bootloader.high_fuses=0xDA
-fio.bootloader.extended_fuses=0x05
-fio.bootloader.path=arduino:atmega
-fio.bootloader.file=ATmegaBOOT_168_atmega328_pro_8MHz.hex
-fio.bootloader.unlock_bits=0x3F
-fio.bootloader.lock_bits=0x0F
-
-fio.build.mcu=atmega328p
-fio.build.f_cpu=8000000L
-fio.build.core=arduino:arduino
-
-##############################################################
-
-bt328.name=Arduino BT w/ ATmega328
-
-bt328.upload.protocol=stk500
-bt328.upload.maximum_size=28672
-bt328.upload.speed=19200
-bt328.upload.disable_flushing=true
-
-bt328.bootloader.low_fuses=0xff
-bt328.bootloader.high_fuses=0xd8
-bt328.bootloader.extended_fuses=0x05
-bt328.bootloader.path=bt
-bt328.bootloader.file=ATmegaBOOT_168_atmega328_bt.hex
-bt328.bootloader.unlock_bits=0x3F
-bt328.bootloader.lock_bits=0x0F
-
-bt328.build.mcu=atmega328p
-bt328.build.f_cpu=16000000L
-bt328.build.core=arduino
-
-##############################################################
-
-bt.name=Arduino BT w/ ATmega168
-
-bt.upload.protocol=stk500
-bt.upload.maximum_size=14336
-bt.upload.speed=19200
-bt.upload.disable_flushing=true
-
-bt.bootloader.low_fuses=0xff
-bt.bootloader.high_fuses=0xdd
-bt.bootloader.extended_fuses=0x00
-bt.bootloader.path=bt
-bt.bootloader.file=ATmegaBOOT_168.hex
-bt.bootloader.unlock_bits=0x3F
-bt.bootloader.lock_bits=0x0F
-
-bt.build.mcu=atmega168
-bt.build.f_cpu=16000000L
-bt.build.core=arduino
-
-##############################################################
-
-lilypad328.name=LilyPad Arduino w/ ATmega328
-
-lilypad328.upload.protocol=stk500
-lilypad328.upload.maximum_size=30720
-lilypad328.upload.speed=57600
-
-lilypad328.bootloader.low_fuses=0xFF
-lilypad328.bootloader.high_fuses=0xDA
-lilypad328.bootloader.extended_fuses=0x05
-lilypad328.bootloader.path=atmega
-lilypad328.bootloader.file=ATmegaBOOT_168_atmega328_pro_8MHz.hex
-lilypad328.bootloader.unlock_bits=0x3F
-lilypad328.bootloader.lock_bits=0x0F
-
-lilypad328.build.mcu=atmega328p
-lilypad328.build.f_cpu=8000000L
-lilypad328.build.core=arduino
-
-##############################################################
-
-lilypad.name=LilyPad Arduino w/ ATmega168
-
-lilypad.upload.protocol=stk500
-lilypad.upload.maximum_size=14336
-lilypad.upload.speed=19200
-
-lilypad.bootloader.low_fuses=0xe2
-lilypad.bootloader.high_fuses=0xdd
-lilypad.bootloader.extended_fuses=0x00
-lilypad.bootloader.path=lilypad
-lilypad.bootloader.file=LilyPadBOOT_168.hex
-lilypad.bootloader.unlock_bits=0x3F
-lilypad.bootloader.lock_bits=0x0F
-
-lilypad.build.mcu=atmega168
-lilypad.build.f_cpu=8000000L
-lilypad.build.core=arduino
-
-##############################################################
-
-pro5v328.name=Arduino Pro or Pro Mini (5V, 16 MHz) w/ ATmega328
-
-pro5v328.upload.protocol=stk500
-pro5v328.upload.maximum_size=30720
-pro5v328.upload.speed=57600
-
-pro5v328.bootloader.low_fuses=0xFF
-pro5v328.bootloader.high_fuses=0xDA
-pro5v328.bootloader.extended_fuses=0x05
-pro5v328.bootloader.path=atmega
-pro5v328.bootloader.file=ATmegaBOOT_168_atmega328.hex
-pro5v328.bootloader.unlock_bits=0x3F
-pro5v328.bootloader.lock_bits=0x0F
-
-pro5v328.build.mcu=atmega328p
-pro5v328.build.f_cpu=16000000L
-pro5v328.build.core=arduino
-
-##############################################################
-
-pro5v.name=Arduino Pro or Pro Mini (5V, 16 MHz) w/ ATmega168
-
-pro5v.upload.protocol=stk500
-pro5v.upload.maximum_size=14336
-pro5v.upload.speed=19200
-
-pro5v.bootloader.low_fuses=0xff
-pro5v.bootloader.high_fuses=0xdd
-pro5v.bootloader.extended_fuses=0x00
-pro5v.bootloader.path=atmega
-pro5v.bootloader.file=ATmegaBOOT_168_diecimila.hex
-pro5v.bootloader.unlock_bits=0x3F
-pro5v.bootloader.lock_bits=0x0F
-
-pro5v.build.mcu=atmega168
-pro5v.build.f_cpu=16000000L
-pro5v.build.core=arduino
-
-##############################################################
-
-pro328.name=Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega328
-
-pro328.upload.protocol=stk500
-pro328.upload.maximum_size=30720
-pro328.upload.speed=57600
-
-pro328.bootloader.low_fuses=0xFF
-pro328.bootloader.high_fuses=0xDA
-pro328.bootloader.extended_fuses=0x05
-pro328.bootloader.path=atmega
-pro328.bootloader.file=ATmegaBOOT_168_atmega328_pro_8MHz.hex
-pro328.bootloader.unlock_bits=0x3F
-pro328.bootloader.lock_bits=0x0F
-
-pro328.build.mcu=atmega328p
-pro328.build.f_cpu=8000000L
-pro328.build.core=arduino
-
-##############################################################
-
-pro.name=Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega168
-
-pro.upload.protocol=stk500
-pro.upload.maximum_size=14336
-pro.upload.speed=19200
-
-pro.bootloader.low_fuses=0xc6
-pro.bootloader.high_fuses=0xdd
-pro.bootloader.extended_fuses=0x00
-pro.bootloader.path=atmega
-pro.bootloader.file=ATmegaBOOT_168_pro_8MHz.hex
-pro.bootloader.unlock_bits=0x3F
-pro.bootloader.lock_bits=0x0F
-
-pro.build.mcu=atmega168
-pro.build.f_cpu=8000000L
-pro.build.core=arduino
-
-##############################################################
-
-atmega168.name=Arduino NG or older w/ ATmega168
-
-atmega168.upload.protocol=stk500
-atmega168.upload.maximum_size=14336
-atmega168.upload.speed=19200
-
-atmega168.bootloader.low_fuses=0xff
-atmega168.bootloader.high_fuses=0xdd
-atmega168.bootloader.extended_fuses=0x00
-atmega168.bootloader.path=atmega
-atmega168.bootloader.file=ATmegaBOOT_168_ng.hex
-atmega168.bootloader.unlock_bits=0x3F
-atmega168.bootloader.lock_bits=0x0F
-
-atmega168.build.mcu=atmega168
-atmega168.build.f_cpu=16000000L
-atmega168.build.core=arduino
-
-##############################################################
-
-atmega8.name=Arduino NG or older w/ ATmega8
-
-atmega8.upload.protocol=stk500
-atmega8.upload.maximum_size=7168
-atmega8.upload.speed=19200
-
-atmega8.bootloader.low_fuses=0xdf
-atmega8.bootloader.high_fuses=0xca
-atmega8.bootloader.path=atmega8
-atmega8.bootloader.file=ATmegaBOOT.hex
-atmega8.bootloader.unlock_bits=0x3F
-atmega8.bootloader.lock_bits=0x0F
-
-atmega8.build.mcu=atmega8
-atmega8.build.f_cpu=16000000L
-atmega8.build.core=arduino
-
diff --git a/arduino/boards.txt.arduino1.6.9 b/arduino/boards.txt.arduino1.6.9
deleted file mode 100644
index 4cd982d3..00000000
--- a/arduino/boards.txt.arduino1.6.9
+++ /dev/null
@@ -1,866 +0,0 @@
-# See: http://code.google.com/p/arduino/wiki/Platforms
-
-menu.cpu=Processor
-
-##############################################################
-## OpenEVSE with Programmer selected from Tools->Programmer
-## ---------------------------------------------
-openevse.name=[Programmer]OpenEVSE
-openevse.upload.tool=avrdude
-openevse.upload.maximum_size=32768
-openevse.upload.maximum_data_size=2048
-
-openevse.bootloader.tool=avrdude
-openevse.bootloader.low_fuses=0xFF
-openevse.bootloader.high_fuses=0xDF
-openevse.bootloader.extended_fuses=0x04
-openevse.bootloader.unlock_bits=0x3F
-openevse.bootloader.lock_bits=0x0F
-openevse.bootloader.file=optiboot/optiboot_atmega328.hex
-
-openevse.build.mcu=atmega328p
-openevse.build.f_cpu=16000000L
-openevse.build.board=AVR_DUEMILANOVE
-openevse.build.core=arduino
-openevse.build.variant=standard
-openevse.menu.cpu.atmega328=ATmega328
-
-##############################################################
-
-yun.name=Arduino Yún
-yun.upload.via_ssh=true
-
-yun.vid.0=0x2341
-yun.pid.0=0x0041
-yun.vid.1=0x2341
-yun.pid.1=0x8041
-yun.vid.2=0x2A03
-yun.pid.2=0x0041
-yun.vid.3=0x2A03
-yun.pid.3=0x8041
-
-yun.upload.tool=avrdude
-yun.upload.protocol=avr109
-yun.upload.maximum_size=28672
-yun.upload.maximum_data_size=2560
-yun.upload.speed=57600
-yun.upload.disable_flushing=true
-yun.upload.use_1200bps_touch=true
-yun.upload.wait_for_upload_port=true
-
-yun.bootloader.tool=avrdude
-yun.bootloader.low_fuses=0xff
-yun.bootloader.high_fuses=0xd8
-yun.bootloader.extended_fuses=0xfb
-yun.bootloader.file=caterina/Caterina-Yun.hex
-yun.bootloader.noblink=caterina/Caterina-Yun-noblink.hex
-yun.bootloader.unlock_bits=0x3F
-yun.bootloader.lock_bits=0x2F
-
-yun.build.mcu=atmega32u4
-yun.build.f_cpu=16000000L
-yun.build.vid=0x2341
-yun.build.pid=0x8041
-yun.build.usb_product="Arduino Yun"
-yun.build.board=AVR_YUN
-yun.build.core=arduino
-yun.build.variant=yun
-yun.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-uno.name=Arduino/Genuino Uno
-
-uno.vid.0=0x2341
-uno.pid.0=0x0043
-uno.vid.1=0x2341
-uno.pid.1=0x0001
-uno.vid.2=0x2A03
-uno.pid.2=0x0043
-uno.vid.3=0x2341
-uno.pid.3=0x0243
-
-uno.upload.tool=avrdude
-uno.upload.protocol=arduino
-uno.upload.maximum_size=32256
-uno.upload.maximum_data_size=2048
-uno.upload.speed=115200
-
-uno.bootloader.tool=avrdude
-uno.bootloader.low_fuses=0xFF
-uno.bootloader.high_fuses=0xDE
-uno.bootloader.extended_fuses=0x05
-uno.bootloader.unlock_bits=0x3F
-uno.bootloader.lock_bits=0x0F
-uno.bootloader.file=optiboot/optiboot_atmega328.hex
-
-uno.build.mcu=atmega328p
-uno.build.f_cpu=16000000L
-uno.build.board=AVR_UNO
-uno.build.core=arduino
-uno.build.variant=standard
-
-##############################################################
-
-diecimila.name=Arduino Duemilanove or Diecimila
-
-diecimila.upload.tool=avrdude
-diecimila.upload.protocol=arduino
-
-diecimila.bootloader.tool=avrdude
-diecimila.bootloader.low_fuses=0xFF
-diecimila.bootloader.unlock_bits=0x3F
-diecimila.bootloader.lock_bits=0x0F
-
-diecimila.build.f_cpu=16000000L
-diecimila.build.board=AVR_DUEMILANOVE
-diecimila.build.core=arduino
-diecimila.build.variant=standard
-
-## Arduino Duemilanove or Diecimila w/ ATmega328
-## ---------------------------------------------
-diecimila.menu.cpu.atmega328=ATmega328
-
-diecimila.menu.cpu.atmega328.upload.maximum_size=30720
-diecimila.menu.cpu.atmega328.upload.maximum_data_size=2048
-diecimila.menu.cpu.atmega328.upload.speed=57600
-
-diecimila.menu.cpu.atmega328.bootloader.high_fuses=0xDA
-diecimila.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-diecimila.menu.cpu.atmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328.hex
-
-diecimila.menu.cpu.atmega328.build.mcu=atmega328p
-
-## Arduino Duemilanove or Diecimila w/ ATmega168
-## ---------------------------------------------
-diecimila.menu.cpu.atmega168=ATmega168
-
-diecimila.menu.cpu.atmega168.upload.maximum_size=14336
-diecimila.menu.cpu.atmega168.upload.maximum_data_size=1024
-diecimila.menu.cpu.atmega168.upload.speed=19200
-
-diecimila.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-diecimila.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-diecimila.menu.cpu.atmega168.bootloader.file=atmega/ATmegaBOOT_168_diecimila.hex
-
-diecimila.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-nano.name=Arduino Nano
-
-nano.upload.tool=avrdude
-nano.upload.protocol=arduino
-
-nano.bootloader.tool=avrdude
-nano.bootloader.unlock_bits=0x3F
-nano.bootloader.lock_bits=0x0F
-
-nano.build.f_cpu=16000000L
-nano.build.board=AVR_NANO
-nano.build.core=arduino
-nano.build.variant=eightanaloginputs
-
-## Arduino Nano w/ ATmega328
-## -------------------------
-nano.menu.cpu.atmega328=ATmega328
-
-nano.menu.cpu.atmega328.upload.maximum_size=30720
-nano.menu.cpu.atmega328.upload.maximum_data_size=2048
-nano.menu.cpu.atmega328.upload.speed=57600
-
-nano.menu.cpu.atmega328.bootloader.low_fuses=0xFF
-nano.menu.cpu.atmega328.bootloader.high_fuses=0xDA
-nano.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-nano.menu.cpu.atmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328.hex
-
-nano.menu.cpu.atmega328.build.mcu=atmega328p
-
-## Arduino Nano w/ ATmega168
-## -------------------------
-nano.menu.cpu.atmega168=ATmega168
-
-nano.menu.cpu.atmega168.upload.maximum_size=14336
-nano.menu.cpu.atmega168.upload.maximum_data_size=1024
-nano.menu.cpu.atmega168.upload.speed=19200
-
-nano.menu.cpu.atmega168.bootloader.low_fuses=0xff
-nano.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-nano.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-nano.menu.cpu.atmega168.bootloader.file=atmega/ATmegaBOOT_168_diecimila.hex
-
-nano.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-mega.name=Arduino/Genuino Mega or Mega 2560
-
-mega.vid.0=0x2341
-mega.pid.0=0x0010
-mega.vid.1=0x2341
-mega.pid.1=0x0042
-mega.vid.2=0x2A03
-mega.pid.2=0x0010
-mega.vid.3=0x2A03
-mega.pid.3=0x0042
-mega.vid.4=0x2341
-mega.pid.4=0x0210
-mega.vid.5=0x2341
-mega.pid.5=0x0242
-
-mega.upload.tool=avrdude
-mega.upload.maximum_data_size=8192
-
-mega.bootloader.tool=avrdude
-mega.bootloader.low_fuses=0xFF
-mega.bootloader.unlock_bits=0x3F
-mega.bootloader.lock_bits=0x0F
-
-mega.build.f_cpu=16000000L
-mega.build.core=arduino
-mega.build.variant=mega
-# default board may be overridden by the cpu menu
-mega.build.board=AVR_MEGA2560
-
-## Arduino/Genuino Mega w/ ATmega2560
-## -------------------------
-mega.menu.cpu.atmega2560=ATmega2560 (Mega 2560)
-
-mega.menu.cpu.atmega2560.upload.protocol=wiring
-mega.menu.cpu.atmega2560.upload.maximum_size=253952
-mega.menu.cpu.atmega2560.upload.speed=115200
-
-mega.menu.cpu.atmega2560.bootloader.high_fuses=0xD8
-mega.menu.cpu.atmega2560.bootloader.extended_fuses=0xFD
-mega.menu.cpu.atmega2560.bootloader.file=stk500v2/stk500boot_v2_mega2560.hex
-
-mega.menu.cpu.atmega2560.build.mcu=atmega2560
-mega.menu.cpu.atmega2560.build.board=AVR_MEGA2560
-
-## Arduino Mega w/ ATmega1280
-## -------------------------
-mega.menu.cpu.atmega1280=ATmega1280
-
-mega.menu.cpu.atmega1280.upload.protocol=arduino
-mega.menu.cpu.atmega1280.upload.maximum_size=126976
-mega.menu.cpu.atmega1280.upload.speed=57600
-
-mega.menu.cpu.atmega1280.bootloader.high_fuses=0xDA
-mega.menu.cpu.atmega1280.bootloader.extended_fuses=0xF5
-mega.menu.cpu.atmega1280.bootloader.file=atmega/ATmegaBOOT_168_atmega1280.hex
-
-mega.menu.cpu.atmega1280.build.mcu=atmega1280
-mega.menu.cpu.atmega1280.build.board=AVR_MEGA
-
-##############################################################
-
-megaADK.name=Arduino Mega ADK
-
-megaADK.vid.0=0x2341
-megaADK.pid.0=0x003f
-megaADK.vid.1=0x2341
-megaADK.pid.1=0x0044
-megaADK.vid.2=0x2A03
-megaADK.pid.2=0x003f
-megaADK.vid.3=0x2A03
-megaADK.pid.3=0x0044
-
-megaADK.upload.tool=avrdude
-megaADK.upload.protocol=wiring
-megaADK.upload.maximum_size=253952
-megaADK.upload.maximum_data_size=8192
-megaADK.upload.speed=115200
-
-megaADK.bootloader.tool=avrdude
-megaADK.bootloader.low_fuses=0xFF
-megaADK.bootloader.high_fuses=0xD8
-megaADK.bootloader.extended_fuses=0xFD
-megaADK.bootloader.file=stk500v2/stk500boot_v2_mega2560.hex
-megaADK.bootloader.unlock_bits=0x3F
-megaADK.bootloader.lock_bits=0x0F
-
-megaADK.build.mcu=atmega2560
-megaADK.build.f_cpu=16000000L
-megaADK.build.board=AVR_ADK
-megaADK.build.core=arduino
-megaADK.build.variant=mega
-
-##############################################################
-
-leonardo.name=Arduino Leonardo
-leonardo.vid.0=0x2341
-leonardo.pid.0=0x0036
-leonardo.vid.1=0x2341
-leonardo.pid.1=0x8036
-leonardo.vid.2=0x2A03
-leonardo.pid.2=0x0036
-leonardo.vid.3=0x2A03
-leonardo.pid.3=0x8036
-
-leonardo.upload.tool=avrdude
-leonardo.upload.protocol=avr109
-leonardo.upload.maximum_size=28672
-leonardo.upload.maximum_data_size=2560
-leonardo.upload.speed=57600
-leonardo.upload.disable_flushing=true
-leonardo.upload.use_1200bps_touch=true
-leonardo.upload.wait_for_upload_port=true
-
-leonardo.bootloader.tool=avrdude
-leonardo.bootloader.low_fuses=0xff
-leonardo.bootloader.high_fuses=0xd8
-leonardo.bootloader.extended_fuses=0xcb
-leonardo.bootloader.file=caterina/Caterina-Leonardo.hex
-leonardo.bootloader.unlock_bits=0x3F
-leonardo.bootloader.lock_bits=0x2F
-
-leonardo.build.mcu=atmega32u4
-leonardo.build.f_cpu=16000000L
-leonardo.build.vid=0x2341
-leonardo.build.pid=0x8036
-leonardo.build.usb_product="Arduino Leonardo"
-leonardo.build.board=AVR_LEONARDO
-leonardo.build.core=arduino
-leonardo.build.variant=leonardo
-leonardo.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-micro.name=Arduino/Genuino Micro
-
-micro.vid.0=0x2341
-micro.pid.0=0x0037
-micro.vid.1=0x2341
-micro.pid.1=0x8037
-micro.vid.2=0x2A03
-micro.pid.2=0x0037
-micro.vid.3=0x2A03
-micro.pid.3=0x8037
-
-micro.vid.4=0x2341
-micro.pid.4=0x0237
-# If the board is a 2341:0237 use 2341:8237 for build and set
-# other parameters as well
-micro.vid.4.build.vid=0x2341
-micro.vid.4.build.pid=0x8237
-micro.vid.4.build.usb_product="Genuino Micro"
-micro.vid.4.bootloader.file=caterina/Caterina-Genuino-Micro.hex
-
-micro.vid.5=0x2341
-micro.pid.5=0x8237
-# If the board is a 2341:8237 use 2341:8237 for build and set
-# other paramters as well
-micro.vid.5.build.vid=0x2341
-micro.vid.5.build.pid=0x8237
-micro.vid.5.build.usb_product="Genuino Micro"
-micro.vid.5.bootloader.file=caterina/Caterina-Genuino-Micro.hex
-
-micro.upload.tool=avrdude
-micro.upload.protocol=avr109
-micro.upload.maximum_size=28672
-micro.upload.maximum_data_size=2560
-micro.upload.speed=57600
-micro.upload.disable_flushing=true
-micro.upload.use_1200bps_touch=true
-micro.upload.wait_for_upload_port=true
-
-micro.bootloader.tool=avrdude
-micro.bootloader.low_fuses=0xff
-micro.bootloader.high_fuses=0xd8
-micro.bootloader.extended_fuses=0xcb
-micro.bootloader.file=caterina/Caterina-Micro.hex
-micro.bootloader.unlock_bits=0x3F
-micro.bootloader.lock_bits=0x2F
-
-micro.build.mcu=atmega32u4
-micro.build.f_cpu=16000000L
-micro.build.vid=0x2341
-micro.build.pid=0x8037
-micro.build.usb_product="Arduino Micro"
-micro.build.board=AVR_MICRO
-micro.build.core=arduino
-micro.build.variant=micro
-micro.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-esplora.name=Arduino Esplora
-esplora.vid.0=0x2341
-esplora.pid.0=0x003C
-esplora.vid.1=0x2341
-esplora.pid.1=0x803C
-esplora.vid.2=0x2A03
-esplora.pid.2=0x003C
-esplora.vid.3=0x2A03
-esplora.pid.3=0x803C
-
-esplora.upload.tool=avrdude
-esplora.upload.protocol=avr109
-esplora.upload.maximum_size=28672
-esplora.upload.maximum_data_size=2560
-esplora.upload.speed=57600
-esplora.upload.disable_flushing=true
-esplora.upload.use_1200bps_touch=true
-esplora.upload.wait_for_upload_port=true
-
-esplora.bootloader.tool=avrdude
-esplora.bootloader.low_fuses=0xff
-esplora.bootloader.high_fuses=0xd8
-esplora.bootloader.extended_fuses=0xcb
-esplora.bootloader.file=caterina/Caterina-Esplora.hex
-esplora.bootloader.unlock_bits=0x3F
-esplora.bootloader.lock_bits=0x2F
-
-esplora.build.mcu=atmega32u4
-esplora.build.f_cpu=16000000L
-esplora.build.vid=0x2341
-esplora.build.pid=0x803c
-esplora.build.usb_product="Arduino Esplora"
-esplora.build.board=AVR_ESPLORA
-esplora.build.core=arduino
-esplora.build.variant=leonardo
-esplora.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-mini.name=Arduino Mini
-
-mini.upload.tool=avrdude
-mini.upload.protocol=arduino
-
-mini.bootloader.tool=avrdude
-mini.bootloader.low_fuses=0xff
-mini.bootloader.unlock_bits=0x3F
-mini.bootloader.lock_bits=0x0F
-
-mini.build.f_cpu=16000000L
-mini.build.board=AVR_MINI
-mini.build.core=arduino
-mini.build.variant=eightanaloginputs
-
-## Arduino Mini w/ ATmega328
-## -------------------------
-mini.menu.cpu.atmega328=ATmega328
-
-mini.menu.cpu.atmega328.upload.maximum_size=28672
-mini.menu.cpu.atmega328.upload.maximum_data_size=2048
-mini.menu.cpu.atmega328.upload.speed=115200
-
-mini.menu.cpu.atmega328.bootloader.high_fuses=0xd8
-mini.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-mini.menu.cpu.atmega328.bootloader.file=optiboot/optiboot_atmega328-Mini.hex
-
-mini.menu.cpu.atmega328.build.mcu=atmega328p
-
-## Arduino Mini w/ ATmega168
-## -------------------------
-mini.menu.cpu.atmega168=ATmega168
-
-mini.menu.cpu.atmega168.upload.maximum_size=14336
-mini.menu.cpu.atmega168.upload.maximum_data_size=1024
-mini.menu.cpu.atmega168.upload.speed=19200
-
-mini.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-mini.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-mini.menu.cpu.atmega168.bootloader.file=atmega/ATmegaBOOT_168_ng.hex
-
-mini.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-ethernet.name=Arduino Ethernet
-
-ethernet.upload.tool=avrdude
-ethernet.upload.protocol=arduino
-ethernet.upload.maximum_size=32256
-ethernet.upload.maximum_data_size=2048
-ethernet.upload.speed=115200
-
-ethernet.bootloader.tool=avrdude
-ethernet.bootloader.low_fuses=0xff
-ethernet.bootloader.high_fuses=0xde
-ethernet.bootloader.extended_fuses=0x05
-ethernet.bootloader.file=optiboot/optiboot_atmega328.hex
-ethernet.bootloader.unlock_bits=0x3F
-ethernet.bootloader.lock_bits=0x0F
-
-ethernet.build.variant=ethernet
-ethernet.build.mcu=atmega328p
-ethernet.build.f_cpu=16000000L
-ethernet.build.board=AVR_ETHERNET
-ethernet.build.core=arduino
-
-##############################################################
-
-fio.name=Arduino Fio
-
-fio.upload.tool=avrdude
-fio.upload.protocol=arduino
-fio.upload.maximum_size=30720
-fio.upload.maximum_data_size=2048
-fio.upload.speed=57600
-
-fio.bootloader.tool=avrdude
-fio.bootloader.low_fuses=0xFF
-fio.bootloader.high_fuses=0xDA
-fio.bootloader.extended_fuses=0x05
-fio.bootloader.file=atmega/ATmegaBOOT_168_atmega328_pro_8MHz.hex
-fio.bootloader.unlock_bits=0x3F
-fio.bootloader.lock_bits=0x0F
-
-fio.build.mcu=atmega328p
-fio.build.f_cpu=8000000L
-fio.build.board=AVR_FIO
-fio.build.core=arduino
-fio.build.variant=eightanaloginputs
-
-##############################################################
-
-bt.name=Arduino BT
-
-bt.upload.tool=avrdude
-bt.upload.protocol=arduino
-bt.upload.speed=19200
-bt.upload.disable_flushing=true
-
-bt.bootloader.tool=avrdude
-bt.bootloader.low_fuses=0xff
-bt.bootloader.unlock_bits=0x3F
-bt.bootloader.lock_bits=0x0F
-
-bt.build.f_cpu=16000000L
-bt.build.board=AVR_BT
-bt.build.core=arduino
-bt.build.variant=eightanaloginputs
-
-## Arduino BT w/ ATmega328
-## -----------------------
-bt.menu.cpu.atmega328=ATmega328
-bt.menu.cpu.atmega328.upload.maximum_size=28672
-bt.menu.cpu.atmega328.upload.maximum_data_size=2048
-
-bt.menu.cpu.atmega328.bootloader.high_fuses=0xd8
-bt.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-bt.menu.cpu.atmega328.bootloader.file=bt/ATmegaBOOT_168_atmega328_bt.hex
-
-bt.menu.cpu.atmega328.build.mcu=atmega328p
-
-## Arduino BT w/ ATmega168
-## -----------------------
-bt.menu.cpu.atmega168=ATmega168
-bt.menu.cpu.atmega168.upload.maximum_size=14336
-bt.menu.cpu.atmega168.upload.maximum_data_size=1024
-
-bt.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-bt.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-bt.menu.cpu.atmega168.bootloader.file=bt/ATmegaBOOT_168.hex
-
-bt.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-LilyPadUSB.name=LilyPad Arduino USB
-LilyPadUSB.vid.0=0x1B4F
-LilyPadUSB.pid.0=0x9207
-LilyPadUSB.vid.1=0x1B4F
-LilyPadUSB.pid.1=0x9208
-
-LilyPadUSB.upload.tool=avrdude
-LilyPadUSB.upload.protocol=avr109
-LilyPadUSB.upload.maximum_size=28672
-LilyPadUSB.upload.maximum_data_size=2560
-LilyPadUSB.upload.speed=57600
-LilyPadUSB.upload.disable_flushing=true
-LilyPadUSB.upload.use_1200bps_touch=true
-LilyPadUSB.upload.wait_for_upload_port=true
-
-LilyPadUSB.bootloader.tool=avrdude
-LilyPadUSB.bootloader.low_fuses=0xff
-LilyPadUSB.bootloader.high_fuses=0xd8
-LilyPadUSB.bootloader.extended_fuses=0xce
-LilyPadUSB.bootloader.file=caterina-LilyPadUSB/Caterina-LilyPadUSB.hex
-LilyPadUSB.bootloader.unlock_bits=0x3F
-LilyPadUSB.bootloader.lock_bits=0x2F
-
-LilyPadUSB.build.mcu=atmega32u4
-LilyPadUSB.build.f_cpu=8000000L
-LilyPadUSB.build.vid=0x1B4F
-LilyPadUSB.build.pid=0x9208
-LilyPadUSB.build.usb_product="LilyPad USB"
-LilyPadUSB.build.board=AVR_LILYPAD_USB
-LilyPadUSB.build.core=arduino
-LilyPadUSB.build.variant=leonardo
-LilyPadUSB.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-lilypad.name=LilyPad Arduino
-
-lilypad.upload.tool=avrdude
-lilypad.upload.protocol=arduino
-
-lilypad.bootloader.tool=avrdude
-lilypad.bootloader.unlock_bits=0x3F
-lilypad.bootloader.lock_bits=0x0F
-
-lilypad.build.f_cpu=8000000L
-lilypad.build.board=AVR_LILYPAD
-lilypad.build.core=arduino
-lilypad.build.variant=standard
-
-## LilyPad Arduino w/ ATmega328
-## ----------------------------
-lilypad.menu.cpu.atmega328=ATmega328
-
-lilypad.menu.cpu.atmega328.upload.maximum_size=30720
-lilypad.menu.cpu.atmega328.upload.maximum_data_size=2048
-lilypad.menu.cpu.atmega328.upload.speed=57600
-
-lilypad.menu.cpu.atmega328.bootloader.low_fuses=0xFF
-lilypad.menu.cpu.atmega328.bootloader.high_fuses=0xDA
-lilypad.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-lilypad.menu.cpu.atmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328_pro_8MHz.hex
-
-lilypad.menu.cpu.atmega328.build.mcu=atmega328p
-
-## LilyPad Arduino w/ ATmega168
-## ----------------------------
-lilypad.menu.cpu.atmega168=ATmega168
-
-lilypad.menu.cpu.atmega168.upload.maximum_size=14336
-lilypad.menu.cpu.atmega168.upload.maximum_data_size=1024
-lilypad.menu.cpu.atmega168.upload.speed=19200
-
-lilypad.menu.cpu.atmega168.bootloader.low_fuses=0xe2
-lilypad.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-lilypad.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-lilypad.menu.cpu.atmega168.bootloader.file=lilypad/LilyPadBOOT_168.hex
-
-lilypad.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-pro.name=Arduino Pro or Pro Mini
-
-pro.upload.tool=avrdude
-pro.upload.protocol=arduino
-
-pro.bootloader.tool=avrdude
-pro.bootloader.unlock_bits=0x3F
-pro.bootloader.lock_bits=0x0F
-
-pro.build.board=AVR_PRO
-pro.build.core=arduino
-pro.build.variant=eightanaloginputs
-
-## Arduino Pro or Pro Mini (5V, 16 MHz) w/ ATmega328
-## -------------------------------------------------
-pro.menu.cpu.16MHzatmega328=ATmega328 (5V, 16 MHz)
-
-pro.menu.cpu.16MHzatmega328.upload.maximum_size=30720
-pro.menu.cpu.16MHzatmega328.upload.maximum_data_size=2048
-pro.menu.cpu.16MHzatmega328.upload.speed=57600
-
-pro.menu.cpu.16MHzatmega328.bootloader.low_fuses=0xFF
-pro.menu.cpu.16MHzatmega328.bootloader.high_fuses=0xDA
-pro.menu.cpu.16MHzatmega328.bootloader.extended_fuses=0x05
-pro.menu.cpu.16MHzatmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328.hex
-
-pro.menu.cpu.16MHzatmega328.build.mcu=atmega328p
-pro.menu.cpu.16MHzatmega328.build.f_cpu=16000000L
-
-## Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega328
-## --------------------------------------------------
-pro.menu.cpu.8MHzatmega328=ATmega328 (3.3V, 8 MHz)
-
-pro.menu.cpu.8MHzatmega328.upload.maximum_size=30720
-pro.menu.cpu.8MHzatmega328.upload.maximum_data_size=2048
-pro.menu.cpu.8MHzatmega328.upload.speed=57600
-
-pro.menu.cpu.8MHzatmega328.bootloader.low_fuses=0xFF
-pro.menu.cpu.8MHzatmega328.bootloader.high_fuses=0xDA
-pro.menu.cpu.8MHzatmega328.bootloader.extended_fuses=0x05
-pro.menu.cpu.8MHzatmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328_pro_8MHz.hex
-
-pro.menu.cpu.8MHzatmega328.build.mcu=atmega328p
-pro.menu.cpu.8MHzatmega328.build.f_cpu=8000000L
-
-## Arduino Pro or Pro Mini (5V, 16 MHz) w/ ATmega168
-## -------------------------------------------------
-pro.menu.cpu.16MHzatmega168=ATmega168 (5V, 16 MHz)
-
-pro.menu.cpu.16MHzatmega168.upload.maximum_size=14336
-pro.menu.cpu.16MHzatmega168.upload.maximum_data_size=1024
-pro.menu.cpu.16MHzatmega168.upload.speed=19200
-
-pro.menu.cpu.16MHzatmega168.bootloader.low_fuses=0xff
-pro.menu.cpu.16MHzatmega168.bootloader.high_fuses=0xdd
-pro.menu.cpu.16MHzatmega168.bootloader.extended_fuses=0x00
-pro.menu.cpu.16MHzatmega168.bootloader.file=atmega/ATmegaBOOT_168_diecimila.hex
-
-pro.menu.cpu.16MHzatmega168.build.mcu=atmega168
-pro.menu.cpu.16MHzatmega168.build.f_cpu=16000000L
-
-## Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega168
-## --------------------------------------------------
-pro.menu.cpu.8MHzatmega168=ATmega168 (3.3V, 8 MHz)
-
-pro.menu.cpu.8MHzatmega168.upload.maximum_size=14336
-pro.menu.cpu.8MHzatmega168.upload.maximum_data_size=1024
-pro.menu.cpu.8MHzatmega168.upload.speed=19200
-
-pro.menu.cpu.8MHzatmega168.bootloader.low_fuses=0xc6
-pro.menu.cpu.8MHzatmega168.bootloader.high_fuses=0xdd
-pro.menu.cpu.8MHzatmega168.bootloader.extended_fuses=0x00
-pro.menu.cpu.8MHzatmega168.bootloader.file=atmega/ATmegaBOOT_168_pro_8MHz.hex
-
-pro.menu.cpu.8MHzatmega168.build.mcu=atmega168
-pro.menu.cpu.8MHzatmega168.build.f_cpu=8000000L
-
-##############################################################
-
-atmegang.name=Arduino NG or older
-
-atmegang.upload.tool=avrdude
-atmegang.upload.protocol=arduino
-atmegang.upload.speed=19200
-
-atmegang.bootloader.tool=avrdude
-atmegang.bootloader.unlock_bits=0x3F
-atmegang.bootloader.lock_bits=0x0F
-
-atmegang.build.mcu=atmegang
-atmegang.build.f_cpu=16000000L
-atmegang.build.board=AVR_NG
-atmegang.build.core=arduino
-atmegang.build.variant=standard
-
-## Arduino NG or older w/ ATmega168
-## --------------------------------
-atmegang.menu.cpu.atmega168=ATmega168
-
-atmegang.menu.cpu.atmega168.upload.maximum_size=14336
-atmegang.menu.cpu.atmega168.upload.maximum_data_size=1024
-
-atmegang.menu.cpu.atmega168.bootloader.low_fuses=0xff
-atmegang.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-atmegang.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-atmegang.menu.cpu.atmega168.bootloader.file=atmega/ATmegaBOOT_168_ng.hex
-
-atmegang.menu.cpu.atmega168.build.mcu=atmega168
-
-## Arduino NG or older w/ ATmega8
-## ------------------------------
-atmegang.menu.cpu.atmega8=ATmega8
-
-atmegang.menu.cpu.atmega8.upload.maximum_size=7168
-atmegang.menu.cpu.atmega8.upload.maximum_data_size=1024
-
-atmegang.menu.cpu.atmega8.bootloader.low_fuses=0xdf
-atmegang.menu.cpu.atmega8.bootloader.high_fuses=0xca
-atmegang.menu.cpu.atmega8.bootloader.file=atmega8/ATmegaBOOT-prod-firmware-2009-11-07.hex
-
-atmegang.menu.cpu.atmega8.build.mcu=atmega8
-
-##############################################################
-
-robotControl.name=Arduino Robot Control
-robotControl.vid.0=0x2341
-robotControl.pid.0=0x0038
-robotControl.vid.1=0x2341
-robotControl.pid.1=0x8038
-robotControl.vid.2=0x2A03
-robotControl.pid.2=0x0038
-robotControl.vid.3=0x2A03
-robotControl.pid.3=0x8038
-
-robotControl.upload.tool=avrdude
-robotControl.upload.protocol=avr109
-robotControl.upload.maximum_size=28672
-robotControl.upload.maximum_data_size=2560
-robotControl.upload.speed=57600
-robotControl.upload.disable_flushing=true
-robotControl.upload.use_1200bps_touch=true
-robotControl.upload.wait_for_upload_port=true
-
-robotControl.bootloader.tool=avrdude
-robotControl.bootloader.low_fuses=0xff
-robotControl.bootloader.high_fuses=0xd8
-robotControl.bootloader.extended_fuses=0xcb
-robotControl.bootloader.file=caterina-Arduino_Robot/Caterina-Robot-Control.hex
-robotControl.bootloader.unlock_bits=0x3F
-robotControl.bootloader.lock_bits=0x2F
-
-robotControl.build.mcu=atmega32u4
-robotControl.build.f_cpu=16000000L
-robotControl.build.vid=0x2341
-robotControl.build.pid=0x8038
-robotControl.build.usb_product="Robot Control"
-robotControl.build.board=AVR_ROBOT_CONTROL
-robotControl.build.core=arduino
-robotControl.build.variant=robot_control
-robotControl.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-robotMotor.name=Arduino Robot Motor
-robotMotor.vid.0=0x2341
-robotMotor.pid.0=0x0039
-robotMotor.vid.1=0x2341
-robotMotor.pid.1=0x8039
-robotMotor.vid.2=0x2A03
-robotMotor.pid.2=0x0039
-robotMotor.vid.3=0x2A03
-robotMotor.pid.3=0x8039
-
-robotMotor.upload.tool=avrdude
-robotMotor.upload.protocol=avr109
-robotMotor.upload.maximum_size=28672
-robotMotor.upload.maximum_data_size=2560
-robotMotor.upload.speed=57600
-robotMotor.upload.disable_flushing=true
-robotMotor.upload.use_1200bps_touch=true
-robotMotor.upload.wait_for_upload_port=true
-
-robotMotor.bootloader.tool=avrdude
-robotMotor.bootloader.low_fuses=0xff
-robotMotor.bootloader.high_fuses=0xd8
-robotMotor.bootloader.extended_fuses=0xcb
-robotMotor.bootloader.file=caterina-Arduino_Robot/Caterina-Robot-Motor.hex
-robotMotor.bootloader.unlock_bits=0x3F
-robotMotor.bootloader.lock_bits=0x2F
-
-robotMotor.build.mcu=atmega32u4
-robotMotor.build.f_cpu=16000000L
-robotMotor.build.vid=0x2341
-robotMotor.build.pid=0x8039
-robotMotor.build.usb_product="Robot Motor"
-robotMotor.build.board=AVR_ROBOT_MOTOR
-robotMotor.build.core=arduino
-robotMotor.build.variant=robot_motor
-robotMotor.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-gemma.vid.0=0x2341
-gemma.pid.0=0x0c9f
-
-gemma.name=Arduino Gemma
-
-gemma.bootloader.low_fuses=0xF1
-gemma.bootloader.high_fuses=0xD5
-gemma.bootloader.extended_fuses=0xFE
-gemma.bootloader.tool=avrdude
-gemma.bootloader.lock_bits=
-gemma.bootloader.unlock_bits=
-gemma.bootloader.file=gemma/gemma_v1.hex
-
-gemma.build.mcu=attiny85
-gemma.build.f_cpu=8000000L
-gemma.build.core=arduino
-gemma.build.variant=gemma
-gemma.build.board=AVR_GEMMA
-
-gemma.upload.tool=avrdude
-gemma.upload.maximum_size=5310
-
diff --git a/arduino/boards.txt.arduino1.6.x b/arduino/boards.txt.arduino1.6.x
deleted file mode 100644
index 4046336d..00000000
--- a/arduino/boards.txt.arduino1.6.x
+++ /dev/null
@@ -1,834 +0,0 @@
-# See: http://code.google.com/p/arduino/wiki/Platforms
-
-menu.cpu=Processor
-
-##############################################################
-## OpenEVSE with Programmer selected from Tools->Programmer
-## ---------------------------------------------
-openevse.name=[Programmer]OpenEVSE
-openevse.upload.tool=avrdude
-openevse.upload.maximum_size=32768
-openevse.upload.maximum_data_size=2048
-
-openevse.bootloader.tool=avrdude
-openevse.bootloader.low_fuses=0xFF
-openevse.bootloader.high_fuses=0xDF
-openevse.bootloader.extended_fuses=0x04
-openevse.bootloader.unlock_bits=0x3F
-openevse.bootloader.lock_bits=0x0F
-openevse.bootloader.file=optiboot/optiboot_atmega328.hex
-
-openevse.build.mcu=atmega328p
-openevse.build.f_cpu=16000000L
-openevse.build.board=AVR_DUEMILANOVE
-openevse.build.core=arduino
-openevse.build.variant=standard
-openevse.menu.cpu.atmega328=ATmega328
-
-##############################################################
-
-yun.name=Arduino Yún
-yun.upload.via_ssh=true
-
-yun.vid.0=0x2341
-yun.pid.0=0x0041
-yun.vid.1=0x2341
-yun.pid.1=0x8041
-yun.vid.2=0x2A03
-yun.pid.2=0x0041
-yun.vid.3=0x2A03
-yun.pid.3=0x8041
-
-yun.vid.0x2A03.warning=Uncertified
-
-yun.upload.tool=avrdude
-yun.upload.protocol=avr109
-yun.upload.maximum_size=28672
-yun.upload.maximum_data_size=2560
-yun.upload.speed=57600
-yun.upload.disable_flushing=true
-yun.upload.use_1200bps_touch=true
-yun.upload.wait_for_upload_port=true
-
-yun.bootloader.tool=avrdude
-yun.bootloader.low_fuses=0xff
-yun.bootloader.high_fuses=0xd8
-yun.bootloader.extended_fuses=0xfb
-yun.bootloader.file=caterina/Caterina-Yun.hex
-yun.bootloader.unlock_bits=0x3F
-yun.bootloader.lock_bits=0x2F
-
-yun.build.mcu=atmega32u4
-yun.build.f_cpu=16000000L
-yun.build.vid=0x2341
-yun.build.pid=0x8041
-yun.build.usb_product="Arduino Yun"
-yun.build.board=AVR_YUN
-yun.build.core=arduino
-yun.build.variant=yun
-yun.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-uno.name=Arduino Uno
-
-uno.vid.0=0x2341
-uno.pid.0=0x0043
-uno.vid.1=0x2341
-uno.pid.1=0x0001
-uno.vid.2=0x2A03
-uno.pid.2=0x0043
-
-uno.vid.0x2A03.warning=Uncertified
-
-uno.upload.tool=avrdude
-uno.upload.protocol=arduino
-uno.upload.maximum_size=32256
-uno.upload.maximum_data_size=2048
-uno.upload.speed=115200
-
-uno.bootloader.tool=avrdude
-uno.bootloader.low_fuses=0xFF
-uno.bootloader.high_fuses=0xDE
-uno.bootloader.extended_fuses=0x05
-uno.bootloader.unlock_bits=0x3F
-uno.bootloader.lock_bits=0x0F
-uno.bootloader.file=optiboot/optiboot_atmega328.hex
-
-uno.build.mcu=atmega328p
-uno.build.f_cpu=16000000L
-uno.build.board=AVR_UNO
-uno.build.core=arduino
-uno.build.variant=standard
-
-##############################################################
-
-diecimila.name=Arduino Duemilanove or Diecimila
-
-diecimila.upload.tool=avrdude
-diecimila.upload.protocol=arduino
-
-diecimila.bootloader.tool=avrdude
-diecimila.bootloader.low_fuses=0xFF
-diecimila.bootloader.unlock_bits=0x3F
-diecimila.bootloader.lock_bits=0x0F
-
-diecimila.build.f_cpu=16000000L
-diecimila.build.board=AVR_DUEMILANOVE
-diecimila.build.core=arduino
-diecimila.build.variant=standard
-
-## Arduino Duemilanove or Diecimila w/ ATmega328
-## ---------------------------------------------
-diecimila.menu.cpu.atmega328=ATmega328
-
-diecimila.menu.cpu.atmega328.upload.maximum_size=30720
-diecimila.menu.cpu.atmega328.upload.maximum_data_size=2048
-diecimila.menu.cpu.atmega328.upload.speed=57600
-
-diecimila.menu.cpu.atmega328.bootloader.high_fuses=0xDA
-diecimila.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-diecimila.menu.cpu.atmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328.hex
-
-diecimila.menu.cpu.atmega328.build.mcu=atmega328p
-
-## Arduino Duemilanove or Diecimila w/ ATmega168
-## ---------------------------------------------
-diecimila.menu.cpu.atmega168=ATmega168
-
-diecimila.menu.cpu.atmega168.upload.maximum_size=14336
-diecimila.menu.cpu.atmega168.upload.maximum_data_size=1024
-diecimila.menu.cpu.atmega168.upload.speed=19200
-
-diecimila.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-diecimila.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-diecimila.menu.cpu.atmega168.bootloader.file=atmega/ATmegaBOOT_168_diecimila.hex
-
-diecimila.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-nano.name=Arduino Nano
-
-nano.upload.tool=avrdude
-nano.upload.protocol=arduino
-
-nano.bootloader.tool=avrdude
-nano.bootloader.unlock_bits=0x3F
-nano.bootloader.lock_bits=0x0F
-
-nano.build.f_cpu=16000000L
-nano.build.board=AVR_NANO
-nano.build.core=arduino
-nano.build.variant=eightanaloginputs
-
-## Arduino Nano w/ ATmega328
-## -------------------------
-nano.menu.cpu.atmega328=ATmega328
-
-nano.menu.cpu.atmega328.upload.maximum_size=30720
-nano.menu.cpu.atmega328.upload.maximum_data_size=2048
-nano.menu.cpu.atmega328.upload.speed=57600
-
-nano.menu.cpu.atmega328.bootloader.low_fuses=0xFF
-nano.menu.cpu.atmega328.bootloader.high_fuses=0xDA
-nano.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-nano.menu.cpu.atmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328.hex
-
-nano.menu.cpu.atmega328.build.mcu=atmega328p
-
-## Arduino Nano w/ ATmega168
-## -------------------------
-nano.menu.cpu.atmega168=ATmega168
-
-nano.menu.cpu.atmega168.upload.maximum_size=14336
-nano.menu.cpu.atmega168.upload.maximum_data_size=1024
-nano.menu.cpu.atmega168.upload.speed=19200
-
-nano.menu.cpu.atmega168.bootloader.low_fuses=0xff
-nano.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-nano.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-nano.menu.cpu.atmega168.bootloader.file=atmega/ATmegaBOOT_168_diecimila.hex
-
-nano.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-mega.name=Arduino Mega or Mega 2560
-
-mega.vid.0=0x2341
-mega.pid.0=0x0010
-mega.vid.1=0x2341
-mega.pid.1=0x0042
-mega.vid.2=0x2A03
-mega.pid.2=0x0010
-mega.vid.3=0x2A03
-mega.pid.3=0x0042
-
-mega.vid.0x2A03.warning=Uncertified
-
-mega.upload.tool=avrdude
-mega.upload.maximum_data_size=8192
-
-mega.bootloader.tool=avrdude
-mega.bootloader.low_fuses=0xFF
-mega.bootloader.unlock_bits=0x3F
-mega.bootloader.lock_bits=0x0F
-
-mega.build.f_cpu=16000000L
-mega.build.core=arduino
-mega.build.variant=mega
-# default board  may be overridden by the cpu menu
-mega.build.board=AVR_MEGA2560
-
-## Arduino Mega w/ ATmega2560
-## -------------------------
-mega.menu.cpu.atmega2560=ATmega2560 (Mega 2560)
-
-mega.menu.cpu.atmega2560.upload.protocol=wiring
-mega.menu.cpu.atmega2560.upload.maximum_size=253952
-mega.menu.cpu.atmega2560.upload.speed=115200
-
-mega.menu.cpu.atmega2560.bootloader.high_fuses=0xD8
-mega.menu.cpu.atmega2560.bootloader.extended_fuses=0xFD
-mega.menu.cpu.atmega2560.bootloader.file=stk500v2/stk500boot_v2_mega2560.hex
-
-mega.menu.cpu.atmega2560.build.mcu=atmega2560
-mega.menu.cpu.atmega2560.build.board=AVR_MEGA2560
-
-## Arduino Mega w/ ATmega1280
-## -------------------------
-mega.menu.cpu.atmega1280=ATmega1280
-
-mega.menu.cpu.atmega1280.upload.protocol=arduino
-mega.menu.cpu.atmega1280.upload.maximum_size=126976
-mega.menu.cpu.atmega1280.upload.speed=57600
-
-mega.menu.cpu.atmega1280.bootloader.high_fuses=0xDA
-mega.menu.cpu.atmega1280.bootloader.extended_fuses=0xF5
-mega.menu.cpu.atmega1280.bootloader.file=atmega/ATmegaBOOT_168_atmega1280.hex
-
-mega.menu.cpu.atmega1280.build.mcu=atmega1280
-mega.menu.cpu.atmega1280.build.board=AVR_MEGA
-
-##############################################################
-
-megaADK.name=Arduino Mega ADK
-
-megaADK.vid.0=0x2341
-megaADK.pid.0=0x003f
-megaADK.vid.1=0x2341
-megaADK.pid.1=0x0044
-megaADK.vid.2=0x2A03
-megaADK.pid.2=0x003f
-megaADK.vid.3=0x2A03
-megaADK.pid.3=0x0044
-
-megaADK.vid.0x2A03.warning=Uncertified
-
-megaADK.upload.tool=avrdude
-megaADK.upload.protocol=wiring
-megaADK.upload.maximum_size=253952
-megaADK.upload.maximum_data_size=8192
-megaADK.upload.speed=115200
-
-megaADK.bootloader.tool=avrdude
-megaADK.bootloader.low_fuses=0xFF
-megaADK.bootloader.high_fuses=0xD8
-megaADK.bootloader.extended_fuses=0xFD
-megaADK.bootloader.file=stk500v2/stk500boot_v2_mega2560.hex
-megaADK.bootloader.unlock_bits=0x3F
-megaADK.bootloader.lock_bits=0x0F
-
-megaADK.build.mcu=atmega2560
-megaADK.build.f_cpu=16000000L
-megaADK.build.board=AVR_ADK
-megaADK.build.core=arduino
-megaADK.build.variant=mega
-
-##############################################################
-
-leonardo.name=Arduino Leonardo
-leonardo.vid.0=0x2341
-leonardo.pid.0=0x0036
-leonardo.vid.1=0x2341
-leonardo.pid.1=0x8036
-leonardo.vid.2=0x2A03
-leonardo.pid.2=0x0036
-leonardo.vid.3=0x2A03
-leonardo.pid.3=0x8036
-
-leonardo.vid.0x2A03.warning=Uncertified
-
-leonardo.upload.tool=avrdude
-leonardo.upload.protocol=avr109
-leonardo.upload.maximum_size=28672
-leonardo.upload.maximum_data_size=2560
-leonardo.upload.speed=57600
-leonardo.upload.disable_flushing=true
-leonardo.upload.use_1200bps_touch=true
-leonardo.upload.wait_for_upload_port=true
-
-leonardo.bootloader.tool=avrdude
-leonardo.bootloader.low_fuses=0xff
-leonardo.bootloader.high_fuses=0xd8
-leonardo.bootloader.extended_fuses=0xcb
-leonardo.bootloader.file=caterina/Caterina-Leonardo.hex
-leonardo.bootloader.unlock_bits=0x3F
-leonardo.bootloader.lock_bits=0x2F
-
-leonardo.build.mcu=atmega32u4
-leonardo.build.f_cpu=16000000L
-leonardo.build.vid=0x2341
-leonardo.build.pid=0x8036
-leonardo.build.usb_product="Arduino Leonardo"
-leonardo.build.board=AVR_LEONARDO
-leonardo.build.core=arduino
-leonardo.build.variant=leonardo
-leonardo.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-micro.name=Arduino Micro
-micro.vid.0=0x2341
-micro.pid.0=0x0037
-micro.vid.1=0x2341
-micro.pid.1=0x8037
-micro.vid.2=0x2A03
-micro.pid.2=0x0037
-micro.vid.3=0x2A03
-micro.pid.3=0x8037
-
-micro.vid.0x2A03.warning=Uncertified
-
-micro.upload.tool=avrdude
-micro.upload.protocol=avr109
-micro.upload.maximum_size=28672
-micro.upload.maximum_data_size=2560
-micro.upload.speed=57600
-micro.upload.disable_flushing=true
-micro.upload.use_1200bps_touch=true
-micro.upload.wait_for_upload_port=true
-
-micro.bootloader.tool=avrdude
-micro.bootloader.low_fuses=0xff
-micro.bootloader.high_fuses=0xd8
-micro.bootloader.extended_fuses=0xcb
-micro.bootloader.file=caterina/Caterina-Micro.hex
-micro.bootloader.unlock_bits=0x3F
-micro.bootloader.lock_bits=0x2F
-
-micro.build.mcu=atmega32u4
-micro.build.f_cpu=16000000L
-micro.build.vid=0x2341
-micro.build.pid=0x8037
-micro.build.usb_product="Arduino Micro"
-micro.build.board=AVR_MICRO
-micro.build.core=arduino
-micro.build.variant=micro
-micro.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-esplora.name=Arduino Esplora
-esplora.vid.0=0x2341
-esplora.pid.0=0x003C
-esplora.vid.1=0x2341
-esplora.pid.1=0x803C
-esplora.vid.2=0x2A03
-esplora.pid.2=0x003C
-esplora.vid.3=0x2A03
-esplora.pid.3=0x803C
-
-esplora.vid.0x2A03.warning=Uncertified
-
-esplora.upload.tool=avrdude
-esplora.upload.protocol=avr109
-esplora.upload.maximum_size=28672
-esplora.upload.maximum_data_size=2560
-esplora.upload.speed=57600
-esplora.upload.disable_flushing=true
-esplora.upload.use_1200bps_touch=true
-esplora.upload.wait_for_upload_port=true
-
-esplora.bootloader.tool=avrdude
-esplora.bootloader.low_fuses=0xff
-esplora.bootloader.high_fuses=0xd8
-esplora.bootloader.extended_fuses=0xcb
-esplora.bootloader.file=caterina/Caterina-Esplora.hex
-esplora.bootloader.unlock_bits=0x3F
-esplora.bootloader.lock_bits=0x2F
-
-esplora.build.mcu=atmega32u4
-esplora.build.f_cpu=16000000L
-esplora.build.vid=0x2341
-esplora.build.pid=0x803c
-esplora.build.usb_product="Arduino Esplora"
-esplora.build.board=AVR_ESPLORA
-esplora.build.core=arduino
-esplora.build.variant=leonardo
-esplora.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-mini.name=Arduino Mini
-
-mini.upload.tool=avrdude
-mini.upload.protocol=arduino
-
-mini.bootloader.tool=avrdude
-mini.bootloader.low_fuses=0xff
-mini.bootloader.unlock_bits=0x3F
-mini.bootloader.lock_bits=0x0F
-
-mini.build.f_cpu=16000000L
-mini.build.board=AVR_MINI
-mini.build.core=arduino
-mini.build.variant=eightanaloginputs
-
-## Arduino Mini w/ ATmega328
-## -------------------------
-mini.menu.cpu.atmega328=ATmega328
-
-mini.menu.cpu.atmega328.upload.maximum_size=28672
-mini.menu.cpu.atmega328.upload.maximum_data_size=2048
-mini.menu.cpu.atmega328.upload.speed=115200
-
-mini.menu.cpu.atmega328.bootloader.high_fuses=0xd8
-mini.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-mini.menu.cpu.atmega328.bootloader.file=optiboot/optiboot_atmega328-Mini.hex
-
-mini.menu.cpu.atmega328.build.mcu=atmega328p
-
-## Arduino Mini w/ ATmega168
-## -------------------------
-mini.menu.cpu.atmega168=ATmega168
-
-mini.menu.cpu.atmega168.upload.maximum_size=14336
-mini.menu.cpu.atmega168.upload.maximum_data_size=1024
-mini.menu.cpu.atmega168.upload.speed=19200
-
-mini.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-mini.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-mini.menu.cpu.atmega168.bootloader.file=atmega/ATmegaBOOT_168_ng.hex
-
-mini.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-ethernet.name=Arduino Ethernet
-
-ethernet.upload.tool=avrdude
-ethernet.upload.protocol=arduino
-ethernet.upload.maximum_size=32256
-ethernet.upload.maximum_data_size=2048
-ethernet.upload.speed=115200
-
-ethernet.bootloader.tool=avrdude
-ethernet.bootloader.low_fuses=0xff
-ethernet.bootloader.high_fuses=0xde
-ethernet.bootloader.extended_fuses=0x05
-ethernet.bootloader.file=optiboot/optiboot_atmega328.hex
-ethernet.bootloader.unlock_bits=0x3F
-ethernet.bootloader.lock_bits=0x0F
-
-ethernet.build.variant=ethernet
-ethernet.build.mcu=atmega328p
-ethernet.build.f_cpu=16000000L
-ethernet.build.board=AVR_ETHERNET
-ethernet.build.core=arduino
-
-##############################################################
-
-fio.name=Arduino Fio
-
-fio.upload.tool=avrdude
-fio.upload.protocol=arduino
-fio.upload.maximum_size=30720
-fio.upload.maximum_data_size=2048
-fio.upload.speed=57600
-
-fio.bootloader.tool=avrdude
-fio.bootloader.low_fuses=0xFF
-fio.bootloader.high_fuses=0xDA
-fio.bootloader.extended_fuses=0x05
-fio.bootloader.file=atmega/ATmegaBOOT_168_atmega328_pro_8MHz.hex
-fio.bootloader.unlock_bits=0x3F
-fio.bootloader.lock_bits=0x0F
-
-fio.build.mcu=atmega328p
-fio.build.f_cpu=8000000L
-fio.build.board=AVR_FIO
-fio.build.core=arduino
-fio.build.variant=eightanaloginputs
-
-##############################################################
-
-bt.name=Arduino BT
-
-bt.upload.tool=avrdude
-bt.upload.protocol=arduino
-bt.upload.speed=19200
-bt.upload.disable_flushing=true
-
-bt.bootloader.tool=avrdude
-bt.bootloader.low_fuses=0xff
-bt.bootloader.unlock_bits=0x3F
-bt.bootloader.lock_bits=0x0F
-
-bt.build.f_cpu=16000000L
-bt.build.board=AVR_BT
-bt.build.core=arduino
-bt.build.variant=eightanaloginputs
-
-## Arduino BT w/ ATmega328
-## -----------------------
-bt.menu.cpu.atmega328=ATmega328
-bt.menu.cpu.atmega328.upload.maximum_size=28672
-bt.menu.cpu.atmega328.upload.maximum_data_size=2048
-
-bt.menu.cpu.atmega328.bootloader.high_fuses=0xd8
-bt.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-bt.menu.cpu.atmega328.bootloader.file=bt/ATmegaBOOT_168_atmega328_bt.hex
-
-bt.menu.cpu.atmega328.build.mcu=atmega328p
-
-## Arduino BT w/ ATmega168
-## -----------------------
-bt.menu.cpu.atmega168=ATmega168
-bt.menu.cpu.atmega168.upload.maximum_size=14336
-bt.menu.cpu.atmega168.upload.maximum_data_size=1024
-
-bt.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-bt.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-bt.menu.cpu.atmega168.bootloader.file=bt/ATmegaBOOT_168.hex
-
-bt.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-LilyPadUSB.name=LilyPad Arduino USB
-LilyPadUSB.vid.0=0x1B4F
-LilyPadUSB.pid.0=0x9207
-LilyPadUSB.vid.1=0x1B4F
-LilyPadUSB.pid.1=0x9208
-
-LilyPadUSB.upload.tool=avrdude
-LilyPadUSB.upload.protocol=avr109
-LilyPadUSB.upload.maximum_size=28672
-LilyPadUSB.upload.maximum_data_size=2560
-LilyPadUSB.upload.speed=57600
-LilyPadUSB.upload.disable_flushing=true
-LilyPadUSB.upload.use_1200bps_touch=true
-LilyPadUSB.upload.wait_for_upload_port=true
-
-LilyPadUSB.bootloader.tool=avrdude
-LilyPadUSB.bootloader.low_fuses=0xff
-LilyPadUSB.bootloader.high_fuses=0xd8
-LilyPadUSB.bootloader.extended_fuses=0xce
-LilyPadUSB.bootloader.file=caterina-LilyPadUSB/Caterina-LilyPadUSB.hex
-LilyPadUSB.bootloader.unlock_bits=0x3F
-LilyPadUSB.bootloader.lock_bits=0x2F
-
-LilyPadUSB.build.mcu=atmega32u4
-LilyPadUSB.build.f_cpu=8000000L
-LilyPadUSB.build.vid=0x1B4F
-LilyPadUSB.build.pid=0x9208
-LilyPadUSB.build.usb_product="LilyPad USB"
-LilyPadUSB.build.board=AVR_LILYPAD_USB
-LilyPadUSB.build.core=arduino
-LilyPadUSB.build.variant=leonardo
-LilyPadUSB.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-lilypad.name=LilyPad Arduino
-
-lilypad.upload.tool=avrdude
-lilypad.upload.protocol=arduino
-
-lilypad.bootloader.tool=avrdude
-lilypad.bootloader.unlock_bits=0x3F
-lilypad.bootloader.lock_bits=0x0F
-
-lilypad.build.f_cpu=8000000L
-lilypad.build.board=AVR_LILYPAD
-lilypad.build.core=arduino
-lilypad.build.variant=standard
-
-## LilyPad Arduino w/ ATmega328
-## ----------------------------
-lilypad.menu.cpu.atmega328=ATmega328
-
-lilypad.menu.cpu.atmega328.upload.maximum_size=30720
-lilypad.menu.cpu.atmega328.upload.maximum_data_size=2048
-lilypad.menu.cpu.atmega328.upload.speed=57600
-
-lilypad.menu.cpu.atmega328.bootloader.low_fuses=0xFF
-lilypad.menu.cpu.atmega328.bootloader.high_fuses=0xDA
-lilypad.menu.cpu.atmega328.bootloader.extended_fuses=0x05
-lilypad.menu.cpu.atmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328_pro_8MHz.hex
-
-lilypad.menu.cpu.atmega328.build.mcu=atmega328p
-
-## LilyPad Arduino w/ ATmega168
-## ----------------------------
-lilypad.menu.cpu.atmega168=ATmega168
-
-lilypad.menu.cpu.atmega168.upload.maximum_size=14336
-lilypad.menu.cpu.atmega168.upload.maximum_data_size=1024
-lilypad.menu.cpu.atmega168.upload.speed=19200
-
-lilypad.menu.cpu.atmega168.bootloader.low_fuses=0xe2
-lilypad.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-lilypad.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-lilypad.menu.cpu.atmega168.bootloader.file=lilypad/LilyPadBOOT_168.hex
-
-lilypad.menu.cpu.atmega168.build.mcu=atmega168
-
-##############################################################
-
-pro.name=Arduino Pro or Pro Mini
-
-pro.upload.tool=avrdude
-pro.upload.protocol=arduino
-
-pro.bootloader.tool=avrdude
-pro.bootloader.unlock_bits=0x3F
-pro.bootloader.lock_bits=0x0F
-
-pro.build.board=AVR_PRO
-pro.build.core=arduino
-pro.build.variant=eightanaloginputs
-
-## Arduino Pro or Pro Mini (5V, 16 MHz) w/ ATmega328
-## -------------------------------------------------
-pro.menu.cpu.16MHzatmega328=ATmega328 (5V, 16 MHz)
-
-pro.menu.cpu.16MHzatmega328.upload.maximum_size=30720
-pro.menu.cpu.16MHzatmega328.upload.maximum_data_size=2048
-pro.menu.cpu.16MHzatmega328.upload.speed=57600
-
-pro.menu.cpu.16MHzatmega328.bootloader.low_fuses=0xFF
-pro.menu.cpu.16MHzatmega328.bootloader.high_fuses=0xDA
-pro.menu.cpu.16MHzatmega328.bootloader.extended_fuses=0x05
-pro.menu.cpu.16MHzatmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328.hex
-
-pro.menu.cpu.16MHzatmega328.build.mcu=atmega328p
-pro.menu.cpu.16MHzatmega328.build.f_cpu=16000000L
-
-## Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega328
-## --------------------------------------------------
-pro.menu.cpu.8MHzatmega328=ATmega328 (3.3V, 8 MHz)
-
-pro.menu.cpu.8MHzatmega328.upload.maximum_size=30720
-pro.menu.cpu.8MHzatmega328.upload.maximum_data_size=2048
-pro.menu.cpu.8MHzatmega328.upload.speed=57600
-
-pro.menu.cpu.8MHzatmega328.bootloader.low_fuses=0xFF
-pro.menu.cpu.8MHzatmega328.bootloader.high_fuses=0xDA
-pro.menu.cpu.8MHzatmega328.bootloader.extended_fuses=0x05
-pro.menu.cpu.8MHzatmega328.bootloader.file=atmega/ATmegaBOOT_168_atmega328_pro_8MHz.hex
-
-pro.menu.cpu.8MHzatmega328.build.mcu=atmega328p
-pro.menu.cpu.8MHzatmega328.build.f_cpu=8000000L
-
-## Arduino Pro or Pro Mini (5V, 16 MHz) w/ ATmega168
-## -------------------------------------------------
-pro.menu.cpu.16MHzatmega168=ATmega168 (5V, 16 MHz)
-
-pro.menu.cpu.16MHzatmega168.upload.maximum_size=14336
-pro.menu.cpu.16MHzatmega168.upload.maximum_data_size=1024
-pro.menu.cpu.16MHzatmega168.upload.speed=19200
-
-pro.menu.cpu.16MHzatmega168.bootloader.low_fuses=0xff
-pro.menu.cpu.16MHzatmega168.bootloader.high_fuses=0xdd
-pro.menu.cpu.16MHzatmega168.bootloader.extended_fuses=0x00
-pro.menu.cpu.16MHzatmega168.bootloader.file=atmega/ATmegaBOOT_168_diecimila.hex
-
-pro.menu.cpu.16MHzatmega168.build.mcu=atmega168
-pro.menu.cpu.16MHzatmega168.build.f_cpu=16000000L
-
-## Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega168
-## --------------------------------------------------
-pro.menu.cpu.8MHzatmega168=ATmega168 (3.3V, 8 MHz)
-
-pro.menu.cpu.8MHzatmega168.upload.maximum_size=14336
-pro.menu.cpu.8MHzatmega168.upload.maximum_data_size=1024
-pro.menu.cpu.8MHzatmega168.upload.speed=19200
-
-pro.menu.cpu.8MHzatmega168.bootloader.low_fuses=0xc6
-pro.menu.cpu.8MHzatmega168.bootloader.high_fuses=0xdd
-pro.menu.cpu.8MHzatmega168.bootloader.extended_fuses=0x00
-pro.menu.cpu.8MHzatmega168.bootloader.file=atmega/ATmegaBOOT_168_pro_8MHz.hex
-
-pro.menu.cpu.8MHzatmega168.build.mcu=atmega168
-pro.menu.cpu.8MHzatmega168.build.f_cpu=8000000L
-
-##############################################################
-
-atmegang.name=Arduino NG or older
-
-atmegang.upload.tool=avrdude
-atmegang.upload.protocol=arduino
-atmegang.upload.speed=19200
-
-atmegang.bootloader.tool=avrdude
-atmegang.bootloader.unlock_bits=0x3F
-atmegang.bootloader.lock_bits=0x0F
-
-atmegang.build.mcu=atmegang
-atmegang.build.f_cpu=16000000L
-atmegang.build.board=AVR_NG
-atmegang.build.core=arduino
-atmegang.build.variant=standard
-
-## Arduino NG or older w/ ATmega168
-## --------------------------------
-atmegang.menu.cpu.atmega168=ATmega168
-
-atmegang.menu.cpu.atmega168.upload.maximum_size=14336
-atmegang.menu.cpu.atmega168.upload.maximum_data_size=1024
-
-atmegang.menu.cpu.atmega168.bootloader.low_fuses=0xff
-atmegang.menu.cpu.atmega168.bootloader.high_fuses=0xdd
-atmegang.menu.cpu.atmega168.bootloader.extended_fuses=0x00
-atmegang.menu.cpu.atmega168.bootloader.file=atmega/ATmegaBOOT_168_ng.hex
-
-atmegang.menu.cpu.atmega168.build.mcu=atmega168
-
-## Arduino NG or older w/ ATmega8
-## ------------------------------
-atmegang.menu.cpu.atmega8=ATmega8
-
-atmegang.menu.cpu.atmega8.upload.maximum_size=7168
-atmegang.menu.cpu.atmega8.upload.maximum_data_size=1024
-
-atmegang.menu.cpu.atmega8.bootloader.low_fuses=0xdf
-atmegang.menu.cpu.atmega8.bootloader.high_fuses=0xca
-atmegang.menu.cpu.atmega8.bootloader.file=atmega8/ATmegaBOOT-prod-firmware-2009-11-07.hex
-
-atmegang.menu.cpu.atmega8.build.mcu=atmega8
-
-##############################################################
-
-robotControl.name=Arduino Robot Control
-robotControl.vid.0=0x2341
-robotControl.pid.0=0x0038
-robotControl.vid.1=0x2341
-robotControl.pid.1=0x8038
-robotControl.vid.2=0x2A03
-robotControl.pid.2=0x0038
-robotControl.vid.3=0x2A03
-robotControl.pid.3=0x8038
-
-robotControl.vid.0x2A03.warning=Uncertified
-
-robotControl.upload.tool=avrdude
-robotControl.upload.protocol=avr109
-robotControl.upload.maximum_size=28672
-robotControl.upload.maximum_data_size=2560
-robotControl.upload.speed=57600
-robotControl.upload.disable_flushing=true
-robotControl.upload.use_1200bps_touch=true
-robotControl.upload.wait_for_upload_port=true
-
-robotControl.bootloader.tool=avrdude
-robotControl.bootloader.low_fuses=0xff
-robotControl.bootloader.high_fuses=0xd8
-robotControl.bootloader.extended_fuses=0xcb
-robotControl.bootloader.file=caterina-Arduino_Robot/Caterina-Robot-Control.hex
-robotControl.bootloader.unlock_bits=0x3F
-robotControl.bootloader.lock_bits=0x2F
-
-robotControl.build.mcu=atmega32u4
-robotControl.build.f_cpu=16000000L
-robotControl.build.vid=0x2341
-robotControl.build.pid=0x8038
-robotControl.build.usb_product="Robot Control"
-robotControl.build.board=AVR_ROBOT_CONTROL
-robotControl.build.core=arduino
-robotControl.build.variant=robot_control
-robotControl.build.extra_flags={build.usb_flags}
-
-##############################################################
-
-robotMotor.name=Arduino Robot Motor
-robotMotor.vid.0=0x2341
-robotMotor.pid.0=0x0039
-robotMotor.vid.1=0x2341
-robotMotor.pid.1=0x8039
-robotMotor.vid.2=0x2A03
-robotMotor.pid.2=0x0039
-robotMotor.vid.3=0x2A03
-robotMotor.pid.3=0x8039
-
-robotMotor.vid.0x2A03.warning=Uncertified
-
-robotMotor.upload.tool=avrdude
-robotMotor.upload.protocol=avr109
-robotMotor.upload.maximum_size=28672
-robotMotor.upload.maximum_data_size=2560
-robotMotor.upload.speed=57600
-robotMotor.upload.disable_flushing=true
-robotMotor.upload.use_1200bps_touch=true
-robotMotor.upload.wait_for_upload_port=true
-
-robotMotor.bootloader.tool=avrdude
-robotMotor.bootloader.low_fuses=0xff
-robotMotor.bootloader.high_fuses=0xd8
-robotMotor.bootloader.extended_fuses=0xcb
-robotMotor.bootloader.file=caterina-Arduino_Robot/Caterina-Robot-Motor.hex
-robotMotor.bootloader.unlock_bits=0x3F
-robotMotor.bootloader.lock_bits=0x2F
-
-robotMotor.build.mcu=atmega32u4
-robotMotor.build.f_cpu=16000000L
-robotMotor.build.vid=0x2341
-robotMotor.build.pid=0x8039
-robotMotor.build.usb_product="Robot Motor"
-robotMotor.build.board=AVR_ROBOT_MOTOR
-robotMotor.build.core=arduino
-robotMotor.build.variant=robot_motor
-robotMotor.build.extra_flags={build.usb_flags}
-
diff --git a/arduino/boards.txt.arduino106 b/arduino/boards.txt.arduino106
deleted file mode 100644
index bc3402c3..00000000
--- a/arduino/boards.txt.arduino106
+++ /dev/null
@@ -1,580 +0,0 @@
-# See: http://code.google.com/p/arduino/wiki/Platforms
-#############################################################
-evse.name=[USBasp]OpenEVSE
-evse.upload.using=USBasp
-evse.upload.maximum_size=32768
-evse.bootloader.low_fuses=0xff
-evse.bootloader.high_fuses=0xdf
-evse.bootloader.extended_fuses=0x04
-evse.bootloader.unlock_bits=0x3F
-evse.bootloader.lock_bits=0x0F
-evse.build.mcu=atmega328p
-evse.build.f_cpu=16000000L
-evse.build.core=arduino
-evse.build.variant=standard
-
-##############################################################
-
-uno.name=Arduino Uno
-uno.upload.protocol=arduino
-uno.upload.maximum_size=32256
-uno.upload.speed=115200
-uno.bootloader.low_fuses=0xff
-uno.bootloader.high_fuses=0xde
-uno.bootloader.extended_fuses=0x05
-uno.bootloader.path=optiboot
-uno.bootloader.file=optiboot_atmega328.hex
-uno.bootloader.unlock_bits=0x3F
-uno.bootloader.lock_bits=0x0F
-uno.build.mcu=atmega328p
-uno.build.f_cpu=16000000L
-uno.build.core=arduino
-uno.build.variant=standard
-
-##############################################################
-
-atmega328.name=Arduino Duemilanove w/ ATmega328
-
-atmega328.upload.protocol=arduino
-atmega328.upload.maximum_size=30720
-atmega328.upload.speed=57600
-
-atmega328.bootloader.low_fuses=0xFF
-atmega328.bootloader.high_fuses=0xDA
-atmega328.bootloader.extended_fuses=0x05
-atmega328.bootloader.path=atmega
-atmega328.bootloader.file=ATmegaBOOT_168_atmega328.hex
-atmega328.bootloader.unlock_bits=0x3F
-atmega328.bootloader.lock_bits=0x0F
-
-atmega328.build.mcu=atmega328p
-atmega328.build.f_cpu=16000000L
-atmega328.build.core=arduino
-atmega328.build.variant=standard
-
-##############################################################
-
-diecimila.name=Arduino Diecimila or Duemilanove w/ ATmega168
-
-diecimila.upload.protocol=arduino
-diecimila.upload.maximum_size=14336
-diecimila.upload.speed=19200
-
-diecimila.bootloader.low_fuses=0xff
-diecimila.bootloader.high_fuses=0xdd
-diecimila.bootloader.extended_fuses=0x00
-diecimila.bootloader.path=atmega
-diecimila.bootloader.file=ATmegaBOOT_168_diecimila.hex
-diecimila.bootloader.unlock_bits=0x3F
-diecimila.bootloader.lock_bits=0x0F
-
-diecimila.build.mcu=atmega168
-diecimila.build.f_cpu=16000000L
-diecimila.build.core=arduino
-diecimila.build.variant=standard
-
-##############################################################
-
-nano328.name=Arduino Nano w/ ATmega328
-
-nano328.upload.protocol=arduino
-nano328.upload.maximum_size=30720
-nano328.upload.speed=57600
-
-nano328.bootloader.low_fuses=0xFF
-nano328.bootloader.high_fuses=0xDA
-nano328.bootloader.extended_fuses=0x05
-nano328.bootloader.path=atmega
-nano328.bootloader.file=ATmegaBOOT_168_atmega328.hex
-nano328.bootloader.unlock_bits=0x3F
-nano328.bootloader.lock_bits=0x0F
-
-nano328.build.mcu=atmega328p
-nano328.build.f_cpu=16000000L
-nano328.build.core=arduino
-nano328.build.variant=eightanaloginputs
-
-##############################################################
-
-nano.name=Arduino Nano w/ ATmega168
-
-nano.upload.protocol=arduino
-nano.upload.maximum_size=14336
-nano.upload.speed=19200
-
-nano.bootloader.low_fuses=0xff
-nano.bootloader.high_fuses=0xdd
-nano.bootloader.extended_fuses=0x00
-nano.bootloader.path=atmega
-nano.bootloader.file=ATmegaBOOT_168_diecimila.hex
-nano.bootloader.unlock_bits=0x3F
-nano.bootloader.lock_bits=0x0F
-
-nano.build.mcu=atmega168
-nano.build.f_cpu=16000000L
-nano.build.core=arduino
-nano.build.variant=eightanaloginputs
-
-##############################################################
-
-mega2560.name=Arduino Mega 2560 or Mega ADK
-
-mega2560.upload.protocol=wiring
-mega2560.upload.maximum_size=258048
-mega2560.upload.speed=115200
-
-mega2560.bootloader.low_fuses=0xFF
-mega2560.bootloader.high_fuses=0xD8
-mega2560.bootloader.extended_fuses=0xFD
-mega2560.bootloader.path=stk500v2
-mega2560.bootloader.file=stk500boot_v2_mega2560.hex
-mega2560.bootloader.unlock_bits=0x3F
-mega2560.bootloader.lock_bits=0x0F
-
-mega2560.build.mcu=atmega2560
-mega2560.build.f_cpu=16000000L
-mega2560.build.core=arduino
-mega2560.build.variant=mega
-
-##############################################################
-
-mega.name=Arduino Mega (ATmega1280)
-
-mega.upload.protocol=arduino
-mega.upload.maximum_size=126976
-mega.upload.speed=57600
-
-mega.bootloader.low_fuses=0xFF
-mega.bootloader.high_fuses=0xDA
-mega.bootloader.extended_fuses=0xF5
-mega.bootloader.path=atmega
-mega.bootloader.file=ATmegaBOOT_168_atmega1280.hex
-mega.bootloader.unlock_bits=0x3F
-mega.bootloader.lock_bits=0x0F
-
-mega.build.mcu=atmega1280
-mega.build.f_cpu=16000000L
-mega.build.core=arduino
-mega.build.variant=mega
-
-##############################################################
-
-leonardo.name=Arduino Leonardo
-leonardo.upload.protocol=avr109
-leonardo.upload.maximum_size=28672
-leonardo.upload.speed=57600
-leonardo.upload.disable_flushing=true
-leonardo.bootloader.low_fuses=0xff
-leonardo.bootloader.high_fuses=0xd8
-leonardo.bootloader.extended_fuses=0xcb
-leonardo.bootloader.path=caterina
-leonardo.bootloader.file=Caterina-Leonardo.hex
-leonardo.bootloader.unlock_bits=0x3F
-leonardo.bootloader.lock_bits=0x2F
-leonardo.build.mcu=atmega32u4
-leonardo.build.f_cpu=16000000L
-leonardo.build.vid=0x2341
-leonardo.build.pid=0x8036
-leonardo.build.core=arduino
-leonardo.build.variant=leonardo
-
-##############################################################
-
-esplora.name=Arduino Esplora
-esplora.upload.protocol=avr109
-esplora.upload.maximum_size=28672
-esplora.upload.speed=57600
-esplora.upload.disable_flushing=true
-esplora.bootloader.low_fuses=0xff
-esplora.bootloader.high_fuses=0xd8
-esplora.bootloader.extended_fuses=0xcb
-esplora.bootloader.path=caterina
-esplora.bootloader.file=Caterina-Esplora.hex
-esplora.bootloader.unlock_bits=0x3F
-esplora.bootloader.lock_bits=0x2F
-esplora.build.mcu=atmega32u4
-esplora.build.f_cpu=16000000L
-esplora.build.vid=0x2341
-esplora.build.pid=0x803C
-esplora.build.core=arduino
-esplora.build.variant=leonardo
-
-##############################################################
-
-micro.name=Arduino Micro
-micro.upload.protocol=avr109
-micro.upload.maximum_size=28672
-micro.upload.speed=57600
-micro.upload.disable_flushing=true
-micro.bootloader.low_fuses=0xff
-micro.bootloader.high_fuses=0xd8
-micro.bootloader.extended_fuses=0xcb
-micro.bootloader.path=caterina
-micro.bootloader.file=Caterina-Micro.hex
-micro.bootloader.unlock_bits=0x3F
-micro.bootloader.lock_bits=0x2F
-micro.build.mcu=atmega32u4
-micro.build.f_cpu=16000000L
-micro.build.vid=0x2341
-micro.build.pid=0x8037
-micro.build.core=arduino
-micro.build.variant=micro
-
-##############################################################
-
-mini328.name=Arduino Mini w/ ATmega328
-
-mini328.upload.protocol=arduino
-mini328.upload.maximum_size=28672
-mini328.upload.speed=115200
-
-mini328.bootloader.low_fuses=0xff
-mini328.bootloader.high_fuses=0xd8
-mini328.bootloader.extended_fuses=0x05
-mini328.bootloader.path=optiboot
-mini328.bootloader.file=optiboot_atmega328-Mini.hex
-mini328.bootloader.unlock_bits=0x3F
-mini328.bootloader.lock_bits=0x0F
-
-mini328.build.mcu=atmega328p
-mini328.build.f_cpu=16000000L
-mini328.build.core=arduino
-mini328.build.variant=eightanaloginputs
-
-##############################################################
-
-mini.name=Arduino Mini w/ ATmega168
-
-mini.upload.protocol=arduino
-mini.upload.maximum_size=14336
-mini.upload.speed=19200
-
-mini.bootloader.low_fuses=0xff
-mini.bootloader.high_fuses=0xdd
-mini.bootloader.extended_fuses=0x00
-mini.bootloader.path=atmega
-mini.bootloader.file=ATmegaBOOT_168_ng.hex
-mini.bootloader.unlock_bits=0x3F
-mini.bootloader.lock_bits=0x0F
-
-mini.build.mcu=atmega168
-mini.build.f_cpu=16000000L
-mini.build.core=arduino
-mini.build.variant=eightanaloginputs
-
-##############################################################
-
-ethernet.name=Arduino Ethernet
-
-ethernet.upload.protocol=arduino
-ethernet.upload.maximum_size=32256
-ethernet.upload.speed=115200
-
-ethernet.bootloader.low_fuses=0xff
-ethernet.bootloader.high_fuses=0xde
-ethernet.bootloader.extended_fuses=0x05
-ethernet.bootloader.path=optiboot
-ethernet.bootloader.file=optiboot_atmega328.hex
-ethernet.bootloader.unlock_bits=0x3F
-ethernet.bootloader.lock_bits=0x0F
-
-ethernet.build.variant=ethernet
-ethernet.build.mcu=atmega328p
-ethernet.build.f_cpu=16000000L
-ethernet.build.core=arduino
-
-##############################################################
-
-fio.name=Arduino Fio
-
-fio.upload.protocol=arduino
-fio.upload.maximum_size=30720
-fio.upload.speed=57600
-
-fio.bootloader.low_fuses=0xFF
-fio.bootloader.high_fuses=0xDA
-fio.bootloader.extended_fuses=0x05
-fio.bootloader.path=arduino:atmega
-fio.bootloader.file=ATmegaBOOT_168_atmega328_pro_8MHz.hex
-fio.bootloader.unlock_bits=0x3F
-fio.bootloader.lock_bits=0x0F
-
-fio.build.mcu=atmega328p
-fio.build.f_cpu=8000000L
-fio.build.core=arduino
-fio.build.variant=eightanaloginputs
-
-##############################################################
-
-bt328.name=Arduino BT w/ ATmega328
-
-bt328.upload.protocol=arduino
-bt328.upload.maximum_size=28672
-bt328.upload.speed=19200
-bt328.upload.disable_flushing=true
-
-bt328.bootloader.low_fuses=0xff
-bt328.bootloader.high_fuses=0xd8
-bt328.bootloader.extended_fuses=0x05
-bt328.bootloader.path=bt
-bt328.bootloader.file=ATmegaBOOT_168_atmega328_bt.hex
-bt328.bootloader.unlock_bits=0x3F
-bt328.bootloader.lock_bits=0x0F
-
-bt328.build.mcu=atmega328p
-bt328.build.f_cpu=16000000L
-bt328.build.core=arduino
-bt328.build.variant=eightanaloginputs
-
-##############################################################
-
-bt.name=Arduino BT w/ ATmega168
-
-bt.upload.protocol=arduino
-bt.upload.maximum_size=14336
-bt.upload.speed=19200
-bt.upload.disable_flushing=true
-
-bt.bootloader.low_fuses=0xff
-bt.bootloader.high_fuses=0xdd
-bt.bootloader.extended_fuses=0x00
-bt.bootloader.path=bt
-bt.bootloader.file=ATmegaBOOT_168.hex
-bt.bootloader.unlock_bits=0x3F
-bt.bootloader.lock_bits=0x0F
-
-bt.build.mcu=atmega168
-bt.build.f_cpu=16000000L
-bt.build.core=arduino
-bt.build.variant=eightanaloginputs
-
-##############################################################
-
-LilyPadUSB.name=LilyPad Arduino USB
-LilyPadUSB.upload.protocol=avr109
-LilyPadUSB.upload.maximum_size=28672
-LilyPadUSB.upload.speed=57600
-LilyPadUSB.upload.disable_flushing=true
-LilyPadUSB.bootloader.low_fuses=0xff
-LilyPadUSB.bootloader.high_fuses=0xd8
-LilyPadUSB.bootloader.extended_fuses=0xce
-LilyPadUSB.bootloader.path=caterina-LilyPadUSB
-LilyPadUSB.bootloader.file=Caterina-LilyPadUSB.hex
-LilyPadUSB.bootloader.unlock_bits=0x3F
-LilyPadUSB.bootloader.lock_bits=0x2F
-LilyPadUSB.build.mcu=atmega32u4
-LilyPadUSB.build.f_cpu=8000000L
-LilyPadUSB.build.vid=0x1B4F
-LilyPadUSB.build.pid=0x9208
-LilyPadUSB.build.core=arduino
-LilyPadUSB.build.variant=leonardo
-
-##############################################################
-
-lilypad328.name=LilyPad Arduino w/ ATmega328
-
-lilypad328.upload.protocol=arduino
-lilypad328.upload.maximum_size=30720
-lilypad328.upload.speed=57600
-
-lilypad328.bootloader.low_fuses=0xFF
-lilypad328.bootloader.high_fuses=0xDA
-lilypad328.bootloader.extended_fuses=0x05
-lilypad328.bootloader.path=atmega
-lilypad328.bootloader.file=ATmegaBOOT_168_atmega328_pro_8MHz.hex
-lilypad328.bootloader.unlock_bits=0x3F
-lilypad328.bootloader.lock_bits=0x0F
-
-lilypad328.build.mcu=atmega328p
-lilypad328.build.f_cpu=8000000L
-lilypad328.build.core=arduino
-lilypad328.build.variant=standard
-
-##############################################################
-
-lilypad.name=LilyPad Arduino w/ ATmega168
-
-lilypad.upload.protocol=arduino
-lilypad.upload.maximum_size=14336
-lilypad.upload.speed=19200
-
-lilypad.bootloader.low_fuses=0xe2
-lilypad.bootloader.high_fuses=0xdd
-lilypad.bootloader.extended_fuses=0x00
-lilypad.bootloader.path=lilypad
-lilypad.bootloader.file=LilyPadBOOT_168.hex
-lilypad.bootloader.unlock_bits=0x3F
-lilypad.bootloader.lock_bits=0x0F
-
-lilypad.build.mcu=atmega168
-lilypad.build.f_cpu=8000000L
-lilypad.build.core=arduino
-lilypad.build.variant=standard
-
-##############################################################
-
-pro5v328.name=Arduino Pro or Pro Mini (5V, 16 MHz) w/ ATmega328
-
-pro5v328.upload.protocol=arduino
-pro5v328.upload.maximum_size=30720
-pro5v328.upload.speed=57600
-
-pro5v328.bootloader.low_fuses=0xFF
-pro5v328.bootloader.high_fuses=0xDA
-pro5v328.bootloader.extended_fuses=0x05
-pro5v328.bootloader.path=atmega
-pro5v328.bootloader.file=ATmegaBOOT_168_atmega328.hex
-pro5v328.bootloader.unlock_bits=0x3F
-pro5v328.bootloader.lock_bits=0x0F
-
-pro5v328.build.mcu=atmega328p
-pro5v328.build.f_cpu=16000000L
-pro5v328.build.core=arduino
-pro5v328.build.variant=standard
-
-##############################################################
-
-pro5v.name=Arduino Pro or Pro Mini (5V, 16 MHz) w/ ATmega168
-
-pro5v.upload.protocol=arduino
-pro5v.upload.maximum_size=14336
-pro5v.upload.speed=19200
-
-pro5v.bootloader.low_fuses=0xff
-pro5v.bootloader.high_fuses=0xdd
-pro5v.bootloader.extended_fuses=0x00
-pro5v.bootloader.path=atmega
-pro5v.bootloader.file=ATmegaBOOT_168_diecimila.hex
-pro5v.bootloader.unlock_bits=0x3F
-pro5v.bootloader.lock_bits=0x0F
-
-pro5v.build.mcu=atmega168
-pro5v.build.f_cpu=16000000L
-pro5v.build.core=arduino
-pro5v.build.variant=standard
-
-##############################################################
-
-pro328.name=Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega328
-
-pro328.upload.protocol=arduino
-pro328.upload.maximum_size=30720
-pro328.upload.speed=57600
-
-pro328.bootloader.low_fuses=0xFF
-pro328.bootloader.high_fuses=0xDA
-pro328.bootloader.extended_fuses=0x05
-pro328.bootloader.path=atmega
-pro328.bootloader.file=ATmegaBOOT_168_atmega328_pro_8MHz.hex
-pro328.bootloader.unlock_bits=0x3F
-pro328.bootloader.lock_bits=0x0F
-
-pro328.build.mcu=atmega328p
-pro328.build.f_cpu=8000000L
-pro328.build.core=arduino
-pro328.build.variant=standard
-
-##############################################################
-
-pro.name=Arduino Pro or Pro Mini (3.3V, 8 MHz) w/ ATmega168
-
-pro.upload.protocol=arduino
-pro.upload.maximum_size=14336
-pro.upload.speed=19200
-
-pro.bootloader.low_fuses=0xc6
-pro.bootloader.high_fuses=0xdd
-pro.bootloader.extended_fuses=0x00
-pro.bootloader.path=atmega
-pro.bootloader.file=ATmegaBOOT_168_pro_8MHz.hex
-pro.bootloader.unlock_bits=0x3F
-pro.bootloader.lock_bits=0x0F
-
-pro.build.mcu=atmega168
-pro.build.f_cpu=8000000L
-pro.build.core=arduino
-pro.build.variant=standard
-
-##############################################################
-
-atmega168.name=Arduino NG or older w/ ATmega168
-
-atmega168.upload.protocol=arduino
-atmega168.upload.maximum_size=14336
-atmega168.upload.speed=19200
-
-atmega168.bootloader.low_fuses=0xff
-atmega168.bootloader.high_fuses=0xdd
-atmega168.bootloader.extended_fuses=0x00
-atmega168.bootloader.path=atmega
-atmega168.bootloader.file=ATmegaBOOT_168_ng.hex
-atmega168.bootloader.unlock_bits=0x3F
-atmega168.bootloader.lock_bits=0x0F
-
-atmega168.build.mcu=atmega168
-atmega168.build.f_cpu=16000000L
-atmega168.build.core=arduino
-atmega168.build.variant=standard
-
-##############################################################
-
-atmega8.name=Arduino NG or older w/ ATmega8
-
-atmega8.upload.protocol=arduino
-atmega8.upload.maximum_size=7168
-atmega8.upload.speed=19200
-
-atmega8.bootloader.low_fuses=0xdf
-atmega8.bootloader.high_fuses=0xca
-atmega8.bootloader.path=atmega8
-atmega8.bootloader.file=ATmegaBOOT-prod-firmware-2009-11-07.hex
-atmega8.bootloader.unlock_bits=0x3F
-atmega8.bootloader.lock_bits=0x0F
-
-atmega8.build.mcu=atmega8
-atmega8.build.f_cpu=16000000L
-atmega8.build.core=arduino
-atmega8.build.variant=standard
-
-##############################################################
-
-robotControl.name=Arduino Robot Control
-robotControl.upload.protocol=avr109
-robotControl.upload.maximum_size=28672
-robotControl.upload.speed=57600
-robotControl.upload.disable_flushing=true
-robotControl.bootloader.low_fuses=0xff
-robotControl.bootloader.high_fuses=0xd8
-robotControl.bootloader.extended_fuses=0xcb
-robotControl.bootloader.path=caterina-Arduino_Robot
-robotControl.bootloader.file=Caterina-Robot-Control.hex
-robotControl.bootloader.unlock_bits=0x3F
-robotControl.bootloader.lock_bits=0x2F
-robotControl.build.mcu=atmega32u4
-robotControl.build.f_cpu=16000000L
-robotControl.build.vid=0x2341
-robotControl.build.pid=0x8038
-robotControl.build.core=robot
-robotControl.build.variant=robot_control
-
-##############################################################
-
-robotMotor.name=Arduino Robot Motor
-robotMotor.upload.protocol=avr109
-robotMotor.upload.maximum_size=28672
-robotMotor.upload.speed=57600
-robotMotor.upload.disable_flushing=true
-robotMotor.bootloader.low_fuses=0xff
-robotMotor.bootloader.high_fuses=0xd8
-robotMotor.bootloader.extended_fuses=0xcb
-robotMotor.bootloader.path=caterina-Arduino_Robot
-robotMotor.bootloader.file=Caterina-Robot-Motor.hex
-robotMotor.bootloader.unlock_bits=0x3F
-robotMotor.bootloader.lock_bits=0x2F
-robotMotor.build.mcu=atmega32u4
-robotMotor.build.f_cpu=16000000L
-robotMotor.build.vid=0x2341
-robotMotor.build.pid=0x8039
-robotMotor.build.core=robot
-robotMotor.build.variant=robot_motor
-
diff --git a/firmware/open_evse/open_evse.ino b/firmware/open_evse/open_evse.ino
deleted file mode 100644
index 1966b9fb..00000000
--- a/firmware/open_evse/open_evse.ino
+++ /dev/null
@@ -1 +0,0 @@
-// placeholder for Arduino IDE builds - see main.cpp for code
diff --git a/firmware/open_evse/open_evse.ino.with_bootloader.standard.hex b/firmware/open_evse/open_evse.ino.with_bootloader.standard.hex
deleted file mode 100644
index 6de5eafb..00000000
--- a/firmware/open_evse/open_evse.ino.with_bootloader.standard.hex
+++ /dev/null
@@ -1,2004 +0,0 @@
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-    <ClInclude Include="rapi_proc.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-    <ClInclude Include="RTClib.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-    <ClInclude Include="serialcli.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-    <ClInclude Include="strings.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-    <ClInclude Include="Time.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-    <ClInclude Include="twi.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-    <ClInclude Include="Wire.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-    <ClInclude Include="EnergyMeter.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-  </ItemGroup>
-  <ItemGroup>
-    <ClCompile Include="Adafruit_TMP007.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="AutoCurrentCapacityController.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="avrstuff.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="Gfi.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="I2CIO.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="J1772EvseController.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="J1772Pilot.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="LCD.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="LiquidCrystal_I2C.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="LiquidTWI2.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="MCP9808.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="MennekesLock.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="rapi_proc.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="RTClib.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="serialcli.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="strings.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="Time.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="twi.c">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="Wire.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="EnergyMeter.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-  </ItemGroup>
-</Project>
\ No newline at end of file

From 360ba1751373e89a9c86a3db47cbffd1658ba113 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Tue, 3 Feb 2026 17:10:06 -0800
Subject: [PATCH 02/59] add $FC - reset fault counters+tot energy

---
 firmware/open_evse/EnergyMeter.cpp       | 6 ++++++
 firmware/open_evse/EnergyMeter.h         | 1 +
 firmware/open_evse/J1772EvseController.h | 8 ++++++++
 firmware/open_evse/rapi_proc.cpp         | 5 +++++
 firmware/open_evse/rapi_proc.h           | 1 +
 5 files changed, 21 insertions(+)

diff --git a/firmware/open_evse/EnergyMeter.cpp b/firmware/open_evse/EnergyMeter.cpp
index 7f7e4b68..9c6ec2b6 100644
--- a/firmware/open_evse/EnergyMeter.cpp
+++ b/firmware/open_evse/EnergyMeter.cpp
@@ -127,5 +127,11 @@ void EnergyMeter::SaveTotkWh()
   eeprom_write_dword((uint32_t*)EOFS_KWH_ACCUMULATED,m_wattHoursTot);
 }
 
+
+void EnergyMeter::ResetTotkWh() {
+  eeprom_write_dword((uint32_t*)EOFS_KWH_ACCUMULATED,0);
+  m_wattHoursTot = 0;
+}
+
 #endif // KWH_RECORDING
 
diff --git a/firmware/open_evse/EnergyMeter.h b/firmware/open_evse/EnergyMeter.h
index 7db9e4fd..8c4308bc 100644
--- a/firmware/open_evse/EnergyMeter.h
+++ b/firmware/open_evse/EnergyMeter.h
@@ -38,6 +38,7 @@ class EnergyMeter {
   void SetTotkWh(uint32_t whtot) { m_wattHoursTot = whtot; }
   uint32_t GetTotkWh() { return m_wattHoursTot; }
   uint32_t GetSessionWs() { return m_wattSeconds; }
+  void ResetTotkWh();
 };
 
 
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index a35cb354..e9eaa684 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -591,7 +591,15 @@ int GetHearbeatTrigger();
   void LockMennekes() { m_MennekesLock.Lock(1); }
   void UnlockMennekes() { m_MennekesLock.Unlock(1); }
 #endif // MENNEKES_LOCK
+  void ResetFaultCounters() {
+    m_GfiTripCnt = 0xff;
+    m_NoGndTripCnt = 0xff;
+    m_StuckRelayTripCnt = 0xff;
 
+    eeprom_write_byte((uint8_t*)EOFS_GFI_TRIP_CNT,0xff);
+    eeprom_write_byte((uint8_t*)EOFS_NOGND_TRIP_CNT,0xff);
+    eeprom_write_byte((uint8_t*)EOFS_STUCK_RELAY_TRIP_CNT,0xff);
+  }
 };
 
 #ifdef FT_ENDURANCE
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index 3b6633b5..cd3b0a33 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -290,6 +290,11 @@ int EvseRapiProcessor::processCmd()
       }
       break;
 #endif // LCD16X2
+    case 'C': // reset fault counters + total energy
+      g_EvseController.ResetFaultCounters();
+      g_EnergyMeter.ResetTotkWh();
+      rc = 0;
+      break;
     case 'D': // disable EVSE
       g_EvseController.Disable();
       rc = 0;
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index 1aa77988..06ff0d87 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -116,6 +116,7 @@ FB color - set LCD backlight color
  WHITE 7
 
  $FB 7*03 - set backlight to white
+FC - reset fault counters and total energy
 FD - disable EVSE
  $FD*AE
 FE - enable EVSE

From 047a756ff0875a54d0a6f51a3694655e7229fa40 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Tue, 3 Feb 2026 17:24:03 -0800
Subject: [PATCH 03/59] fix compiler warnings

---
 firmware/open_evse/J1772EvseController.cpp |  2 +-
 firmware/open_evse/LiquidTWI2.cpp          | 16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index cc971c0c..930b604f 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -720,7 +720,7 @@ uint8_t J1772EVSEController::doPost()
 #else //!OPENEVSE_2
     
     delay(150); // delay reading for stable pilot before reading
-    int reading = adcPilot.read(); //read pilot
+    uint16_t reading = adcPilot.read(); //read pilot
 #ifdef SERDBG
     if (SerDbgEnabled()) {
       Serial.print("Pilot: ");Serial.println((int)reading);
diff --git a/firmware/open_evse/LiquidTWI2.cpp b/firmware/open_evse/LiquidTWI2.cpp
index d0e547e1..ba51535e 100644
--- a/firmware/open_evse/LiquidTWI2.cpp
+++ b/firmware/open_evse/LiquidTWI2.cpp
@@ -689,15 +689,15 @@ void LiquidTWI2::buzz(long duration, uint16_t freq) {
   while (cycles-- > 0)
   {
     ontime = micros();
-        Wire.beginTransmission(MCP23017_ADDRESS | _i2cAddr);
-        wiresend(MCP23017_GPIOA);
-        wiresend(currentRegister |= M17_BIT_BZ);
-        while(Wire.endTransmission());
+    Wire.beginTransmission(MCP23017_ADDRESS | _i2cAddr);
+    wiresend(MCP23017_GPIOA);
+    wiresend(currentRegister |= M17_BIT_BZ);
+    while(Wire.endTransmission());
     while((long)(ontime + (cycletime/2) - micros()) > 0);
-        Wire.beginTransmission(MCP23017_ADDRESS | _i2cAddr);
-        wiresend(MCP23017_GPIOA);
-        wiresend(currentRegister &= ~M17_BIT_BZ);
-        while(Wire.endTransmission());
+    Wire.beginTransmission(MCP23017_ADDRESS | _i2cAddr);
+    wiresend(MCP23017_GPIOA);
+    wiresend(currentRegister &= ~M17_BIT_BZ);
+    while(Wire.endTransmission());
     while((long)(ontime + cycletime - micros()) > 0);
    }
 }

From 521edf63f47dec4913fb96664738fa86935a9d00 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Tue, 3 Feb 2026 17:24:56 -0800
Subject: [PATCH 04/59] don't enable HEARTBEAT_SUPERVISION and RTC in header

---
 firmware/open_evse/main.cpp    | 2 ++
 firmware/open_evse/open_evse.h | 8 ++++++--
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/firmware/open_evse/main.cpp b/firmware/open_evse/main.cpp
index d138ac43..6eead8d2 100644
--- a/firmware/open_evse/main.cpp
+++ b/firmware/open_evse/main.cpp
@@ -126,7 +126,9 @@ Menu *g_SettingsMenuList[] = {
 Menu *g_SetupMenuList[] = {
 #ifdef NOSETUP_MENU
   &g_MaxCurrentMenu,
+#ifdef RTC
   &g_RTCMenu,
+#endif
 #else // !NOSETUP_MENU
 #ifdef DELAYTIMER_MENU
   &g_RTCMenu,
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index ffecb5ba..e73e194a 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -193,7 +193,7 @@ extern AutoCurrentCapacityController g_ACCController;
 
 #define TEMPERATURE_MONITORING  // Temperature monitoring support
 
-#define HEARTBEAT_SUPERVISION // Heartbeat Supervision support
+//#define HEARTBEAT_SUPERVISION // Heartbeat Supervision support
 
 #ifdef AMMETER
 
@@ -278,7 +278,7 @@ extern AutoCurrentCapacityController g_ACCController;
 
 // Option for RTC and DelayTime
 // REQUIRES HARDWARE RTC: DS1307 or DS3231 connected via I2C
-#define RTC // enable RTC & timer functions
+//#define RTC // enable RTC & timer functions
 
 #ifdef RTC
 // Option for Delay Timer - GoldServe
@@ -349,6 +349,10 @@ extern AutoCurrentCapacityController g_ACCController;
 // PWM parameters written to/loaded from EEPROM
 #define RELAY_HOLD_DELAY_TUNING // enable Z0
 
+// OEV6 w/ CGMI - when power is loss, temporarily triggers NO GROUND fault
+// delay recording of NO GROUND fault to avoid recording this spurious fault
+#define NO_GND_RECORD_DELAY 2000
+
 //-- end features
 
 #ifndef DEFAULT_LCD_BKL_TYPE

From 51e21fa12c810fd2f3f87a05b84c8df84f7d6b79 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Tue, 3 Feb 2026 17:34:34 -0800
Subject: [PATCH 05/59] bug fix fault counter ovf check

---
 firmware/open_evse/J1772EvseController.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 930b604f..ce2d1d5c 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -1362,7 +1362,7 @@ void J1772EVSEController::Update(uint8_t forcetransition)
           m_EvseState = EVSE_STATE_NO_GROUND;
           
           chargingOff(); // open the relay
-          if ((prevevsestate != EVSE_STATE_NO_GROUND) && (((uint8_t)(m_NoGndTripCnt+1)) < 254)) {
+          if ((prevevsestate != EVSE_STATE_NO_GROUND) && (((uint8_t)(m_NoGndTripCnt+1)) < 253)) {
             m_NoGndTripCnt++;
             eeprom_write_byte((uint8_t*)EOFS_NOGND_TRIP_CNT,m_NoGndTripCnt);
           }
@@ -1414,7 +1414,7 @@ void J1772EVSEController::Update(uint8_t forcetransition)
                  ((curms - m_StuckRelayStartTimeMS) > STUCK_RELAY_DELAY) ) ||  // start delay de-bounce
                (prevevsestate == EVSE_STATE_STUCK_RELAY) ) { // already in error state
             // stuck relay
-            if ((prevevsestate != EVSE_STATE_STUCK_RELAY) && (((uint8_t)(m_StuckRelayTripCnt+1)) < 254)) {
+            if ((prevevsestate != EVSE_STATE_STUCK_RELAY) && (((uint8_t)(m_StuckRelayTripCnt+1)) < 253)) {
               m_StuckRelayTripCnt++;
               eeprom_write_byte((uint8_t*)EOFS_STUCK_RELAY_TRIP_CNT,m_StuckRelayTripCnt);
             }   
@@ -1435,7 +1435,7 @@ void J1772EVSEController::Update(uint8_t forcetransition)
     m_EvseState = EVSE_STATE_GFCI_FAULT;
 
     if (prevevsestate != EVSE_STATE_GFCI_FAULT) { // state transition
-      if (((uint8_t)(m_GfiTripCnt+1)) < 254) {
+      if (((uint8_t)(m_GfiTripCnt+1)) < 253) {
 	m_GfiTripCnt++;
 	eeprom_write_byte((uint8_t*)EOFS_GFI_TRIP_CNT,m_GfiTripCnt);
       }

From 5de03f246d67a5119c3bfccc30cbe8ed821e0b1e Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Tue, 3 Feb 2026 17:37:09 -0800
Subject: [PATCH 06/59] update flash.bat

---
 firmware/open_evse/flash.bat | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/firmware/open_evse/flash.bat b/firmware/open_evse/flash.bat
index 584b2315..26bb4c23 100644
--- a/firmware/open_evse/flash.bat
+++ b/firmware/open_evse/flash.bat
@@ -1,3 +1,2 @@
-avrdude -c USBasp -p m328p -U lfuse:w:0xFF:m -U hfuse:w:0xDF:m -U efuse:w:0x05:m
-avrdude -c USBasp -p m328p -U flash:w:open_evse-384.hex
-pause
+rem avrdude -c USBasp -p m328p -B16 -U lfuse:w:0xFF:m -U hfuse:w:0xDF:m -U efuse:w:0xFD:m
+avrdude -c USBasp -p m328p -B0.5 -U flash:w:%1

From 6c74856b287cd9e68e175fd14743e927754bfd70 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Tue, 3 Feb 2026 17:45:19 -0800
Subject: [PATCH 07/59] don't enable RGBLCD by default

---
 firmware/open_evse/open_evse.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index e73e194a..3413d291 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -230,7 +230,7 @@ extern AutoCurrentCapacityController g_ACCController;
 #endif //AMMETER
 
 //Adafruit RGBLCD (MCP23017) - can have RGB or monochrome backlight
-#define RGBLCD
+//#define RGBLCD
 
 //select default LCD backlight mode. can be overridden w/CLI/RAPI
 #define BKL_TYPE_MONO 0

From b542727613affb7917dc634335e8956da6e0ba7a Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 5 Feb 2026 17:31:29 -0800
Subject: [PATCH 08/59] remove obsolete WProgram.h

---
 firmware/open_evse/I2CIO.cpp   | 5 +----
 firmware/open_evse/LCD.cpp     | 4 ----
 firmware/open_evse/open_evse.h | 4 ----
 3 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/firmware/open_evse/I2CIO.cpp b/firmware/open_evse/I2CIO.cpp
index 03e583e5..7e8755b0 100644
--- a/firmware/open_evse/I2CIO.cpp
+++ b/firmware/open_evse/I2CIO.cpp
@@ -24,11 +24,8 @@
 //
 // @author F. Malpartida - fmalpartida@gmail.com
 // ---------------------------------------------------------------------------
-#if (ARDUINO <  100)
-#include <WProgram.h>
-#else
+
 #include <Arduino.h>
-#endif
 
 #include <inttypes.h>
 
diff --git a/firmware/open_evse/LCD.cpp b/firmware/open_evse/LCD.cpp
index 0c86d972..120e8129 100644
--- a/firmware/open_evse/LCD.cpp
+++ b/firmware/open_evse/LCD.cpp
@@ -36,11 +36,7 @@
 #include <string.h>
 #include <inttypes.h>
 
-#if (ARDUINO <  100)
-#include <WProgram.h>
-#else
 #include <Arduino.h>
-#endif
 #include "./LCD.h"
 
 // CLASS CONSTRUCTORS
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index 3413d291..1b54a9fd 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -39,11 +39,7 @@
 #include "avrstuff.h"
 #include "i2caddr.h"
 
-#if defined(ARDUINO) && (ARDUINO >= 100)
 #include "Arduino.h"
-#else
-#include "WProgram.h" // shouldn't need this but arduino sometimes messes up and puts inside an #ifdef
-#endif // ARDUINO
 
 #define setBits(flags,bits) (flags |= (bits))
 #define clrBits(flags,bits) (flags &= ~(bits))

From a2c4946802fbff34fd339936c49637a37f1edc76 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 5 Feb 2026 17:32:51 -0800
Subject: [PATCH 09/59] prepare for different MCU variants

---
 firmware/open_evse/srec_cat.exe               | Bin 1440270 -> 0 bytes
 .../{open_evse => variants/m328p}/Wire.cpp    |   0
 firmware/{open_evse => variants/m328p}/Wire.h |   0
 .../m328p}/avrstuff.cpp                       |   0
 .../{open_evse => variants/m328p}/avrstuff.h  |   0
 firmware/variants/m328p/platformio.ini        |  78 ++++++++++++++++++
 firmware/{open_evse => variants/m328p}/twi.c  |   0
 firmware/{open_evse => variants/m328p}/twi.h  |   0
 platformio.ini                                |  72 ++--------------
 9 files changed, 86 insertions(+), 64 deletions(-)
 delete mode 100644 firmware/open_evse/srec_cat.exe
 rename firmware/{open_evse => variants/m328p}/Wire.cpp (100%)
 rename firmware/{open_evse => variants/m328p}/Wire.h (100%)
 rename firmware/{open_evse => variants/m328p}/avrstuff.cpp (100%)
 rename firmware/{open_evse => variants/m328p}/avrstuff.h (100%)
 create mode 100644 firmware/variants/m328p/platformio.ini
 rename firmware/{open_evse => variants/m328p}/twi.c (100%)
 rename firmware/{open_evse => variants/m328p}/twi.h (100%)

diff --git a/firmware/open_evse/srec_cat.exe b/firmware/open_evse/srec_cat.exe
deleted file mode 100644
index 39c7b3c87df617de117d5ff0317c900e1836a513..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/firmware/open_evse/Wire.cpp b/firmware/variants/m328p/Wire.cpp
similarity index 100%
rename from firmware/open_evse/Wire.cpp
rename to firmware/variants/m328p/Wire.cpp
diff --git a/firmware/open_evse/Wire.h b/firmware/variants/m328p/Wire.h
similarity index 100%
rename from firmware/open_evse/Wire.h
rename to firmware/variants/m328p/Wire.h
diff --git a/firmware/open_evse/avrstuff.cpp b/firmware/variants/m328p/avrstuff.cpp
similarity index 100%
rename from firmware/open_evse/avrstuff.cpp
rename to firmware/variants/m328p/avrstuff.cpp
diff --git a/firmware/open_evse/avrstuff.h b/firmware/variants/m328p/avrstuff.h
similarity index 100%
rename from firmware/open_evse/avrstuff.h
rename to firmware/variants/m328p/avrstuff.h
diff --git a/firmware/variants/m328p/platformio.ini b/firmware/variants/m328p/platformio.ini
new file mode 100644
index 00000000..3335deda
--- /dev/null
+++ b/firmware/variants/m328p/platformio.ini
@@ -0,0 +1,78 @@
+
+[m328p]
+upload_protocol = usbasp
+upload_flags = "-e -B0.5"
+build_src_flags =
+  -I firmware/variants/m328p
+  ${common.us_build_flags}
+build_src_filter =
+  ${common.build_src_filter}
+  +<../variants/m328p>
+
+[env:openevse_latest]
+platform = atmelavr
+board = openevse
+framework = arduino
+lib_deps = ${common.lib_deps}
+upload_protocol = ${m328p.upload_protocol}
+upload_flags = ${m328p.upload_flags}
+build_src_flags=
+  ${common.us_build_flags}
+  ${m328p.build_src_flags}
+  -D 'VERSION="${common.version}"'
+
+[env:openevse]
+platform = atmelavr@3.4.0
+board = openevse
+framework = arduino
+lib_deps = ${common.lib_deps}
+upload_protocol = ${m328p.upload_protocol}
+upload_flags = ${m328p.upload_flags}
+build_src_filter =
+  ${m328p.build_src_filter}
+build_src_flags=
+  ${m328p.build_src_flags}
+  -D 'VERSION="${common.version}"'
+
+# v6 CGMI OpenEVSE
+[env:openevse_v6]
+extends = env:openevse
+build_src_flags=
+  ${m328p.build_src_flags}
+  -D ENABLE_CGMI
+  -D NO_AUTOSVCLEVEL
+  -D DEFAULT_SERVICE_LEVEL=2
+  #-D BTN_MENU
+  #-D RTC
+  -D 'VERSION="${common.version}.CGMI"'
+
+  # EU OpenEVSE
+[env:openevse_eu]
+extends = env:openevse
+build_src_flags=
+  ${m328p.build_src_flags}
+  ${common.eu_build_flags}
+  -D MV_FOR_L2=230000L
+  -D 'VERSION="${common.version}.EU"'
+
+# Non-tethered T2 EmonEVSE single-phase
+[env:emonevse]
+extends = env:openevse
+build_src_flags=
+  ${m328p.build_src_flags}
+  ${common.eu_build_flags}
+  -D PP_AUTO_AMPACITY
+  -D MV_FOR_L2=230000L
+  -D 'VERSION="${common.version}.T2"'
+
+# Non-tethered T2 EmonEVSE three-phase
+# Deprecated, unneeded with wifi fw > 4.1.7
+; [env:emonevse_3ph]
+; extends = env:openevse
+; build_src_flags=
+;   ${common.eu_build_flags}
+;   -D PP_AUTO_AMPACITY
+;   -D THREEPHASE
+;   -D 'VERSION="${common.version}.3P"'
+
+
diff --git a/firmware/open_evse/twi.c b/firmware/variants/m328p/twi.c
similarity index 100%
rename from firmware/open_evse/twi.c
rename to firmware/variants/m328p/twi.c
diff --git a/firmware/open_evse/twi.h b/firmware/variants/m328p/twi.h
similarity index 100%
rename from firmware/open_evse/twi.h
rename to firmware/variants/m328p/twi.h
diff --git a/platformio.ini b/platformio.ini
index 744363fd..c99a3880 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -11,11 +11,14 @@
 #default_envs = openevse
 src_dir = firmware/open_evse
 
+extra_configs =
+	firmware/variants/*/platformio.ini
+
 [common]
 lib_deps =
-upload_protocol = usbasp
-upload_flags = "-e -B0.5"
 version = 8.2.3
+build_src_filter =
+   +<*.cpp>
 build_flags =
   -D OEV6
   -D RELAY_PWM
@@ -43,67 +46,8 @@ eu_build_flags =
   -D OVERCURRENT_TIMEOUT=10000UL
   -D DEFAULT_SERVICE_LEVEL=2
 
-[env:openevse_1-8-3]
-platform = atmelavr@3.4.0
-board = openevse
-framework = arduino
-lib_deps = ${common.lib_deps}
-upload_protocol = ${common.upload_protocol}
-upload_flags = ${common.upload_flags}
-build_src_flags=
-  ${common.us_build_flags}
-
-[env:openevse_latest]
-platform = atmelavr
-board = openevse
-framework = arduino
-lib_deps = ${common.lib_deps}
-upload_protocol = ${common.upload_protocol}
-upload_flags = ${common.upload_flags}
-build_src_flags=
-  ${common.us_build_flags}
-
-[env:openevse]
-extends = env:openevse_1-8-3
-build_src_flags=
-  ${common.us_build_flags}
-  -D 'VERSION="${common.version}"'
-
-# v6 CGMI OpenEVSE
-[env:openevse_v6]
-extends = env:openevse
-build_src_flags=
-  ${common.us_build_flags}
-  -D ENABLE_CGMI
-  -D NO_AUTOSVCLEVEL
-  -D DEFAULT_SERVICE_LEVEL=2
-  #-D BTN_MENU
-  #-D RTC
-  -D 'VERSION="${common.version}.CGMI"'
-
-# EU OpenEVSE
-[env:openevse_eu]
-extends = env:openevse
-build_src_flags=
-  ${common.eu_build_flags}
-  -D MV_FOR_L2=230000L
-  -D 'VERSION="${common.version}.EU"'
 
-# Non-tethered T2 EmonEVSE single-phase
-[env:emonevse]
-extends = env:openevse
-build_src_flags=
-  ${common.eu_build_flags}
-  -D PP_AUTO_AMPACITY
-  -D MV_FOR_L2=230000L
-  -D 'VERSION="${common.version}.T2"'
+[env:samd21g18a]
+platform = atmelsam
+board = samd21g18a
 
-# Non-tethered T2 EmonEVSE three-phase
-# Deprecated, unneeded with wifi fw > 4.1.7
-; [env:emonevse_3ph]
-; extends = env:openevse
-; build_src_flags=
-;   ${common.eu_build_flags}
-;   -D PP_AUTO_AMPACITY
-;   -D THREEPHASE
-;   -D 'VERSION="${common.version}.3P"'

From 37af09c58839b327304c6d8eeb316e03ba82d2d6 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 5 Feb 2026 17:33:26 -0800
Subject: [PATCH 10/59] update efuse

---
 firmware/open_evse/fuse.bat | 2 +-
 flash.bat                   | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)
 create mode 100644 flash.bat

diff --git a/firmware/open_evse/fuse.bat b/firmware/open_evse/fuse.bat
index 1a17902c..795f4a23 100644
--- a/firmware/open_evse/fuse.bat
+++ b/firmware/open_evse/fuse.bat
@@ -1,2 +1,2 @@
-avrdude -c usbasp -p m328p -U lfuse:w:0xFF:m -U hfuse:w:0xDF:m -U efuse:w:0x05:m
+avrdude -c usbasp -p m328p -U lfuse:w:0xFF:m -U hfuse:w:0xDF:m -U efuse:w:0xFD:m
 pause
diff --git a/flash.bat b/flash.bat
new file mode 100644
index 00000000..26bb4c23
--- /dev/null
+++ b/flash.bat
@@ -0,0 +1,2 @@
+rem avrdude -c USBasp -p m328p -B16 -U lfuse:w:0xFF:m -U hfuse:w:0xDF:m -U efuse:w:0xFD:m
+avrdude -c USBasp -p m328p -B0.5 -U flash:w:%1

From edb585d631e7bc251a2d5852164f7cfff8ab0ddc Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 5 Feb 2026 17:33:57 -0800
Subject: [PATCH 11/59] move srec_cat.exe

---
 utils/srec_cat.exe | Bin 0 -> 1440270 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 utils/srec_cat.exe

diff --git a/utils/srec_cat.exe b/utils/srec_cat.exe
new file mode 100644
index 0000000000000000000000000000000000000000..39c7b3c87df617de117d5ff0317c900e1836a513
GIT binary patch
literal 1440270
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literal 0
HcmV?d00001


From e1782d88d0cc813e6837493a23b7dca17b6a3576 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 5 Feb 2026 17:41:37 -0800
Subject: [PATCH 12/59] add NO_GROUND_RECORD_DELAY for CGMI

---
 firmware/open_evse/J1772EvseController.cpp | 11 +++++++----
 firmware/open_evse/open_evse.h             |  4 +++-
 firmware/variants/m328p/platformio.ini     |  1 +
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index ce2d1d5c..545acbca 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -1337,10 +1337,13 @@ void J1772EVSEController::Update(uint8_t forcetransition)
     tmpevsestate = EVSE_STATE_NO_GROUND;
     m_EvseState = EVSE_STATE_NO_GROUND;
     chargingOff(); // open the relay
-    if ((prevevsestate != EVSE_STATE_NO_GROUND) &&
-        (((uint8_t)(m_NoGndTripCnt+1)) < 254)) {
-      m_NoGndTripCnt++;
-      eeprom_write_byte((uint8_t*)EOFS_NOGND_TRIP_CNT,m_NoGndTripCnt);
+    if (prevevsestate != EVSE_STATE_NO_GROUND) {
+      m_NoGndStart = curms;
+    }
+    else if (m_NoGndStart && ((curms - m_NoGndStart) >= NO_GND_RECORD_DELAY) &&
+             (((uint8_t)(m_NoGndTripCnt+1)) < 253)) {
+      eeprom_write_byte((uint8_t*)EOFS_NOGND_TRIP_CNT,++m_NoGndTripCnt);
+      m_NoGndStart = 0;
     }
     nofault = 0;
   }
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index 1b54a9fd..a445b8ae 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -347,7 +347,9 @@ extern AutoCurrentCapacityController g_ACCController;
 
 // OEV6 w/ CGMI - when power is loss, temporarily triggers NO GROUND fault
 // delay recording of NO GROUND fault to avoid recording this spurious fault
-#define NO_GND_RECORD_DELAY 2000
+#ifndef NO_GND_RECORD_DELAY
+#define NO_GND_RECORD_DELAY 0
+#endif
 
 //-- end features
 
diff --git a/firmware/variants/m328p/platformio.ini b/firmware/variants/m328p/platformio.ini
index 3335deda..79f5df50 100644
--- a/firmware/variants/m328p/platformio.ini
+++ b/firmware/variants/m328p/platformio.ini
@@ -40,6 +40,7 @@ extends = env:openevse
 build_src_flags=
   ${m328p.build_src_flags}
   -D ENABLE_CGMI
+  -D NO_GROUND_RECORD_DELAY=2000
   -D NO_AUTOSVCLEVEL
   -D DEFAULT_SERVICE_LEVEL=2
   #-D BTN_MENU

From 99daad4da07fb225e13ce656269b112b5d1f7a1c Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 5 Feb 2026 17:43:25 -0800
Subject: [PATCH 13/59] update CHANGELOG

---
 firmware/open_evse/CHANGELOG   | 8 ++++++++
 firmware/open_evse/rapi_proc.h | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/firmware/open_evse/CHANGELOG b/firmware/open_evse/CHANGELOG
index 276c4a92..51ee081f 100644
--- a/firmware/open_evse/CHANGELOG
+++ b/firmware/open_evse/CHANGELOG
@@ -1,5 +1,13 @@
 Change Log
 
+20260205 SCL
+- OEV6 w/ CGMI - when power is lost, temporarily triggers NO GROUND fault
+   delay recording of NO GROUND fault by NO_GND_RECORD_DELAY (currently 2s)
+   to avoid recording this spurious fault
+- add RAPI $FC to clear fault counters + total energy
+- had bug in max fault counters.. was checking < 254 instead of <253, so when
+  maxed out would be zero instead of 255 (since returned value is count+1)
+	
 20230207 SCL
 - PP_AUTO_AMPACITY changes
   -> used to change current capacity to PP ampacity. now, only change it
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index 06ff0d87..c535b1a4 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -364,7 +364,7 @@ Z0 closems holdpwm
 
 #ifdef RAPI
 
-#define RAPIVER "5.2.1"
+#define RAPIVER "5.3.0"
 
 #define WIFI_MODE_AP 0
 #define WIFI_MODE_CLIENT 1

From 362beeca9bd4f280aa7e21e66521caba609c6ff9 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 5 Feb 2026 18:18:51 -0800
Subject: [PATCH 14/59] more variant prep

---
 firmware/open_evse/AutoCurrentCapacityController.h    | 2 +-
 firmware/open_evse/open_evse.h                        | 7 ++-----
 firmware/variants/m328p/platformio.ini                | 2 +-
 firmware/variants/m328p/{avrstuff.cpp => variant.cpp} | 2 +-
 firmware/variants/m328p/{avrstuff.h => variant.h}     | 4 +++-
 platformio.ini                                        | 3 ++-
 6 files changed, 10 insertions(+), 10 deletions(-)
 rename firmware/variants/m328p/{avrstuff.cpp => variant.cpp} (99%)
 rename firmware/variants/m328p/{avrstuff.h => variant.h} (98%)

diff --git a/firmware/open_evse/AutoCurrentCapacityController.h b/firmware/open_evse/AutoCurrentCapacityController.h
index 076d570b..51bcd3f3 100644
--- a/firmware/open_evse/AutoCurrentCapacityController.h
+++ b/firmware/open_evse/AutoCurrentCapacityController.h
@@ -13,7 +13,7 @@
 // See LICENSE for a copy of the GNU General Public License or see
 // it online at <http://www.gnu.org/licenses/>.
 
-#include "avrstuff.h"
+#include "variant.h"
 
 typedef struct pp_amps {
   uint16_t adcVal;
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index a445b8ae..d85c7b17 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -31,12 +31,9 @@
 
 #define OPEN_EVSE
 
-#include <avr/wdt.h>
-#include <avr/pgmspace.h>
-#include <avr/eeprom.h>
 #include <pins_arduino.h>
-#include "./Wire.h"
-#include "avrstuff.h"
+#include "Wire.h"
+#include "variant.h"
 #include "i2caddr.h"
 
 #include "Arduino.h"
diff --git a/firmware/variants/m328p/platformio.ini b/firmware/variants/m328p/platformio.ini
index 79f5df50..7eb68219 100644
--- a/firmware/variants/m328p/platformio.ini
+++ b/firmware/variants/m328p/platformio.ini
@@ -47,7 +47,7 @@ build_src_flags=
   #-D RTC
   -D 'VERSION="${common.version}.CGMI"'
 
-  # EU OpenEVSE
+# EU OpenEVSE
 [env:openevse_eu]
 extends = env:openevse
 build_src_flags=
diff --git a/firmware/variants/m328p/avrstuff.cpp b/firmware/variants/m328p/variant.cpp
similarity index 99%
rename from firmware/variants/m328p/avrstuff.cpp
rename to firmware/variants/m328p/variant.cpp
index 8165a054..027c8b43 100644
--- a/firmware/variants/m328p/avrstuff.cpp
+++ b/firmware/variants/m328p/variant.cpp
@@ -12,7 +12,7 @@
 // See LICENSE for a copy of the GNU General Public License or see
 // it online at <http://www.gnu.org/licenses/>.
 
-#include "avrstuff.h"
+#include "variant.h"
 
 void DigitalPin::init(volatile uint8_t* _reg,uint8_t idx,PinMode _mode)
 {
diff --git a/firmware/variants/m328p/avrstuff.h b/firmware/variants/m328p/variant.h
similarity index 98%
rename from firmware/variants/m328p/avrstuff.h
rename to firmware/variants/m328p/variant.h
index 60422646..93bdee26 100644
--- a/firmware/variants/m328p/avrstuff.h
+++ b/firmware/variants/m328p/variant.h
@@ -14,7 +14,9 @@
 // it online at <http://www.gnu.org/licenses/>.
 
 #pragma once
-
+#include <avr/wdt.h>
+#include <avr/pgmspace.h>
+#include <avr/eeprom.h>
 #include <avr/io.h>
 #include <avr/interrupt.h>
 #if defined(ARDUINO) && (ARDUINO >= 100)
diff --git a/platformio.ini b/platformio.ini
index c99a3880..a5b7debc 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -16,7 +16,7 @@ extra_configs =
 
 [common]
 lib_deps =
-version = 8.2.3
+version = D8.2.3
 build_src_filter =
    +<*.cpp>
 build_flags =
@@ -49,5 +49,6 @@ eu_build_flags =
 
 [env:samd21g18a]
 platform = atmelsam
+framework = arduino
 board = samd21g18a
 

From 13a00258ac30b7ca0257f0f8d7a794e24ea8ff07 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 18 Feb 2026 17:02:43 -0800
Subject: [PATCH 15/59] TEMPERATURE_THROTTLING, $FO,$GO

---
 firmware/open_evse/CHANGELOG               |  6 ++++++
 firmware/open_evse/J1772EvseController.cpp | 15 ++++++++-------
 firmware/open_evse/main.cpp                | 20 +++++++++-----------
 firmware/open_evse/open_evse.h             | 15 +++++++++++++--
 firmware/open_evse/rapi_proc.cpp           | 18 +++++++++++++-----
 firmware/open_evse/rapi_proc.h             | 13 ++++++++++---
 6 files changed, 59 insertions(+), 28 deletions(-)

diff --git a/firmware/open_evse/CHANGELOG b/firmware/open_evse/CHANGELOG
index 51ee081f..17fc0aa7 100644
--- a/firmware/open_evse/CHANGELOG
+++ b/firmware/open_evse/CHANGELOG
@@ -1,5 +1,11 @@
 Change Log
 
+20260218 SCL
+- added TEMPERATURE_THROTTLING - if not enabled, only TEMPERATURE_AMBIENT_PANIC
+  is enforced
+- RAPI: added $FO - set panic temperature, $GO get panic temperature
+  panic temperature is saved to EEPROM. if exceeded, go into EVSE_STATE_OVER_TEMPERATURE
+	
 20260205 SCL
 - OEV6 w/ CGMI - when power is lost, temporarily triggers NO GROUND fault
    delay recording of NO GROUND fault by NO_GND_RECORD_DELAY (currently 2s)
diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 545acbca..4a87d0d1 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -272,8 +272,8 @@ void J1772EVSEController::chargingOn()
 #ifdef OEV6
   if (isV6()) {
 #ifdef RELAY_PWM
-    Serial.print("\nrelayCloseMs: ");Serial.println(m_relayCloseMs);
-    Serial.print("relayHoldPwm: ");Serial.println(m_relayHoldPwm);
+//    Serial.print("\nrelayCloseMs: ");Serial.println(m_relayCloseMs);
+//    Serial.print("relayHoldPwm: ");Serial.println(m_relayHoldPwm);
     // turn on charging pin to close relay
     digitalWrite(V6_CHARGING_PIN,HIGH);
     digitalWrite(V6_CHARGING_PIN2,HIGH);
@@ -960,8 +960,8 @@ void J1772EVSEController::Init()
     m_relayCloseMs = DEFAULT_RELAY_CLOSE_MS;
     m_relayHoldPwm = DEFAULT_RELAY_HOLD_PWM;
   }
-  Serial.print("\nrelayCloseMs: ");Serial.println(m_relayCloseMs);
-  Serial.print("relayHoldPwm: ");Serial.println(m_relayHoldPwm);
+//  Serial.print("\nrelayCloseMs: ");Serial.println(m_relayCloseMs);
+//  Serial.print("relayHoldPwm: ");Serial.println(m_relayHoldPwm);
 #endif // RELAY_PWM
 
 
@@ -1478,9 +1478,10 @@ void J1772EVSEController::Update(uint8_t forcetransition)
 
 #ifdef TEMPERATURE_MONITORING                 //  A state for OverTemp fault
 if (TempChkEnabled()) {
+  int16_t thresh = g_TempMonitor.GetPanicTemperature();
   if ((g_TempMonitor.m_TMP007_temperature >= TEMPERATURE_INFRARED_PANIC)  ||
-      (g_TempMonitor.m_MCP9808_temperature >= TEMPERATURE_AMBIENT_PANIC)  ||
-      (g_TempMonitor.m_DS3231_temperature >= TEMPERATURE_AMBIENT_PANIC))  {
+      (g_TempMonitor.m_MCP9808_temperature >= thresh)  ||
+      (g_TempMonitor.m_DS3231_temperature >= thresh))  {
     tmpevsestate = EVSE_STATE_OVER_TEMPERATURE;
     m_EvseState = EVSE_STATE_OVER_TEMPERATURE;
     nofault = 0;
@@ -1873,7 +1874,7 @@ if (TempChkEnabled()) {
     this->HsExpirationCheck();  //Check to see if HS is engaged, and if so whether we missed a pulse
 #endif //HEARTBEAT_SUPERVISION
 
-#ifdef TEMPERATURE_MONITORING
+#ifdef TEMPERATURE_THROTTLING
     if(TempChkEnabled()) {
       uint8_t currcap = GetMaxCurrentCapacity();
       uint8_t setit = 0;
diff --git a/firmware/open_evse/main.cpp b/firmware/open_evse/main.cpp
index 6eead8d2..cdce55f8 100644
--- a/firmware/open_evse/main.cpp
+++ b/firmware/open_evse/main.cpp
@@ -272,10 +272,8 @@ void TempMonitor::Init()
   m_MCP9808_temperature = TEMPERATURE_NOT_INSTALLED;  // 230 means 23.0C  Using an integer to save on floating point library use
   m_DS3231_temperature = TEMPERATURE_NOT_INSTALLED;   // the DS3231 RTC has a built in temperature sensor
   m_TMP007_temperature = TEMPERATURE_NOT_INSTALLED;
-
-#ifdef TEMPERATURE_MONITORING_NY
-  LoadThresh();
-#endif
+  m_panicTemperature = (int16_t) eeprom_read_word((uint16_t*)EOFS_PANIC_TEMP);
+  if (m_panicTemperature <= 0) m_panicTemperature = TEMPERATURE_AMBIENT_PANIC;
 
 #ifdef MCP9808_IS_ON_I2C
   m_tempSensor.begin();
@@ -2427,14 +2425,19 @@ void ProcessInputs()
 void EvseReset()
 {
   Wire.begin();
+
   g_OBD.Init();
 
 #ifdef RAPI
   RapiInit();
 #endif
 
-  g_EvseController.Init();
 
+#ifdef TEMPERATURE_MONITORING
+  g_TempMonitor.Init();
+#endif
+
+  g_EvseController.Init();
 #ifdef DELAYTIMER
   g_DelayTimer.Init(); // this *must* run after g_EvseController.Init() because it sets one of the vFlags
 #endif  // DELAYTIMER
@@ -2488,13 +2491,8 @@ void setup()
 #ifdef PP_AUTO_AMPACITY
   g_EvseController.SetStateTransitionReqFunc(&StateTransitionReqFunc);
 #endif //PP_AUTO_AMPACITY
-  EvseReset();
-  
-#ifdef TEMPERATURE_MONITORING
-  g_TempMonitor.Init();
-#endif
 
-  
+  EvseReset();
 
 #ifdef BOOTLOCK
 #ifdef LCD16X2
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index d85c7b17..bc1e2c87 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -185,6 +185,11 @@ extern AutoCurrentCapacityController g_ACCController;
 #endif //UL_COMPLIANT
 
 #define TEMPERATURE_MONITORING  // Temperature monitoring support
+// TEMPERATURE_THROTTLING enables adjusting max current based on temperature
+// if not defined, and TEMPERATURE_MONITORING is enabled, then only
+// TEMPERATURE_AMBIENT_PANIC is checked
+//#define TEMPERATURE_THROTTLING
+
 
 //#define HEARTBEAT_SUPERVISION // Heartbeat Supervision support
 
@@ -554,8 +559,8 @@ extern AutoCurrentCapacityController g_ACCController;
 
 #define EOFS_VOLT_OFFSET 20 // 4 bytes
 #define EOFS_VOLT_SCALE_FACTOR 24 // 2 bytes
-#define EOFS_THRESH_AMBIENT 26 // 2 bytes
-#define EOFS_THRESH_IR 28 // 2 bytes
+#define EOFS_PANIC_TEMP 26 // 2 bytes
+//notused#define EOFS_THRESH_IR 28 // 2 bytes
 
 // for I2C RAPI
 #define EOFS_LOCAL_I2C_ADDR 30 // 1 byte
@@ -997,6 +1002,7 @@ class TempMonitor {
   int16_t m_MCP9808_temperature;  // 230 means 23.0C  Using an integer to save on floating point library use
   int16_t m_DS3231_temperature;   // the DS3231 RTC has a built in temperature sensor
   int16_t m_TMP007_temperature;
+  int16_t m_panicTemperature;
 
   TempMonitor() {}
   void Init();
@@ -1012,6 +1018,11 @@ class TempMonitor {
     else m_Flags &= ~TMF_OVERTEMPERATURE;
   }
   int8_t OverTemperature() { return (m_Flags & TMF_OVERTEMPERATURE) ? 1 : 0; }
+  int16_t GetPanicTemperature() { return m_panicTemperature; }
+  void SetPanicTemperature(int16_t panictemp) {
+    m_panicTemperature = panictemp;
+    eeprom_write_word((uint16_t*)EOFS_PANIC_TEMP, panictemp);
+ }
   void SetOverTemperatureShutdown(int8_t tf) {
     if (tf) m_Flags |= (TMF_OVERTEMPERATURE_SHUTDOWN|TMF_OVERTEMPERATURE_LOGGED);
     else m_Flags &= ~TMF_OVERTEMPERATURE_SHUTDOWN;
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index cd3b0a33..91e445c9 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -345,6 +345,17 @@ int EvseRapiProcessor::processCmd()
 	}
       }
       break;
+#ifdef TEMPERATURE_MONITORING
+    case 'O': // print to LCD
+      if (tokenCnt == 2) {
+        u1.i16 = dtou32(tokens[1]);
+        if (u1.i16 > 0) {
+          g_TempMonitor.SetPanicTemperature(u1.i16);
+          rc = 0;
+        }
+      }
+      break;
+#endif // TEMPERATURE_MONITORING
 #ifdef LCD16X2
     case 'P': // print to LCD
       if ((tokenCnt >= 4) && !g_EvseController.InHardFault()) {
@@ -753,15 +764,12 @@ int EvseRapiProcessor::processCmd()
       break;
 #endif // VOLTMETER
 #ifdef TEMPERATURE_MONITORING
-#ifdef TEMPERATURE_MONITORING_NY
     case 'O':
-      u1.i = g_TempMonitor.m_ambient_thresh;
-      u2.i = g_TempMonitor.m_ir_thresh;
-      sprintf(buffer,"%d %d",u1.i,u2.i);
+      u1.i = g_TempMonitor.m_panicTemperature;
+      sprintf(buffer,"%d",u1.i);
       bufCnt = 1; // flag response text output
       rc = 0;
       break;
-#endif // TEMPERATURE_MONITORING_NY
     case 'P':
       sprintf(buffer,"%d %d %d",(int)g_TempMonitor.m_DS3231_temperature,
 	      (int)g_TempMonitor.m_MCP9808_temperature,
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index c535b1a4..e0597188 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -121,6 +121,12 @@ FD - disable EVSE
  $FD*AE
 FE - enable EVSE
  $FE*AF
+FO set Overtemperature threshold
+ $FO panicthresh
+ panicthresh in 10ths of a degree Celsius
+ $FO 705 - set panic threshold to 70.5C
+ if temperature exceeds panicthresh, EVSE goes into OVER_TEMPERATURE fault state
+
 FP x y text - print text on lcd display
   OPTIONAL: can substitute character 0x11 for spaces within a string, because they print as <SPC> on HD44780. More reliable.
 FR - restart EVSE
@@ -304,9 +310,10 @@ GM - get voltMeter settings
  response: $OK voltcalefactor voltoffset
  $GM^2E
 
-GO get Overtemperature thresholds
- response: $OK ambientthresh irthresh
- thresholds are in 10ths of a degree Celcius
+GO get Overtemperature threshold
+ response: $OK panicthresh
+ panicthresh in 10ths of a degree Celsius
+ if temperature exceeds panicthresh, EVSE goes into OVER_TEMPERATURE fault state
  $GO^2C
 GP - get temPerature (v1.0.3+)
  response: $OK ds3231temp mcp9808temp tmp007temp

From 66f05e7a9c4f9d7bda2c955241b871f8854a13d0 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 18 Feb 2026 17:17:12 -0800
Subject: [PATCH 16/59] comment out #define BTN_MENU

---
 firmware/open_evse/CHANGELOG   | 1 +
 firmware/open_evse/open_evse.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/firmware/open_evse/CHANGELOG b/firmware/open_evse/CHANGELOG
index 17fc0aa7..405bd48f 100644
--- a/firmware/open_evse/CHANGELOG
+++ b/firmware/open_evse/CHANGELOG
@@ -5,6 +5,7 @@ Change Log
   is enforced
 - RAPI: added $FO - set panic temperature, $GO get panic temperature
   panic temperature is saved to EEPROM. if exceeded, go into EVSE_STATE_OVER_TEMPERATURE
+- it's a NO-OP, but don't enable BTN_MENU by default in open_evse.h, anyway
 	
 20260205 SCL
 - OEV6 w/ CGMI - when power is lost, temporarily triggers NO GROUND fault
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index bc1e2c87..84ea0099 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -257,7 +257,7 @@ extern AutoCurrentCapacityController g_ACCController;
 // How to use 1-button menu
 // Long press activates menu
 // When within menus, short press cycles menu items, long press selects and exits current submenu
-#define BTN_MENU
+//#define BTN_MENU
 
 // take out basic setup stuff that the user really shouldn't be changing,
 // which can be set via RAPI/WiFi module.. reclaims a lot of code space

From f76bc114d985225d161332a0bf61576aa5d5968f Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 18 Feb 2026 17:24:23 -0800
Subject: [PATCH 17/59] clarify $SY

---
 firmware/open_evse/rapi_proc.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index e0597188..80892123 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -220,7 +220,9 @@ SV mv - Set Voltage for power calculations to mv millivolts
  NOTES:
   - only available if VOLTMETER not defined and KWH_RECORDING defined
   - volatile - value is lost, and replaced with VOLTS_FOR_Lx at boot
-SY heartbeatinterval hearbeatcurrentlimit
+SY heartbeatinterval heartbeatcurrentlimit
+ heartbeatinterval - seconds. 0 to disable
+ heartbeatcurrentlimit - max current when no heartbeat within heartbeatinterval
  Response includes heartbeatinterval hearbeatcurrentlimit hearbeattrigger
  hearbeattrigger: 0 - There has never been a missed pulse, 
  2 - there is a missed pulse, and HS is still in current limit

From 15c874ae07b86e48f3190b321369c475e9a3a96e Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 19 Feb 2026 12:32:17 -0800
Subject: [PATCH 18/59] enable/disable boot lock $FF L 0|1

---
 firmware/open_evse/CHANGELOG               |  4 ++++
 firmware/open_evse/J1772EvseController.cpp |  5 +++--
 firmware/open_evse/J1772EvseController.h   | 15 +++++++++++----
 firmware/open_evse/rapi_proc.cpp           |  5 +++++
 firmware/open_evse/rapi_proc.h             |  3 ++-
 firmware/variants/m328p/platformio.ini     |  1 +
 6 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/firmware/open_evse/CHANGELOG b/firmware/open_evse/CHANGELOG
index 405bd48f..84614814 100644
--- a/firmware/open_evse/CHANGELOG
+++ b/firmware/open_evse/CHANGELOG
@@ -1,5 +1,9 @@
 Change Log
 
+20260219 SCL
+- added $FF L 0|1 command to enable/disable boot lock feature
+- added ECF_BOOT_LOCK_DISABLED
+	
 20260218 SCL
 - added TEMPERATURE_THROTTLING - if not enabled, only TEMPERATURE_AMBIENT_PANIC
   is enforced
diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 4a87d0d1..88d1cfcb 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -1087,10 +1087,11 @@ void J1772EVSEController::Init()
   m_wFlags |= ECF_MONO_LCD;
 #endif
 
-  m_wVFlags = ECVF_DEFAULT;
+  setVFlags(ECVF_DEFAULT);
 
 #ifdef BOOTLOCK
-  m_wVFlags |= ECVF_BOOT_LOCK;
+  if (BootLockIsEnabled())
+    setVFlags(ECVF_BOOT_LOCK);
 #endif
 
   m_MaxHwCurrentCapacity = eeprom_read_byte((uint8_t*)EOFS_MAX_HW_CURRENT_CAPACITY);
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index e9eaa684..81e64405 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -77,13 +77,13 @@ typedef uint8_t (*EvseStateTransitionReqFunc)(uint8_t prevPilotState,uint8_t cur
 #define ECF_GND_CHK_DISABLED   0x0008 // no chk for ground fault
 #define ECF_STUCK_RELAY_CHK_DISABLED 0x0010 // no chk for stuck relay
 #define ECF_AUTO_SVC_LEVEL_DISABLED  0x0020 // auto detect svc level - requires ADVPWR
-// Ability set the EVSE for manual button press to start charging - GoldServe
-#define ECF_AUTO_START_DISABLED 0x0040  // no auto start charging
+//obsolete #define ECF_AUTO_START_DISABLED 0x0040  // no auto start charging
 #define ECF_SERIAL_DBG         0x0080 // enable debugging messages via serial
 #define ECF_MONO_LCD           0x0100 // monochrome LCD backlight
 #define ECF_GFI_TEST_DISABLED  0x0200 // no GFI self test
 #define ECF_TEMP_CHK_DISABLED  0x0400 // no Temperature Monitoring
 #define ECF_CGMI               0x1000 // continuous GMI
+#define ECF_BOOT_LOCK_DISABLED 0x2000 // boot lock
 #define ECF_BUTTON_DISABLED    0x8000 // front panel button disabled
 #define ECF_DEFAULT            0x0000
 
@@ -325,6 +325,12 @@ class J1772EVSEController {
   void ClrHardFault() { clrVFlags(ECVF_HARD_FAULT); }
   int8_t InHardFault() { return vFlagIsSet(ECVF_HARD_FAULT); }
   int8_t CGMIisEnabled() { return flagIsSet(ECF_CGMI); }
+  int8_t BootLockIsEnabled() { return !flagIsSet(ECF_BOOT_LOCK_DISABLED); }
+  void EnableBootLock(uint8_t tf) {
+    if (!tf) setFlags(ECF_BOOT_LOCK_DISABLED); 
+    else clrFlags(ECF_BOOT_LOCK_DISABLED);
+    SaveEvseFlags();
+  }
   unsigned long GetResetMs();
 
   uint8_t SetMaxHwCurrentCapacity(uint8_t amps);
@@ -394,7 +400,8 @@ class J1772EVSEController {
   }
   uint8_t IsBootLocked() {
 #ifdef BOOTLOCK
-    return vFlagIsSet(ECVF_BOOT_LOCK) ? 1 : 0;
+    if (flagIsSet(ECF_BOOT_LOCK_DISABLED)) return 0;
+    return vFlagIsSet(ECVF_BOOT_LOCK);
 #else
     return 0;
 #endif
@@ -576,7 +583,7 @@ int GetHearbeatTrigger();
     else clrFlags(ECF_BUTTON_DISABLED);
     SaveEvseFlags();
   }
-  uint8_t ButtonIsEnabled() { return flagIsSet(ECF_BUTTON_DISABLED) ? 0 : 1; }
+  uint8_t ButtonIsEnabled() { return flagIsSet(ECF_BUTTON_DISABLED); }
 #endif // BTN_MENU
 
 #if defined(KWH_RECORDING) && !defined(VOLTMETER)
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index 91e445c9..1316c061 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -331,6 +331,11 @@ int EvseRapiProcessor::processCmd()
 	    g_EvseController.EnableStuckRelayChk(u1.u8);
 	    break;
 #endif // ADVPWR
+#ifdef BOOTLOCK
+	  case 'L': // boot lock
+	    g_EvseController.EnableBootLock(u1.u8);
+	    break;
+#endif // BOOTLOCK
 #ifdef TEMPERATURE_MONITORING
 	  case 'T': // temperature monitoring
 	    g_EvseController.EnableTempChk(u1.u8);
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index 80892123..ccb82d78 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -145,6 +145,7 @@ FF - enable/disable feature
    after its replies. Valid only over a serial connection, DO NOT USE on I2C
   F = GFI self test
   G = Ground check
+  L = boot Lock
   R = stuck Relay check
   T = temperature monitoring
   V = Vent required check
@@ -373,7 +374,7 @@ Z0 closems holdpwm
 
 #ifdef RAPI
 
-#define RAPIVER "5.3.0"
+#define RAPIVER "6.0.0"
 
 #define WIFI_MODE_AP 0
 #define WIFI_MODE_CLIENT 1
diff --git a/firmware/variants/m328p/platformio.ini b/firmware/variants/m328p/platformio.ini
index 7eb68219..9d644fa4 100644
--- a/firmware/variants/m328p/platformio.ini
+++ b/firmware/variants/m328p/platformio.ini
@@ -43,6 +43,7 @@ build_src_flags=
   -D NO_GROUND_RECORD_DELAY=2000
   -D NO_AUTOSVCLEVEL
   -D DEFAULT_SERVICE_LEVEL=2
+  -D BOOTLOCK
   #-D BTN_MENU
   #-D RTC
   -D 'VERSION="${common.version}.CGMI"'

From 181b7c592851cbaee7e65101018e2825dd8cf6e9 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 19 Feb 2026 19:28:11 -0800
Subject: [PATCH 19/59] added $FF O 0|1 disable overcurrent check

---
 firmware/open_evse/CHANGELOG               |  4 +-
 firmware/open_evse/J1772EvseController.cpp | 57 ++++++++++++----------
 firmware/open_evse/J1772EvseController.h   |  7 +++
 firmware/open_evse/rapi_proc.cpp           |  5 ++
 firmware/open_evse/rapi_proc.h             |  1 +
 5 files changed, 47 insertions(+), 27 deletions(-)

diff --git a/firmware/open_evse/CHANGELOG b/firmware/open_evse/CHANGELOG
index 84614814..07bfce00 100644
--- a/firmware/open_evse/CHANGELOG
+++ b/firmware/open_evse/CHANGELOG
@@ -2,7 +2,9 @@ Change Log
 
 20260219 SCL
 - added $FF L 0|1 command to enable/disable boot lock feature
-- added ECF_BOOT_LOCK_DISABLED
+  added ECF_BOOT_LOCK_DISABLED
+- added $FF O 0|1 command to enable/disable overcurrent check
+  adde ECF_OVERCURRENT_DISABLED
 	
 20260218 SCL
 - added TEMPERATURE_THROTTLING - if not enabled, only TEMPERATURE_AMBIENT_PANIC
diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 88d1cfcb..c4dd53fb 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -1833,40 +1833,45 @@ if (TempChkEnabled()) {
   }
 
 #ifdef OVERCURRENT_THRESHOLD
-  if (m_EvseState == EVSE_STATE_C) {
-    //testing    m_ChargingCurrent = (m_CurrentCapacity+OVERCURRENT_THRESHOLD+12)*1000L;
-    if (m_ChargingCurrent >= ((m_CurrentCapacity+OVERCURRENT_THRESHOLD)*1000L)) {
-      if (m_OverCurrentStartMs) { // already in overcurrent state
-	if ((millis()-m_OverCurrentStartMs) >= OVERCURRENT_TIMEOUT) {
-	  //
-	  // overcurrent for too long. stop charging and hard fault
-	  //
-	  m_EvseState = EVSE_STATE_OVER_CURRENT;
-
-	  m_Pilot.SetState(PILOT_STATE_P12); // Signal the EV to pause
-	  curms = millis();
-	  while ((millis()-curms) < 1000) { // give EV 1s to stop charging
-	    wdt_reset();
-	  }
-	  chargingOff(); // open the EVSE relays hopefully the EV has already discon
-
-	  // spin until EV is disconnected
-	  HardFault(1);
-	  
-	  m_OverCurrentStartMs = 0; // clear overcurrent
-	}
+  if (OverCurrentCheckIsEnabled()) {
+    if (m_EvseState == EVSE_STATE_C) {
+      // testing    m_ChargingCurrent =
+      // (m_CurrentCapacity+OVERCURRENT_THRESHOLD+12)*1000L;
+      if (m_ChargingCurrent >=
+          ((m_CurrentCapacity + OVERCURRENT_THRESHOLD) * 1000L)) {
+        if (m_OverCurrentStartMs) { // already in overcurrent state
+          if ((millis() - m_OverCurrentStartMs) >= OVERCURRENT_TIMEOUT) {
+            //
+            // overcurrent for too long. stop charging and hard fault
+            //
+            m_EvseState = EVSE_STATE_OVER_CURRENT;
+
+            m_Pilot.SetState(PILOT_STATE_P12); // Signal the EV to pause
+            curms = millis();
+            while ((millis() - curms) < 1000) { // give EV 1s to stop charging
+              wdt_reset();
+            }
+            chargingOff(); // open the EVSE relays hopefully the EV
+                           // has already discon
+
+            // spin until EV is disconnected
+            HardFault(1);
+
+            m_OverCurrentStartMs = 0; // clear overcurrent
+          }
+        }
+        else {
+          m_OverCurrentStartMs = millis();
+        }
       }
       else {
-	m_OverCurrentStartMs = millis();
+        m_OverCurrentStartMs = 0; // clear overcurrent
       }
     }
     else {
       m_OverCurrentStartMs = 0; // clear overcurrent
     }
   }
-  else {
-    m_OverCurrentStartMs = 0; // clear overcurrent
-  }
 #endif // OVERCURRENT_THRESHOLD
 #endif // AMMETER
 
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index 81e64405..36173566 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -84,6 +84,7 @@ typedef uint8_t (*EvseStateTransitionReqFunc)(uint8_t prevPilotState,uint8_t cur
 #define ECF_TEMP_CHK_DISABLED  0x0400 // no Temperature Monitoring
 #define ECF_CGMI               0x1000 // continuous GMI
 #define ECF_BOOT_LOCK_DISABLED 0x2000 // boot lock
+#define ECF_OVERCURRENT_DISABLED 0x0400 // disable overcurrent check
 #define ECF_BUTTON_DISABLED    0x8000 // front panel button disabled
 #define ECF_DEFAULT            0x0000
 
@@ -331,6 +332,12 @@ class J1772EVSEController {
     else clrFlags(ECF_BOOT_LOCK_DISABLED);
     SaveEvseFlags();
   }
+  int8_t OverCurrentCheckIsEnabled() { return !flagIsSet(ECF_OVERCURRENT_DISABLED); }
+  void EnableOverCurrentCheck(uint8_t tf) {
+    if (!tf) setFlags(ECF_OVERCURRENT_DISABLED); 
+    else clrFlags(ECF_OVERCURRENT_DISABLED);
+    SaveEvseFlags();
+  }
   unsigned long GetResetMs();
 
   uint8_t SetMaxHwCurrentCapacity(uint8_t amps);
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index 1316c061..9d13645f 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -336,6 +336,11 @@ int EvseRapiProcessor::processCmd()
 	    g_EvseController.EnableBootLock(u1.u8);
 	    break;
 #endif // BOOTLOCK
+#ifdef OVERCURRENT_THRESHOLD
+	  case 'O': // overcurrent check
+	    g_EvseController.EnableOverCurrentCheck(u1.u8);
+	    break;
+#endif // OVERCURRENT_THRESHOLD
 #ifdef TEMPERATURE_MONITORING
 	  case 'T': // temperature monitoring
 	    g_EvseController.EnableTempChk(u1.u8);
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index ccb82d78..4f7edb87 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -146,6 +146,7 @@ FF - enable/disable feature
   F = GFI self test
   G = Ground check
   L = boot Lock
+  O = overcurrent check
   R = stuck Relay check
   T = temperature monitoring
   V = Vent required check

From f004230c51d7a3453148171c1915ac1284c06444 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 19 Feb 2026 20:31:23 -0800
Subject: [PATCH 20/59] fix ButtonIsEnabled() inverted, 16x2LCD countdown bugs

---
 firmware/open_evse/CHANGELOG             |  5 ++++-
 firmware/open_evse/J1772EvseController.h |  3 ++-
 firmware/open_evse/main.cpp              | 14 ++++++++------
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/firmware/open_evse/CHANGELOG b/firmware/open_evse/CHANGELOG
index 07bfce00..82678909 100644
--- a/firmware/open_evse/CHANGELOG
+++ b/firmware/open_evse/CHANGELOG
@@ -4,7 +4,10 @@ Change Log
 - added $FF L 0|1 command to enable/disable boot lock feature
   added ECF_BOOT_LOCK_DISABLED
 - added $FF O 0|1 command to enable/disable overcurrent check
-  adde ECF_OVERCURRENT_DISABLED
+  added ECF_OVERCURRENT_DISABLED
+- fix bug: J1772EvseController::ButtonIsEnabled() was returning true when disabled
+- fix bug: when in fault countdown, 16x2 LCD was still counting down on 2nd
+  line of LCD when in menus
 	
 20260218 SCL
 - added TEMPERATURE_THROTTLING - if not enabled, only TEMPERATURE_AMBIENT_PANIC
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index 36173566..7b65f0cd 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -582,6 +582,7 @@ int GetHearbeatTrigger();
   }
   void SetInMenu() { setVFlags(ECVF_UI_IN_MENU); }
   void ClrInMenu() { clrVFlags(ECVF_UI_IN_MENU); }
+  int8_t IsInMenu() { return vFlagIsSet(ECVF_UI_IN_MENU); }
   void SetDelayTimerOnFlag() {setVFlags(ECVF_TIMER_ON); }
   void ClrDelayTimerOnFlag() {clrVFlags(ECVF_TIMER_ON); }
 #ifdef BTN_MENU
@@ -590,7 +591,7 @@ int GetHearbeatTrigger();
     else clrFlags(ECF_BUTTON_DISABLED);
     SaveEvseFlags();
   }
-  uint8_t ButtonIsEnabled() { return flagIsSet(ECF_BUTTON_DISABLED); }
+  uint8_t ButtonIsEnabled() { return !flagIsSet(ECF_BUTTON_DISABLED); }
 #endif // BTN_MENU
 
 #if defined(KWH_RECORDING) && !defined(VOLTMETER)
diff --git a/firmware/open_evse/main.cpp b/firmware/open_evse/main.cpp
index cdce55f8..91899174 100644
--- a/firmware/open_evse/main.cpp
+++ b/firmware/open_evse/main.cpp
@@ -797,12 +797,14 @@ void OnboardDisplay::Update(int8_t updmode)
     if (!g_EvseController.InHardFault() &&
 	((curstate == EVSE_STATE_GFCI_FAULT) || (curstate == EVSE_STATE_NO_GROUND))) {
 #ifdef LCD16X2
-      strcpy(g_sTmp,g_sRetryIn);
-      int resetsec = (int)(g_EvseController.GetResetMs() / 1000ul);
-      if (resetsec >= 0) {
-	sprintf(g_sTmp+sizeof(g_sTmp)-6,g_sHHMMfmt,resetsec / 60,resetsec % 60);
-	strcat(g_sTmp,g_sTmp+sizeof(g_sTmp)-6);
-	LcdPrint(1,g_sTmp);
+      if (!g_EvseController.IsInMenu()) {
+        strcpy(g_sTmp,g_sRetryIn);
+        int resetsec = (int)(g_EvseController.GetResetMs() / 1000ul);
+        if (resetsec >= 0) {
+          sprintf(g_sTmp+sizeof(g_sTmp)-6,g_sHHMMfmt,resetsec / 60,resetsec % 60);
+          strcat(g_sTmp,g_sTmp+sizeof(g_sTmp)-6);
+          LcdPrint(1,g_sTmp);
+        }
       }
 #endif // LCD16X2
       return;

From ccf0927fdae4f416f34afbab80815f52fb2c8c15 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 19 Feb 2026 20:32:50 -0800
Subject: [PATCH 21/59] add OG 16x2 RGBLCD build

---
 firmware/variants/m328p/platformio.ini | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

diff --git a/firmware/variants/m328p/platformio.ini b/firmware/variants/m328p/platformio.ini
index 9d644fa4..d1e7e173 100644
--- a/firmware/variants/m328p/platformio.ini
+++ b/firmware/variants/m328p/platformio.ini
@@ -34,6 +34,26 @@ build_src_flags=
   ${m328p.build_src_flags}
   -D 'VERSION="${common.version}"'
 
+# openevse with 16x2 RGBLCD and front panel button
+[env:openevse_rgblcd]
+extends = env:openevse
+build_src_flags=
+  ${m328p.build_src_flags}
+  -UOEV6
+  -UHEARTBEAT_SUPERVISION
+  -UBOOTLOCK
+  -D ENABLE_CGMI
+  -D OVERCURRENT_THRESHOLD=5
+  -D OVERCURRENT_TIMEOUT=10000UL
+  -D BTN_MENU
+  -D RTC
+  -D DELAY_TIMER
+  -D RGBLCD
+  -D CHARGE_LIMIT
+  -D TIME_LIMIT
+  -D TEMPERATURE_THROTTLING
+
+
 # v6 CGMI OpenEVSE
 [env:openevse_v6]
 extends = env:openevse
@@ -43,9 +63,9 @@ build_src_flags=
   -D NO_GROUND_RECORD_DELAY=2000
   -D NO_AUTOSVCLEVEL
   -D DEFAULT_SERVICE_LEVEL=2
+  -D OVERCURRENT_THRESHOLD=5
+  -D OVERCURRENT_TIMEOUT=10000UL
   -D BOOTLOCK
-  #-D BTN_MENU
-  #-D RTC
   -D 'VERSION="${common.version}.CGMI"'
 
 # EU OpenEVSE

From c9a056a5c7ea1ed5153627cd714f331d52db3583 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 12 Mar 2026 19:59:42 -0700
Subject: [PATCH 22/59] checkpoint - multi target samd/m328p

---
 .gitignore                                    |   2 +
 .../open_evse/AutoCurrentCapacityController.h |   2 +-
 firmware/open_evse/CHANGELOG                  |   2 +-
 firmware/open_evse/J1772EvseController.cpp    |  51 ++++--
 firmware/open_evse/main.cpp                   |  65 ++-----
 firmware/open_evse/open_evse.h                | 148 +++-------------
 firmware/open_evse/rapi_proc.cpp              |  31 ++--
 firmware/open_evse/rapi_proc.h                |   8 +-
 .../m328p}/Adafruit_TMP007.cpp                |   0
 .../m328p}/Adafruit_TMP007.h                  |   0
 firmware/{open_evse => targets/m328p}/Gfi.cpp |   1 +
 firmware/{open_evse => targets/m328p}/Gfi.h   |   0
 .../{open_evse => targets/m328p}/I2CIO.cpp    |   0
 firmware/{open_evse => targets/m328p}/I2CIO.h |   0
 .../m328p}/J1772Pilot.cpp                     |   0
 .../{open_evse => targets/m328p}/J1772Pilot.h |   0
 firmware/{open_evse => targets/m328p}/LCD.cpp |   0
 firmware/{open_evse => targets/m328p}/LCD.h   |   0
 .../m328p}/LiquidCrystal_I2C.cpp              |   0
 .../m328p}/LiquidCrystal_I2C.h                |   0
 .../m328p}/LiquidTWI2.cpp                     |   0
 .../{open_evse => targets/m328p}/LiquidTWI2.h |   0
 .../{open_evse => targets/m328p}/RTClib.cpp   |   0
 .../{open_evse => targets/m328p}/RTClib.h     |   0
 firmware/{variants => targets}/m328p/Wire.cpp |   0
 firmware/{variants => targets}/m328p/Wire.h   |   0
 .../{open_evse => targets/m328p}/flash.bat    |   0
 .../{open_evse => targets/m328p}/fuse.bat     |   0
 firmware/targets/m328p/pindefs.h              | 130 ++++++++++++++
 .../m328p/platformio.ini                      |  84 ++++-----
 .../{open_evse => targets/m328p}/strings.cpp  |   0
 .../{open_evse => targets/m328p}/strings.h    |   0
 .../variant.cpp => targets/m328p/target.cpp}  |  50 ++++--
 .../variant.h => targets/m328p/target.h}      |  42 ++++-
 firmware/{variants => targets}/m328p/twi.c    |   0
 firmware/{variants => targets}/m328p/twi.h    |   0
 firmware/targets/samd/Gfi.cpp                 | 111 ++++++++++++
 firmware/targets/samd/Gfi.h                   |  49 ++++++
 firmware/targets/samd/J1772Pilot.cpp          | 123 +++++++++++++
 firmware/targets/samd/J1772Pilot.h            |  40 +++++
 firmware/targets/samd/eeprom_emulation.h      |  10 ++
 firmware/targets/samd/pindefs.h               |  42 +++++
 firmware/targets/samd/platformio.ini          |  86 +++++++++
 firmware/targets/samd/samd_pins.h             | 163 ++++++++++++++++++
 firmware/targets/samd/target.cpp              |  70 ++++++++
 firmware/targets/samd/target.h                |  94 ++++++++++
 platformio.ini                                |  16 +-
 47 files changed, 1123 insertions(+), 297 deletions(-)
 rename firmware/{open_evse => targets/m328p}/Adafruit_TMP007.cpp (100%)
 rename firmware/{open_evse => targets/m328p}/Adafruit_TMP007.h (100%)
 rename firmware/{open_evse => targets/m328p}/Gfi.cpp (99%)
 rename firmware/{open_evse => targets/m328p}/Gfi.h (100%)
 rename firmware/{open_evse => targets/m328p}/I2CIO.cpp (100%)
 rename firmware/{open_evse => targets/m328p}/I2CIO.h (100%)
 rename firmware/{open_evse => targets/m328p}/J1772Pilot.cpp (100%)
 rename firmware/{open_evse => targets/m328p}/J1772Pilot.h (100%)
 rename firmware/{open_evse => targets/m328p}/LCD.cpp (100%)
 rename firmware/{open_evse => targets/m328p}/LCD.h (100%)
 rename firmware/{open_evse => targets/m328p}/LiquidCrystal_I2C.cpp (100%)
 rename firmware/{open_evse => targets/m328p}/LiquidCrystal_I2C.h (100%)
 rename firmware/{open_evse => targets/m328p}/LiquidTWI2.cpp (100%)
 rename firmware/{open_evse => targets/m328p}/LiquidTWI2.h (100%)
 rename firmware/{open_evse => targets/m328p}/RTClib.cpp (100%)
 rename firmware/{open_evse => targets/m328p}/RTClib.h (100%)
 rename firmware/{variants => targets}/m328p/Wire.cpp (100%)
 rename firmware/{variants => targets}/m328p/Wire.h (100%)
 rename firmware/{open_evse => targets/m328p}/flash.bat (100%)
 rename firmware/{open_evse => targets/m328p}/fuse.bat (100%)
 create mode 100644 firmware/targets/m328p/pindefs.h
 rename firmware/{variants => targets}/m328p/platformio.ini (70%)
 rename firmware/{open_evse => targets/m328p}/strings.cpp (100%)
 rename firmware/{open_evse => targets/m328p}/strings.h (100%)
 rename firmware/{variants/m328p/variant.cpp => targets/m328p/target.cpp} (78%)
 rename firmware/{variants/m328p/variant.h => targets/m328p/target.h} (85%)
 rename firmware/{variants => targets}/m328p/twi.c (100%)
 rename firmware/{variants => targets}/m328p/twi.h (100%)
 create mode 100644 firmware/targets/samd/Gfi.cpp
 create mode 100644 firmware/targets/samd/Gfi.h
 create mode 100644 firmware/targets/samd/J1772Pilot.cpp
 create mode 100644 firmware/targets/samd/J1772Pilot.h
 create mode 100644 firmware/targets/samd/eeprom_emulation.h
 create mode 100644 firmware/targets/samd/pindefs.h
 create mode 100644 firmware/targets/samd/platformio.ini
 create mode 100644 firmware/targets/samd/samd_pins.h
 create mode 100644 firmware/targets/samd/target.cpp
 create mode 100644 firmware/targets/samd/target.h

diff --git a/.gitignore b/.gitignore
index 1de75d79..a565f7a4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,5 @@
+.pio/**
+kicad/**
 download/**
 archive/**
 genrapi/**
diff --git a/firmware/open_evse/AutoCurrentCapacityController.h b/firmware/open_evse/AutoCurrentCapacityController.h
index 51bcd3f3..ce58f4cf 100644
--- a/firmware/open_evse/AutoCurrentCapacityController.h
+++ b/firmware/open_evse/AutoCurrentCapacityController.h
@@ -13,7 +13,7 @@
 // See LICENSE for a copy of the GNU General Public License or see
 // it online at <http://www.gnu.org/licenses/>.
 
-#include "variant.h"
+#include "open_evse.h"
 
 typedef struct pp_amps {
   uint16_t adcVal;
diff --git a/firmware/open_evse/CHANGELOG b/firmware/open_evse/CHANGELOG
index 82678909..5ac061f3 100644
--- a/firmware/open_evse/CHANGELOG
+++ b/firmware/open_evse/CHANGELOG
@@ -244,7 +244,7 @@ D5.0.1 20181018 SCL
 - added RELAY_AUTO_PWM code - not tested - needs PWM-capable pin to function
 	
 20180523 SCL
-- when RTC not defined, g++ bug pops out:
+- when HAVE_RTC not defined, g++ bug pops out:
 	open_evse:2384: error: unable to find a register to spill in class 'NO_REGS'
   -> add GPPBUGKLUDGE
 	
diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index c4dd53fb..e528f656 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -26,9 +26,6 @@ long g_CycleHalfStart;
 uint8_t g_CycleState;
 #endif
 
-//                                               A/B B/C C/D D DS
-THRESH_DATA J1772EVSEController::m_ThreshData = {875,780,690,0,260};
-
 J1772EVSEController g_EvseController;
 
 #ifdef AMMETER
@@ -66,11 +63,10 @@ void J1772EVSEController::readAmmeter()
   uint16_t last_sample;
   unsigned int sample_count = 0;
   for(unsigned long start = millis(); ((now_ms = millis()) - start) < CURRENT_SAMPLE_INTERVAL; ) {
-    // the A/d is 0 to 1023.
     uint16_t sample = adcCurrent.read();
     // If this isn't the first sample, and if the sign of the value differs from the
     // sign of the previous value, then count that as a zero crossing.
-    if (!is_first_sample && ((last_sample > 512) != (sample > 512))) {
+    if (!is_first_sample && ((last_sample > ADC_HALF) != (sample > ADC_HALF))) {
       // Once we've seen a zero crossing, don't look for one for a little bit.
       // It's possible that a little noise near zero could cause a two-sample
       // inversion.
@@ -146,7 +142,7 @@ uint32_t MovingAverage(uint32_t samp)
 #endif // AMMETER
 
 J1772EVSEController::J1772EVSEController() :
-  adcPilot(PILOT_PIN)
+  adcPilot(PILOT_SENSE_PIN)
 #ifdef CURRENT_PIN
   , adcCurrent(CURRENT_PIN)
 #endif
@@ -204,9 +200,13 @@ void J1772EVSEController::Reboot()
     wdt_delay(3000);
   }
 
+#ifdef TARGET_SAMD
+  NVIC_SystemReset();
+#else // !TARGET_SAMD
   // hardware reset by forcing watchdog to timeout
-  wdt_enable(WDTO_1S);   // enable watchdog timer
+  WDT_ENABLE_1S();   // enable watchdog timer
   delay(1500);
+#endif
 }
 
 
@@ -288,6 +288,10 @@ void J1772EVSEController::chargingOn()
   }
   else {
 #endif // OEV6
+
+#ifdef CHARGINGAC_REG
+    pinChargingAC.write(1);
+#endif
 #ifdef CHARGING_REG
     pinCharging.write(1);
 #endif
@@ -297,9 +301,6 @@ void J1772EVSEController::chargingOn()
 #ifdef OEV6
   }
 #endif // OEV6
-#ifdef CHARGINGAC_REG
-    pinChargingAC.write(1);
-#endif
 
   setVFlags(ECVF_CHARGING_ON);
   
@@ -689,8 +690,16 @@ uint8_t J1772EVSEController::doPost()
   }
 #endif //#ifdef SERDBG
 
+#ifdef CALIBRATE
+  while (1) {
+    CALIB_DATA cd;
+    Calibrate(&cd);
+}
 
-  m_Pilot.SetState(PILOT_STATE_P12); //check to see if EV is plugged in
+#endif // CALIBRATE
+
+
+  m_Pilot.SetState(PILOT_STATE_PWM); //check to see if EV is plugged in
 
   g_OBD.SetRedLed(1);
 #ifdef LCD16X2 //Adafruit RGB LCD
@@ -729,10 +738,10 @@ uint8_t J1772EVSEController::doPost()
     
     m_Pilot.SetState(PILOT_STATE_N12);
     if (reading >= m_ThreshData.m_ThreshAB) {  // IF EV is not connected its Okay to open the relay the do the L1/L2 and ground Check
-      
+
       // save state with both relays off - for stuck relay state
       RelayOff = ReadACPins();
-      
+
       // save state with Relay 1 on 
 #ifdef OEV6
       if (isV6()) {
@@ -750,7 +759,7 @@ uint8_t J1772EVSEController::doPost()
       pinChargingAC.write(1);
 #endif
 
-      delay(RelaySettlingTime);
+      wdt_delay(RelaySettlingTime);
       Relay1 = ReadACPins();
 
 #ifdef OEV6
@@ -1193,10 +1202,10 @@ void J1772EVSEController::Init()
 
 void J1772EVSEController::ReadPilot(uint16_t *plow,uint16_t *phigh)
 {
-  uint16_t pl = 1023;
+  uint16_t pl = ADC_MAX;
   uint16_t ph = 0;
 
-  // 1x = 114us 20x = 2.3ms 100x = 11.3ms
+  //  uint32_t sms = millis();
   for (int i=0;i < PILOT_LOOP_CNT;i++) {
     uint16_t reading = adcPilot.read();  // measures pilot voltage
     
@@ -1207,6 +1216,7 @@ void J1772EVSEController::ReadPilot(uint16_t *plow,uint16_t *phigh)
       pl = reading;
     }
   }
+  //  RAPI_SERIAL_PORT.print("pilotread ");RAPI_SERIAL_PORT.println(millis()-sms);
 
   if (m_Pilot.GetState() != PILOT_STATE_N12) {
     // update prev state
@@ -1245,9 +1255,10 @@ void J1772EVSEController::ReadPilot(uint16_t *plow,uint16_t *phigh)
 void J1772EVSEController::Update(uint8_t forcetransition)
 {
   uint16_t plow;
-  uint16_t phigh = 0xffff;
+  uint16_t phigh = ADC_MAX;
 
   unsigned long curms = millis();
+  WDT_RESET();
 
   if (m_EvseState == EVSE_STATE_DISABLED) {
     m_PrevEvseState = m_EvseState; // cancel state transition
@@ -1993,7 +2004,7 @@ void J1772EVSEController::Calibrate(PCALIB_DATA pcd)
   for (int l=0;l < 2;l++) {
     int reading;
     uint32_t tot = 0;
-    uint16_t plow = 1023;
+    uint16_t plow = ADC_MAX
     uint16_t phigh = 0;
     uint16_t avg = 0;
     m_Pilot.SetState(l ? PILOT_STATE_N12 : PILOT_STATE_P12);
@@ -2027,6 +2038,10 @@ void J1772EVSEController::Calibrate(PCALIB_DATA pcd)
       pavg = avg;
     }
   }
+
+  sprintf(g_sTmp,"p %d %d %d,n %d %d %d",pmax,pavg,pmin,nmax,navg,nmin);
+  RAPI_SERIAL_PORT.println(g_sTmp);
+
   pcd->m_pMax = pmax;
   pcd->m_pAvg = pavg;
   pcd->m_pMin = pmin;
diff --git a/firmware/open_evse/main.cpp b/firmware/open_evse/main.cpp
index 91899174..35d0d4d3 100644
--- a/firmware/open_evse/main.cpp
+++ b/firmware/open_evse/main.cpp
@@ -41,26 +41,8 @@
  * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  * Boston, MA 02111-1307, USA.
  */
-#include <avr/io.h>
-#include <avr/eeprom.h>
-#include <avr/wdt.h>
-#include <avr/pgmspace.h>
-#include <pins_arduino.h>
-#include "./Wire.h"
-#include "./RTClib.h"
 #include "open_evse.h"
 
-// if using I2CLCD_PCF8574 uncomment below line  and comment out LiquidTWI2.h above
-//#include "./LiquidCrystal_I2C.h"
-#ifdef TEMPERATURE_MONITORING
-  #ifdef MCP9808_IS_ON_I2C
-  #include "MCP9808.h"  //  adding the ambient temp sensor to I2C
-  #endif 
-  #ifdef TMP007_IS_ON_I2C
-  #include "./Adafruit_TMP007.h"   //  adding the TMP007 IR I2C sensor
-  #endif 
-#endif // TEMPERATURE_MONITORING
-
 
 #ifdef BTN_MENU
 SettingsMenu g_SettingsMenu;
@@ -126,7 +108,7 @@ Menu *g_SettingsMenuList[] = {
 Menu *g_SetupMenuList[] = {
 #ifdef NOSETUP_MENU
   &g_MaxCurrentMenu,
-#ifdef RTC
+#ifdef HAVE_RTC
   &g_RTCMenu,
 #endif
 #else // !NOSETUP_MENU
@@ -165,7 +147,7 @@ char g_sTmp[TMP_BUF_SIZE];
 OnboardDisplay g_OBD;
 
 // Instantiate RTC and Delay Timer - GoldServe
-#ifdef RTC
+#ifdef HAVE_RTC
 RTC_DS1307 g_RTC;
 
 #if defined(RAPI)
@@ -177,7 +159,7 @@ void GetRTC(char *buf) {
   sprintf(buf,"%d %d %d %d %d %d",t.year()-2000,t.month(),t.day(),t.hour(),t.minute(),t.second());
 }
 #endif // RAPI
-#endif // RTC
+#endif // HAVE_RTC
 #ifdef DELAYTIMER
 DelayTimer g_DelayTimer;
 #ifdef DELAYTIMER_MENU
@@ -205,17 +187,10 @@ AutoCurrentCapacityController g_ACCController;
 // *do not* call this before WDT_ENABLE() is called
 void wdt_delay(uint32_t ms)
 {
+  uint32_t startms = millis();
   do {
     WDT_RESET();
-    if (ms > WATCHDOG_TIMEOUT/2) {
-      delay(WATCHDOG_TIMEOUT/2);
-      ms -= WATCHDOG_TIMEOUT/2;
-    }
-    else {
-      delay(ms);
-      ms = 0;
-    }
-  } while(ms);
+  } while((millis()-startms) < ms);
 }
 
 static inline void wiresend(uint8_t x) {
@@ -251,18 +226,6 @@ char *u2a(unsigned long x,int8_t digits)
   return s;
 }
 
-// wdt_init turns off the watchdog timer after we use it
-// to reboot
-
-void wdt_init(void) __attribute__((naked,used)) __attribute__((section(".init3")));
-void wdt_init(void)
-{
-  MCUSR = 0;
-  wdt_disable();
-
-  return;
-}
-
 
 #ifdef TEMPERATURE_MONITORING
 
@@ -296,7 +259,7 @@ void TempMonitor::Read()
 #endif
 
        
-#ifdef RTC
+#ifdef HAVE_RTC
 #ifdef OPENEVSE_2
     m_DS3231_temperature = TEMPERATURE_NOT_INSTALLED;  // OpenEVSE II does not use the DS3231
 #else // !OPENEVSE_2
@@ -327,7 +290,7 @@ void TempMonitor::Read()
       m_DS3231_temperature = TEMPERATURE_NOT_INSTALLED;
     
 #endif // OPENEVSE_2
-#endif // RTC
+#endif // HAVE_RTC
 
     m_LastUpdate = curms;
   }
@@ -811,7 +774,7 @@ void OnboardDisplay::Update(int8_t updmode)
     }
 #endif // GFI
 
-#ifdef RTC
+#ifdef HAVE_RTC
     DateTime currentTime = g_RTC.now();
 #endif
 
@@ -883,7 +846,7 @@ void OnboardDisplay::Update(int8_t updmode)
 	}
 #endif
 
-#ifdef RTC	
+#ifdef HAVE_RTC	
 	if ( g_TempMonitor.m_DS3231_temperature != TEMPERATURE_NOT_INSTALLED) {
 	  sprintf(g_sTmp,tempfmt,g_TempMonitor.m_DS3231_temperature/10, abs(g_TempMonitor.m_DS3231_temperature % 10));      //  sensor built into the DS3231 RTC Chip
 	  LcdPrint(5,1,g_sTmp);
@@ -926,12 +889,12 @@ void OnboardDisplay::Update(int8_t updmode)
       int m = (elapsedTime % 3600) / 60;
       int s = elapsedTime % 60;
       sprintf(g_sTmp,"%02d:%02d:%02d",h,m,s);
-#ifdef RTC
+#ifdef HAVE_RTC
       g_sTmp[8]=' ';
       g_sTmp[9]=' ';
       g_sTmp[10]=' ';
       sprintf(g_sTmp+11,g_sHHMMfmt,currentTime.hour(),currentTime.minute());
-#endif //RTC
+#endif //HAVE_RTC
       LcdPrint(1,g_sTmp);
 #endif // KWH_RECORDING
 #ifdef TEMPERATURE_MONITORING
@@ -2413,12 +2376,14 @@ void DelayTimer::PrintTimerIcon(){
 void ProcessInputs()
 {
 #ifdef RAPI
+  WDT_RESET();
   RapiDoCmd();
 #endif
 #ifdef BTN_MENU
   g_BtnHandler.ChkBtn();
 #endif
 #ifdef TEMPERATURE_MONITORING
+  WDT_RESET();
   g_TempMonitor.Read();  //   update temperatures once per second
 #endif
 }
@@ -2480,12 +2445,14 @@ uint8_t StateTransitionReqFunc(uint8_t curPilotState,uint8_t newPilotState,uint8
 
 void setup()
 {
-  wdt_disable();
+  WDT_DISABLE();
   
   delay(400);  // give I2C devices time to be ready before running code that wants to initialize I2C devices.  Otherwise a hang can occur upon powerup.
   
   Serial.begin(SERIAL_BAUD);
 
+  initTarget();
+
 #ifdef BTN_MENU
   g_BtnHandler.init();
 #endif // BTN_MENU
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index 84ea0099..a78ee179 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -33,10 +33,10 @@
 
 #include <pins_arduino.h>
 #include "Wire.h"
-#include "variant.h"
 #include "i2caddr.h"
-
+#include "pindefs.h"
 #include "Arduino.h"
+#include "target.h"
 
 #define setBits(flags,bits) (flags |= (bits))
 #define clrBits(flags,bits) (flags &= ~(bits))
@@ -47,8 +47,6 @@
 
 #include "Language_default.h"   //Default language should always be included as bottom layer
 
-typedef unsigned long time_t;
-
 //Language preferences: Add your custom languagefile here. See Language_default.h for more info.
 //#include "Language_norwegian.h"
 
@@ -137,7 +135,7 @@ typedef unsigned long time_t;
 #define MCU_ID_LEN 10
 
 // enable watchdog timer
-#define WATCHDOG
+//#define WATCHDOG
 
 #ifdef PP_AUTO_AMPACITY
 #define STATE_TRANSITION_REQ_FUNC
@@ -193,6 +191,10 @@ extern AutoCurrentCapacityController g_ACCController;
 
 //#define HEARTBEAT_SUPERVISION // Heartbeat Supervision support
 
+#ifdef MENNEKES_LOCK
+#include "MennekesLock.h"
+#endif
+
 #ifdef AMMETER
 
 // if OVERCURRENT_THRESHOLD is defined, then EVSE will hard fault in
@@ -274,11 +276,11 @@ extern AutoCurrentCapacityController g_ACCController;
 #endif // RGBLCD
 #endif // BTN_MENU
 
-// Option for RTC and DelayTime
+// Option for HAVE_RTC and DelayTime
 // REQUIRES HARDWARE RTC: DS1307 or DS3231 connected via I2C
-//#define RTC // enable RTC & timer functions
+//#define HAVE_RTC // enable RTC & timer functions
 
-#ifdef RTC
+#ifdef HAVE_RTC
 // Option for Delay Timer - GoldServe
 #define DELAYTIMER
 
@@ -286,7 +288,7 @@ extern AutoCurrentCapacityController g_ACCController;
 #define DELAYTIMER_MENU
 #endif
 
-#else // !RTC
+#else // !HAVE_RTC
 // this weird error comes out if RTC not defined, due to a bug in g++
 //D:\git\open_evse\firmware\open_evse\open_evse.ino: In function 'ProcessInputs'//:
 //
@@ -302,7 +304,7 @@ extern AutoCurrentCapacityController g_ACCController;
 //
 ////        (subreg:QI (reg/f:HI 1065) 1)) C:\Users\Geek\AppData\Local\Temp\arduino_build_853681\sketch\rapi_proc.cpp:418 1 {pushqi1}
 #define GPPBUGKLUDGE
-#endif // RTC
+#endif // HAVE_RTC
 
 #ifdef OCPP
 #define AUTH_LOCK 1
@@ -310,21 +312,6 @@ extern AutoCurrentCapacityController g_ACCController;
 #endif // OCPP
 
 
-// if defined, this pin goes HIGH when the EVSE is sleeping, and LOW otherwise
-//#define SLEEP_STATUS_REG &PINB
-//#define SLEEP_STATUS_IDX 4
-
-#ifdef AUTH_LOCK
-// AUTH_LOCK_REG/IDX - use an input pin to control AUTH_LOCK instead of
-// manual function calls
-// digital pin is configured as input with internal pull-up enabled
-// EVSE is locked when input HIGH and unlocked when input LOW
-//#define AUTH_LOCK_REG &PINC
-//#define AUTH_LOCK_IDX 2
-#endif // AUTH_LOCK
-
-
-
 // for stability testing - shorter timeout/higher retry count
 //#define GFI_TESTING
 
@@ -429,7 +416,7 @@ extern AutoCurrentCapacityController g_ACCController;
 
 // WARNING: ALL DELAYS *MUST* BE SHORTER THAN THIS TIMER OR WE WILL GET INTO
 // AN INFINITE RESET LOOP
-#define WATCHDOG_TIMEOUT WDTO_2S
+#define WATCHDOG_TIMEOUT_MS (WATCHDOG_TIMEOUT_SEC * 1000UL)
 
 #define LCD_MAX_CHARS_PER_LINE 16
 
@@ -464,72 +451,6 @@ extern AutoCurrentCapacityController g_ACCController;
 
 //J1772EVSEController
 
-#define CURRENT_PIN 0 // analog current reading pin ADCx
-#define PILOT_PIN 1 // analog pilot voltage reading pin ADCx
-#define PP_PIN 2 // PP_READ - ADC2
-#ifdef VOLTMETER
-// N.B. Note, ADC2 is already used as PP_PIN so beware of potential clashes
-// voltmeter pin is ADC2 on OPENEVSE_2
-#define VOLTMETER_PIN 2 // analog AC Line voltage voltmeter pin ADCx
-#endif // VOLTMETER
-#ifdef OPENEVSE_2
-// This pin must match the last write to CHARGING_PIN, modulo a delay. If
-// it is low when CHARGING_PIN is high, that's a missing ground.
-// If it's high when CHARGING_PIN is low, that's a stuck relay.
-// Auto L1/L2 is done with the voltmeter.
-#define ACLINE1_REG &PIND // OpenEVSE II has only one AC test pin.
-#define ACLINE1_IDX 3
-
-#define CHARGING_REG &PIND // OpenEVSE II has just one relay pin.
-#define CHARGING_IDX 7 // OpenEVSE II has just one relay pin.
-#else // !OPENEVSE_2
-
- // TEST PIN 1 for L1/L2, ground and stuck relay
-#define ACLINE1_REG &PIND
-#define ACLINE1_IDX 3
- // TEST PIN 2 for L1/L2, ground and stuck relay
-#define ACLINE2_REG &PIND
-#define ACLINE2_IDX 4
-
-#define V6_CHARGING_PIN  5
-#define V6_CHARGING_PIN2 6
-
-// digital Relay trigger pin
-#define CHARGING_REG &PINB
-#define CHARGING_IDX 0
-// digital Relay trigger pin for second relay
-#define CHARGING2_REG &PIND
-#define CHARGING2_IDX 7
-//digital Charging pin for AC relay
-#define CHARGINGAC_REG &PINB
-#define CHARGINGAC_IDX 1
-
-// obsolete LED pin
-//#define RED_LED_REG &PIND
-//#define RED_LED_IDX 5
-// obsolete LED pin
-//#define GREEN_LED_REG &PINB
-//#define GREEN_LED_IDX 5
-#endif // OPENEVSE_2
-
-// N.B. if PAFC_PWM is enabled, then pilot pin can be PB1 or PB2
-// if using fast PWM (PAFC_PWM disabled) pilot pin *MUST* be PB2
-#define PILOT_REG &PINB
-#define PILOT_IDX 2
-
-#ifdef MENNEKES_LOCK
-// requires external 12V H-bridge driver such as Polulu 1451
-
-//D11 - MOSI
-#define MENNEKES_LOCK_PINA_REG &PINB
-#define MENNEKES_LOCK_PINA_IDX 3
-
-//D12 - MISO
-#define MENNEKES_LOCK_PINB_REG &PINB
-#define MENNEKES_LOCK_PINB_IDX 4
-#include "MennekesLock.h"
-#endif // MENNEKES_LOCK
-
 
 
 
@@ -604,25 +525,8 @@ extern AutoCurrentCapacityController g_ACCController;
 #define AC_SAMPLE_MS 20 // 1 cycle @ 60Hz = 16.6667ms @ 50Hz = 20ms
 
 
-// V6 has PD7 tied to ground
-#define V6_ID_REG D
-#define V6_ID_IDX 7
-
 #ifdef GFI
-#define GFI_INTERRUPT 0 // interrupt number 0 = PD2, 1 = PD3
-// interrupt number 0 = PD2, 1 = PD3
-#define GFI_REG &PIND
-#define GFI_IDX 2
-
 #ifdef GFI_SELFTEST
-// pin is supposed to be wrapped around the GFI CT 5+ times
-#define GFITEST_REG &PIND
-#define GFITEST_IDX 6
-// V6 GFI test pin PB0
-#define V6_GFITEST_REG &PINB
-#define V6_GFITEST_IDX 0
-
-
 
 #define GFI_TEST_CYCLES 60
 // GFI pulse should be 50% duty cycle
@@ -667,26 +571,20 @@ extern AutoCurrentCapacityController g_ACCController;
 #endif // I2CLCD_PCF8574
 #endif // RGBLCD || I2CLCD
 
-// button sensing pin
-#define BTN_REG &PINC
-#define BTN_IDX 3
 #define BTN_PRESS_SHORT 50  // ms
 #define BTN_PRESS_LONG 500 // ms
 #define BTN_PRESS_VERYLONG 10000
 
 
-#ifdef RTC
+#ifdef HAVE_RTC
 // Default start/stop timers for un-initialized EEPROMs.
 // Makes it easy to compile in default time without need to set it up the first time.
 #define DEFAULT_START_HOUR    0x00 //Start time: 00:05
 #define DEFAULT_START_MIN     0x05
 #define DEFAULT_STOP_HOUR     0x06 //End time: 6:55
 #define DEFAULT_STOP_MIN      0x37
-#endif // RTC
+#endif // HAVE_RTC
 
-// for J1772.ReadPilot()
-// 1x = 114us 20x = 2.3ms 100x = 11.3ms
-#define PILOT_LOOP_CNT 100
 
 #ifdef AMMETER
 // This multiplier is the number of milliamps per A/d converter unit.
@@ -832,14 +730,6 @@ typedef union union4b {
 
 //-- begin class definitions
 
-#ifdef WATCHDOG
-#define WDT_RESET() wdt_reset() // pat the dog
-#define WDT_ENABLE() wdt_enable(WATCHDOG_TIMEOUT)
-#else
-#define WDT_RESET()
-#define WDT_ENABLE()
-#endif // WATCHDOG
-
 // OnboardDisplay.m_bFlags
 #define OBDF_MONO_BACKLIGHT 0x01
 #define OBDF_AMMETER_DIRTY  0x80
@@ -977,9 +867,13 @@ class OnboardDisplay
 #endif // GFI
 
 #ifdef TEMPERATURE_MONITORING
-#include "./MCP9808.h"  //  adding the ambient temp sensor to I2C
-#include "./Adafruit_TMP007.h"   //  adding the TMP007 IR I2C sensor
 
+#ifdef MCP9808_IS_ON_I2C
+#include "MCP9808.h"  //  adding the ambient temp sensor to I2C
+#endif 
+#ifdef TMP007_IS_ON_I2C
+#include "./Adafruit_TMP007.h"   //  adding the TMP007 IR I2C sensor
+#endif 
 
 #define TEMPERATURE_NOT_INSTALLED -2560 // fake temp to return when hardware not installed
 #define TEMPMONITOR_UPDATE_INTERVAL 1000ul
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index 9d13645f..e49f54de 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -33,18 +33,6 @@
 const char RAPI_VER[] PROGMEM = RAPIVER;
 
 
-#ifdef MCU_ID_LEN
-// mcuid *must* be of size MCU_ID_LEN
-#include <avr/boot.h>
-void getMcuId(uint8_t *mcuid)
-{
-  for (int i=0;i < MCU_ID_LEN;i++) {
-    mcuid[i] = boot_signature_byte_get(0x0E + i);
-  }
-}
-#endif // MCU_ID_LEN
-
-
 // convert 2-digit hex string to uint8_t
 uint8_t htou8(const char *s)
 {
@@ -162,7 +150,7 @@ void EvseRapiProcessor::sendBootNotification()
 
 void EvseRapiProcessor::sendEvseState()
 {
-    sprintf(g_sTmp,"%cAT %02x %02x %d %04x",ESRAPI_SOC,g_EvseController.GetState(),g_EvseController.GetPilotState(),g_EvseController.GetCurrentCapacity(),g_EvseController.GetVFlags());
+  sprintf(g_sTmp,"%cAT %02x %02x %d %04x",ESRAPI_SOC,g_EvseController.GetState(),g_EvseController.GetPilotState(),g_EvseController.GetCurrentCapacity(),g_EvseController.GetVFlags());
   appendChk(g_sTmp);
   writeStart();
   write(g_sTmp);
@@ -402,7 +390,7 @@ int EvseRapiProcessor::processCmd()
       }
       break;
 #endif // LCD16X2
-#ifdef RTC
+#ifdef HAVE_RTC
     case '1': // set RTC
       if (tokenCnt == 7) {
 	extern void SetRTC(uint8_t y,uint8_t m,uint8_t d,uint8_t h,uint8_t mn,uint8_t s);
@@ -411,7 +399,7 @@ int EvseRapiProcessor::processCmd()
 	rc = 0;
       }
       break;
-#endif // RTC
+#endif // HAVE_RTC
 #if defined(AMMETER) && defined(ECVF_AMMETER_CAL)
     case '2': // ammeter calibration mode
       if (tokenCnt == 2) {
@@ -799,18 +787,22 @@ int EvseRapiProcessor::processCmd()
       u1.u8 = g_EvseController.GetState();
       u2.u8 = g_EvseController.GetPilotState();
       u3.u16 = g_EvseController.GetVFlags();
+#ifdef TARGET_M328P
       sprintf(buffer,"%02x %ld %02x %04x",u1.u8,g_EvseController.GetElapsedChargeTime(),u2.u8,u3.u16);
+#else
+      sprintf(buffer,"%02x %ld %02x %04x",u1.u8,(long int)g_EvseController.GetElapsedChargeTime(),u2.u8,u3.u16);
+#endif
       bufCnt = 1; // flag response text output
       rc = 0;
       break;
-#ifdef RTC
+#ifdef HAVE_RTC
     case 'T': // get time
       extern void GetRTC(char *buf);
       GetRTC(buffer);
       bufCnt = 1; // flag response text output
       rc = 0;
       break;
-#endif // RTC
+#endif // HAVE_RTC
 #ifdef KWH_RECORDING
     case 'U':
       sprintf(buffer,"%lu %lu",g_EnergyMeter.GetSessionWs(),g_EnergyMeter.GetTotkWh());
@@ -853,7 +845,7 @@ int EvseRapiProcessor::processCmd()
     }
     break;
 #endif //RAPI_T_COMMANDS
-#if defined(RELAY_HOLD_DELAY_TUNING)
+#if defined(RELAY_PWM) && defined(RELAY_HOLD_DELAY_TUNING)
   case 'Z': // reserved op
     switch(*s) {
     case '0': // set relayCloseMs
@@ -1053,6 +1045,7 @@ EvseSerialRapiProcessor::EvseSerialRapiProcessor()
 
 void EvseSerialRapiProcessor::init()
 {
+  RAPI_SERIAL_PORT.begin(SERIAL_BAUD);
   EvseRapiProcessor::init();
 }
 #endif // RAPI_SERIAL
@@ -1085,11 +1078,11 @@ EvseI2cRapiProcessor g_EIRP;
 void RapiInit()
 {
 #ifdef RAPI_SERIAL
-  g_ESRP.init();
 #ifdef GPPBUGKLUDGE
   static char g_rapiSerialBuffer[ESRAPI_BUFLEN];
   g_ESRP.setBuffer(g_rapiSerialBuffer);
 #endif // GPPBUGKLUDGE
+  g_ESRP.init();
 #endif // RAPI_SERIAL
 #ifdef RAPI_I2C
   g_EIRP.init();
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index 4f7edb87..e0f49804 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -457,10 +457,10 @@ class EvseRapiProcessor {
 
 #ifdef RAPI_SERIAL
 class EvseSerialRapiProcessor : public EvseRapiProcessor {
-  int available() { return Serial.available(); }
-  int read() { return Serial.read(); }
-  int write(uint8_t u8) { return Serial.write(u8); }
-  int write(const char *str) { return Serial.write(str); }
+  int available() { return RAPI_SERIAL_PORT.available(); }
+  int read() { return RAPI_SERIAL_PORT.read(); }
+  int write(uint8_t u8) { return RAPI_SERIAL_PORT.write(u8); }
+  int write(const char *str) { return RAPI_SERIAL_PORT.write(str); }
 
 public:
   EvseSerialRapiProcessor();
diff --git a/firmware/open_evse/Adafruit_TMP007.cpp b/firmware/targets/m328p/Adafruit_TMP007.cpp
similarity index 100%
rename from firmware/open_evse/Adafruit_TMP007.cpp
rename to firmware/targets/m328p/Adafruit_TMP007.cpp
diff --git a/firmware/open_evse/Adafruit_TMP007.h b/firmware/targets/m328p/Adafruit_TMP007.h
similarity index 100%
rename from firmware/open_evse/Adafruit_TMP007.h
rename to firmware/targets/m328p/Adafruit_TMP007.h
diff --git a/firmware/open_evse/Gfi.cpp b/firmware/targets/m328p/Gfi.cpp
similarity index 99%
rename from firmware/open_evse/Gfi.cpp
rename to firmware/targets/m328p/Gfi.cpp
index 470f2ab4..aacf0b85 100644
--- a/firmware/open_evse/Gfi.cpp
+++ b/firmware/targets/m328p/Gfi.cpp
@@ -79,6 +79,7 @@ uint8_t Gfi::SelfTest()
 
   testInProgress = 1;
   testSuccess = 0;
+  WDT_RESET();
   for(int i=0; !testSuccess && (i < GFI_TEST_CYCLES); i++) {
     pinTest.write(1);
     delayMicroseconds(GFI_PULSE_ON_US);
diff --git a/firmware/open_evse/Gfi.h b/firmware/targets/m328p/Gfi.h
similarity index 100%
rename from firmware/open_evse/Gfi.h
rename to firmware/targets/m328p/Gfi.h
diff --git a/firmware/open_evse/I2CIO.cpp b/firmware/targets/m328p/I2CIO.cpp
similarity index 100%
rename from firmware/open_evse/I2CIO.cpp
rename to firmware/targets/m328p/I2CIO.cpp
diff --git a/firmware/open_evse/I2CIO.h b/firmware/targets/m328p/I2CIO.h
similarity index 100%
rename from firmware/open_evse/I2CIO.h
rename to firmware/targets/m328p/I2CIO.h
diff --git a/firmware/open_evse/J1772Pilot.cpp b/firmware/targets/m328p/J1772Pilot.cpp
similarity index 100%
rename from firmware/open_evse/J1772Pilot.cpp
rename to firmware/targets/m328p/J1772Pilot.cpp
diff --git a/firmware/open_evse/J1772Pilot.h b/firmware/targets/m328p/J1772Pilot.h
similarity index 100%
rename from firmware/open_evse/J1772Pilot.h
rename to firmware/targets/m328p/J1772Pilot.h
diff --git a/firmware/open_evse/LCD.cpp b/firmware/targets/m328p/LCD.cpp
similarity index 100%
rename from firmware/open_evse/LCD.cpp
rename to firmware/targets/m328p/LCD.cpp
diff --git a/firmware/open_evse/LCD.h b/firmware/targets/m328p/LCD.h
similarity index 100%
rename from firmware/open_evse/LCD.h
rename to firmware/targets/m328p/LCD.h
diff --git a/firmware/open_evse/LiquidCrystal_I2C.cpp b/firmware/targets/m328p/LiquidCrystal_I2C.cpp
similarity index 100%
rename from firmware/open_evse/LiquidCrystal_I2C.cpp
rename to firmware/targets/m328p/LiquidCrystal_I2C.cpp
diff --git a/firmware/open_evse/LiquidCrystal_I2C.h b/firmware/targets/m328p/LiquidCrystal_I2C.h
similarity index 100%
rename from firmware/open_evse/LiquidCrystal_I2C.h
rename to firmware/targets/m328p/LiquidCrystal_I2C.h
diff --git a/firmware/open_evse/LiquidTWI2.cpp b/firmware/targets/m328p/LiquidTWI2.cpp
similarity index 100%
rename from firmware/open_evse/LiquidTWI2.cpp
rename to firmware/targets/m328p/LiquidTWI2.cpp
diff --git a/firmware/open_evse/LiquidTWI2.h b/firmware/targets/m328p/LiquidTWI2.h
similarity index 100%
rename from firmware/open_evse/LiquidTWI2.h
rename to firmware/targets/m328p/LiquidTWI2.h
diff --git a/firmware/open_evse/RTClib.cpp b/firmware/targets/m328p/RTClib.cpp
similarity index 100%
rename from firmware/open_evse/RTClib.cpp
rename to firmware/targets/m328p/RTClib.cpp
diff --git a/firmware/open_evse/RTClib.h b/firmware/targets/m328p/RTClib.h
similarity index 100%
rename from firmware/open_evse/RTClib.h
rename to firmware/targets/m328p/RTClib.h
diff --git a/firmware/variants/m328p/Wire.cpp b/firmware/targets/m328p/Wire.cpp
similarity index 100%
rename from firmware/variants/m328p/Wire.cpp
rename to firmware/targets/m328p/Wire.cpp
diff --git a/firmware/variants/m328p/Wire.h b/firmware/targets/m328p/Wire.h
similarity index 100%
rename from firmware/variants/m328p/Wire.h
rename to firmware/targets/m328p/Wire.h
diff --git a/firmware/open_evse/flash.bat b/firmware/targets/m328p/flash.bat
similarity index 100%
rename from firmware/open_evse/flash.bat
rename to firmware/targets/m328p/flash.bat
diff --git a/firmware/open_evse/fuse.bat b/firmware/targets/m328p/fuse.bat
similarity index 100%
rename from firmware/open_evse/fuse.bat
rename to firmware/targets/m328p/fuse.bat
diff --git a/firmware/targets/m328p/pindefs.h b/firmware/targets/m328p/pindefs.h
new file mode 100644
index 00000000..d3d04d79
--- /dev/null
+++ b/firmware/targets/m328p/pindefs.h
@@ -0,0 +1,130 @@
+//#define PZEM_RX_PIN MISO // ICSP 1
+//#define PZEM_TX_PIN MOSI // ICSP 4
+//#define PZEM_RX_PIN 9 // AUX_B = PB1
+//#define PZEM_TX_PIN A3 // AUX_A = PC3
+
+// V6 has PD7 tied to ground
+#define V6_ID_REG D
+#define V6_ID_IDX 7
+
+#define GFI_INTERRUPT 0 // interrupt number 0 = PD2, 1 = PD3
+// interrupt number 0 = PD2, 1 = PD3
+#define GFI_REG &PIND
+#define GFI_IDX 2
+
+// pin is supposed to be wrapped around the GFI CT 5+ times
+// pin is supposed to be wrapped around the GFI CT 5+ times
+#define GFITEST_REG &PIND
+#define GFITEST_IDX 6
+// V6 GFI test pin PB0
+#define V6_GFITEST_REG &PINB
+#define V6_GFITEST_IDX 0
+
+
+// button sensing pin
+#define BTN_REG &PINC
+#define BTN_IDX 3
+
+
+//J1772EVSEController
+#define CURRENT_PIN 0 // analog current reading pin ADCx
+#define PILOT_SENSE_PIN 1 // analog pilot voltage reading pin ADCx
+#define PP_PIN 2 // PP_READ - ADC2
+
+ // TEST PIN 1 for L1/L2, ground and stuck relay
+#define ACLINE1_REG &PIND
+#define ACLINE1_IDX 3
+// TEST PIN 2 for L1/L2, ground and stuck relay
+#define ACLINE2_REG &PIND
+#define ACLINE2_IDX 4
+
+#ifdef OEV6
+// digital Relay trigger pin
+#define CHARGING_REG &PIND
+#define CHARGING_IDX 5
+// digital Relay trigger pin for second relay
+//#define CHARGING2_REG &PIND
+//#define CHARGING2_IDX 6
+#else // !OEV6
+// digital Relay trigger pin
+#define CHARGING_REG &PINB
+#define CHARGING_IDX 0
+// digital Relay trigger pin for second relay - OE1 only
+//#define CHARGING2_REG &PIND
+//#define CHARGING2_IDX 7
+#endif // OEV6
+
+#ifdef VOLTMETER
+// N.B. Note, ADC2 is already used as PP_PIN so beware of potential clashes
+// voltmeter pin is ADC2 on OPENEVSE_2
+#define VOLTMETER_PIN 2 // analog AC Line voltage voltmeter pin ADCx
+#endif // VOLTMETER
+
+#ifdef OPENEVSE_2
+// This pin must match the last write to CHARGING_PIN, modulo a delay. If
+// it is low when CHARGING_PIN is high, that's a missing ground.
+// If it's high when CHARGING_PIN is low, that's a stuck relay.
+// Auto L1/L2 is done with the voltmeter.
+#define ACLINE1_REG &PIND // OpenEVSE II has only one AC test pin.
+#define ACLINE1_IDX 3
+
+#define CHARGING_REG &PIND // OpenEVSE II has just one relay pin.
+#define CHARGING_IDX 7 // OpenEVSE II has just one relay pin.
+#else // !OPENEVSE_2
+
+ // TEST PIN 1 for L1/L2, ground and stuck relay
+#define ACLINE1_REG &PIND
+#define ACLINE1_IDX 3
+ // TEST PIN 2 for L1/L2, ground and stuck relay
+#define ACLINE2_REG &PIND
+#define ACLINE2_IDX 4
+
+#define V6_CHARGING_PIN  5
+#define V6_CHARGING_PIN2 6
+
+// digital Relay trigger pin for second relay
+#define CHARGING2_REG &PIND
+#define CHARGING2_IDX 7
+//digital Charging pin for AC relay
+#define CHARGINGAC_REG &PINB
+#define CHARGINGAC_IDX 1
+
+// obsolete LED pin
+//#define RED_LED_REG &PIND
+//#define RED_LED_IDX 5
+// obsolete LED pin
+//#define GREEN_LED_REG &PINB
+//#define GREEN_LED_IDX 5
+#endif // OPENEVSE_2
+
+// N.B. if PAFC_PWM is enabled, then pilot pin can be PB1 or PB2
+// if using fast PWM (PAFC_PWM disabled) pilot pin *MUST* be PB2
+#define PILOT_REG &PINB
+#define PILOT_IDX 2
+
+#ifdef MENNEKES_LOCK
+// requires external 12V H-bridge driver such as Polulu 1451
+
+//D11 - MOSI
+#define MENNEKES_LOCK_PINA_REG &PINB
+#define MENNEKES_LOCK_PINA_IDX 3
+
+//D12 - MISO
+#define MENNEKES_LOCK_PINB_REG &PINB
+#define MENNEKES_LOCK_PINB_IDX 4
+#endif // MENNEKES_LOCK
+
+
+// if defined, this pin goes HIGH when the EVSE is sleeping, and LOW otherwise
+//#define SLEEP_STATUS_REG &PINB
+//#define SLEEP_STATUS_IDX 4
+
+#ifdef AUTH_LOCK
+// AUTH_LOCK_REG/IDX - use an input pin to control AUTH_LOCK instead of
+// manual function calls
+// digital pin is configured as input with internal pull-up enabled
+// EVSE is locked when input HIGH and unlocked when input LOW
+//#define AUTH_LOCK_REG &PINC
+//#define AUTH_LOCK_IDX 2
+#endif // AUTH_LOCK
+
diff --git a/firmware/variants/m328p/platformio.ini b/firmware/targets/m328p/platformio.ini
similarity index 70%
rename from firmware/variants/m328p/platformio.ini
rename to firmware/targets/m328p/platformio.ini
index d1e7e173..b4e7949a 100644
--- a/firmware/variants/m328p/platformio.ini
+++ b/firmware/targets/m328p/platformio.ini
@@ -2,61 +2,29 @@
 [m328p]
 upload_protocol = usbasp
 upload_flags = "-e -B0.5"
+lib_deps = ${common.lib_deps}
 build_src_flags =
-  -I firmware/variants/m328p
+  -D TARGET_M328P
+  -D RAPI_SERIAL_PORT=Serial
+  -D OEV6
+  -D RELAY_PWM
+  -D SHOW_DISABLED_TESTS
+  -I firmware/targets/m328p
   ${common.us_build_flags}
 build_src_filter =
   ${common.build_src_filter}
-  +<../variants/m328p>
+  +<../targets/m328p>
 
-[env:openevse_latest]
-platform = atmelavr
-board = openevse
-framework = arduino
-lib_deps = ${common.lib_deps}
-upload_protocol = ${m328p.upload_protocol}
-upload_flags = ${m328p.upload_flags}
-build_src_flags=
-  ${common.us_build_flags}
-  ${m328p.build_src_flags}
-  -D 'VERSION="${common.version}"'
-
-[env:openevse]
+# v6 CGMI OpenEVSE
+[env:m328p_v6]
 platform = atmelavr@3.4.0
 board = openevse
 framework = arduino
-lib_deps = ${common.lib_deps}
 upload_protocol = ${m328p.upload_protocol}
 upload_flags = ${m328p.upload_flags}
+lib_deps = ${m328p.lib_deps}
 build_src_filter =
   ${m328p.build_src_filter}
-build_src_flags=
-  ${m328p.build_src_flags}
-  -D 'VERSION="${common.version}"'
-
-# openevse with 16x2 RGBLCD and front panel button
-[env:openevse_rgblcd]
-extends = env:openevse
-build_src_flags=
-  ${m328p.build_src_flags}
-  -UOEV6
-  -UHEARTBEAT_SUPERVISION
-  -UBOOTLOCK
-  -D ENABLE_CGMI
-  -D OVERCURRENT_THRESHOLD=5
-  -D OVERCURRENT_TIMEOUT=10000UL
-  -D BTN_MENU
-  -D RTC
-  -D DELAY_TIMER
-  -D RGBLCD
-  -D CHARGE_LIMIT
-  -D TIME_LIMIT
-  -D TEMPERATURE_THROTTLING
-
-
-# v6 CGMI OpenEVSE
-[env:openevse_v6]
-extends = env:openevse
 build_src_flags=
   ${m328p.build_src_flags}
   -D ENABLE_CGMI
@@ -69,8 +37,8 @@ build_src_flags=
   -D 'VERSION="${common.version}.CGMI"'
 
 # EU OpenEVSE
-[env:openevse_eu]
-extends = env:openevse
+[env:m328p_eu]
+extends = env:m328p_v6
 build_src_flags=
   ${m328p.build_src_flags}
   ${common.eu_build_flags}
@@ -78,8 +46,8 @@ build_src_flags=
   -D 'VERSION="${common.version}.EU"'
 
 # Non-tethered T2 EmonEVSE single-phase
-[env:emonevse]
-extends = env:openevse
+[env:m328p_emonevse]
+extends = env:m328p_v6
 build_src_flags=
   ${m328p.build_src_flags}
   ${common.eu_build_flags}
@@ -87,10 +55,30 @@ build_src_flags=
   -D MV_FOR_L2=230000L
   -D 'VERSION="${common.version}.T2"'
 
+# legacy openevse with 16x2 RGBLCD and front panel button
+[env:m328p_rgblcd]
+extends = env:m328p_v6
+build_src_flags=
+  ${m328p.build_src_flags}
+  -UOEV6
+  -UHEARTBEAT_SUPERVISION
+  -UBOOTLOCK
+  -D ENABLE_CGMI
+  -D OVERCURRENT_THRESHOLD=5
+  -D OVERCURRENT_TIMEOUT=10000UL
+  -D BTN_MENU
+  -D HAVE_RTC
+  -D DELAY_TIMER
+  -D RGBLCD
+  -D CHARGE_LIMIT
+  -D TIME_LIMIT
+  -D TEMPERATURE_THROTTLING
+  -D 'VERSION="${common.version}"'
+
 # Non-tethered T2 EmonEVSE three-phase
 # Deprecated, unneeded with wifi fw > 4.1.7
 ; [env:emonevse_3ph]
-; extends = env:openevse
+; extends = env:m328p
 ; build_src_flags=
 ;   ${common.eu_build_flags}
 ;   -D PP_AUTO_AMPACITY
diff --git a/firmware/open_evse/strings.cpp b/firmware/targets/m328p/strings.cpp
similarity index 100%
rename from firmware/open_evse/strings.cpp
rename to firmware/targets/m328p/strings.cpp
diff --git a/firmware/open_evse/strings.h b/firmware/targets/m328p/strings.h
similarity index 100%
rename from firmware/open_evse/strings.h
rename to firmware/targets/m328p/strings.h
diff --git a/firmware/variants/m328p/variant.cpp b/firmware/targets/m328p/target.cpp
similarity index 78%
rename from firmware/variants/m328p/variant.cpp
rename to firmware/targets/m328p/target.cpp
index 027c8b43..51facb69 100644
--- a/firmware/variants/m328p/variant.cpp
+++ b/firmware/targets/m328p/target.cpp
@@ -1,18 +1,33 @@
-// Copyright (C) 2015 Sam C. Lin
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// See LICENSE for a copy of the GNU General Public License or see
-// it online at <http://www.gnu.org/licenses/>.
+#include "open_evse.h"
+
+
+// wdt_init turns off the watchdog timer after we use it
+// to reboot
+
+#ifdef MCU_ID_LEN
+// mcuid *must* be of size MCU_ID_LEN
+#include <avr/boot.h>
+void getMcuId(uint8_t *mcuid)
+{
+  for (int i=0;i < MCU_ID_LEN;i++) {
+    mcuid[i] = boot_signature_byte_get(0x0E + i);
+  }
+}
+#endif // MCU_ID_LEN
+
+
+void wdt_init(void) __attribute__((naked,used)) __attribute__((section(".init3")));
+void wdt_init(void)
+{
+  MCUSR = 0;
+  wdt_disable();
+
+  return;
+}
+
+//                                               A/B B/C C/D D DS
+THRESH_DATA J1772EVSEController::m_ThreshData = {875,780,690,0,260};
 
-#include "variant.h"
 
 void DigitalPin::init(volatile uint8_t* _reg,uint8_t idx,PinMode _mode)
 {
@@ -105,3 +120,10 @@ uint16_t AdcPin::read()
   // combine the two bytes
   return (high << 8) | low;
 }
+
+
+// platform-specific init
+void initTarget()
+{
+
+}
diff --git a/firmware/variants/m328p/variant.h b/firmware/targets/m328p/target.h
similarity index 85%
rename from firmware/variants/m328p/variant.h
rename to firmware/targets/m328p/target.h
index 93bdee26..cd582b3f 100644
--- a/firmware/variants/m328p/variant.h
+++ b/firmware/targets/m328p/target.h
@@ -14,16 +14,31 @@
 // it online at <http://www.gnu.org/licenses/>.
 
 #pragma once
+#include <avr/io.h>
+#include <avr/eeprom.h>
+#include <avr/wdt.h>
+#include <avr/pgmspace.h>
+#include <pins_arduino.h>
 #include <avr/wdt.h>
 #include <avr/pgmspace.h>
 #include <avr/eeprom.h>
 #include <avr/io.h>
 #include <avr/interrupt.h>
-#if defined(ARDUINO) && (ARDUINO >= 100)
 #include "Arduino.h"
-#else
-#include "WProgram.h" // shouldn't need this but arduino sometimes messes up and puts inside an #ifdef
-#endif // ARDUINO
+#include "./Wire.h"
+#include "./RTClib.h"
+
+
+#define ADC_RESOLUTION_BITS 10
+#define ADC_MAX 1023
+#define ADC_HALF 512
+
+// for J1772.ReadPilot()
+// 1x = 114us 20x = 2.3ms 100x = 11.3ms
+#define PILOT_LOOP_CNT 100
+
+
+typedef unsigned long time_t;
 
 #ifdef __cplusplus
 class CriticalSection {
@@ -91,6 +106,24 @@ example
 
 #ifdef __cplusplus
 
+void getMcuId(uint8_t *mcuid);
+
+#if WATCHDOG_TIMEOUT_SEC != 2
+#error "unsupported WATCHDOG_TIMEOUT_SEC value"
+#endif
+
+#ifdef WATCHDOG
+#define WDT_RESET() wdt_reset()
+#define WDT_ENABLE() wdt_enable(WDTO_2S)
+#define WDT_ENABLE_1S() wdt_enable(WDTO_1S)
+#define WDT_DISABLE() wdt_disable()
+#else
+#define WDT_RESET()
+#define WDT_ENABLE()
+#define WDT_ENABLE_1S()
+#define WDT_DISABLE()
+#endif // WATCHDOG
+
 //
 // begin digitalPin class
 // using this class beautifies the code, but wastes 3 bytes per pin
@@ -183,4 +216,5 @@ class Led {
 // end digital pin class
 //
 
+void initTarget();
 #endif // __cplusplus
diff --git a/firmware/variants/m328p/twi.c b/firmware/targets/m328p/twi.c
similarity index 100%
rename from firmware/variants/m328p/twi.c
rename to firmware/targets/m328p/twi.c
diff --git a/firmware/variants/m328p/twi.h b/firmware/targets/m328p/twi.h
similarity index 100%
rename from firmware/variants/m328p/twi.h
rename to firmware/targets/m328p/twi.h
diff --git a/firmware/targets/samd/Gfi.cpp b/firmware/targets/samd/Gfi.cpp
new file mode 100644
index 00000000..070114cd
--- /dev/null
+++ b/firmware/targets/samd/Gfi.cpp
@@ -0,0 +1,111 @@
+/*
+ * This file is part of Open EVSE.
+ *
+ * Copyright (c) 2011-2019 Sam C. Lin
+ *
+ * Open EVSE is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+
+ * Open EVSE is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with Open EVSE; see the file COPYING.  If not, write to the
+ * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * Boston, MA 02111-1307, USA.
+ */
+#include "open_evse.h"
+
+#ifdef GFI
+// interrupt service routing
+void gfi_isr()
+{
+  g_EvseController.SetGfiTripped();
+}
+
+
+void Gfi::Init(uint8_t v6)
+{
+  pin.init(GFI_REG,GFI_IDX,DigitalPin::INP);
+  // GFI triggers on rising edge
+  attachInterrupt(digitalPinToInterrupt(GFI_REG),gfi_isr,RISING);
+
+#ifdef GFI_SELFTEST
+  uint32_t reg = GFITEST_REG;
+  uint32_t idx  = GFITEST_IDX;
+
+  pinTest.init(reg,idx,DigitalPin::OUT);
+#endif // GFI_SELFTEST
+
+  Reset();
+}
+
+
+//RESET GFI LOGIC
+void Gfi::Reset()
+{
+  WDT_RESET();
+
+#ifdef GFI_SELFTEST
+  testInProgress = 0;
+  testSuccess = 0;
+#endif // GFI_SELFTEST
+
+  if (pin.read()) m_GfiFault = 1; // if interrupt pin is high, set fault
+  else m_GfiFault = 0;
+}
+
+#ifdef GFI_SELFTEST
+
+uint8_t Gfi::SelfTest()
+{
+  int i;
+  // wait for GFI pin to clear
+  for (i=0;i < 20;i++) {
+    WDT_RESET();
+    if (!pin.read()) break;
+    delay(50);
+  }
+  if (i == 20) return 2;
+
+  testInProgress = 1;
+  testSuccess = 0;
+  WDT_RESET();
+  //  uint32_t sms = millis();
+  for(int i=0; !testSuccess && (i < 200); i++) {
+    pinTest.write(1);
+    delayMicroseconds(GFI_PULSE_ON_US);
+    pinTest.write(0);
+    delayMicroseconds(GFI_PULSE_OFF_US);
+  }
+  //  RAPI_SERIAL_PORT.print("GFI ");RAPI_SERIAL_PORT.println(millis()-sms);
+
+  // wait for GFI pin to clear
+  for (i=0;i < 40;i++) {
+    WDT_RESET();
+    if (!pin.read()) break;
+    delay(50);
+  }
+  if (i == 40) return 3;
+
+
+#ifdef dontneed
+  // sometimes getting spurious GFI faults when testing just before closing
+  // relay.
+  // wait a little more for everything to settle down
+  // this delay is needed only if 10uF cap is in the circuit, which makes the circuit
+  // temporarily overly sensitive to trips until it discharges
+  wdt_delay(1000);
+#endif 
+
+  m_GfiFault = 0;
+  testInProgress = 0;
+
+  return !testSuccess;
+}
+#endif // GFI_SELFTEST
+#endif // GFI
diff --git a/firmware/targets/samd/Gfi.h b/firmware/targets/samd/Gfi.h
new file mode 100644
index 00000000..289c8841
--- /dev/null
+++ b/firmware/targets/samd/Gfi.h
@@ -0,0 +1,49 @@
+/*
+ * Open EVSE Firmware
+ *
+ * This file is part of Open EVSE.
+ *
+ * Copyright (c) 2011-2019 Sam C. Lin
+ *
+ * Open EVSE is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+
+ * Open EVSE is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with Open EVSE; see the file COPYING.  If not, write to the
+ * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * Boston, MA 02111-1307, USA.
+ */
+#pragma once
+
+class Gfi {
+  DigitalPin pin;
+  uint8_t m_GfiFault;
+#ifdef GFI_SELFTEST
+  volatile uint8_t testSuccess;
+  uint8_t testInProgress;
+#endif // GFI_SELFTEST
+public:
+#ifdef GFI_SELFTEST
+  DigitalPin pinTest;
+#endif
+
+  Gfi() {}
+
+  void Init(uint8_t v6=0);
+  void Reset();
+  void SetFault() { m_GfiFault = 1; }
+  uint8_t Fault() { return m_GfiFault; }
+#ifdef GFI_SELFTEST
+  uint8_t SelfTest();
+  void SetTestSuccess() { testSuccess = 1; }
+  uint8_t SelfTestSuccess() { return testSuccess; }
+  uint8_t SelfTestInProgress() { return testInProgress; }
+#endif
+};
diff --git a/firmware/targets/samd/J1772Pilot.cpp b/firmware/targets/samd/J1772Pilot.cpp
new file mode 100644
index 00000000..329cfd34
--- /dev/null
+++ b/firmware/targets/samd/J1772Pilot.cpp
@@ -0,0 +1,123 @@
+#include "open_evse.h"
+#include <wiring_private.h>
+
+static constexpr uint32_t kPilotTop = 47999; // 48MHz / 1 / (47999 + 1) = 1kHz
+
+void J1772Pilot::pwmEnable(bool tf)
+{
+  if (tf) {
+  // configure PWM
+  pinPeripheral(PILOT_REG, PIO_TIMER_ALT); // PA18 -> TCC0/WO[2]
+
+  PM->APBCMASK.reg |= PM_APBCMASK_TCC0;
+
+  GCLK->CLKCTRL.reg = (uint16_t)(GCLK_CLKCTRL_CLKEN |
+                                 GCLK_CLKCTRL_GEN_GCLK0 |
+                                 GCLK_CLKCTRL_ID_TCC0_TCC1);
+  while (GCLK->STATUS.bit.SYNCBUSY) {
+  }
+
+  TCC0->CTRLA.bit.ENABLE = 0;
+  while (TCC0->SYNCBUSY.bit.ENABLE) {
+  }
+
+  TCC0->CTRLA.reg = TCC_CTRLA_PRESCALER_DIV1;
+  TCC0->WAVE.reg = TCC_WAVE_WAVEGEN_NPWM;
+  while (TCC0->SYNCBUSY.bit.WAVE) {
+  }
+
+  TCC0->PER.reg = kPilotTop;
+  while (TCC0->SYNCBUSY.bit.PER) {
+  }
+
+  TCC0->CC[2].reg = 0;
+  while (TCC0->SYNCBUSY.bit.CC2) {
+  }
+
+  TCC0->CTRLA.bit.ENABLE = 1;
+  while (TCC0->SYNCBUSY.bit.ENABLE) {
+  }
+  // end configure PWM
+  }
+  else {
+    TCC0->CTRLA.bit.ENABLE = 0;
+    while (TCC0->SYNCBUSY.bit.ENABLE) {
+    }
+
+    pinMode(PILOT_REG, OUTPUT);
+  }
+}
+
+void J1772Pilot::pwmSetCompareCounts(uint32_t compare)
+{
+  if (compare > kPilotTop) {
+    compare = kPilotTop;
+  }
+
+  TCC0->CC[2].reg = compare;
+  while (TCC0->SYNCBUSY.bit.CC2) {
+  }
+}
+
+
+void J1772Pilot::Init()
+{
+  pinMode(PILOT_REG,OUTPUT);
+
+
+
+  SetState(PILOT_STATE_P12); // turns the pilot on 12V steady state
+}
+
+
+// no PWM pilot signal - steady state
+// PILOT_STATE_P12 = steady +12V (EVSE_STATE_A - VEHICLE NOT CONNECTED)
+// PILOT_STATE_N12 = steady -12V (EVSE_STATE_F - FAULT) 
+void J1772Pilot::SetState(PILOT_STATE state)
+{
+  if (m_State == PILOT_STATE_PWM) pwmEnable(0);
+
+  digitalWrite(PILOT_REG,(state == PILOT_STATE_P12) ? HIGH : LOW);
+
+  m_State = state;
+  //  g_serial->printf("pstate: %s\n",(state == PILOT_STATE_P12) ? "P12":"N12");
+}
+
+//
+// set EVSE current capacity in Amperes
+// 
+// outputting a 1KHz square wave w/ proper duty cycle
+// quick reference:
+//   6A  -> 10%
+//   16A -> 26.67%
+//   32A -> 53.33%
+//   51A -> 85%
+//   52A -> 84.8%
+//   80A -> 96%
+//
+int J1772Pilot::SetPWM(int amps)
+{
+  uint32_t compare;
+  if ((amps >= 6) && (amps <= 51)) {
+    // amps = (duty cycle %) X 0.6
+    // duty% = amps / 0.6 = amps * 5 / 3
+    // compare = duty% * (PER+1) / 100 = amps * 800 (exact integer)
+    compare = (uint32_t)amps * 800u;
+  } else if ((amps > 51) && (amps <= 80)) {
+    // amps = (duty cycle % - 64) X 2.5
+    // duty% = 64 + amps / 2.5 = 64 + 2*amps/5
+    // compare = 64%*(PER+1) + amps*192 (exact integer)
+    compare = 30720u + ((uint32_t)amps * 192u);
+  }
+  else {
+    return 1;
+  }
+
+  pwmEnable(1);
+  pwmSetCompareCounts(compare);
+
+  m_State = PILOT_STATE_PWM;
+
+  //  g_serial->printf("pwm cnt: %d\n",cnt);
+  return 0;
+}
diff --git a/firmware/targets/samd/J1772Pilot.h b/firmware/targets/samd/J1772Pilot.h
new file mode 100644
index 00000000..7d88f87e
--- /dev/null
+++ b/firmware/targets/samd/J1772Pilot.h
@@ -0,0 +1,40 @@
+#pragma once
+/*
+ * This file is part of Open EVSE.
+ *
+ * Copyright (c) 2011-2019 Sam C. Lin
+ *
+ * Open EVSE is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+
+ * Open EVSE is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with Open EVSE; see the file COPYING.  If not, write to the
+ * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * Boston, MA 02111-1307, USA.
+ */
+
+typedef enum {
+  PILOT_STATE_P12, PILOT_STATE_PWM, PILOT_STATE_N12
+}
+PILOT_STATE;
+class J1772Pilot {
+  PILOT_STATE m_State;
+
+  void pwmEnable(bool tf);
+  void pwmSetCompareCounts(uint32_t compare);
+public:
+  J1772Pilot() {}
+  void Init();
+  void SetState(PILOT_STATE pstate); // P12/N12
+  PILOT_STATE GetState() { 
+    return m_State; 
+  }
+  int SetPWM(int amps); // 12V 1KHz PWM
+};
diff --git a/firmware/targets/samd/eeprom_emulation.h b/firmware/targets/samd/eeprom_emulation.h
new file mode 100644
index 00000000..b86c723d
--- /dev/null
+++ b/firmware/targets/samd/eeprom_emulation.h
@@ -0,0 +1,10 @@
+#pragma once
+
+#include <stdint.h>
+
+static uint8_t eeprom_read_byte (const uint8_t *__p) { return 0;}
+static uint16_t eeprom_read_word (const uint16_t *__p) { return 0;}
+static uint32_t eeprom_read_dword (const uint32_t *__p) { return 0;}
+static void eeprom_write_byte (uint8_t *__p, uint8_t __value) {}
+static void eeprom_write_word (uint16_t *__p, uint16_t __value) {}
+static void eeprom_write_dword (uint32_t *__p, uint32_t __value) {}
diff --git a/firmware/targets/samd/pindefs.h b/firmware/targets/samd/pindefs.h
new file mode 100644
index 00000000..ea976592
--- /dev/null
+++ b/firmware/targets/samd/pindefs.h
@@ -0,0 +1,42 @@
+#include "samd_pins.h"
+
+#define GFI_REG ZERO_PA14
+
+// pin is supposed to be wrapped around the GFI CT 5+ times
+#define GFITEST_REG ZERO_PA06
+
+#define PILOT_REG ZERO_PA18 // PWM
+
+// analog pins
+#define CURRENT_PIN     ZERO_PA02 // analog current reading pin A0
+#define PILOT_SENSE_PIN ZERO_PB08 // analog pilot voltage reading pin A1
+#define PP_PIN          ZERO_PB09 // PP_READ - A2
+
+
+#define ACLINE1_REG ZERO_PA08 // WELD_DETECT
+#define ACLINE2_REG ZERO_PA09 // GMI_LINE
+
+// digital Relay trigger pin
+#define CHARGING_REG   ZERO_PA15 // DC_RELAY_1
+#define CHARGING2_REG  ZERO_PA20 // DC_RELAY_2
+#define CHARGINGAC_REG ZERO_PA07 // AC_RELAY
+
+// requires external 12V H-bridge driver such as Polulu 1451
+#define MENNEKES_LOCK_PINA_REG ZERO_PA16 // LOCK
+#define MENNEKES_LOCK_PINB_REG ZERO_PA19 // UNLOCK
+
+
+
+// dummies - unused
+#define PILOT_IDX 0
+#define CHARGING_IDX 0
+#define CHARGING2_IDX 0
+#define CHARGINGAC_IDX 0
+#define ACLINE1_IDX 0
+#define ACLINE2_IDX 0
+
+#define GFI_IDX 0
+#define GFITEST_IDX 0
+
+#define MENNEKES_LOCK_PINA_IDX 0
+#define MENNEKES_LOCK_PINB_IDX 0
diff --git a/firmware/targets/samd/platformio.ini b/firmware/targets/samd/platformio.ini
new file mode 100644
index 00000000..ae3a0214
--- /dev/null
+++ b/firmware/targets/samd/platformio.ini
@@ -0,0 +1,86 @@
+[samd]
+lib_deps = ${common.lib_deps}
+  https://github.com/lincomatic/Adafruit_SleepyDog.git
+;extra_scripts = pre:firmware/targets/samd/no_erase_upload.py
+build_src_flags =
+  -D TARGET_SAMD
+  -D EEPROM_FLASH_STORE_KB=48
+  -D RAPI_SERIAL_PORT=Serial1
+  ;-D RELAY_PWM
+  -I firmware/targets/samd
+  ${common.us_build_flags}
+build_src_filter =
+  ${common.build_src_filter}
+  +<../targets/samd>
+
+
+# v6 CGMI OpenEVSE
+[env:samd_us]
+platform = atmelsam
+framework = arduino
+board = zeroUSB
+build_type = release
+#board = samd21g18a
+monitor_speed=115200
+;extra_scripts = ${samd.extra_scripts}
+lib_deps = ${samd.lib_deps}
+build_src_filter =
+  ${samd.build_src_filter}
+build_src_flags=
+  ${samd.build_src_flags}
+  -D ENABLE_CGMI
+  -D NO_GROUND_RECORD_DELAY=2000
+  -D NO_AUTOSVCLEVEL
+  -D DEFAULT_SERVICE_LEVEL=2
+  -D OVERCURRENT_THRESHOLD=5
+  -D OVERCURRENT_TIMEOUT=10000UL
+  -D BOOTLOCK
+  -D 'VERSION="${common.version}.CGMI"'
+
+# v6 CGMI OpenEVSE (Atmel-ICE upload/programming)
+[env:samd_us_ice]
+extends = env:samd_us
+build_type = release ;debug
+upload_protocol = atmel-ice
+debug_tool = atmel-ice
+; Start the debugger and break at the beginning of setup()
+;debug_init_break = tbreak setup
+build_src_flags=
+  ${env:samd_us.build_src_flags}
+  ;-UWATCHDOG
+  -UBOOTLOCK
+  -UHEARTBEAT_SUPERVISION
+;  -DCALIBRATE ; pilot calibration mode - for initial setup only
+
+# EU OpenEVSE
+[env:samd_eu]
+extends = env:samd_us
+;extra_scripts = ${samd.extra_scripts}
+build_src_flags=
+  ${samd.build_src_flags}
+  ${common.eu_build_flags}
+  -D MV_FOR_L2=230000L
+  -D 'VERSION="${common.version}.EU"'
+
+# Non-tethered T2 EmonEVSE single-phase
+[env:samd_emonevse]
+extends = env:samd_us
+;extra_scripts = ${samd.extra_scripts}
+build_src_flags=
+  ${samd.build_src_flags}
+  ${common.eu_build_flags}
+  -D PP_AUTO_AMPACITY
+  -D MV_FOR_L2=230000L
+  -D 'VERSION="${common.version}.T2"'
+
+# Non-tethered T2 EmonEVSE three-phase
+# Deprecated, unneeded with wifi fw > 4.1.7
+; [env:emonevse_3ph]
+; extends = env:openevse
+; build_src_flags=
+;   ${common.eu_build_flags}
+;   -D PP_AUTO_AMPACITY
+;   -D THREEPHASE
+;   -D 'VERSION="${common.version}.3P"'
+
+
diff --git a/firmware/targets/samd/samd_pins.h b/firmware/targets/samd/samd_pins.h
new file mode 100644
index 00000000..27064502
--- /dev/null
+++ b/firmware/targets/samd/samd_pins.h
@@ -0,0 +1,163 @@
+// table from C:\Users\Geek\.platformio\packages\framework-arduino-samd\variants\arduino_zero\variant.cpp
+#pragma once
+/*
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * + Pin number +  ZERO Board pin  |  PIN   | Label/Name      | Comments (* is for default peripheral in use)
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            | Digital Low      |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 0          | 0 -> RX          |  PA11  |                 | EIC/EXTINT[11] ADC/AIN[19]           PTC/X[3] *SERCOM0/PAD[3]  SERCOM2/PAD[3]  TCC0/WO[3]  TCC1/WO[1]
+ * | 1          | 1 <- TX          |  PA10  |                 | EIC/EXTINT[10] ADC/AIN[18]           PTC/X[2] *SERCOM0/PAD[2]                  TCC0/WO[2]  TCC1/WO[0]
+ * | 2          | 2                |  PA14  |                 | EIC/EXTINT[14]                                 SERCOM2/PAD[2]  SERCOM4/PAD[2]  TC3/WO[0]   TCC0/WO[4]
+ * | 3          | ~3               |  PA09  |                 | EIC/EXTINT[9]  ADC/AIN[17]           PTC/X[1]  SERCOM0/PAD[1]  SERCOM2/PAD[1] *TCC0/WO[1]  TCC1/WO[3]
+ * | 4          | ~4               |  PA08  |                 | EIC/NMI        ADC/AIN[16]           PTC/X[0]  SERCOM0/PAD[0]  SERCOM2/PAD[0] *TCC0/WO[0]  TCC1/WO[2]
+ * | 5          | ~5               |  PA15  |                 | EIC/EXTINT[15]                                 SERCOM2/PAD[3]  SERCOM4/PAD[3] *TC3/WO[1]   TCC0/WO[5]
+ * | 6          | ~6               |  PA20  |                 | EIC/EXTINT[4]                        PTC/X[8]  SERCOM5/PAD[2]  SERCOM3/PAD[2]             *TCC0/WO[6]
+ * | 7          | 7                |  PA21  |                 | EIC/EXTINT[5]                        PTC/X[9]  SERCOM5/PAD[3]  SERCOM3/PAD[3]              TCC0/WO[7]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            | Digital High     |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 8          | ~8               |  PA06  |                 | EIC/EXTINT[6]  ADC/AIN[6]  AC/AIN[2] PTC/Y[4]  SERCOM0/PAD[2]                 *TCC1/WO[0]
+ * | 9          | ~9               |  PA07  |                 | EIC/EXTINT[7]  ADC/AIN[7]  AC/AIN[3] PTC/Y[5]  SERCOM0/PAD[3]                 *TCC1/WO[1]
+ * | 10         | ~10              |  PA18  |                 | EIC/EXTINT[2]                        PTC/X[6] +SERCOM1/PAD[2]  SERCOM3/PAD[2] *TC3/WO[0]    TCC0/WO[2]
+ * | 11         | ~11              |  PA16  |                 | EIC/EXTINT[0]                        PTC/X[4] +SERCOM1/PAD[0]  SERCOM3/PAD[0] *TCC2/WO[0]   TCC0/WO[6]
+ * | 12         | ~12              |  PA19  |                 | EIC/EXTINT[3]                        PTC/X[7] +SERCOM1/PAD[3]  SERCOM3/PAD[3]  TC3/WO[1]   *TCC0/WO[3]
+ * | 13         | ~13              |  PA17  | LED             | EIC/EXTINT[1]                        PTC/X[5] +SERCOM1/PAD[1]  SERCOM3/PAD[1] *TCC2/WO[1]   TCC0/WO[7]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            | Analog Connector |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 14         | A0               |  PA02  | A0              | EIC/EXTINT[2] *ADC/AIN[0]  DAC/VOUT  PTC/Y[0]
+ * | 15         | A1               |  PB08  | A1              | EIC/EXTINT[8] *ADC/AIN[2]            PTC/Y[14] SERCOM4/PAD[0]                  TC4/WO[0]
+ * | 16         | A2               |  PB09  | A2              | EIC/EXTINT[9] *ADC/AIN[3]            PTC/Y[15] SERCOM4/PAD[1]                  TC4/WO[1]
+ * | 17         | A3               |  PA04  | A3              | EIC/EXTINT[4] *ADC/AIN[4]  AC/AIN[0] PTC/Y[2]  SERCOM0/PAD[0]                  TCC0/WO[0]
+ * | 18         | A4               |  PA05  | A4              | EIC/EXTINT[5] *ADC/AIN[5]  AC/AIN[1] PTC/Y[5]  SERCOM0/PAD[1]                  TCC0/WO[1]
+ * | 19         | A5               |  PB02  | A5              | EIC/EXTINT[2] *ADC/AIN[10]           PTC/Y[8]  SERCOM5/PAD[0]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            | Wire             |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 20         | SDA              |  PA22  | SDA             | EIC/EXTINT[6]                        PTC/X[10] *SERCOM3/PAD[0] SERCOM5/PAD[0] TC4/WO[0] TCC0/WO[4]
+ * | 21         | SCL              |  PA23  | SCL             | EIC/EXTINT[7]                        PTC/X[11] *SERCOM3/PAD[1] SERCOM5/PAD[1] TC4/WO[1] TCC0/WO[5]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            |SPI (Legacy ICSP) |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 22         | 1                |  PA12  | MISO            | EIC/EXTINT[12] SERCOM2/PAD[0] *SERCOM4/PAD[0] TCC2/WO[0] TCC0/WO[6]
+ * |            | 2                |        | 5V0             |
+ * | 23         | 4                |  PB10  | MOSI            | EIC/EXTINT[10]                *SERCOM4/PAD[2] TC5/WO[0]  TCC0/WO[4]
+ * | 24         | 3                |  PB11  | SCK             | EIC/EXTINT[11]                *SERCOM4/PAD[3] TC5/WO[1]  TCC0/WO[5]
+ * |            | 5                |        | RESET           |
+ * |            | 6                |        | GND             |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            | LEDs             |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 25         |                  |  PB03  | RX              |
+ * | 26         |                  |  PA27  | TX              |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            | USB              |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 27         |                  |  PA28  | USB_HOST_ENABLE | EIC/EXTINT[8]
+ * | 28         |                  |  PA24  | USB_NEGATIVE    | *USB/DM
+ * | 29         |                  |  PA25  | USB_POSITIVE    | *USB/DP
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            | EDBG             |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 30         |                  |  PB22  | EDBG_UART TX    | *SERCOM5/PAD[2]
+ * | 31         |                  |  PB23  | EDBG_UART RX    | *SERCOM5/PAD[3]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 32         |                  |  PA22  | EDBG_SDA        | Pin 20 (SDA)
+ * | 33         |                  |  PA23  | EDBG_SCL        | Pin 21 (SCL)
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 34         |                  |  PA19  | EDBG_MISO       | EIC/EXTINT[3] *SERCOM1/PAD[3] SERCOM3/PAD[3] TC3/WO[1]  TCC0/WO[3]
+ * | 35         |                  |  PA16  | EDBG_MOSI       | EIC/EXTINT[0] *SERCOM1/PAD[0] SERCOM3/PAD[0] TCC2/WO[0] TCC0/WO[6]
+ * | 36         |                  |  PA18  | EDBG_SS         | EIC/EXTINT[2] *SERCOM1/PAD[2] SERCOM3/PAD[2] TC3/WO[0]  TCC0/WO[2]
+ * | 37         |                  |  PA17  | EDBG_SCK        | EIC/EXTINT[1] *SERCOM1/PAD[1] SERCOM3/PAD[1] TCC2/WO[1] TCC0/WO[7]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 38         | ATN              |  PA13  | EDBG_GPIO0      | EIC/EXTINT[13] SERCOM2/PAD[1] SERCOM4/PAD[1] *TCC2/WO[1] TCC0/WO[7]
+ * | 39         |                  |  PA21  | EDBG_GPIO1      | Pin 7
+ * | 40         |                  |  PA06  | EDBG_GPIO2      | Pin 8
+ * | 41         |                  |  PA07  | EDBG_GPIO3      | Pin 9
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            |                  |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            | GND              |        |                 |
+ * | 42         | AREF             |  PA03  |                 | EIC/EXTINT[3] *[ADC|DAC]/VREFA ADC/AIN[1] PTC/Y[1]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 43         |                  |  PA02  |                 | Alternate use of A0 (DAC output)
+ * | 44         |                  |  PA30  |                 | SWCLK, alternate use EXTINT[10] TCC1/WO[0] SERCOM1/PAD[2]
+ * | 45         |                  |  PA31  |                 | SWDIO, alternate use EXTINT[11] TCC1/WO[1] SERCOM1/PAD[3]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            |32.768KHz Crystal |        |                 |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * |            |                  |  PA00  | XIN32           | EIC/EXTINT[0] SERCOM1/PAD[0] TCC2/WO[0]
+ * |            |                  |  PA01  | XOUT32          | EIC/EXTINT[1] SERCOM1/PAD[1] TCC2/WO[1]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ */
+
+/*
+#defines generated by https://grok.com/c/bc3507b4-0f4c-4ff1-81ea-448429308146?rid=118354ef-aedc-4fb8-8796-072878f2a395
+
+Notes:
+
+Only pins that have a clear Pin Number (0–45 range in the left column) are included.
+Pins without an explicit Arduino pin number (e.g. pure USB pins without number, crystal pins PA00/PA01, some EDBG-only entries without number) were skipped.
+Some pins appear multiple times (e.g. PA22 = 20 and 32) because they are shared (SDA / EDBG_SDA). You can choose whether to keep only one or use both depending on your coding style.
+The generated names follow the common pattern seen in many Arduino SAMD variants (e.g. #define ZERO_PAxx N).
+*/
+
+// n.b. we don't use XXXX because they're already defined differently in 
+// C:\Users\Geek\.platformio\packages\framework-cmsis-atmel\CMSIS\Device\ATMEL\samd21\include\pio\samd21g18a.h
+#define ZERO_PA11  0
+#define ZERO_PA10  1
+#define ZERO_PA14  2
+#define ZERO_PA09  3
+#define ZERO_PA08  4
+#define ZERO_PA15  5
+#define ZERO_PA20  6
+#define ZERO_PA21  7
+
+#define ZERO_PA06  8
+#define ZERO_PA07  9
+#define ZERO_PA18 10
+#define ZERO_PA16 11
+#define ZERO_PA19 12
+#define ZERO_PA17 13
+
+#define ZERO_PA02 14   // A0
+#define ZERO_PB08 15   // A1
+#define ZERO_PB09 16   // A2
+#define ZERO_PA04 17   // A3
+#define ZERO_PA05 18   // A4
+#define ZERO_PB02 19   // A5
+
+#define ZERO_PA22 20   // SDA
+#define ZERO_PA23 21   // SCL
+
+#define ZERO_PA12 22   // MISO (legacy ICSP)
+#define ZERO_PB10 23   // MOSI
+#define ZERO_PB11 24   // SCK
+
+#define ZERO_PB03 25   // RX LED related
+#define ZERO_PA27 26   // TX LED related
+
+#define ZERO_PA28 27   // USB_HOST_ENABLE
+
+#define ZERO_PA24 28   // USB/DM
+#define ZERO_PA25 29   // USB/DP
+
+// EDBG related (internal)
+#define ZERO_PB22 30   // EDBG_UART TX
+#define ZERO_PB23 31   // EDBG_UART RX
+
+// EDBG alternate mappings (often same physical pins)
+//#define ZERO_PA22 32   // EDBG_SDA  (same as 20)
+//#define ZERO_PA23 33   // EDBG_SCL  (same as 21)
+//#define ZERO_PA19 34   // EDBG_MISO (same as 12)
+//#define ZERO_PA16 35   // EDBG_MOSI (same as 11)
+//#define ZERO_PA18 36   // EDBG_SS   (same as 10)
+//#define ZERO_PA17 37   // EDBG_SCK  (same as 13)
+
+#define ZERO_PA13 38   // ATN / EDBG_GPIO0
+
+// Additional / special pins
+#define ZERO_PA03 42   // AREF
+#define ZERO_PA30 44   // SWCLK
+#define ZERO_PA31 45   // SWDIO
diff --git a/firmware/targets/samd/target.cpp b/firmware/targets/samd/target.cpp
new file mode 100644
index 00000000..5ab9ae11
--- /dev/null
+++ b/firmware/targets/samd/target.cpp
@@ -0,0 +1,70 @@
+#include "open_evse.h"
+
+//                                               A/B  B/C  C/D  D DS
+THRESH_DATA J1772EVSEController::m_ThreshData = {3948,3539,3258,0,492};
+
+#ifdef MCU_ID_LEN
+// mcuid *must* be of size MCU_ID_LEN
+void getMcuId(uint8_t *mcuid)
+{
+  uint8_t uid[16];
+  for (uint8_t word = 0; word < 4; word++) {
+    uint32_t value;
+    switch (word) {
+      case 0:
+        value = *((volatile uint32_t *)0x0080A00C);
+        break;
+      case 1:
+        value = *((volatile uint32_t *)0x0080A040);
+        break;
+      case 2:
+        value = *((volatile uint32_t *)0x0080A044);
+        break;
+      default:
+        value = *((volatile uint32_t *)0x0080A048);
+        break;
+    }
+    uid[(word * 4) + 0] = (uint8_t)(value & 0xFF);
+    uid[(word * 4) + 1] = (uint8_t)((value >> 8) & 0xFF);
+    uid[(word * 4) + 2] = (uint8_t)((value >> 16) & 0xFF);
+    uid[(word * 4) + 3] = (uint8_t)((value >> 24) & 0xFF);
+  }
+
+  for (uint8_t i = 0; i < MCU_ID_LEN; i++) {
+    mcuid[i] = uid[i % sizeof(uid)];
+  }
+}
+#endif // MCU_ID_LEN
+
+
+void DigitalPin::init(uint32_t pinnum,int idxjunk,PinMode mode)
+{
+  _pinNum = pinnum;
+  if (mode == INP) {
+    _pinMode = INPUT;
+  }
+  else if (mode == INP_PU) {
+    _pinMode = INPUT_PULLUP;
+  }
+  else {
+    _pinMode = OUTPUT;
+  }
+  pinMode(_pinNum,_pinMode);
+}
+
+
+// platform-specific init
+void initTarget()
+{
+  // enable BOD - brown out detection - to prevent lockups when the voltage drops too low
+
+  uint32_t bod33 = SYSCTRL->BOD33.reg;
+
+  bod33 |= SYSCTRL_BOD33_ENABLE;
+  bod33 |= SYSCTRL_BOD33_HYST;
+  bod33 |= SYSCTRL_BOD33_CEN;
+  bod33 &= ~SYSCTRL_BOD33_ACTION_Msk;
+  bod33 |= SYSCTRL_BOD33_ACTION_RESET;
+
+  SYSCTRL->BOD33.reg = bod33;
+}
diff --git a/firmware/targets/samd/target.h b/firmware/targets/samd/target.h
new file mode 100644
index 00000000..dc908cc3
--- /dev/null
+++ b/firmware/targets/samd/target.h
@@ -0,0 +1,94 @@
+#pragma once
+
+
+#define ADC_RESOLUTION_BITS 12
+#define ADC_MAX 4095
+#define ADC_HALF 2048
+
+// for J1772.ReadPilot()
+// 15 = ~13ms
+#define PILOT_LOOP_CNT 15
+
+
+#define GetVerStr(s) strcpy(s,VERSION)
+
+#include "eeprom_emulation.h"
+
+void wdt_disable();
+
+#ifdef WATCHDOG
+#include <Adafruit_SleepyDog.h>
+
+inline void wdt_enable(int sec)
+{
+  Watchdog.enable(sec * 1000);
+}
+
+inline void wdt_disable()
+{
+  Watchdog.disable();
+}
+
+inline void wdt_reset()
+{
+  Watchdog.reset();
+}
+
+#define WDT_RESET() wdt_reset()
+#define WDT_ENABLE() wdt_enable(2)
+#define WDT_ENABLE_1S() wdt_enable(1)
+#define WDT_DISABLE() wdt_disable()
+#else
+#define WDT_RESET()
+#define WDT_ENABLE()
+#define WDT_ENABLE_1S()
+#define WDT_DISABLE()
+#define wdt_reset()
+#define wdt_enable(sec)
+#endif // WATCHDOG
+
+class DigitalPin {
+  uint32_t _pinNum;
+  uint32_t _pinMode;
+  
+public:
+  enum PinMode { INP,INP_PU,OUT };
+
+  DigitalPin() {}
+  DigitalPin(uint32_t pinnum,int idxjunk,PinMode mode) {
+    init(pinnum,idxjunk,mode);
+  }
+
+void init(uint32_t pinnum,int idxjunk,PinMode mode);
+  void mode(PinMode mode);
+
+  uint8_t read() {
+    return digitalRead(_pinNum) ? 1 : 0;
+  }
+  void write(uint32_t state) {
+    digitalWrite(_pinNum,state ? HIGH : LOW);
+  }
+};
+
+class AdcPin {
+  uint32_t _pinNum;
+public:
+
+  AdcPin() {}
+  AdcPin(uint32_t pinnum) {
+    init(pinnum);
+  }
+
+  void init(uint32_t pinnum) {
+    _pinNum = pinnum;
+    analogReadResolution(ADC_RESOLUTION_BITS);
+  }
+
+  uint32_t read() {
+    return analogRead(_pinNum);
+  }
+};
+
+void getMcuId(uint8_t *mcuid);
+
+void initTarget();
diff --git a/platformio.ini b/platformio.ini
index a5b7debc..1f191b05 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -12,7 +12,7 @@
 src_dir = firmware/open_evse
 
 extra_configs =
-	firmware/variants/*/platformio.ini
+	firmware/targets/*/platformio.ini
 
 [common]
 lib_deps =
@@ -20,9 +20,8 @@ version = D8.2.3
 build_src_filter =
    +<*.cpp>
 build_flags =
-  -D OEV6
-  -D RELAY_PWM
-  -D SHOW_DISABLED_TESTS
+  -D WATCHDOG # watchdog MUST be enabled; only turn it off during debugging
+  -D WATCHDOG_TIMEOUT_SEC=2 # do not change this value
   -D AMMETER
   -D RAPI
   -D RAPI_SERIAL
@@ -44,11 +43,4 @@ eu_build_flags =
   -D MAX_CURRENT_CAPACITY_L2=32
   -D OVERCURRENT_THRESHOLD=5
   -D OVERCURRENT_TIMEOUT=10000UL
-  -D DEFAULT_SERVICE_LEVEL=2
-
-
-[env:samd21g18a]
-platform = atmelsam
-framework = arduino
-board = samd21g18a
-
+  -D DEFAULT_SERVICE_LEVEL=2
\ No newline at end of file

From 2f6a3ecf67531a50e58bb40678699f0ff92afbd7 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Fri, 13 Mar 2026 13:28:00 -0700
Subject: [PATCH 23/59] mcuid tweak for SAMD

---
 firmware/open_evse/open_evse.h   |  2 --
 firmware/open_evse/rapi_proc.cpp |  7 +++++++
 firmware/open_evse/rapi_proc.h   | 16 ++++++++++------
 firmware/targets/m328p/target.h  |  3 +++
 firmware/targets/samd/target.cpp | 13 ++++---------
 firmware/targets/samd/target.h   |  3 +++
 6 files changed, 27 insertions(+), 17 deletions(-)

diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index a78ee179..6db1af84 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -131,8 +131,6 @@
 
 #endif // !PLATFORMIO
 
-// enable $GI
-#define MCU_ID_LEN 10
 
 // enable watchdog timer
 //#define WATCHDOG
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index e49f54de..a4161f5f 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -739,6 +739,7 @@ int EvseRapiProcessor::processCmd()
         uint8_t mcuid[MCU_ID_LEN];
         getMcuId(mcuid);
         char *s = buffer;
+#ifdef TARGET_M238P
         *(s++) = ' ';
         for (int i=0;i < 6;i++) {
           *(s++) = mcuid[i];
@@ -747,6 +748,12 @@ int EvseRapiProcessor::processCmd()
           sprintf(s,"%02X",mcuid[i]);
           s += 2;
         }
+#else
+        for (int i=0;i < MCU_ID_LEN;i++) {
+          sprintf(s,"%02X",mcuid[i]);
+          s += 2;
+        }
+#endif
         bufCnt = 1; // flag response text output
         rc = 0;
       }
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index e0f49804..9c36f5a0 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -303,12 +303,16 @@ GH - get cHarge limit
 
 GI - get MCU ID - requires MCU_ID_LEN to be defined
  response: $OK mcuid
- mcuid: AVR serial number
-        mcuid is 6 ASCII characters followed by 4 hex digits
-        first hex digit = FF for 328P
-  WARNING: mcuid is guaranteed to be unique only for the 328PB. Uniqueness is
-	unknown in 328P. The first 6 characters are ASCII, and the rest are
-	hexadecimal.
+ mcuid: MCU serial number
+  AVR:
+    mcuid is 6 ASCII characters followed by 8 hex digits
+    first hex digit = FF for 328P
+    WARNING: mcuid is guaranteed to be unique only for the 328PB. Uniqueness is
+    unknown in 328P. The first 6 characters are ASCII, and the rest are
+    hexadecimal.
+  SAMD:
+   mcuid is 128-bit number
+   returned as a 32-character hex string
 
 GM - get voltMeter settings
  response: $OK voltcalefactor voltoffset
diff --git a/firmware/targets/m328p/target.h b/firmware/targets/m328p/target.h
index cd582b3f..ac86142b 100644
--- a/firmware/targets/m328p/target.h
+++ b/firmware/targets/m328p/target.h
@@ -29,6 +29,9 @@
 #include "./RTClib.h"
 
 
+// enable $GI
+#define MCU_ID_LEN 10
+
 #define ADC_RESOLUTION_BITS 10
 #define ADC_MAX 1023
 #define ADC_HALF 512
diff --git a/firmware/targets/samd/target.cpp b/firmware/targets/samd/target.cpp
index 5ab9ae11..47197e6c 100644
--- a/firmware/targets/samd/target.cpp
+++ b/firmware/targets/samd/target.cpp
@@ -7,7 +7,6 @@ THRESH_DATA J1772EVSEController::m_ThreshData = {3948,3539,3258,0,492};
 // mcuid *must* be of size MCU_ID_LEN
 void getMcuId(uint8_t *mcuid)
 {
-  uint8_t uid[16];
   for (uint8_t word = 0; word < 4; word++) {
     uint32_t value;
     switch (word) {
@@ -24,14 +23,10 @@ void getMcuId(uint8_t *mcuid)
         value = *((volatile uint32_t *)0x0080A048);
         break;
     }
-    uid[(word * 4) + 0] = (uint8_t)(value & 0xFF);
-    uid[(word * 4) + 1] = (uint8_t)((value >> 8) & 0xFF);
-    uid[(word * 4) + 2] = (uint8_t)((value >> 16) & 0xFF);
-    uid[(word * 4) + 3] = (uint8_t)((value >> 24) & 0xFF);
-  }
-
-  for (uint8_t i = 0; i < MCU_ID_LEN; i++) {
-    mcuid[i] = uid[i % sizeof(uid)];
+    mcuid[(word * 4) + 0] = (uint8_t)(value & 0xFF);
+    mcuid[(word * 4) + 1] = (uint8_t)((value >> 8) & 0xFF);
+    mcuid[(word * 4) + 2] = (uint8_t)((value >> 16) & 0xFF);
+    mcuid[(word * 4) + 3] = (uint8_t)((value >> 24) & 0xFF);
   }
 }
 #endif // MCU_ID_LEN
diff --git a/firmware/targets/samd/target.h b/firmware/targets/samd/target.h
index dc908cc3..6f2fe3dc 100644
--- a/firmware/targets/samd/target.h
+++ b/firmware/targets/samd/target.h
@@ -1,6 +1,9 @@
 #pragma once
 
 
+// enable $GI
+#define MCU_ID_LEN 16 // SAMD ID is 128-bit
+
 #define ADC_RESOLUTION_BITS 12
 #define ADC_MAX 4095
 #define ADC_HALF 2048

From 47003d1a77543a3c027d7d15c3743bf063b0879f Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Fri, 13 Mar 2026 13:28:41 -0700
Subject: [PATCH 24/59] path the dog during GFI self test could take 3s

---
 firmware/targets/samd/Gfi.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/firmware/targets/samd/Gfi.cpp b/firmware/targets/samd/Gfi.cpp
index 070114cd..894b1333 100644
--- a/firmware/targets/samd/Gfi.cpp
+++ b/firmware/targets/samd/Gfi.cpp
@@ -81,6 +81,7 @@ uint8_t Gfi::SelfTest()
     delayMicroseconds(GFI_PULSE_ON_US);
     pinTest.write(0);
     delayMicroseconds(GFI_PULSE_OFF_US);
+    if ((i % 50) == 0) WDT_RESET();
   }
   //  RAPI_SERIAL_PORT.print("GFI ");RAPI_SERIAL_PORT.println(millis()-sms);
 

From c39dfd49645b926e613734c7a9124b4240fa59e7 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Fri, 13 Mar 2026 15:52:48 -0700
Subject: [PATCH 25/59] checkpoint

---
 firmware/open_evse/J1772EvseController.cpp |  2 +-
 firmware/targets/samd/Gfi.cpp              | 12 ++++++--
 firmware/targets/samd/platformio.ini       | 32 ++++++++++++----------
 firmware/targets/samd/target.cpp           | 30 ++++++++++++++------
 4 files changed, 50 insertions(+), 26 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index e528f656..a63806f6 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -83,7 +83,7 @@ void J1772EVSEController::readAmmeter()
     case 1:
     case 2:
       // Gather the sum-of-the-squares and count how many samples we've collected.
-      sum += (unsigned long)(((long)sample - 512) * ((long)sample - 512));
+      sum += (unsigned long)(((long)sample - ADC_HALF) * ((long)sample - ADC_HALF));
       sample_count++;
       continue;
     case 3:
diff --git a/firmware/targets/samd/Gfi.cpp b/firmware/targets/samd/Gfi.cpp
index 894b1333..2502a5f7 100644
--- a/firmware/targets/samd/Gfi.cpp
+++ b/firmware/targets/samd/Gfi.cpp
@@ -63,6 +63,8 @@ void Gfi::Reset()
 
 uint8_t Gfi::SelfTest()
 {
+  //  RAPI_SERIAL_PORT.print("GST ");
+  //  uint32_t sms = millis();
   int i;
   // wait for GFI pin to clear
   for (i=0;i < 20;i++) {
@@ -71,19 +73,20 @@ uint8_t Gfi::SelfTest()
     delay(50);
   }
   if (i == 20) return 2;
+  //  RAPI_SERIAL_PORT.print(millis()-sms);
 
   testInProgress = 1;
   testSuccess = 0;
   WDT_RESET();
-  //  uint32_t sms = millis();
-  for(int i=0; !testSuccess && (i < 200); i++) {
+  for(i=0; !testSuccess && (i < 200); i++) {
     pinTest.write(1);
     delayMicroseconds(GFI_PULSE_ON_US);
     pinTest.write(0);
     delayMicroseconds(GFI_PULSE_OFF_US);
     if ((i % 50) == 0) WDT_RESET();
   }
-  //  RAPI_SERIAL_PORT.print("GFI ");RAPI_SERIAL_PORT.println(millis()-sms);
+  //  RAPI_SERIAL_PORT.print(" ST ");RAPI_SERIAL_PORT.print(millis()-sms);
+  //  RAPI_SERIAL_PORT.print(" ");RAPI_SERIAL_PORT.print(i);
 
   // wait for GFI pin to clear
   for (i=0;i < 40;i++) {
@@ -92,6 +95,8 @@ uint8_t Gfi::SelfTest()
     delay(50);
   }
   if (i == 40) return 3;
+  //  RAPI_SERIAL_PORT.print(" w ");RAPI_SERIAL_PORT.print(i);
+  //  RAPI_SERIAL_PORT.print(" s ");RAPI_SERIAL_PORT.println(testSuccess);
 
 
 #ifdef dontneed
@@ -104,6 +109,7 @@ uint8_t Gfi::SelfTest()
 #endif 
 
   m_GfiFault = 0;
+
   testInProgress = 0;
 
   return !testSuccess;
diff --git a/firmware/targets/samd/platformio.ini b/firmware/targets/samd/platformio.ini
index ae3a0214..9ef4d5aa 100644
--- a/firmware/targets/samd/platformio.ini
+++ b/firmware/targets/samd/platformio.ini
@@ -6,7 +6,13 @@ build_src_flags =
   -D TARGET_SAMD
   -D EEPROM_FLASH_STORE_KB=48
   -D RAPI_SERIAL_PORT=Serial1
-  ;-D RELAY_PWM
+  -D ENABLE_CGMI
+  -D NO_GROUND_RECORD_DELAY=2000
+  -D NO_AUTOSVCLEVEL
+  -D DEFAULT_SERVICE_LEVEL=2
+  -D OVERCURRENT_THRESHOLD=5
+  -D OVERCURRENT_TIMEOUT=10000UL
+  -D BOOTLOCK
   -I firmware/targets/samd
   ${common.us_build_flags}
 build_src_filter =
@@ -14,7 +20,7 @@ build_src_filter =
   +<../targets/samd>
 
 
-# v6 CGMI OpenEVSE
+# SAMD CGMI OpenEVSE
 [env:samd_us]
 platform = atmelsam
 framework = arduino
@@ -28,23 +34,21 @@ build_src_filter =
   ${samd.build_src_filter}
 build_src_flags=
   ${samd.build_src_flags}
-  -D ENABLE_CGMI
-  -D NO_GROUND_RECORD_DELAY=2000
-  -D NO_AUTOSVCLEVEL
-  -D DEFAULT_SERVICE_LEVEL=2
-  -D OVERCURRENT_THRESHOLD=5
-  -D OVERCURRENT_TIMEOUT=10000UL
-  -D BOOTLOCK
-  -D 'VERSION="${common.version}.CGMI"'
+  -D 'VERSION="${common.version}.SAMD"'
 
-# v6 CGMI OpenEVSE (Atmel-ICE upload/programming)
+# # SAMD CGMI OpenEVSE (Atmel-ICE upload/programming)
 [env:samd_us_ice]
 extends = env:samd_us
-build_type = release ;debug
 upload_protocol = atmel-ice
+build_type = release
+build_src_flags=
+  ${env:samd_us.build_src_flags}
+
+[env:samd_us_ice_dev] ; don't use this.. for dev/debug only
+extends = env:samd_us
+upload_protocol = atmel-ice
+build_type = release ;debug
 debug_tool = atmel-ice
-; Start the debugger and break at the beginning of setup()
-;debug_init_break = tbreak setup
 build_src_flags=
   ${env:samd_us.build_src_flags}
   ;-UWATCHDOG
diff --git a/firmware/targets/samd/target.cpp b/firmware/targets/samd/target.cpp
index 47197e6c..7259fc2f 100644
--- a/firmware/targets/samd/target.cpp
+++ b/firmware/targets/samd/target.cpp
@@ -51,15 +51,29 @@ void DigitalPin::init(uint32_t pinnum,int idxjunk,PinMode mode)
 // platform-specific init
 void initTarget()
 {
-  // enable BOD - brown out detection - to prevent lockups when the voltage drops too low
+  //n.b. set BOD via fuses, not this code, as fuses may lock out BOD from being
+  // manipulated in code, anyway
+  // default factory fuse setting is 1.78V BOD enabled
+#ifdef DONTUSE
+    // 1. Prepare the configuration value level 7 = ~1.78V
+    uint32_t bod33_config = SYSCTRL_BOD33_LEVEL(7)     | 
+                            SYSCTRL_BOD33_HYST      | 
+                            SYSCTRL_BOD33_ACTION_RESET | 
+                            SYSCTRL_BOD33_ENABLE;
 
-  uint32_t bod33 = SYSCTRL->BOD33.reg;
+    // 2. Wait for the SYSCTRL to be ready/synchronized 
+    // (BOD33 is often in a different clock domain)
+    while (SYSCTRL->PCLKSR.bit.BOD33RDY == 0);
 
-  bod33 |= SYSCTRL_BOD33_ENABLE;
-  bod33 |= SYSCTRL_BOD33_HYST;
-  bod33 |= SYSCTRL_BOD33_CEN;
-  bod33 &= ~SYSCTRL_BOD33_ACTION_Msk;
-  bod33 |= SYSCTRL_BOD33_ACTION_RESET;
+    // 3. Disable before configuring if it was already running 
+    // (Optional, but ensures Level change takes effect cleanly)
+    SYSCTRL->BOD33.bit.ENABLE = 0;
+    while (SYSCTRL->PCLKSR.bit.BOD33RDY == 0);
 
-  SYSCTRL->BOD33.reg = bod33;
+    // 4. Write the full configuration
+    SYSCTRL->BOD33.reg = bod33_config;
+
+    // 5. Wait for synchronization again to ensure it's active
+    while (SYSCTRL->PCLKSR.bit.BOD33RDY == 0);
+#endif // DONTUSE
 }

From 2ca3cf396e2717626bc10fcf813d0895e8c92c7e Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Mon, 16 Mar 2026 16:53:43 -0700
Subject: [PATCH 26/59] SAMD ammeter initial cal

---
 firmware/open_evse/J1772EvseController.cpp | 18 ++++++++--
 firmware/open_evse/J1772EvseController.h   |  8 ++---
 firmware/open_evse/open_evse.h             | 34 -------------------
 firmware/targets/m328p/target.h            | 38 ++++++++++++++++++++++
 firmware/targets/samd/Gfi.cpp              |  5 +++
 firmware/targets/samd/eeprom_emulation.h   |  6 ++--
 firmware/targets/samd/platformio.ini       |  4 ++-
 firmware/targets/samd/target.h             |  4 +++
 8 files changed, 73 insertions(+), 44 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index a63806f6..7dd23ad9 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -1062,8 +1062,8 @@ void J1772EVSEController::Init()
 #endif
 
 #ifdef AMMETER
-  m_AmmeterCurrentOffset = eeprom_read_word((uint16_t*)EOFS_AMMETER_CURR_OFFSET);
-  m_CurrentScaleFactor = eeprom_read_word((uint16_t*)EOFS_CURRENT_SCALE_FACTOR);
+  m_AmmeterCurrentOffset = (int16_t)eeprom_read_word((uint16_t*)EOFS_AMMETER_CURR_OFFSET);
+  m_CurrentScaleFactor = (int16_t)eeprom_read_word((uint16_t*)EOFS_CURRENT_SCALE_FACTOR);
   
   if (m_AmmeterCurrentOffset == (int16_t)0xffff) {
     m_AmmeterCurrentOffset = DEFAULT_AMMETER_CURRENT_OFFSET;
@@ -1074,6 +1074,20 @@ void J1772EVSEController::Init()
   
   m_AmmeterReading = 0;
   m_ChargingCurrent = 0;
+
+#ifdef AMMETER_TEST
+  // for debugging only
+  while (1) {
+    char s[80];
+    readAmmeter();
+      long instantma = m_AmmeterReading*m_CurrentScaleFactor - m_AmmeterCurrentOffset;
+      sprintf(s,"%u %u %d\n",(unsigned)adcCurrent.read(),m_AmmeterReading,instantma);
+    RAPI_SERIAL_PORT.print(s);
+    delay(250);
+  }
+#endif // AMMETER_TEST
+
+
 #ifdef OVERCURRENT_THRESHOLD
   m_OverCurrentStartMs = 0;
 #endif //OVERCURRENT_THRESHOLD
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index 7b65f0cd..4c4a3f95 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -264,8 +264,8 @@ class J1772EVSEController {
 #ifdef AMMETER
   unsigned long m_AmmeterReading;
   int32_t m_ChargingCurrent;
-  int16_t m_AmmeterCurrentOffset;
-  int16_t m_CurrentScaleFactor;
+  int32_t m_AmmeterCurrentOffset;
+  int32_t m_CurrentScaleFactor;
 #ifdef CHARGE_LIMIT
   uint8_t m_chargeLimitkWh; // kWh to extend session
   uint32_t m_chargeLimitTotWs; // total Ws limit
@@ -487,11 +487,11 @@ int GetHearbeatTrigger();
 
   int16_t GetAmmeterCurrentOffset() { return m_AmmeterCurrentOffset; }
   int16_t GetCurrentScaleFactor() { return m_CurrentScaleFactor; }
-  void SetAmmeterCurrentOffset(int16_t offset) {
+  void SetAmmeterCurrentOffset(int32_t offset) {
     m_AmmeterCurrentOffset = offset;
     eeprom_write_word((uint16_t*)EOFS_AMMETER_CURR_OFFSET,offset);
   }
-  void SetCurrentScaleFactor(int16_t scale) {
+  void SetCurrentScaleFactor(int32_t scale) {
     m_CurrentScaleFactor = scale;
     eeprom_write_word((uint16_t*)EOFS_CURRENT_SCALE_FACTOR,scale);
   }
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index 6db1af84..a4e5d216 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -585,40 +585,6 @@ extern AutoCurrentCapacityController g_ACCController;
 
 
 #ifdef AMMETER
-// This multiplier is the number of milliamps per A/d converter unit.
-
-// First, you need to select the burden resistor for the CT. You choose the largest value possible such that
-// the maximum peak-to-peak voltage for the current range is 5 volts. To obtain this value, divide the maximum
-// outlet current by the Te. That value is the maximum CT current RMS. You must convert that to P-P, so multiply
-// by 2*sqrt(2). Divide 5 by that value and select the next lower standard resistor value. For the reference
-// design, Te is 1018 and the outlet maximum is 30. 5/((30/1018)*2*sqrt(2)) = 59.995, so a 56 ohm resistor
-// is called for. Call this value Rb (burden resistor).
-
-// Next, one must use Te and Rb to determine the volts-per-amp value. Note that the readCurrent()
-// method calculates the RMS value before the scaling factor, so RMS need not be taken into account.
-// (1 / Te) * Rb = Rb / Te = Volts per Amp. For the reference design, that's 55.009 mV.
-// Each count of the A/d converter is 4.882 mV (5/1024). V/A divided by V/unit is unit/A. For the reference
-// design, that's 11.26. But we want milliamps per unit, so divide that into 1000 to get 88.7625558. Round near...
-//#define DEFAULT_CURRENT_SCALE_FACTOR 106 // for RB = 47 - recommended for 30A max
-//#define DEFAULT_CURRENT_SCALE_FACTOR 184 // for RB = 27 - recommended for 50A max
-// Craig K, I arrived at 213 by scaling my previous multiplier of 225 down by the ratio of my panel meter reading of 28 with the OpenEVSE uncalibrated reading of 29.6
-// then upped the scale factor to 220 after fixing the zero offset by subtracing 900ma
-//#define DEFAULT_CURRENT_SCALE_FACTOR 220 // for RB = 22 - measured by Craig on his new OpenEVSE V3
-// NOTE: setting DEFAULT_CURRENT_SCALE_FACTOR TO 0 will disable the ammeter
-// until it is overridden via RAPI
-//#define DEFAULT_CURRENT_SCALE_FACTOR 220   // Craig K, average of three OpenEVSE controller calibrations
-#ifdef OPENEVSE_2
-#define DEFAULT_CURRENT_SCALE_FACTOR 186   // OpenEVSE II with a 27 Ohm burden resistor, after a 2-point calibration at 12.5A and 50A
-#else
-#define DEFAULT_CURRENT_SCALE_FACTOR 220   // OpenEVSE v2.5 and v3 with a 22 Ohm burden resistor (note that the schematic may say 28 Ohms by mistake)
-#endif
-
-// subtract this from ammeter current reading to correct zero offset
-#ifdef OPENEVSE_2
-#define DEFAULT_AMMETER_CURRENT_OFFSET 230 // OpenEVSE II with a 27 Ohm burden resistor, after a 2-point calibration at 12.5A and 50A
-#else
-#define DEFAULT_AMMETER_CURRENT_OFFSET 0   // OpenEVSE v2.5 and v3 with a 22 Ohm burden resistor.  Could use a more thorough calibration exercise to nails this down.
-#endif
 
 // The maximum number of milliseconds to sample an ammeter pin in order to find three zero-crossings.
 // one and a half cycles at 50 Hz is 30 ms.
diff --git a/firmware/targets/m328p/target.h b/firmware/targets/m328p/target.h
index ac86142b..c8d5a1f8 100644
--- a/firmware/targets/m328p/target.h
+++ b/firmware/targets/m328p/target.h
@@ -41,6 +41,44 @@
 #define PILOT_LOOP_CNT 100
 
 
+
+// This multiplier is the number of milliamps per A/d converter unit.
+
+// First, you need to select the burden resistor for the CT. You choose the largest value possible such that
+// the maximum peak-to-peak voltage for the current range is 5 volts. To obtain this value, divide the maximum
+// outlet current by the Te. That value is the maximum CT current RMS. You must convert that to P-P, so multiply
+// by 2*sqrt(2). Divide 5 by that value and select the next lower standard resistor value. For the reference
+// design, Te is 1018 and the outlet maximum is 30. 5/((30/1018)*2*sqrt(2)) = 59.995, so a 56 ohm resistor
+// is called for. Call this value Rb (burden resistor).
+
+// Next, one must use Te and Rb to determine the volts-per-amp value. Note that the readCurrent()
+// method calculates the RMS value before the scaling factor, so RMS need not be taken into account.
+// (1 / Te) * Rb = Rb / Te = Volts per Amp. For the reference design, that's 55.009 mV.
+// Each count of the A/d converter is 4.882 mV (5/1024). V/A divided by V/unit is unit/A. For the reference
+// design, that's 11.26. But we want milliamps per unit, so divide that into 1000 to get 88.7625558. Round near...
+//#define DEFAULT_CURRENT_SCALE_FACTOR 106 // for RB = 47 - recommended for 30A max
+//#define DEFAULT_CURRENT_SCALE_FACTOR 184 // for RB = 27 - recommended for 50A max
+// Craig K, I arrived at 213 by scaling my previous multiplier of 225 down by the ratio of my panel meter reading of 28 with the OpenEVSE uncalibrated reading of 29.6
+// then upped the scale factor to 220 after fixing the zero offset by subtracing 900ma
+//#define DEFAULT_CURRENT_SCALE_FACTOR 220 // for RB = 22 - measured by Craig on his new OpenEVSE V3
+// NOTE: setting DEFAULT_CURRENT_SCALE_FACTOR TO 0 will disable the ammeter
+// until it is overridden via RAPI
+//#define DEFAULT_CURRENT_SCALE_FACTOR 220   // Craig K, average of three OpenEVSE controller calibrations
+#ifdef OPENEVSE_2
+#define DEFAULT_CURRENT_SCALE_FACTOR 186   // OpenEVSE II with a 27 Ohm burden resistor, after a 2-point calibration at 12.5A and 50A
+#else
+#define DEFAULT_CURRENT_SCALE_FACTOR 220   // OpenEVSE v2.5 and v3 with a 22 Ohm burden resistor (note that the schematic may say 28 Ohms by mistake)
+#endif
+
+// subtract this from ammeter current reading to correct zero offset
+#ifdef OPENEVSE_2
+#define DEFAULT_AMMETER_CURRENT_OFFSET 230 // OpenEVSE II with a 27 Ohm burden resistor, after a 2-point calibration at 12.5A and 50A
+#else
+#define DEFAULT_AMMETER_CURRENT_OFFSET 0   // OpenEVSE v2.5 and v3 with a 22 Ohm burden resistor.  Could use a more thorough calibration exercise to nails this down.
+#endif
+
+
+
 typedef unsigned long time_t;
 
 #ifdef __cplusplus
diff --git a/firmware/targets/samd/Gfi.cpp b/firmware/targets/samd/Gfi.cpp
index 2502a5f7..d1ab7824 100644
--- a/firmware/targets/samd/Gfi.cpp
+++ b/firmware/targets/samd/Gfi.cpp
@@ -24,7 +24,9 @@
 // interrupt service routing
 void gfi_isr()
 {
+#ifndef BYPASS_GFI
   g_EvseController.SetGfiTripped();
+#endif
 }
 
 
@@ -63,6 +65,9 @@ void Gfi::Reset()
 
 uint8_t Gfi::SelfTest()
 {
+#ifdef BYPASS_GFI
+  return 0;
+#endif
   //  RAPI_SERIAL_PORT.print("GST ");
   //  uint32_t sms = millis();
   int i;
diff --git a/firmware/targets/samd/eeprom_emulation.h b/firmware/targets/samd/eeprom_emulation.h
index b86c723d..4abb3abd 100644
--- a/firmware/targets/samd/eeprom_emulation.h
+++ b/firmware/targets/samd/eeprom_emulation.h
@@ -2,9 +2,9 @@
 
 #include <stdint.h>
 
-static uint8_t eeprom_read_byte (const uint8_t *__p) { return 0;}
-static uint16_t eeprom_read_word (const uint16_t *__p) { return 0;}
-static uint32_t eeprom_read_dword (const uint32_t *__p) { return 0;}
+static uint8_t eeprom_read_byte (const uint8_t *__p) { return 0xff;}
+static uint16_t eeprom_read_word (const uint16_t *__p) { return 0xffff;}
+static uint32_t eeprom_read_dword (const uint32_t *__p) { return 0xffffffff;}
 static void eeprom_write_byte (uint8_t *__p, uint8_t __value) {}
 static void eeprom_write_word (uint16_t *__p, uint16_t __value) {}
 static void eeprom_write_dword (uint32_t *__p, uint32_t __value) {}
diff --git a/firmware/targets/samd/platformio.ini b/firmware/targets/samd/platformio.ini
index 9ef4d5aa..4d06dc53 100644
--- a/firmware/targets/samd/platformio.ini
+++ b/firmware/targets/samd/platformio.ini
@@ -48,13 +48,15 @@ build_src_flags=
 extends = env:samd_us
 upload_protocol = atmel-ice
 build_type = release ;debug
-debug_tool = atmel-ice
+;debug_tool = atmel-ice
 build_src_flags=
   ${env:samd_us.build_src_flags}
   ;-UWATCHDOG
   -UBOOTLOCK
   -UHEARTBEAT_SUPERVISION
+  -DBYPASS_GFI ; disable GFI
 ;  -DCALIBRATE ; pilot calibration mode - for initial setup only
+; -DAMMETER_TEST ; ammeter test mode - for initial setup only
 
 # EU OpenEVSE
 [env:samd_eu]
diff --git a/firmware/targets/samd/target.h b/firmware/targets/samd/target.h
index 6f2fe3dc..1150b30a 100644
--- a/firmware/targets/samd/target.h
+++ b/firmware/targets/samd/target.h
@@ -8,6 +8,10 @@
 #define ADC_MAX 4095
 #define ADC_HALF 2048
 
+#define DEFAULT_CURRENT_SCALE_FACTOR    42
+#define DEFAULT_AMMETER_CURRENT_OFFSET 412
+
+
 // for J1772.ReadPilot()
 // 15 = ~13ms
 #define PILOT_LOOP_CNT 15

From 457c46c839d7a28949d50023d65d6b1979c0b98e Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Mon, 16 Mar 2026 20:31:38 -0700
Subject: [PATCH 27/59] SAMD ammeter calc

---
 firmware/open_evse/J1772EvseController.cpp | 16 ++++-
 firmware/open_evse/J1772EvseController.h   |  4 +-
 firmware/open_evse/rapi_proc.cpp           | 72 ++++++++++++----------
 firmware/targets/samd/platformio.ini       |  2 +-
 firmware/targets/samd/target.h             |  4 +-
 5 files changed, 61 insertions(+), 37 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 7dd23ad9..ab0300b4 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -56,6 +56,9 @@ void J1772EVSEController::readAmmeter()
 {
   WDT_RESET();
 
+#ifdef AMMETER_TEST
+  uint32_t max = 0;
+#endif
   unsigned long sum = 0;
   uint8_t zero_crossings = 0;
   unsigned long last_zero_crossing_time = 0, now_ms;
@@ -64,6 +67,9 @@ void J1772EVSEController::readAmmeter()
   unsigned int sample_count = 0;
   for(unsigned long start = millis(); ((now_ms = millis()) - start) < CURRENT_SAMPLE_INTERVAL; ) {
     uint16_t sample = adcCurrent.read();
+#ifdef AMMETER_TEST
+    if (max < sample) max = sample;
+#endif
     // If this isn't the first sample, and if the sign of the value differs from the
     // sign of the previous value, then count that as a zero crossing.
     if (!is_first_sample && ((last_sample > ADC_HALF) != (sample > ADC_HALF))) {
@@ -91,6 +97,14 @@ void J1772EVSEController::readAmmeter()
       // But additionally, that value must be scaled to a real current value.
       // we will do that elsewhere
       m_AmmeterReading = ulong_sqrt(sum / sample_count);
+#ifdef AMMETER_TEST
+      {
+        char s[80];
+        long instantma = m_AmmeterReading*m_CurrentScaleFactor - m_AmmeterCurrentOffset;
+        sprintf(s,"%u %u %d",max,m_AmmeterReading,instantma);
+        RAPI_SERIAL_PORT.println(s);
+      }
+#endif
       return;
     }
   }
@@ -1075,7 +1089,7 @@ void J1772EVSEController::Init()
   m_AmmeterReading = 0;
   m_ChargingCurrent = 0;
 
-#ifdef AMMETER_TEST
+#ifdef AMMETER_TESTtt
   // for debugging only
   while (1) {
     char s[80];
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index 4c4a3f95..b1475e02 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -489,11 +489,11 @@ int GetHearbeatTrigger();
   int16_t GetCurrentScaleFactor() { return m_CurrentScaleFactor; }
   void SetAmmeterCurrentOffset(int32_t offset) {
     m_AmmeterCurrentOffset = offset;
-    eeprom_write_word((uint16_t*)EOFS_AMMETER_CURR_OFFSET,offset);
+    eeprom_write_word((uint16_t*)EOFS_AMMETER_CURR_OFFSET,((int16_t)offset));
   }
   void SetCurrentScaleFactor(int32_t scale) {
     m_CurrentScaleFactor = scale;
-    eeprom_write_word((uint16_t*)EOFS_CURRENT_SCALE_FACTOR,scale);
+    eeprom_write_word((uint16_t*)EOFS_CURRENT_SCALE_FACTOR,((int16_t)scale));
   }
 #ifdef ECVF_AMMETER_CAL
   uint8_t AmmeterCalEnabled() { 
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index a4161f5f..95d39680 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -59,15 +59,25 @@ uint8_t htou8(const char *s)
   return u;
 }
 
-// convert decimal string to uint32_t
-uint32_t dtou32(const char *s)
+
+// convert decimal string to int32_t
+uint32_t dtoi32(const char *s)
 {
-  uint32_t u = 0;
+  int minus;
+  int32_t i = 0;
+  if (*s == '-') {
+    minus = 1;
+    s++;
+  }
+  else minus = 0;
+  
   while (*s) {
-    u *= 10;
-    u += *(s++) - '0';
+    i *= 10;
+    i += *(s++) - '0';
   }
-  return u;
+  if (minus) i = -i;
+
+  return i;
 }
 
 #ifdef RAPI_I2C
@@ -273,7 +283,7 @@ int EvseRapiProcessor::processCmd()
 #ifdef LCD16X2
     case 'B': // LCD backlight
       if (tokenCnt == 2) {
-	g_OBD.LcdSetBacklightColor(dtou32(tokens[1]));
+	g_OBD.LcdSetBacklightColor(dtoi32(tokens[1]));
 	rc = 0;
       }
       break;
@@ -346,7 +356,7 @@ int EvseRapiProcessor::processCmd()
 #ifdef TEMPERATURE_MONITORING
     case 'O': // print to LCD
       if (tokenCnt == 2) {
-        u1.i16 = dtou32(tokens[1]);
+        u1.i16 = dtoi32(tokens[1]);
         if (u1.i16 > 0) {
           g_TempMonitor.SetPanicTemperature(u1.i16);
           rc = 0;
@@ -357,8 +367,8 @@ int EvseRapiProcessor::processCmd()
 #ifdef LCD16X2
     case 'P': // print to LCD
       if ((tokenCnt >= 4) && !g_EvseController.InHardFault()) {
-	u1.u = dtou32(tokens[1]); // x
-	u2.u = dtou32(tokens[2]); // y
+	u1.u = dtoi32(tokens[1]); // x
+	u2.u = dtoi32(tokens[2]); // y
 	// now restore the spaces that were replaced w/ nulls by tokenizing
 	for (u3.i=4;u3.i < tokenCnt;u3.i++) {
 	  *(tokens[u3.i]-1) = ' ';
@@ -394,8 +404,8 @@ int EvseRapiProcessor::processCmd()
     case '1': // set RTC
       if (tokenCnt == 7) {
 	extern void SetRTC(uint8_t y,uint8_t m,uint8_t d,uint8_t h,uint8_t mn,uint8_t s);
-	SetRTC(dtou32(tokens[1]),dtou32(tokens[2]),dtou32(tokens[3]),
-	       dtou32(tokens[4]),dtou32(tokens[5]),dtou32(tokens[6]));
+	SetRTC(dtoi32(tokens[1]),dtoi32(tokens[2]),dtoi32(tokens[3]),
+	       dtoi32(tokens[4]),dtoi32(tokens[5]),dtoi32(tokens[6]));
 	rc = 0;
       }
       break;
@@ -412,7 +422,7 @@ int EvseRapiProcessor::processCmd()
     case '3': // set time limit
       if (tokenCnt == 2) {
 	if (g_EvseController.LimitsAllowed()) {
-	  g_EvseController.SetTimeLimit15(dtou32(tokens[1]));
+	  g_EvseController.SetTimeLimit15(dtoi32(tokens[1]));
 	  if (!g_OBD.UpdatesDisabled()) g_OBD.Update(OBD_UPD_FORCE);
 	  rc = 0;
 	}
@@ -422,7 +432,7 @@ int EvseRapiProcessor::processCmd()
 #if defined(AUTH_LOCK) && !defined(AUTH_LOCK_REG)
     case '4': // auth lock
       if (tokenCnt == 2) {
-	g_EvseController.AuthLock((int8_t)dtou32(tokens[1]),1);
+	g_EvseController.AuthLock((int8_t)dtoi32(tokens[1]),1);
 	rc = 0;
       }
       break;
@@ -453,8 +463,8 @@ int EvseRapiProcessor::processCmd()
 #ifdef AMMETER
     case 'A':
       if (tokenCnt == 3) {
-	g_EvseController.SetCurrentScaleFactor(dtou32(tokens[1]));
-	g_EvseController.SetAmmeterCurrentOffset(dtou32(tokens[2]));
+	g_EvseController.SetCurrentScaleFactor(dtoi32(tokens[1]));
+	g_EvseController.SetAmmeterCurrentOffset(dtoi32(tokens[2]));
 	rc = 0;
       }
       break;
@@ -474,7 +484,7 @@ int EvseRapiProcessor::processCmd()
 #endif // BOOTLOCK
     case 'C': // current capacity
       if ((tokenCnt == 2) || (tokenCnt == 3)) {
-	u2.u8 = dtou32(tokens[1]);
+	u2.u8 = dtoi32(tokens[1]);
 	if ((tokenCnt == 3) && (*tokens[2] == 'M')) {
 	  rc = g_EvseController.SetMaxHwCurrentCapacity(u2.u8);
 	  sprintf(buffer,"%d",(int)g_EvseController.GetMaxHwCurrentCapacity());
@@ -510,7 +520,7 @@ int EvseRapiProcessor::processCmd()
     case 'H': // cHarge limit
       if (tokenCnt == 2) {
 	if (g_EvseController.LimitsAllowed()) {
-	  g_EvseController.SetChargeLimitkWh(dtou32(tokens[1]));
+	  g_EvseController.SetChargeLimitkWh(dtoi32(tokens[1]));
 	  if (!g_OBD.UpdatesDisabled()) g_OBD.Update(OBD_UPD_FORCE);
 	  rc = 0;
 	}
@@ -519,7 +529,7 @@ int EvseRapiProcessor::processCmd()
 #endif // CHARGE_LIMIT
 #ifdef KWH_RECORDING
     case 'K': // set accumulated kwh
-      g_EnergyMeter.SetTotkWh(dtou32(tokens[1]));
+      g_EnergyMeter.SetTotkWh(dtoi32(tokens[1]));
       g_EnergyMeter.SaveTotkWh();
       rc = 0;
       break;
@@ -547,7 +557,7 @@ int EvseRapiProcessor::processCmd()
 #ifdef VOLTMETER
     case 'M':
       if (tokenCnt == 3) {
-        g_EvseController.SetVoltmeter(dtou32(tokens[1]),dtou32(tokens[2]));
+        g_EvseController.SetVoltmeter(dtoi32(tokens[1]),dtoi32(tokens[2]));
 	rc = 0;
       }
       break;
@@ -556,10 +566,10 @@ int EvseRapiProcessor::processCmd()
     case 'T': // timer
       if (tokenCnt == 5) {
 	extern DelayTimer g_DelayTimer;
-	u1.u8 = (uint8_t)dtou32(tokens[1]);
-	u2.u8 = (uint8_t)dtou32(tokens[2]);
-	u3.u8 = (uint8_t)dtou32(tokens[3]);
-	u4.u8 = (uint8_t)dtou32(tokens[4]);
+	u1.u8 = (uint8_t)dtoi32(tokens[1]);
+	u2.u8 = (uint8_t)dtoi32(tokens[2]);
+	u3.u8 = (uint8_t)dtoi32(tokens[3]);
+	u4.u8 = (uint8_t)dtoi32(tokens[4]);
 	if ((u1.u8 == 0) && (u2.u8 == 0) && (u3.u8 == 0) && (u4.u8 == 0)) {
 	  g_DelayTimer.Disable();
 	}
@@ -576,7 +586,7 @@ int EvseRapiProcessor::processCmd()
 #if defined(KWH_RECORDING) && !defined(VOLTMETER)
     case 'V': // set voltage
       if (tokenCnt == 2) {
-        g_EvseController.SetMV(dtou32(tokens[1]));
+        g_EvseController.SetMV(dtoi32(tokens[1]));
 	rc = 0;
       }
       break;
@@ -589,15 +599,15 @@ int EvseRapiProcessor::processCmd()
       }
       else if (tokenCnt == 3) { //This is a full HEARTBEAT_SUPERVISION setpoint command with both parameters
 	    rc = 0;
-        u1.u16 = (uint16_t)dtou32(tokens[1]);	// HS Interval in seconds.  0 = disabled
-        u2.u8 = (uint8_t)dtou32(tokens[2]);	// HS fallback current, in amperes 
+        u1.u16 = (uint16_t)dtoi32(tokens[1]);	// HS Interval in seconds.  0 = disabled
+        u2.u8 = (uint8_t)dtoi32(tokens[2]);	// HS fallback current, in amperes 
 		if (u1.u16 == 0) { //Test for deactivation {
           rc = g_EvseController.HsRestoreAmpacity();
 		}
 		rc |= g_EvseController.HeartbeatSupervision(u1.u16, u2.u8);
       }
       else if (tokenCnt == 2) { //This is a command to ack a heartbeat supervision miss
-        u1.u8 = (uint8_t)dtou32(tokens[1]); //Magic cookie
+        u1.u8 = (uint8_t)dtoi32(tokens[1]); //Magic cookie
         rc = g_EvseController.HsAckMissedPulse(u1.u8);
       }
       else { //Invalid number of tokens, return 1
@@ -842,7 +852,7 @@ int EvseRapiProcessor::processCmd()
 #ifdef FAKE_CHARGING_CURRENT
     case '0': // set fake charging current
       if (tokenCnt == 2) {
-	g_EvseController.SetChargingCurrent(dtou32(tokens[1])*1000);
+	g_EvseController.SetChargingCurrent(dtoi32(tokens[1])*1000);
 	g_OBD.SetAmmeterDirty(1);
 	g_OBD.Update(OBD_UPD_FORCE);
 	rc = 0;
@@ -857,8 +867,8 @@ int EvseRapiProcessor::processCmd()
     switch(*s) {
     case '0': // set relayCloseMs
       if (tokenCnt == 3) {
-	u1.u8 = dtou32(tokens[1]);
-	u2.u8 = dtou32(tokens[2]);
+	u1.u8 = dtoi32(tokens[1]);
+	u2.u8 = dtoi32(tokens[2]);
 	g_EvseController.setPwmPinParms(u1.u8,u2.u8);
 	sprintf(g_sTmp,"\nZ0 %u %u",(unsigned)u1.u8,(unsigned)u2.u8);
 	Serial.println(g_sTmp);
diff --git a/firmware/targets/samd/platformio.ini b/firmware/targets/samd/platformio.ini
index 4d06dc53..bfa86905 100644
--- a/firmware/targets/samd/platformio.ini
+++ b/firmware/targets/samd/platformio.ini
@@ -56,7 +56,7 @@ build_src_flags=
   -UHEARTBEAT_SUPERVISION
   -DBYPASS_GFI ; disable GFI
 ;  -DCALIBRATE ; pilot calibration mode - for initial setup only
-; -DAMMETER_TEST ; ammeter test mode - for initial setup only
+;  -DAMMETER_TEST ; ammeter test mode - for initial setup only
 
 # EU OpenEVSE
 [env:samd_eu]
diff --git a/firmware/targets/samd/target.h b/firmware/targets/samd/target.h
index 1150b30a..5798f6ca 100644
--- a/firmware/targets/samd/target.h
+++ b/firmware/targets/samd/target.h
@@ -8,8 +8,8 @@
 #define ADC_MAX 4095
 #define ADC_HALF 2048
 
-#define DEFAULT_CURRENT_SCALE_FACTOR    42
-#define DEFAULT_AMMETER_CURRENT_OFFSET 412
+#define DEFAULT_CURRENT_SCALE_FACTOR    37
+#define DEFAULT_AMMETER_CURRENT_OFFSET -135
 
 
 // for J1772.ReadPilot()

From 7ab2b658dea20e72d74870eb863cd3ccf9638473 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 25 Mar 2026 17:03:47 -0700
Subject: [PATCH 28/59] Sparkfun EEPROM support for SAMD

---
 firmware/open_evse/EnergyMeter.cpp       |  2 +-
 firmware/open_evse/EnergyMeter.h         |  3 ++-
 firmware/open_evse/J1772EvseController.h |  6 ++++-
 firmware/open_evse/main.cpp              |  4 ++-
 firmware/targets/samd/eeprom_emulation.h | 10 --------
 firmware/targets/samd/platformio.ini     |  5 ++--
 firmware/targets/samd/target.cpp         | 11 ++++++++
 firmware/targets/samd/target.h           | 32 ++++++++++++++++++++++--
 8 files changed, 54 insertions(+), 19 deletions(-)
 delete mode 100644 firmware/targets/samd/eeprom_emulation.h

diff --git a/firmware/open_evse/EnergyMeter.cpp b/firmware/open_evse/EnergyMeter.cpp
index 9c6ec2b6..4b0f4af5 100644
--- a/firmware/open_evse/EnergyMeter.cpp
+++ b/firmware/open_evse/EnergyMeter.cpp
@@ -5,7 +5,7 @@
 EnergyMeter g_EnergyMeter;
 
 
-EnergyMeter::EnergyMeter()
+void EnergyMeter::Init()
 {
   m_bFlags = 0;
   m_wattSeconds = 0;
diff --git a/firmware/open_evse/EnergyMeter.h b/firmware/open_evse/EnergyMeter.h
index 8c4308bc..713526d1 100644
--- a/firmware/open_evse/EnergyMeter.h
+++ b/firmware/open_evse/EnergyMeter.h
@@ -31,8 +31,9 @@ class EnergyMeter {
   void endSession();
 
 public:
-  EnergyMeter();
+  EnergyMeter() {}
 
+  void Init();
   void Update();
   void SaveTotkWh();
   void SetTotkWh(uint32_t whtot) { m_wattHoursTot = whtot; }
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index b1475e02..e20a6d61 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -38,7 +38,8 @@
 //reserved #define EVSE_STATE_PILOT_ERROR 0x0C // pilot self test error
 //reserved #define EVSE_STATE_TEMP_SENSOR_FAULT 0x0D // temp sensor dead
 #define EVSE_STATE_RELAY_CLOSURE_FAULT 0x0E
-#define EVSE_FAULT_STATE_END EVSE_STATE_RELAY_CLOSURE_FAULT
+#define EVSE_STATE_EEPROM_FAILURE 0x0F // SAMD only
+#define EVSE_FAULT_STATE_END EVSE_STATE_EEPROM_FAILURE
            
 #define EVSE_STATE_SLEEPING 0xfe // waiting for timer
 #define EVSE_STATE_DISABLED 0xff // disabled
@@ -300,6 +301,9 @@ class J1772EVSEController {
   uint8_t GetState() { 
     return m_EvseState; 
   }
+  void SetState(uint8_t state) {
+    m_EvseState = state;
+  }
   uint8_t GetPrevState() { 
     return m_PrevEvseState; 
   }
diff --git a/firmware/open_evse/main.cpp b/firmware/open_evse/main.cpp
index 35d0d4d3..b424dd3e 100644
--- a/firmware/open_evse/main.cpp
+++ b/firmware/open_evse/main.cpp
@@ -2449,10 +2449,12 @@ void setup()
   
   delay(400);  // give I2C devices time to be ready before running code that wants to initialize I2C devices.  Otherwise a hang can occur upon powerup.
   
-  Serial.begin(SERIAL_BAUD);
+  RAPI_SERIAL_PORT.begin(SERIAL_BAUD);
 
   initTarget();
 
+  g_EnergyMeter.Init();
+
 #ifdef BTN_MENU
   g_BtnHandler.init();
 #endif // BTN_MENU
diff --git a/firmware/targets/samd/eeprom_emulation.h b/firmware/targets/samd/eeprom_emulation.h
deleted file mode 100644
index 4abb3abd..00000000
--- a/firmware/targets/samd/eeprom_emulation.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#pragma once
-
-#include <stdint.h>
-
-static uint8_t eeprom_read_byte (const uint8_t *__p) { return 0xff;}
-static uint16_t eeprom_read_word (const uint16_t *__p) { return 0xffff;}
-static uint32_t eeprom_read_dword (const uint32_t *__p) { return 0xffffffff;}
-static void eeprom_write_byte (uint8_t *__p, uint8_t __value) {}
-static void eeprom_write_word (uint16_t *__p, uint16_t __value) {}
-static void eeprom_write_dword (uint32_t *__p, uint32_t __value) {}
diff --git a/firmware/targets/samd/platformio.ini b/firmware/targets/samd/platformio.ini
index bfa86905..4eefa764 100644
--- a/firmware/targets/samd/platformio.ini
+++ b/firmware/targets/samd/platformio.ini
@@ -1,7 +1,7 @@
 [samd]
 lib_deps = ${common.lib_deps}
   https://github.com/lincomatic/Adafruit_SleepyDog.git
-;extra_scripts = pre:firmware/targets/samd/no_erase_upload.py
+  https://github.com/sparkfun/SparkFun_External_EEPROM_Arduino_Library.git
 build_src_flags =
   -D TARGET_SAMD
   -D EEPROM_FLASH_STORE_KB=48
@@ -26,7 +26,6 @@ platform = atmelsam
 framework = arduino
 board = zeroUSB
 build_type = release
-#board = samd21g18a
 monitor_speed=115200
 ;extra_scripts = ${samd.extra_scripts}
 lib_deps = ${samd.lib_deps}
@@ -51,7 +50,7 @@ build_type = release ;debug
 ;debug_tool = atmel-ice
 build_src_flags=
   ${env:samd_us.build_src_flags}
-  ;-UWATCHDOG
+  -UWATCHDOG
   -UBOOTLOCK
   -UHEARTBEAT_SUPERVISION
   -DBYPASS_GFI ; disable GFI
diff --git a/firmware/targets/samd/target.cpp b/firmware/targets/samd/target.cpp
index 7259fc2f..3349b0fa 100644
--- a/firmware/targets/samd/target.cpp
+++ b/firmware/targets/samd/target.cpp
@@ -1,5 +1,7 @@
 #include "open_evse.h"
 
+ExternalEEPROM g_eeprom;
+
 //                                               A/B  B/C  C/D  D DS
 THRESH_DATA J1772EVSEController::m_ThreshData = {3948,3539,3258,0,492};
 
@@ -51,6 +53,15 @@ void DigitalPin::init(uint32_t pinnum,int idxjunk,PinMode mode)
 // platform-specific init
 void initTarget()
 {
+  Wire.begin();
+  g_eeprom.setMemoryType(512);
+  if (g_eeprom.begin() == false) {
+    g_EvseController.SetState(EVSE_STATE_EEPROM_FAILURE);
+    RapiInit();
+    RapiSendBootNotification();
+    while(1);
+  }
+
   //n.b. set BOD via fuses, not this code, as fuses may lock out BOD from being
   // manipulated in code, anyway
   // default factory fuse setting is 1.78V BOD enabled
diff --git a/firmware/targets/samd/target.h b/firmware/targets/samd/target.h
index 5798f6ca..3d1d3b7c 100644
--- a/firmware/targets/samd/target.h
+++ b/firmware/targets/samd/target.h
@@ -19,8 +19,6 @@
 
 #define GetVerStr(s) strcpy(s,VERSION)
 
-#include "eeprom_emulation.h"
-
 void wdt_disable();
 
 #ifdef WATCHDOG
@@ -98,4 +96,34 @@ class AdcPin {
 
 void getMcuId(uint8_t *mcuid);
 
+#include "SparkFun_External_EEPROM.h"
+extern ExternalEEPROM g_eeprom;
+
+static uint8_t eeprom_read_byte (const uint8_t *ofs) {
+  uint8_t ret = 0xFF;
+  g_eeprom.read((uint32_t) ofs,(uint8_t *)&ret,sizeof(ret));
+  return ret;
+}
+static uint16_t eeprom_read_word (const uint16_t *ofs) {
+  uint16_t ret = 0xFFFF;
+  g_eeprom.read((uint32_t) ofs,(uint8_t *)&ret,sizeof(ret));
+  return ret;
+}
+static uint32_t eeprom_read_dword (const uint32_t *ofs) {
+  uint32_t ret = 0xFFFFFFFF;
+  g_eeprom.read((uint32_t) ofs,(uint8_t *)&ret,sizeof(ret));
+  return ret;
+}
+static void eeprom_write_byte (uint8_t *ofs, uint8_t val) {
+  g_eeprom.write((uint32_t)ofs, (const uint8_t *)&val, sizeof(val));
+}
+static void eeprom_write_word (uint16_t *ofs, uint16_t val) {
+  g_eeprom.write((uint32_t)ofs, (const uint8_t *)&val, sizeof(val));
+}
+static void eeprom_write_dword (uint32_t *ofs, uint32_t val) {
+  g_eeprom.write((uint32_t)ofs, (const uint8_t *)&val, sizeof(val));
+}
+
+
+
 void initTarget();

From 0e8cd06b0c44ab9ebd235df966587cdb955e102b Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sun, 24 May 2026 18:04:42 -0400
Subject: [PATCH 29/59] Update build targets for v5/v6 hardware, bump version
 to D8.5.0, extend RTC year range to 2036

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 README.md                             | 32 ++-----------
 firmware/open_evse/main.cpp           |  4 +-
 firmware/targets/m328p/platformio.ini | 69 +++++++++++----------------
 firmware/targets/samd/platformio.ini  | 49 +++----------------
 platformio.ini                        | 21 ++++----
 prepare-release.sh                    | 28 ++++++-----
 6 files changed, 66 insertions(+), 137 deletions(-)

diff --git a/README.md b/README.md
index ff2bde14..5f2d87ce 100644
--- a/README.md
+++ b/README.md
@@ -1,42 +1,20 @@
 # OpenEVSE
 
-Firmware for OpenEVSE controller used in OpenEVSE Charging Stations sold in the USA, and OpenEnergyMonitor EmonEVSE units sold in (UK/EU).
+Firmware for OpenEVSE controller used in OpenEVSE Charging Stations.
 
 - OpenEVSE: <https://store.openevse.com/collections/all-products>
-- EmonEVSE: <https://shop.openenergymonitor.com/evse/>
 
-Based on OpenEVSE: Open Source Hardware J1772 Electric Vehicle Supply Equipment
-
-## USA
-
-TODO: add notes about USA OpenEVSE
-
-## UK/EU
-
-- Disable `AUTOSVCLEVEL` (autodetection is designed for split-phase)
-- Charging level default to `L2`
-- Set `MAX_CURRENT_CAPACITY_L2 32` (limit for single-phase charging in UK/EU)
-- Add '.EU' to version number
-- Enable LCD Redraw every couple of min (required for EMC/CE)
 
-### EmonEVSE
-
-EmonEVSE (non-tethered type-2 EVSE unit)
+Based on OpenEVSE: Open Source Hardware J1772 Electric Vehicle Supply Equipment
 
-- `PP_AUTO_AMPACITY` enabled to set max current based on non-tethered cable connected
-- Three-phase option with `THREEPHASE` enabled to calculate three-phase energy ( Unneeded with ESP32_WiFi firmware >= 4.2
 
 ## API Documentation
 
 - WIFI API: <http://github.com/openevse/ESP32_WiFi_V4.x/>
-- RAPI API: <https://github.com/openenergymonitor/open_evse/blob/master/firmware/open_evse/rapi_proc.h>
 
-## Resources
 
-- [OpenEnergyMonitor OpenEVSE Setup Guide](https://guide.openenergymonitor.org/integrations/openevse)
-- [OpenEnergyMonitor OpenEVSE Shop](https://shop.openenergymonitor.com/ev-charging/)
+## Resources
 
-- [OpenEVSE Controller Datasheet](https://github.com/OpenEVSE/OpenEVSE_PLUS/blob/master/OpenEVSE_PLUS_v5/OpenEVSE_Plus_v5.pdf)
 - [OpenEVSE Controller Hardware Repo](https://github.com/OpenEVSE/OpenEVSE_PLUS)
 - [OpenEVSE Project Homepage](https://openevse.com)
 
@@ -53,7 +31,7 @@ NOTES:
 
 `$ avrdude -p atmega328p -B6 -c usbasp -P usb -e -U flash:w:firmware.hex`
 
-ISP programmer required e.g [USBASP](https://www.amazon.co.uk/Hobby-Components-USBASP-Programmer-Adapter/dp/B06XYV162N)
+ISP programmer required
 
 ### Set AVR fuses
 
@@ -65,7 +43,7 @@ If writing eFuse fails ISBasp may need a [firmware update](https://www.vishnumai
 
 ***
 
-Tip Jar: I developed/maintain this firmware on a volunteer basis. Any donation, no matter how small, is greatly appreciated.
+Tip Jar: Lincomatic developed/maintain this firmware on a volunteer basis. Any donation, no matter how small, is greatly appreciated.
 
 [![Donate](https://img.shields.io/badge/Donate-PayPal-green.svg)](https://www.paypal.me/lincomatic)
 
diff --git a/firmware/open_evse/main.cpp b/firmware/open_evse/main.cpp
index b424dd3e..9e75a4c1 100644
--- a/firmware/open_evse/main.cpp
+++ b/firmware/open_evse/main.cpp
@@ -1729,8 +1729,8 @@ Menu *RTCMenuDay::Select()
 RTCMenuYear::RTCMenuYear()
 {
 }
-#define YEAR_MIN 23
-#define YEAR_MAX 33
+#define YEAR_MIN 26
+#define YEAR_MAX 36
 void RTCMenuYear::Init()
 {
   g_OBD.LcdPrint_P(0,g_psRTC_Year);
diff --git a/firmware/targets/m328p/platformio.ini b/firmware/targets/m328p/platformio.ini
index b4e7949a..e03f4ddb 100644
--- a/firmware/targets/m328p/platformio.ini
+++ b/firmware/targets/m328p/platformio.ini
@@ -4,19 +4,19 @@ upload_protocol = usbasp
 upload_flags = "-e -B0.5"
 lib_deps = ${common.lib_deps}
 build_src_flags =
+  ${common.build_flags}
   -D TARGET_M328P
   -D RAPI_SERIAL_PORT=Serial
   -D OEV6
   -D RELAY_PWM
   -D SHOW_DISABLED_TESTS
   -I firmware/targets/m328p
-  ${common.us_build_flags}
 build_src_filter =
   ${common.build_src_filter}
   +<../targets/m328p>
 
-# v6 CGMI OpenEVSE
-[env:m328p_v6]
+# v5 OpenEVSE
+[env:m328p_v5]
 platform = atmelavr@3.4.0
 board = openevse
 framework = arduino
@@ -27,45 +27,37 @@ build_src_filter =
   ${m328p.build_src_filter}
 build_src_flags=
   ${m328p.build_src_flags}
-  -D ENABLE_CGMI
-  -D NO_GROUND_RECORD_DELAY=2000
-  -D NO_AUTOSVCLEVEL
-  -D DEFAULT_SERVICE_LEVEL=2
-  -D OVERCURRENT_THRESHOLD=5
-  -D OVERCURRENT_TIMEOUT=10000UL
-  -D BOOTLOCK
-  -D 'VERSION="${common.version}.CGMI"'
+ -D 'VERSION="${common.version}"'
 
-# EU OpenEVSE
-[env:m328p_eu]
-extends = env:m328p_v6
+ # v6 CGMI OpenEVSE
+[env:m328p_v6]
+extends = env:m328p_v5
 build_src_flags=
   ${m328p.build_src_flags}
-  ${common.eu_build_flags}
-  -D MV_FOR_L2=230000L
-  -D 'VERSION="${common.version}.EU"'
+  -D ENABLE_CGMI
+  -D 'VERSION="${common.version}.CGMI"'
 
-# Non-tethered T2 EmonEVSE single-phase
-[env:m328p_emonevse]
-extends = env:m328p_v6
+ # v5 OpenEVSE RTC LCD BTN
+[env:m328p_v5_RTC_BTN_LCD]
+extends = env:m328p_v5
 build_src_flags=
   ${m328p.build_src_flags}
-  ${common.eu_build_flags}
-  -D PP_AUTO_AMPACITY
-  -D MV_FOR_L2=230000L
-  -D 'VERSION="${common.version}.T2"'
+  -D AUTOSVCLEVEL
+  -D BTN_MENU
+  -D HAVE_RTC
+  -D DELAY_TIMER
+  -D RGBLCD
+  -D CHARGE_LIMIT
+  -D TIME_LIMIT
+  -D TEMPERATURE_THROTTLING
+  -D 'VERSION="${common.version}.v5RTCRGBLCD"'
 
-# legacy openevse with 16x2 RGBLCD and front panel button
-[env:m328p_rgblcd]
+# openevse v6 with 16x2 RGBLCD and front panel button
+[env:m328p_v6_RTC_BTN_LCD]
 extends = env:m328p_v6
 build_src_flags=
   ${m328p.build_src_flags}
-  -UOEV6
-  -UHEARTBEAT_SUPERVISION
-  -UBOOTLOCK
   -D ENABLE_CGMI
-  -D OVERCURRENT_THRESHOLD=5
-  -D OVERCURRENT_TIMEOUT=10000UL
   -D BTN_MENU
   -D HAVE_RTC
   -D DELAY_TIMER
@@ -73,16 +65,11 @@ build_src_flags=
   -D CHARGE_LIMIT
   -D TIME_LIMIT
   -D TEMPERATURE_THROTTLING
-  -D 'VERSION="${common.version}"'
+  -D 'VERSION="${common.version}.CGMI_RTCRGBLCD"'
+
+   
+
+
 
-# Non-tethered T2 EmonEVSE three-phase
-# Deprecated, unneeded with wifi fw > 4.1.7
-; [env:emonevse_3ph]
-; extends = env:m328p
-; build_src_flags=
-;   ${common.eu_build_flags}
-;   -D PP_AUTO_AMPACITY
-;   -D THREEPHASE
-;   -D 'VERSION="${common.version}.3P"'
 
 
diff --git a/firmware/targets/samd/platformio.ini b/firmware/targets/samd/platformio.ini
index 4eefa764..f8637d44 100644
--- a/firmware/targets/samd/platformio.ini
+++ b/firmware/targets/samd/platformio.ini
@@ -7,21 +7,14 @@ build_src_flags =
   -D EEPROM_FLASH_STORE_KB=48
   -D RAPI_SERIAL_PORT=Serial1
   -D ENABLE_CGMI
-  -D NO_GROUND_RECORD_DELAY=2000
-  -D NO_AUTOSVCLEVEL
-  -D DEFAULT_SERVICE_LEVEL=2
-  -D OVERCURRENT_THRESHOLD=5
-  -D OVERCURRENT_TIMEOUT=10000UL
-  -D BOOTLOCK
   -I firmware/targets/samd
-  ${common.us_build_flags}
 build_src_filter =
   ${common.build_src_filter}
   +<../targets/samd>
 
 
 # SAMD CGMI OpenEVSE
-[env:samd_us]
+[env:samd]
 platform = atmelsam
 framework = arduino
 board = zeroUSB
@@ -33,23 +26,21 @@ build_src_filter =
   ${samd.build_src_filter}
 build_src_flags=
   ${samd.build_src_flags}
+  ${common.build_flags}
   -D 'VERSION="${common.version}.SAMD"'
 
 # # SAMD CGMI OpenEVSE (Atmel-ICE upload/programming)
-[env:samd_us_ice]
-extends = env:samd_us
+[env:samd_ice]
+extends = env:samd
 upload_protocol = atmel-ice
 build_type = release
-build_src_flags=
-  ${env:samd_us.build_src_flags}
 
-[env:samd_us_ice_dev] ; don't use this.. for dev/debug only
-extends = env:samd_us
+[env:samd_ice_dev] ; don't use this.. for dev/debug only
+extends = env:samd
 upload_protocol = atmel-ice
 build_type = release ;debug
 ;debug_tool = atmel-ice
 build_src_flags=
-  ${env:samd_us.build_src_flags}
   -UWATCHDOG
   -UBOOTLOCK
   -UHEARTBEAT_SUPERVISION
@@ -57,35 +48,7 @@ build_src_flags=
 ;  -DCALIBRATE ; pilot calibration mode - for initial setup only
 ;  -DAMMETER_TEST ; ammeter test mode - for initial setup only
 
-# EU OpenEVSE
-[env:samd_eu]
-extends = env:samd_us
-;extra_scripts = ${samd.extra_scripts}
-build_src_flags=
-  ${samd.build_src_flags}
-  ${common.eu_build_flags}
-  -D MV_FOR_L2=230000L
-  -D 'VERSION="${common.version}.EU"'
 
-# Non-tethered T2 EmonEVSE single-phase
-[env:samd_emonevse]
-extends = env:samd_us
-;extra_scripts = ${samd.extra_scripts}
-build_src_flags=
-  ${samd.build_src_flags}
-  ${common.eu_build_flags}
-  -D PP_AUTO_AMPACITY
-  -D MV_FOR_L2=230000L
-  -D 'VERSION="${common.version}.T2"'
 
-# Non-tethered T2 EmonEVSE three-phase
-# Deprecated, unneeded with wifi fw > 4.1.7
-; [env:emonevse_3ph]
-; extends = env:openevse
-; build_src_flags=
-;   ${common.eu_build_flags}
-;   -D PP_AUTO_AMPACITY
-;   -D THREEPHASE
-;   -D 'VERSION="${common.version}.3P"'
 
 
diff --git a/platformio.ini b/platformio.ini
index 1f191b05..bab61191 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -16,7 +16,7 @@ extra_configs =
 
 [common]
 lib_deps =
-version = D8.2.3
+version = D8.5.0
 build_src_filter =
    +<*.cpp>
 build_flags =
@@ -27,20 +27,15 @@ build_flags =
   -D RAPI_SERIAL
   -D RAPI_WF
   -D RAPI_BTN
-  #-D TIME_LIMIT
-  #-D CHARGE_LIMIT
   -D MENNEKES_LOCK
+  -D PP_AUTO_AMPACITY
+  -D BOOTLOCK
   -D HEARTBEAT_SUPERVISION
-us_build_flags =
-  ${common.build_flags}
-  -D AUTOSVCLEVEL
-  #-D BOOTLOCK
-eu_build_flags =
-  ${common.build_flags}
   -D NO_AUTOSVCLEVEL
-  -D PERIODIC_LCD_REFRESH_MS=120000UL
-  -D DEFAULT_CURRENT_CAPACITY_L2=32
-  -D MAX_CURRENT_CAPACITY_L2=32
+  -D DEFAULT_SERVICE_LEVEL=2
+  -D DEFAULT_CURRENT_CAPACITY_L2=24
+  -D MAX_CURRENT_CAPACITY_L2=80
   -D OVERCURRENT_THRESHOLD=5
   -D OVERCURRENT_TIMEOUT=10000UL
-  -D DEFAULT_SERVICE_LEVEL=2
\ No newline at end of file
+  -D PERIODIC_LCD_REFRESH_MS=120000UL
+  -D NO_GROUND_RECORD_DELAY=2000
\ No newline at end of file
diff --git a/prepare-release.sh b/prepare-release.sh
index 40d06150..96449ded 100755
--- a/prepare-release.sh
+++ b/prepare-release.sh
@@ -1,18 +1,24 @@
 #!/bin/bash
 
-# Script to compile all released enviroments and copy build artifacts to project root for easy upload to github releases. 
+# Script to compile all released environments and copy build artifacts to firmware/targets/ for easy upload to github releases.
 
-pio run -e emonevse
-pio run -e openevse
-pio run -e emonevse_eu
-pio run -e emonevse_v6
+mkdir -p firmware/targets
 
-cp .pio/build/emonevse/firmware.hex emonevse.hex
-cp .pio/build/openevse/firmware.hex openevse.hex
-cp .pio/build/openevse_eu/firmware.hex openevse_eu.hex
-cp .pio/build/openevse_v6/firmware.hex openevse_v6cgmi.hex
-ls *.hex
+pio run -e m328p_v6
+cp .pio/build/m328p_v6/firmware.hex firmware/targets/m328p_openevse_v6_CGMI.hex
 
-echo "Done" 
+pio run -e m328p_v5
+cp .pio/build/m328p_v5/firmware.hex firmware/targets/m328p_openevse_v5.hex
 
+pio run -e m328p_v6_RTC_BTN_LCD
+cp .pio/build/m328p_v6_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_v6_RTC_BTN_LCD.hex
 
+pio run -e m328p_v5_RTC_BTN_LCD
+cp .pio/build/m328p_v5_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_v5_RTC_BTN_LCD.hex
+
+pio run -e samd
+cp .pio/build/samd_us/firmware.bin firmware/targets/arm_samd_openevse_nxt.bin
+
+ls firmware/targets/
+
+echo "Done"

From a5ee03ce87f3ee558d8d821772ab17118e611403 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sun, 24 May 2026 20:13:28 -0400
Subject: [PATCH 30/59] Update CI workflows for v5/v6/SAMD build targets on
 linco-work branch

- build.yml: trigger on linco-work branch, reference @linco-work workflows
- build_platformio.yml: replace old environments with m328p_v5, m328p_v6,
  m328p_v5_RTC_BTN_LCD, m328p_v6_RTC_BTN_LCD, samd; add SAMD .bin handling
- release.yml: include *.bin artifacts alongside *.hex for SAMD releases

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 .github/workflows/build.yml            | 11 +++---
 .github/workflows/build_platformio.yml | 51 ++++++++++++++++++--------
 .github/workflows/release.yml          | 13 ++++---
 3 files changed, 49 insertions(+), 26 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index a3483190..00159de7 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -4,7 +4,7 @@ on:
   workflow_dispatch:
   push:
     branches:
-      - master
+      - linco-work
   pull_request:
 
 jobs:
@@ -18,18 +18,17 @@ jobs:
 
   build_platform_io:
     name: Build using PlatformIO
-    uses: OpenEVSE/open_evse/.github/workflows/build_platformio.yml@master
+    uses: OpenEVSE/open_evse/.github/workflows/build_platformio.yml@linco-work
 
   build_arduino:
     name: Build using Arduino
-    uses: OpenEVSE/open_evse/.github/workflows/build_arduino.yml@master
+    uses: OpenEVSE/open_evse/.github/workflows/build_arduino.yml@linco-work
 
   release:
     name: Create pre-release
 
     needs:
       - build_platform_io
-      - build_arduino
-    if: github.ref == 'refs/heads/master'
+    if: github.ref == 'refs/heads/linco-work'
 
-    uses: OpenEVSE/open_evse/.github/workflows/release.yml@master
+    uses: OpenEVSE/open_evse/.github/workflows/release.yml@linco-work
diff --git a/.github/workflows/build_platformio.yml b/.github/workflows/build_platformio.yml
index e7a824a0..2cc51522 100644
--- a/.github/workflows/build_platformio.yml
+++ b/.github/workflows/build_platformio.yml
@@ -12,24 +12,31 @@ jobs:
       fail-fast: false
       matrix:
         include:
-          - env: openevse_1-8-3
+          - env: m328p_v5
             python: 3.x
-            platformio: 6.1.5 
-          - env: openevse_latest
+            platformio: 6.1.5
+            arch: avr
+            artifact: firmware.hex
+          - env: m328p_v6
             python: 3.x
-            platformio: 6.1.5 
-          - env: openevse
+            platformio: 6.1.5
+            arch: avr
+            artifact: firmware.hex
+          - env: m328p_v5_RTC_BTN_LCD
             python: 3.x
-            platformio: 6.1.5 
-          - env: openevse_eu
+            platformio: 6.1.5
+            arch: avr
+            artifact: firmware.hex
+          - env: m328p_v6_RTC_BTN_LCD
             python: 3.x
-            platformio: 6.1.5 
-          - env: openevse_v6
+            platformio: 6.1.5
+            arch: avr
+            artifact: firmware.hex
+          - env: samd
             python: 3.x
-            platformio: 6.1.5 
-          - env: emonevse
-            python: 3.x
-            platformio: 6.1.5 
+            platformio: 6.1.5
+            arch: samd
+            artifact: firmware.bin
 
     steps:
     - uses: actions/checkout@v2
@@ -61,7 +68,8 @@ jobs:
     - name: Run PlatformIO
       run: pio run -e ${{ matrix.env }}
 
-    - name: Get compiler and output info
+    - name: Get compiler and output info (AVR)
+      if: matrix.arch == 'avr'
       run: |
         NAME=${{ matrix.env }}
         BUILT_TOOL="Platform IO"
@@ -72,10 +80,23 @@ jobs:
 
         source ci/info_common.sh info.json
 
+    - name: Get build info (SAMD)
+      if: matrix.arch == 'samd'
+      run: |
+        BIN_SIZE=$(ls -l .pio/build/${{ matrix.env }}/firmware.bin | awk '{ print $5 }')
+        cat <<EOF >info.json
+        {
+          "name": "${{ matrix.env }}",
+          "built_tool": "Platform IO",
+          "arch": "samd",
+          "bin_size": $BIN_SIZE
+        }
+        EOF
+
     - name: Upload output to GitHub
       uses: actions/upload-artifact@v4
       with:
         name: ${{ matrix.env }}
         path: |
-          .pio/build/${{ matrix.env }}/firmware.hex
+          .pio/build/${{ matrix.env }}/${{ matrix.artifact }}
           info.json
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml
index 71a902b2..7d53f2d1 100644
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -19,11 +19,13 @@ jobs:
 
     - name: Rename images to something more sensible
       run: |
-        find artifacts -name '*.hex' | while read -r image; do
-          dir=$(dirname "${image}")
-          board=$(basename "${dir}")
-          echo mv "$image" "$board.hex"
-          mv "$image" "$board.hex"
+        for ext in hex bin; do
+          find artifacts -name "*.$ext" | while read -r image; do
+            dir=$(dirname "${image}")
+            board=$(basename "${dir}")
+            echo mv "$image" "$board.$ext"
+            mv "$image" "$board.$ext"
+          done
         done
         jq -s . $(find -name info.json) > build_info.json
         jq -r '(map(keys) | add | unique) as $cols | map(. as $row | $cols | map($row[.])) as $rows | $cols, $rows[] | @csv' build_info.json > build_info.csv
@@ -37,5 +39,6 @@ jobs:
         title: "Development Build"
         files: |
           *.hex
+          *.bin
           build_info.json
           build_info.csv

From 361871dcbf1de31415e26328d06117ec4ac10d3f Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sun, 24 May 2026 20:19:53 -0400
Subject: [PATCH 31/59] Update deprecated GitHub Actions to current versions

actions/cache v2 -> v4, actions/checkout v2 -> v4, actions/setup-python v2 -> v5

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 .github/workflows/build_arduino.yml       | 4 ++--
 .github/workflows/build_platformio.yml    | 8 ++++----
 .github/workflows/release_validation.yaml | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/build_arduino.yml b/.github/workflows/build_arduino.yml
index c1a28e88..86ddc302 100644
--- a/.github/workflows/build_arduino.yml
+++ b/.github/workflows/build_arduino.yml
@@ -27,14 +27,14 @@ jobs:
 
     steps:
       - name: Cache Arduino
-        uses: actions/cache@v2
+        uses: actions/cache@v4
         with:
           path: ~/.arduino15
           key: ${{ runner.os }}-${{ matrix.name }}-arduino-15-${{ hashFiles('**/packages.txt') }}
           restore-keys: |
             ${{ runner.os }}-${{ matrix.name }}-arduino-15-
 
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
 
       - name: Setup Arduino CLI
         uses: arduino/setup-arduino-cli@v1
diff --git a/.github/workflows/build_platformio.yml b/.github/workflows/build_platformio.yml
index 2cc51522..c6b2f56f 100644
--- a/.github/workflows/build_platformio.yml
+++ b/.github/workflows/build_platformio.yml
@@ -39,10 +39,10 @@ jobs:
             artifact: firmware.bin
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v4
 
     - name: Cache pip
-      uses: actions/cache@v2
+      uses: actions/cache@v4
       with:
         path: ~/.cache/pip
         key: ${{ runner.os }}-${{ matrix.env }}-pip-${{ hashFiles('**/requirements.txt') }}
@@ -50,13 +50,13 @@ jobs:
           ${{ runner.os }}-${{ matrix.env }}-pip-
 
     - name: Cache PlatformIO
-      uses: actions/cache@v2
+      uses: actions/cache@v4
       with:
         path: ~/.platformio
         key: ${{ runner.os }}-${{ matrix.env }}-${{ hashFiles('**/lockfiles') }}
 
     - name: Set up Python
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v5
       with:
         python-version: '${{ matrix.python }}'
 
diff --git a/.github/workflows/release_validation.yaml b/.github/workflows/release_validation.yaml
index e7edc112..68b90935 100644
--- a/.github/workflows/release_validation.yaml
+++ b/.github/workflows/release_validation.yaml
@@ -15,7 +15,7 @@ jobs:
 
     steps:
       ### Check the version number in the code matches the tag number
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
 
       - name: Retrieve the version number(s)
         run: |

From 6261a568ec0d24a0d249cc8e4041dfdd5cb90c6d Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sun, 24 May 2026 20:30:55 -0400
Subject: [PATCH 32/59] Opt into Node.js 24 for GitHub Actions to resolve
 deprecation warnings

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 .github/workflows/build_arduino.yml    | 3 +++
 .github/workflows/build_platformio.yml | 3 +++
 .github/workflows/release.yml          | 3 +++
 3 files changed, 9 insertions(+)

diff --git a/.github/workflows/build_arduino.yml b/.github/workflows/build_arduino.yml
index 86ddc302..e27262bb 100644
--- a/.github/workflows/build_arduino.yml
+++ b/.github/workflows/build_arduino.yml
@@ -4,6 +4,9 @@ name: Build using Arduino
 on:
   workflow_call:
 
+env:
+  FORCE_JAVASCRIPT_ACTIONS_TO_NODE24: true
+
 jobs:
   build:
     runs-on: ubuntu-latest
diff --git a/.github/workflows/build_platformio.yml b/.github/workflows/build_platformio.yml
index c6b2f56f..a085dc95 100644
--- a/.github/workflows/build_platformio.yml
+++ b/.github/workflows/build_platformio.yml
@@ -4,6 +4,9 @@ name: Build using PlatformIO
 on:
   workflow_call:
 
+env:
+  FORCE_JAVASCRIPT_ACTIONS_TO_NODE24: true
+
 jobs:
   build:
     runs-on: ubuntu-latest
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml
index 7d53f2d1..2988b518 100644
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -4,6 +4,9 @@ name: Create pre-release
 on:
   workflow_call:
 
+env:
+  FORCE_JAVASCRIPT_ACTIONS_TO_NODE24: true
+
 jobs:
   release:
     runs-on: ubuntu-latest

From 1f36c53e9dcb415377e6c655809fe8a210ee9205 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sun, 24 May 2026 20:32:33 -0400
Subject: [PATCH 33/59] =?UTF-8?q?Remove=20Arduino=20build=20job=20?=
 =?UTF-8?q?=E2=80=94=20arduino/=20support=20files=20not=20present=20in=20l?=
 =?UTF-8?q?inco-work?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 .github/workflows/build.yml | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 00159de7..06f15bb0 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -20,10 +20,6 @@ jobs:
     name: Build using PlatformIO
     uses: OpenEVSE/open_evse/.github/workflows/build_platformio.yml@linco-work
 
-  build_arduino:
-    name: Build using Arduino
-    uses: OpenEVSE/open_evse/.github/workflows/build_arduino.yml@linco-work
-
   release:
     name: Create pre-release
 

From a3fd411566d200699499af2085e22794d2f8b244 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sun, 24 May 2026 20:53:20 -0400
Subject: [PATCH 34/59] Upgrade GitHub Actions to Node.js 24-native versions

checkout v4->v5, cache v4->v5, setup-python v5->v6,
upload-artifact v4->v6, download-artifact v4->v7.
Remove FORCE_JAVASCRIPT_ACTIONS_TO_NODE24 workaround.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 .github/workflows/build_arduino.yml       |  9 +++------
 .github/workflows/build_platformio.yml    | 13 +++++--------
 .github/workflows/release.yml             |  5 +----
 .github/workflows/release_validation.yaml |  2 +-
 4 files changed, 10 insertions(+), 19 deletions(-)

diff --git a/.github/workflows/build_arduino.yml b/.github/workflows/build_arduino.yml
index e27262bb..80329cf9 100644
--- a/.github/workflows/build_arduino.yml
+++ b/.github/workflows/build_arduino.yml
@@ -4,9 +4,6 @@ name: Build using Arduino
 on:
   workflow_call:
 
-env:
-  FORCE_JAVASCRIPT_ACTIONS_TO_NODE24: true
-
 jobs:
   build:
     runs-on: ubuntu-latest
@@ -30,14 +27,14 @@ jobs:
 
     steps:
       - name: Cache Arduino
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         with:
           path: ~/.arduino15
           key: ${{ runner.os }}-${{ matrix.name }}-arduino-15-${{ hashFiles('**/packages.txt') }}
           restore-keys: |
             ${{ runner.os }}-${{ matrix.name }}-arduino-15-
 
-      - uses: actions/checkout@v4
+      - uses: actions/checkout@v5
 
       - name: Setup Arduino CLI
         uses: arduino/setup-arduino-cli@v1
@@ -73,7 +70,7 @@ jobs:
           source ci/info_common.sh info.json
 
       - name: Upload output to GitHub
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@v6
         with:
           name: ${{ matrix.name }}
           path: |
diff --git a/.github/workflows/build_platformio.yml b/.github/workflows/build_platformio.yml
index a085dc95..bfbe6df6 100644
--- a/.github/workflows/build_platformio.yml
+++ b/.github/workflows/build_platformio.yml
@@ -4,9 +4,6 @@ name: Build using PlatformIO
 on:
   workflow_call:
 
-env:
-  FORCE_JAVASCRIPT_ACTIONS_TO_NODE24: true
-
 jobs:
   build:
     runs-on: ubuntu-latest
@@ -42,10 +39,10 @@ jobs:
             artifact: firmware.bin
 
     steps:
-    - uses: actions/checkout@v4
+    - uses: actions/checkout@v5
 
     - name: Cache pip
-      uses: actions/cache@v4
+      uses: actions/cache@v5
       with:
         path: ~/.cache/pip
         key: ${{ runner.os }}-${{ matrix.env }}-pip-${{ hashFiles('**/requirements.txt') }}
@@ -53,13 +50,13 @@ jobs:
           ${{ runner.os }}-${{ matrix.env }}-pip-
 
     - name: Cache PlatformIO
-      uses: actions/cache@v4
+      uses: actions/cache@v5
       with:
         path: ~/.platformio
         key: ${{ runner.os }}-${{ matrix.env }}-${{ hashFiles('**/lockfiles') }}
 
     - name: Set up Python
-      uses: actions/setup-python@v5
+      uses: actions/setup-python@v6
       with:
         python-version: '${{ matrix.python }}'
 
@@ -97,7 +94,7 @@ jobs:
         EOF
 
     - name: Upload output to GitHub
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@v6
       with:
         name: ${{ matrix.env }}
         path: |
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml
index 2988b518..233d0454 100644
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -4,9 +4,6 @@ name: Create pre-release
 on:
   workflow_call:
 
-env:
-  FORCE_JAVASCRIPT_ACTIONS_TO_NODE24: true
-
 jobs:
   release:
     runs-on: ubuntu-latest
@@ -16,7 +13,7 @@ jobs:
         sudo apt-get install jq -y
 
     - name: Download the built assets
-      uses: actions/download-artifact@v4
+      uses: actions/download-artifact@v7
       with:
         path: artifacts
 
diff --git a/.github/workflows/release_validation.yaml b/.github/workflows/release_validation.yaml
index 68b90935..4c1d8acb 100644
--- a/.github/workflows/release_validation.yaml
+++ b/.github/workflows/release_validation.yaml
@@ -15,7 +15,7 @@ jobs:
 
     steps:
       ### Check the version number in the code matches the tag number
-      - uses: actions/checkout@v4
+      - uses: actions/checkout@v5
 
       - name: Retrieve the version number(s)
         run: |

From 303690368cb5f22c2568d9b5cccd1203edb4ddcf Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 27 May 2026 14:33:30 -0700
Subject: [PATCH 35/59] move CHANGELOG

---
 firmware/{open_evse => }/CHANGELOG | 4 ++++
 1 file changed, 4 insertions(+)
 rename firmware/{open_evse => }/CHANGELOG (99%)

diff --git a/firmware/open_evse/CHANGELOG b/firmware/CHANGELOG
similarity index 99%
rename from firmware/open_evse/CHANGELOG
rename to firmware/CHANGELOG
index 5ac061f3..06fbb417 100644
--- a/firmware/open_evse/CHANGELOG
+++ b/firmware/CHANGELOG
@@ -1,5 +1,9 @@
 Change Log
 
+20260527 SCL
+- get rid of old V6 detection code (and INVERT_V6_DETECTION)
+  -> new globals g_isV6 and g_hasCGMI initialized in initTarget()
+
 20260219 SCL
 - added $FF L 0|1 command to enable/disable boot lock feature
   added ECF_BOOT_LOCK_DISABLED

From 92be5ba991fe3f2d66426d68a3cba9cb399115d2 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 27 May 2026 14:34:11 -0700
Subject: [PATCH 36/59] delete superfluous

---
 .../open_evse/__vm/.open_evse.vsarduino.h     | 82 -------------------
 firmware/open_evse/__vm/Compile.vmps.xml      | 37 ---------
 .../__vm/Configuration.Debug.vmps.xml         |  9 --
 .../__vm/Configuration.Release.vmps.xml       |  9 --
 4 files changed, 137 deletions(-)
 delete mode 100644 firmware/open_evse/__vm/.open_evse.vsarduino.h
 delete mode 100644 firmware/open_evse/__vm/Compile.vmps.xml
 delete mode 100644 firmware/open_evse/__vm/Configuration.Debug.vmps.xml
 delete mode 100644 firmware/open_evse/__vm/Configuration.Release.vmps.xml

diff --git a/firmware/open_evse/__vm/.open_evse.vsarduino.h b/firmware/open_evse/__vm/.open_evse.vsarduino.h
deleted file mode 100644
index 3a9a1619..00000000
--- a/firmware/open_evse/__vm/.open_evse.vsarduino.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* 
-	Editor: http://www.visualmicro.com
-			visual micro and the arduino ide ignore this code during compilation. this code is automatically maintained by visualmicro, manual changes to this file will be overwritten
-			the contents of the Visual Micro sketch sub folder can be deleted prior to publishing a project
-			all non-arduino files created by visual micro and all visual studio project or solution files can be freely deleted and are not required to compile a sketch (do not delete your own code!).
-			note: debugger breakpoints are stored in '.sln' or '.asln' files, knowledge of last uploaded breakpoints is stored in the upload.vmps.xml file. Both files are required to continue a previous debug session without needing to compile and upload again
-	
-	Hardware: Arduino/Genuino Uno, Platform=avr, Package=arduino
-*/
-
-#if defined(_VMICRO_INTELLISENSE)
-
-#ifndef _VSARDUINO_H_
-#define _VSARDUINO_H_
-#define __AVR_ATmega328p__
-#define __AVR_ATmega328P__
-#define _VMDEBUG 1
-#define F_CPU 16000000L
-#define ARDUINO 10803
-#define ARDUINO_AVR_UNO
-#define ARDUINO_ARCH_AVR
-#define __cplusplus 201103L
-#define __AVR__
-#define __inline__
-#define __asm__(...)
-#define __extension__
-#define __inline__
-#define __volatile__
-#define GCC_VERSION 40902
-
-#define __cplusplus 201103L
-#undef __cplusplus
-#define __cplusplus 201103L
-
-#define volatile(va_arg) 
-#define _CONST
-#define __builtin_va_start
-#define __builtin_va_end
-#define __attribute__(...)
-#define NOINLINE __attribute__((noinline))
-#define prog_void
-#define PGM_VOID_P int
-
-
-#ifndef __builtin_constant_p
-	#define __builtin_constant_p __attribute__((__const__))
-#endif
-#ifndef __builtin_strlen
-	#define __builtin_strlen  __attribute__((__const__))
-#endif
-
-
-#define NEW_H
-typedef void *__builtin_va_list;
-//extern "C" void __cxa_pure_virtual() {;}
-
-typedef int div_t;
-typedef int ldiv_t;
-
-
-typedef void *__builtin_va_list;
-//extern "C" void __cxa_pure_virtual() {;}
-
-
-
-#include <Arduino.h>
-#include <pins_arduino.h> 
-#undef F
-#define F(string_literal) ((const PROGMEM char *)(string_literal))
-#undef PSTR
-#define PSTR(string_literal) ((const PROGMEM char *)(string_literal))
-
-
-#define pgm_read_byte(address_short) uint8_t() 
-#define pgm_read_word(address_short) uint16_t() 
-#define pgm_read_dword(address_short) uint32_t()
-#define pgm_read_float(address_short) float()
-#define pgm_read_ptr(address_short)   short()
-
-#include "open_evse.ino"
-#endif
-#endif
diff --git a/firmware/open_evse/__vm/Compile.vmps.xml b/firmware/open_evse/__vm/Compile.vmps.xml
deleted file mode 100644
index 2185a69a..00000000
--- a/firmware/open_evse/__vm/Compile.vmps.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<VisualMicro>
-  <Program Name="open_evse" Ext=".ino" Location="D:\git\open_evse\firmware\open_evse">
-    <Compile IsDebugStart="1" IsGdb="0" CompilerErrors="0" ConfigurationName="Debug" UseConfigurationNameInBuildFolder="True" StopOnError="False" OptimiseLibs="True" OptimiseCore="True" BuildPath="C:\Users\Geek\AppData\Local\Temp\VMBuilds\open_evse\uno\Debug" ReCompileIfSourceIsNewer="1" SketchName="open_evse" ReportDigitalPins="0" ReportAnalogPins="0" ReportI2C="0" ReportFreeMemory="0" IncludeDebug="1" LastDebugPreProcessorDefinitions="VM_DEBUG;VM_DEBUG_ENABLE 1;VM_DEBUG_BANDWIDTH_THROTTLE_MS 50;VM_DEBUGGER_TYPE_HARDWARESERIAL 0;VM_DEBUGGER_TYPE_SOFTWARESERIAL 1;VM_DEBUGGER_TYPE_FASTSERIAL 2;VM_DEBUGGER_TYPE_USB 3;VM_DEBUGGER_TYPE_TEENSY 4;VM_DEBUGGER_TYPE_UART 5;VM_DEBUGGER_TYPE_USART 6;VM_DEBUGGER_TYPE_USBSERIAL 7;VM_DEBUGGER_TYPE_TTYUART 8;VM_DEBUGGER_TYPE_NET_CONSOLE 9;VM_DEBUGGER_TYPE_Uart 10;VM_DEBUGGER_TYPE_COSA 11;VM_DEBUGGER_TYPE_CDCSerialClass 12;VM_DEBUGGER_TYPE_HARDWARESERIAL1 13;VM_DEBUGGER_TYPE_HARDWARESERIAL2 14;VM_DEBUGGER_TYPE_HARDWARESERIAL3 15;VM_DEBUGGER_TYPE_NET_UDP 16;VM_DEBUGGER_TYPE_USBAPI 17;VM_DEBUGGER_TYPE_SERIALUSB 18;VM_DEBUGGER_TYPE VM_DEBUGGER_TYPE_HARDWARESERIAL;VM_DEBUG_BREAKPAUSE;" IncludesDebug="1" IsCompiled="1" />
-    <Platform Name="arduino16x" Package="arduino" Platform="avr" Architecture="4.9.2-atmel3.5.3-arduino2">
-      <Board Name="uno" Description="Arduino/Genuino Uno" CoreFolder="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores\arduino" VariantFullPath="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\variants\standard" McuIdePath="D:\hacking\arduino\arduino-1.8.3\" McuSketchBookPath="D:\Geek\Google Drive\arduino\sketchbook" name="Arduino/Genuino Uno" vid.0="0x2341" pid.0="0x0043" vid.1="0x2341" pid.1="0x0001" vid.2="0x2A03" pid.2="0x0043" vid.3="0x2341" pid.3="0x0243" upload.tool="avrdude" upload.protocol="arduino" upload.maximum_size="32256" upload.maximum_data_size="2048" upload.speed="115200" bootloader.tool="avrdude" bootloader.low_fuses="0xFF" bootloader.high_fuses="0xDE" bootloader.extended_fuses="0x05" bootloader.unlock_bits="0x3F" bootloader.lock_bits="0x0F" bootloader.file="optiboot/optiboot_atmega328.hex" build.mcu="atmega328p" build.f_cpu="16000000L" build.board="AVR_UNO" build.core="arduino" build.variant="standard" runtime.ide.path="D:\hacking\arduino\arduino-1.8.3\" runtime.os="windows" build.system.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\system" runtime.ide.version="10803" target_package="arduino" target_platform="avr" runtime.hardware.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr" originalid="uno" intellisense.tools.path="{runtime.tools.avr-gcc.path}\" intellisense.include.paths="{intellisense.tools.path}avr\include\;{intellisense.tools.path}avr\include\avr\;{intellisense.tools.path}lib\gcc\avr\4.8.1\include;{intellisense.tools.path}lib\gcc\avr\4.9.2\include;{intellisense.tools.path}lib\gcc\avr\4.9.3\include" tools.atprogram.cmd.path="%AVRSTUDIO_EXE_PATH%\atbackend\atprogram" tools.atprogram.cmd.setwinpath="true" tools.atprogram.program.params.verbose="-v" tools.atprogram.program.params.quiet="-q" tools.atprogram.program.pattern="&quot;{cmd.path}&quot; -d {build.mcu} {program.verbose} {program.extra_params} program -c -f &quot;{build.path}\{build.project_name}.hex&quot;" tools.atprogram.program.xpattern="&quot;{cmd.path}&quot; {AVRSTUDIO_BACKEND_CONNECTION} -d {build.mcu} {program.verbose} {program.extra_params} program -c -f &quot;{build.path}\{build.project_name}.hex&quot;" tools.atprogram.erase.params.verbose="-v" tools.atprogram.erase.params.quiet="-q" tools.atprogram.bootloader.params.verbose="-v" tools.atprogram.bootloader.params.quiet="-q" tools.atprogram.bootloader.pattern="&quot;{cmd.path}&quot; -d {build.mcu} {bootloader.verbose}  program -c -f &quot;{runtime.ide.path}\hardware\arduino\avr\bootloaders\{bootloader.file}&quot;" version="1.6.15" compiler.warning_flags="-w" compiler.warning_flags.none="-w" compiler.warning_flags.default="" compiler.warning_flags.more="-Wall" compiler.warning_flags.all="-Wall -Wextra" compiler.path="{runtime.tools.avr-gcc.path}/bin/" compiler.c.cmd="avr-gcc" compiler.c.flags="-c -g -Os {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -MMD -flto -fno-fat-lto-objects" compiler.c.elf.flags="{compiler.warning_flags} -Os -flto -fuse-linker-plugin -Wl,--gc-sections" compiler.c.elf.cmd="avr-gcc" compiler.S.flags="-c -g -x assembler-with-cpp -flto" compiler.cpp.cmd="avr-g++" compiler.cpp.flags="-c -g -Os {compiler.warning_flags} -std=gnu++11 -fpermissive -fno-exceptions -ffunction-sections -fdata-sections -fno-threadsafe-statics -MMD -flto" compiler.ar.cmd="avr-gcc-ar" compiler.ar.flags="rcs" compiler.objcopy.cmd="avr-objcopy" compiler.objcopy.eep.flags="-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0" compiler.elf2hex.flags="-O ihex -R .eeprom" compiler.elf2hex.cmd="avr-objcopy" compiler.ldflags="" compiler.size.cmd="avr-size" build.extra_flags="" compiler.c.extra_flags="" compiler.c.elf.extra_flags="" compiler.S.extra_flags="" compiler.cpp.extra_flags="" compiler.ar.extra_flags="" compiler.objcopy.eep.extra_flags="" compiler.elf2hex.extra_flags="" recipe.c.o.pattern="&quot;{compiler.path}{compiler.c.cmd}&quot; {compiler.c.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{object_file}&quot;" recipe.cpp.o.pattern="&quot;{compiler.path}{compiler.cpp.cmd}&quot; {compiler.cpp.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{object_file}&quot;" recipe.S.o.pattern="&quot;{compiler.path}{compiler.c.cmd}&quot; {compiler.S.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{object_file}&quot;" archive_file_path="{build.path}/{archive_file}" recipe.ar.pattern="&quot;{compiler.path}{compiler.ar.cmd}&quot; {compiler.ar.flags} {compiler.ar.extra_flags} &quot;{archive_file_path}&quot; &quot;{object_file}&quot;" recipe.c.combine.pattern="&quot;{compiler.path}{compiler.c.elf.cmd}&quot; {compiler.c.elf.flags} -mmcu={build.mcu} {compiler.c.elf.extra_flags} -o &quot;{build.path}/{build.project_name}.elf&quot; {object_files} &quot;{build.path}/{archive_file}&quot; &quot;-L{build.path}&quot; -lm" recipe.objcopy.eep.pattern="&quot;{compiler.path}{compiler.objcopy.cmd}&quot; {compiler.objcopy.eep.flags} {compiler.objcopy.eep.extra_flags} &quot;{build.path}/{build.project_name}.elf&quot; &quot;{build.path}/{build.project_name}.eep&quot;" recipe.objcopy.hex.pattern="&quot;{compiler.path}{compiler.elf2hex.cmd}&quot; {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} &quot;{build.path}/{build.project_name}.elf&quot; &quot;{build.path}/{build.project_name}.hex&quot;" recipe.output.tmp_file="{build.project_name}.hex" recipe.output.save_file="{build.project_name}.{build.variant}.hex" recipe.size.pattern="&quot;{compiler.path}{compiler.size.cmd}&quot; -A &quot;{build.path}/{build.project_name}.elf&quot;" recipe.size.regex="^(?:\.text|\.data|\.bootloader)\s+([0-9]+).*" recipe.size.regex.data="^(?:\.data|\.bss|\.noinit)\s+([0-9]+).*" recipe.size.regex.eeprom="^(?:\.eeprom)\s+([0-9]+).*" preproc.includes.flags="-w -x c++ -M -MG -MP" recipe.preproc.includes="&quot;{compiler.path}{compiler.cpp.cmd}&quot; {compiler.cpp.flags} {preproc.includes.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot;" preproc.macros.flags="-w -x c++ -E -CC" recipe.preproc.macros="&quot;{compiler.path}{compiler.cpp.cmd}&quot; {compiler.cpp.flags} {preproc.macros.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{preprocessed_file_path}&quot;" tools.avrdude.path="{runtime.tools.avrdude.path}" tools.avrdude.cmd.path="{path}/bin/avrdude" tools.avrdude.config.path="{path}/etc/avrdude.conf" tools.avrdude.upload.params.verbose="-v" tools.avrdude.upload.params.quiet="-q -q" tools.avrdude.upload.verify="" tools.avrdude.upload.params.noverify="-V" tools.avrdude.upload.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {upload.verbose} {upload.verify} -p{build.mcu} -c{upload.protocol} -P{serial.port} -b{upload.speed} -D &quot;-Uflash:w:{build.path}/{build.project_name}.hex:i&quot;" tools.avrdude.program.params.verbose="-v" tools.avrdude.program.params.quiet="-q -q" tools.avrdude.program.verify="" tools.avrdude.program.params.noverify="-V" tools.avrdude.program.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {program.verbose} {program.verify} -p{build.mcu} -c{protocol} {program.extra_params} &quot;-Uflash:w:{build.path}/{build.project_name}.hex:i&quot;" tools.avrdude.erase.params.verbose="-v" tools.avrdude.erase.params.quiet="-q -q" tools.avrdude.erase.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {erase.verbose} -p{build.mcu} -c{protocol} {program.extra_params} -e -Ulock:w:{bootloader.unlock_bits}:m -Uefuse:w:{bootloader.extended_fuses}:m -Uhfuse:w:{bootloader.high_fuses}:m -Ulfuse:w:{bootloader.low_fuses}:m" tools.avrdude.bootloader.params.verbose="-v" tools.avrdude.bootloader.params.quiet="-q -q" tools.avrdude.bootloader.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {bootloader.verbose} -p{build.mcu} -c{protocol} {program.extra_params} &quot;-Uflash:w:{runtime.platform.path}/bootloaders/{bootloader.file}:i&quot; -Ulock:w:{bootloader.lock_bits}:m" tools.avrdude_remote.upload.pattern="/usr/bin/run-avrdude /tmp/sketch.hex {upload.verbose} -p{build.mcu}" build.usb_manufacturer="&quot;Unknown&quot;" build.usb_flags="-DUSB_VID={build.vid} -DUSB_PID={build.pid} '-DUSB_MANUFACTURER={build.usb_manufacturer}' '-DUSB_PRODUCT={build.usb_product}'" vm.platform.root.path="C:\Program Files (x86)\Microsoft Visual Studio 14.0\Common7\IDE\Extensions\bkkxodqu.rgl\Micro Platforms\arduino16x" avrisp.name="AVR ISP" avrisp.communication="serial" avrisp.protocol="stk500v1" avrisp.program.protocol="stk500v1" avrisp.program.tool="avrdude" avrisp.program.extra_params="-P{serial.port}" avrispmkii.name="AVRISP mkII" avrispmkii.communication="usb" avrispmkii.protocol="stk500v2" avrispmkii.program.protocol="stk500v2" avrispmkii.program.tool="avrdude" avrispmkii.program.extra_params="-Pusb" usbtinyisp.name="USBtinyISP" usbtinyisp.protocol="usbtiny" usbtinyisp.program.tool="avrdude" usbtinyisp.program.extra_params="-B1" arduinoisp.name="ArduinoISP" arduinoisp.protocol="arduinoisp" arduinoisp.program.tool="avrdude" arduinoisp.program.extra_params="" usbasp.name="USBasp" usbasp.communication="usb" usbasp.protocol="usbasp" usbasp.program.protocol="usbasp" usbasp.program.tool="avrdude" usbasp.program.extra_params="-Pusb -B0.5" parallel.name="Parallel Programmer" parallel.protocol="dapa" parallel.force="true" parallel.program.tool="avrdude" parallel.program.extra_params="-F" arduinoasisp.name="Arduino as ISP" arduinoasisp.communication="serial" arduinoasisp.protocol="stk500v1" arduinoasisp.speed="19200" arduinoasisp.program.protocol="stk500v1" arduinoasisp.program.speed="19200" arduinoasisp.program.tool="avrdude" arduinoasisp.program.extra_params="-P{serial.port} -b{program.speed}" usbGemma.name="Arduino Gemma" usbGemma.protocol="arduinogemma" usbGemma.program.tool="avrdude" usbGemma.program.extra_params="" usbGemma.config.path="{runtime.platform.path}/bootloaders/gemma/avrdude.conf" stk500.name="Atmel STK500 development board" stk500.communication="serial" stk500.protocol="stk500" stk500.program.protocol="stk500" stk500.program.tool="avrdude" stk500.program.extra_params="-P{serial.port}" buspirate.name="BusPirate as ISP" buspirate.communication="serial" buspirate.protocol="buspirate" buspirate.program.protocol="buspirate" buspirate.program.tool="avrdude" buspirate.program.extra_params="-P{serial.port}" runtime.tools.avr-gcc.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2" runtime.tools.avr-gcc-4.9.2-atmel3.5.3-arduino2.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2" runtime.tools.avrdude.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avrdude\6.3.0-arduino6" runtime.tools.avrdude-6.3.0-arduino6.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avrdude\6.3.0-arduino6" runtime.tools.esptool.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\esptool\0.4.9" runtime.tools.esptool-0.4.9.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\esptool\0.4.9" runtime.tools.mkspiffs.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\mkspiffs\0.1.2" runtime.tools.mkspiffs-0.1.2.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\mkspiffs\0.1.2" runtime.tools.xtensa-lx106-elf-gcc.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\xtensa-lx106-elf-gcc\1.20.0-26-gb404fb9-2" runtime.tools.xtensa-lx106-elf-gcc-1.20.0-26-gb404fb9-2.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\xtensa-lx106-elf-gcc\1.20.0-26-gb404fb9-2" runtime.vm.boardinfo.id="uno" runtime.vm.boardinfo.name="uno" runtime.vm.boardinfo.desc="Arduino/Genuino Uno" runtime.vm.boardinfo.src_location="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" ide.hint="Use installed IDE. Provides built-in hardware, reference/help and libraries." ide.location.key="Arduino16x" ide.location.ide.winreg="Arduino 1.6.x Application" ide.location.sketchbook.winreg="Arduino 1.6.x Sketchbook" ide.location.sketchbook.preferences="sketchbook.path" ide.default.revision_name="1.8.0" ide.default.version="10800" ide.default.package="arduino" ide.default.platform="avr" ide.multiplatform="true" ide.includes="Arduino.h" ide.exe_name="arduino" ide.platformswithoutpackage="false" ide.includes.fallback="wprogram.h" ide.extension="ino" ide.extension.fallback="pde" ide.versionGTEQ="160" ide.exe="arduino.exe" ide.builder.exe="arduinobuilder.exe" ide.builder.name="Arduino Builder" ide.hosts="atmel" ide.url="http://arduino.cc/en/Main/Software" ide.help.reference.path="reference" ide.help.reference.path2="reference\www.arduino.cc\en\Reference" ide.help.reference.serial="reference\www.arduino.cc\en\Serial" ide.location.preferences.portable="{runtime.ide.path}\portable" ide.location.preferences.arduinoData="{runtime.sketchbook.path}\ArduinoData" ide.location.preferences="%VM_APPDATA_LOCAL%\arduino15\preferences.txt" ide.location.preferences_fallback="%VM_APPDATA_ROAMING%\arduino15\preferences.txt" ide.location.contributions="%VM_APPDATA_LOCAL%\arduino15" ide.location.contributions_fallback="%VM_APPDATA_ROAMING%\arduino15" ide.contributions.boards.allow="true" ide.contributions.boards.ignore_unless_rewrite_found="true" ide.contributions.libraries.allow="true" ide.contributions.boards.support.urls.wiki="https://github.com/arduino/Arduino/wiki/Unofficial-list-of-3rd-party-boards-support-urls" ide.create_platforms_from_boardsTXT.teensy="build.core" vm.debug="true" software="ARDUINO" ssh.user.name="root" ssh.user.default.password="arduino" ssh.host.wwwfiles.path="/www/sd" build.working_directory="{runtime.ide.path}\java\bin" ide.appid="arduino16x" location.sketchbook="D:\Geek\Google Drive\arduino\sketchbook" build.core.vmresolved="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores\arduino" build.core.parentfolder.vmresolved="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores" build.core.coresparentfolder.vmresolved="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" build.core.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores\arduino" vm.core.include="Arduino.h" vm.boardsource.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" runtime.platform.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" vm.platformname.name="avr" build.arch="AVR" builder.noino="false" build.architecture="4.9.2-atmel3.5.3-arduino2" vmresolved.compiler.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2\bin\" vmresolved.tools.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2" build.variant.vmresolved.name="standard" build.variant.vmresolved.full_path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\variants\standard" build.path="C:\Users\Geek\AppData\Local\Temp\VMBuilds\open_evse\uno\Debug" build.project_name="open_evse.ino" build.project_path="D:\git\open_evse\firmware\open_evse" ProjectDir="D:\git\open_evse\firmware\open_evse\" vm.runtime.compiler.showwarnings="false" vm.runtime.upload.verbose="false" vm.runtime.upload.verify="false" serial.port.file="COM5" serial.port="COM5" serial.port.num="5" vm.runtime.compiler.auto_discover_includes="true" vm.runtime.compiler.auto_discover_includes_cache="true" build.vm.build.vmdebug="1" build.vm.build.isgdb="0" build.vm.build.optimised="1" vm.last.buildpath="C:\Users\Geek\AppData\Local\Temp\VMBuilds\open_evse\uno\Debug" />
-    </Platform>
-    <Debug EnableBreak="1" DebugEnabled="1" InBreakLiveView="1" PerfStats="1" IsGdb="0" RemotePortSpeedWrittenToDebugSource="115200" />
-    <VCCodeModel>
-      <VCCodeMacros />
-    </VCCodeModel>
-    <BreakPoints>
-      <BreakPoint Index="1" Name="open_evse.ino, line 2400" Id="33f4271f-e378-402b-ab3f-11cf1950dd7d" Enabled="1" Message="  Millis is currently {millis()}.&#xD;&#xA;    This tutorial debug trace point prints a message every 250ms&#xD;&#xA;    The break point property called 'Continue Execution' controls if code should pause here and wait for you to click 'Continue'.&#xD;&#xA;    To stop debug, click stop debugging or close/stop the serial monitor.&#xD;&#xA;    When debug ends, serial debug will continue to break/pause the mcu or transmit trace message, wifi debug will not.&#xD;&#xA;    This breakpoint exists at the start of the loop() function, where you see a red dot.&#xD;&#xA;    The red dot is a ‘breakpoint’. Edit the properties of a breakpoint by right clicking it or open the 'Debug&gt;Other Windows&gt;Breakpoint List'&#xD;&#xA;    This breakpoint is automatically set by Visual Micro to demonstrate the Arduino debugger.&#xD;&#xA;    Add your own breakpoints by placing the cursor on any code line and pressing F9. Press F9 again to delete the breakpoint.&#xD;&#xA;    Read more about the Visual Micro debugger at http://www.visualmicro.com/page/Debugging-for-Arduino.aspx&#xD;&#xA;    Take some time to learn about debugging, it’s worth it!&#xD;&#xA;    To switch the demo breakpoint and other tips off, deselect Visual Micro&gt;Tutorial Mode.&#xD;&#xA;    Switch debugging off by changing from tool bar (Configuratin) from 'Debug' to 'Release'" MessageTextType="0" PreProcessedMessage="  Millis is currently {0}.&#xD;&#xA;    This tutorial debug trace point prints a message every 250ms&#xD;&#xA;    The break point property called 'Continue Execution' controls if code should pause here and wait for you to click 'Continue'.&#xD;&#xA;    To stop debug, click stop debugging or close/stop the serial monitor.&#xD;&#xA;    When debug ends, serial debug will continue to break/pause the mcu or transmit trace message, wifi debug will not.&#xD;&#xA;    This breakpoint exists at the start of the loop() function, where you see a red dot.&#xD;&#xA;    The red dot is a ‘breakpoint’. Edit the properties of a breakpoint by right clicking it or open the 'Debug&gt;Other Windows&gt;Breakpoint List'&#xD;&#xA;    This breakpoint is automatically set by Visual Micro to demonstrate the Arduino debugger.&#xD;&#xA;    Add your own breakpoints by placing the cursor on any code line and pressing F9. Press F9 again to delete the breakpoint.&#xD;&#xA;    Read more about the Visual Micro debugger at http://www.visualmicro.com/page/Debugging-for-Arduino.aspx&#xD;&#xA;    Take some time to learn about debugging, it’s worth it!&#xD;&#xA;    To switch the demo breakpoint and other tips off, deselect Visual Micro&gt;Tutorial Mode.&#xD;&#xA;    Switch debugging off by changing from tool bar (Configuratin) from 'Debug' to 'Release'" Condition="millis()&gt;0 || millis()&gt;1" ConditionType="1" CurrentHits="0" File="d:\git\open_evse\firmware\open_evse\open_evse.ino" FileLine="2400" FileColumn="1" FunctionName="EvseReset()" FunctionLineOffset="12" FunctionColumnOffset="1" HitCountTarget="250" HitCountType="4" Language="C++" LocationType="3" Tag="&lt;vmbp Id='33f4271f-e378-402b-ab3f-11cf1950dd7d'/&gt;" Type="1" ToString="System.__ComObject" BreakWhenHit="0">
-        <Source>2393	  g_RTC.begin();
-2394	#ifdef DELAYTIMER
-2395	  g_DelayTimer.Init();
-2396	#endif  // DELAYTIMER
-2397	#endif // RTC
-2398	
-2399	#ifdef SERIALCLI
---&gt;2400	  g_CLI.Init();
-2401	#endif // SERIALCLI
-2402	
-2403	  g_OBD.Init();
-2404	
-2405	#ifdef RAPI
-2406	  RapiInit();
-2407	#endif
-2408	
-2409	  g_EvseController.Init();
-</Source>
-        <MessageVariables>
-          <MessageVariable Name="millis()" Index="1" />
-        </MessageVariables>
-      </BreakPoint>
-    </BreakPoints>
-  </Program>
-</VisualMicro>
\ No newline at end of file
diff --git a/firmware/open_evse/__vm/Configuration.Debug.vmps.xml b/firmware/open_evse/__vm/Configuration.Debug.vmps.xml
deleted file mode 100644
index 91724e93..00000000
--- a/firmware/open_evse/__vm/Configuration.Debug.vmps.xml
+++ /dev/null
@@ -1,9 +0,0 @@
-<VisualMicro>
-  <Program Name="open_evse" Ext=".ino" Location="D:\git\open_evse\firmware\open_evse">
-    <Compile IsDebugStart="1" IsGdb="0" IsCompiled="0" CompilerErrors="0" ConfigurationName="Debug" UseConfigurationNameInBuildFolder="True" StopOnError="False" OptimiseLibs="True" OptimiseCore="True" BuildPath="C:\Users\Geek\AppData\Local\Temp\VMBuilds\open_evse\uno\Debug" ReCompileIfSourceIsNewer="1" />
-    <Platform Name="arduino16x" Package="arduino" Platform="avr" Architecture="4.9.2-atmel3.5.3-arduino2">
-      <Board Name="uno" Description="Arduino/Genuino Uno" CoreFolder="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores\arduino" VariantFullPath="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\variants\standard" McuIdePath="D:\hacking\arduino\arduino-1.8.3\" McuSketchBookPath="D:\Geek\Google Drive\arduino\sketchbook" name="Arduino/Genuino Uno" vid.0="0x2341" pid.0="0x0043" vid.1="0x2341" pid.1="0x0001" vid.2="0x2A03" pid.2="0x0043" vid.3="0x2341" pid.3="0x0243" upload.tool="avrdude" upload.protocol="arduino" upload.maximum_size="32256" upload.maximum_data_size="2048" upload.speed="115200" bootloader.tool="avrdude" bootloader.low_fuses="0xFF" bootloader.high_fuses="0xDE" bootloader.extended_fuses="0x05" bootloader.unlock_bits="0x3F" bootloader.lock_bits="0x0F" bootloader.file="optiboot/optiboot_atmega328.hex" build.mcu="atmega328p" build.f_cpu="16000000L" build.board="AVR_UNO" build.core="arduino" build.variant="standard" runtime.ide.path="D:\hacking\arduino\arduino-1.8.3\" runtime.os="windows" build.system.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\system" runtime.ide.version="10803" target_package="arduino" target_platform="avr" runtime.hardware.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr" originalid="uno" intellisense.tools.path="{runtime.tools.avr-gcc.path}\" intellisense.include.paths="{intellisense.tools.path}avr\include\;{intellisense.tools.path}avr\include\avr\;{intellisense.tools.path}lib\gcc\avr\4.8.1\include;{intellisense.tools.path}lib\gcc\avr\4.9.2\include;{intellisense.tools.path}lib\gcc\avr\4.9.3\include" tools.atprogram.cmd.path="%AVRSTUDIO_EXE_PATH%\atbackend\atprogram" tools.atprogram.cmd.setwinpath="true" tools.atprogram.program.params.verbose="-v" tools.atprogram.program.params.quiet="-q" tools.atprogram.program.pattern="&quot;{cmd.path}&quot; -d {build.mcu} {program.verbose} {program.extra_params} program -c -f &quot;{build.path}\{build.project_name}.hex&quot;" tools.atprogram.program.xpattern="&quot;{cmd.path}&quot; {AVRSTUDIO_BACKEND_CONNECTION} -d {build.mcu} {program.verbose} {program.extra_params} program -c -f &quot;{build.path}\{build.project_name}.hex&quot;" tools.atprogram.erase.params.verbose="-v" tools.atprogram.erase.params.quiet="-q" tools.atprogram.bootloader.params.verbose="-v" tools.atprogram.bootloader.params.quiet="-q" tools.atprogram.bootloader.pattern="&quot;{cmd.path}&quot; -d {build.mcu} {bootloader.verbose}  program -c -f &quot;{runtime.ide.path}\hardware\arduino\avr\bootloaders\{bootloader.file}&quot;" version="1.6.15" compiler.warning_flags="-w" compiler.warning_flags.none="-w" compiler.warning_flags.default="" compiler.warning_flags.more="-Wall" compiler.warning_flags.all="-Wall -Wextra" compiler.path="{runtime.tools.avr-gcc.path}/bin/" compiler.c.cmd="avr-gcc" compiler.c.flags="-c -g -Os {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -MMD -flto -fno-fat-lto-objects" compiler.c.elf.flags="{compiler.warning_flags} -Os -flto -fuse-linker-plugin -Wl,--gc-sections" compiler.c.elf.cmd="avr-gcc" compiler.S.flags="-c -g -x assembler-with-cpp -flto" compiler.cpp.cmd="avr-g++" compiler.cpp.flags="-c -g -Os {compiler.warning_flags} -std=gnu++11 -fpermissive -fno-exceptions -ffunction-sections -fdata-sections -fno-threadsafe-statics -MMD -flto" compiler.ar.cmd="avr-gcc-ar" compiler.ar.flags="rcs" compiler.objcopy.cmd="avr-objcopy" compiler.objcopy.eep.flags="-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0" compiler.elf2hex.flags="-O ihex -R .eeprom" compiler.elf2hex.cmd="avr-objcopy" compiler.ldflags="" compiler.size.cmd="avr-size" build.extra_flags="" compiler.c.extra_flags="" compiler.c.elf.extra_flags="" compiler.S.extra_flags="" compiler.cpp.extra_flags="" compiler.ar.extra_flags="" compiler.objcopy.eep.extra_flags="" compiler.elf2hex.extra_flags="" recipe.c.o.pattern="&quot;{compiler.path}{compiler.c.cmd}&quot; {compiler.c.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{object_file}&quot;" recipe.cpp.o.pattern="&quot;{compiler.path}{compiler.cpp.cmd}&quot; {compiler.cpp.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{object_file}&quot;" recipe.S.o.pattern="&quot;{compiler.path}{compiler.c.cmd}&quot; {compiler.S.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{object_file}&quot;" archive_file_path="{build.path}/{archive_file}" recipe.ar.pattern="&quot;{compiler.path}{compiler.ar.cmd}&quot; {compiler.ar.flags} {compiler.ar.extra_flags} &quot;{archive_file_path}&quot; &quot;{object_file}&quot;" recipe.c.combine.pattern="&quot;{compiler.path}{compiler.c.elf.cmd}&quot; {compiler.c.elf.flags} -mmcu={build.mcu} {compiler.c.elf.extra_flags} -o &quot;{build.path}/{build.project_name}.elf&quot; {object_files} &quot;{build.path}/{archive_file}&quot; &quot;-L{build.path}&quot; -lm" recipe.objcopy.eep.pattern="&quot;{compiler.path}{compiler.objcopy.cmd}&quot; {compiler.objcopy.eep.flags} {compiler.objcopy.eep.extra_flags} &quot;{build.path}/{build.project_name}.elf&quot; &quot;{build.path}/{build.project_name}.eep&quot;" recipe.objcopy.hex.pattern="&quot;{compiler.path}{compiler.elf2hex.cmd}&quot; {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} &quot;{build.path}/{build.project_name}.elf&quot; &quot;{build.path}/{build.project_name}.hex&quot;" recipe.output.tmp_file="{build.project_name}.hex" recipe.output.save_file="{build.project_name}.{build.variant}.hex" recipe.size.pattern="&quot;{compiler.path}{compiler.size.cmd}&quot; -A &quot;{build.path}/{build.project_name}.elf&quot;" recipe.size.regex="^(?:\.text|\.data|\.bootloader)\s+([0-9]+).*" recipe.size.regex.data="^(?:\.data|\.bss|\.noinit)\s+([0-9]+).*" recipe.size.regex.eeprom="^(?:\.eeprom)\s+([0-9]+).*" preproc.includes.flags="-w -x c++ -M -MG -MP" recipe.preproc.includes="&quot;{compiler.path}{compiler.cpp.cmd}&quot; {compiler.cpp.flags} {preproc.includes.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot;" preproc.macros.flags="-w -x c++ -E -CC" recipe.preproc.macros="&quot;{compiler.path}{compiler.cpp.cmd}&quot; {compiler.cpp.flags} {preproc.macros.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{preprocessed_file_path}&quot;" tools.avrdude.path="{runtime.tools.avrdude.path}" tools.avrdude.cmd.path="{path}/bin/avrdude" tools.avrdude.config.path="{path}/etc/avrdude.conf" tools.avrdude.upload.params.verbose="-v" tools.avrdude.upload.params.quiet="-q -q" tools.avrdude.upload.verify="" tools.avrdude.upload.params.noverify="-V" tools.avrdude.upload.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {upload.verbose} {upload.verify} -p{build.mcu} -c{upload.protocol} -P{serial.port} -b{upload.speed} -D &quot;-Uflash:w:{build.path}/{build.project_name}.hex:i&quot;" tools.avrdude.program.params.verbose="-v" tools.avrdude.program.params.quiet="-q -q" tools.avrdude.program.verify="" tools.avrdude.program.params.noverify="-V" tools.avrdude.program.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {program.verbose} {program.verify} -p{build.mcu} -c{protocol} {program.extra_params} &quot;-Uflash:w:{build.path}/{build.project_name}.hex:i&quot;" tools.avrdude.erase.params.verbose="-v" tools.avrdude.erase.params.quiet="-q -q" tools.avrdude.erase.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {erase.verbose} -p{build.mcu} -c{protocol} {program.extra_params} -e -Ulock:w:{bootloader.unlock_bits}:m -Uefuse:w:{bootloader.extended_fuses}:m -Uhfuse:w:{bootloader.high_fuses}:m -Ulfuse:w:{bootloader.low_fuses}:m" tools.avrdude.bootloader.params.verbose="-v" tools.avrdude.bootloader.params.quiet="-q -q" tools.avrdude.bootloader.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {bootloader.verbose} -p{build.mcu} -c{protocol} {program.extra_params} &quot;-Uflash:w:{runtime.platform.path}/bootloaders/{bootloader.file}:i&quot; -Ulock:w:{bootloader.lock_bits}:m" tools.avrdude_remote.upload.pattern="/usr/bin/run-avrdude /tmp/sketch.hex {upload.verbose} -p{build.mcu}" build.usb_manufacturer="&quot;Unknown&quot;" build.usb_flags="-DUSB_VID={build.vid} -DUSB_PID={build.pid} '-DUSB_MANUFACTURER={build.usb_manufacturer}' '-DUSB_PRODUCT={build.usb_product}'" vm.platform.root.path="C:\Program Files (x86)\Microsoft Visual Studio 14.0\Common7\IDE\Extensions\bkkxodqu.rgl\Micro Platforms\arduino16x" avrisp.name="AVR ISP" avrisp.communication="serial" avrisp.protocol="stk500v1" avrisp.program.protocol="stk500v1" avrisp.program.tool="avrdude" avrisp.program.extra_params="-P{serial.port}" avrispmkii.name="AVRISP mkII" avrispmkii.communication="usb" avrispmkii.protocol="stk500v2" avrispmkii.program.protocol="stk500v2" avrispmkii.program.tool="avrdude" avrispmkii.program.extra_params="-Pusb" usbtinyisp.name="USBtinyISP" usbtinyisp.protocol="usbtiny" usbtinyisp.program.tool="avrdude" usbtinyisp.program.extra_params="-B1" arduinoisp.name="ArduinoISP" arduinoisp.protocol="arduinoisp" arduinoisp.program.tool="avrdude" arduinoisp.program.extra_params="" usbasp.name="USBasp" usbasp.communication="usb" usbasp.protocol="usbasp" usbasp.program.protocol="usbasp" usbasp.program.tool="avrdude" usbasp.program.extra_params="-Pusb -B0.5" parallel.name="Parallel Programmer" parallel.protocol="dapa" parallel.force="true" parallel.program.tool="avrdude" parallel.program.extra_params="-F" arduinoasisp.name="Arduino as ISP" arduinoasisp.communication="serial" arduinoasisp.protocol="stk500v1" arduinoasisp.speed="19200" arduinoasisp.program.protocol="stk500v1" arduinoasisp.program.speed="19200" arduinoasisp.program.tool="avrdude" arduinoasisp.program.extra_params="-P{serial.port} -b{program.speed}" usbGemma.name="Arduino Gemma" usbGemma.protocol="arduinogemma" usbGemma.program.tool="avrdude" usbGemma.program.extra_params="" usbGemma.config.path="{runtime.platform.path}/bootloaders/gemma/avrdude.conf" stk500.name="Atmel STK500 development board" stk500.communication="serial" stk500.protocol="stk500" stk500.program.protocol="stk500" stk500.program.tool="avrdude" stk500.program.extra_params="-P{serial.port}" buspirate.name="BusPirate as ISP" buspirate.communication="serial" buspirate.protocol="buspirate" buspirate.program.protocol="buspirate" buspirate.program.tool="avrdude" buspirate.program.extra_params="-P{serial.port}" runtime.tools.avr-gcc.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2" runtime.tools.avr-gcc-4.9.2-atmel3.5.3-arduino2.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2" runtime.tools.avrdude.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avrdude\6.3.0-arduino6" runtime.tools.avrdude-6.3.0-arduino6.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avrdude\6.3.0-arduino6" runtime.tools.esptool.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\esptool\0.4.9" runtime.tools.esptool-0.4.9.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\esptool\0.4.9" runtime.tools.mkspiffs.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\mkspiffs\0.1.2" runtime.tools.mkspiffs-0.1.2.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\mkspiffs\0.1.2" runtime.tools.xtensa-lx106-elf-gcc.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\xtensa-lx106-elf-gcc\1.20.0-26-gb404fb9-2" runtime.tools.xtensa-lx106-elf-gcc-1.20.0-26-gb404fb9-2.path="C:\Users\Geek\AppData\Local\arduino15\packages\esp8266\tools\xtensa-lx106-elf-gcc\1.20.0-26-gb404fb9-2" runtime.vm.boardinfo.id="uno" runtime.vm.boardinfo.name="uno" runtime.vm.boardinfo.desc="Arduino/Genuino Uno" runtime.vm.boardinfo.src_location="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" ide.hint="Use installed IDE. Provides built-in hardware, reference/help and libraries." ide.location.key="Arduino16x" ide.location.ide.winreg="Arduino 1.6.x Application" ide.location.sketchbook.winreg="Arduino 1.6.x Sketchbook" ide.location.sketchbook.preferences="sketchbook.path" ide.default.revision_name="1.8.0" ide.default.version="10800" ide.default.package="arduino" ide.default.platform="avr" ide.multiplatform="true" ide.includes="Arduino.h" ide.exe_name="arduino" ide.platformswithoutpackage="false" ide.includes.fallback="wprogram.h" ide.extension="ino" ide.extension.fallback="pde" ide.versionGTEQ="160" ide.exe="arduino.exe" ide.builder.exe="arduinobuilder.exe" ide.builder.name="Arduino Builder" ide.hosts="atmel" ide.url="http://arduino.cc/en/Main/Software" ide.help.reference.path="reference" ide.help.reference.path2="reference\www.arduino.cc\en\Reference" ide.help.reference.serial="reference\www.arduino.cc\en\Serial" ide.location.preferences.portable="{runtime.ide.path}\portable" ide.location.preferences.arduinoData="{runtime.sketchbook.path}\ArduinoData" ide.location.preferences="%VM_APPDATA_LOCAL%\arduino15\preferences.txt" ide.location.preferences_fallback="%VM_APPDATA_ROAMING%\arduino15\preferences.txt" ide.location.contributions="%VM_APPDATA_LOCAL%\arduino15" ide.location.contributions_fallback="%VM_APPDATA_ROAMING%\arduino15" ide.contributions.boards.allow="true" ide.contributions.boards.ignore_unless_rewrite_found="true" ide.contributions.libraries.allow="true" ide.contributions.boards.support.urls.wiki="https://github.com/arduino/Arduino/wiki/Unofficial-list-of-3rd-party-boards-support-urls" ide.create_platforms_from_boardsTXT.teensy="build.core" vm.debug="true" software="ARDUINO" ssh.user.name="root" ssh.user.default.password="arduino" ssh.host.wwwfiles.path="/www/sd" build.working_directory="{runtime.ide.path}\java\bin" ide.appid="arduino16x" location.sketchbook="D:\Geek\Google Drive\arduino\sketchbook" build.core.vmresolved="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores\arduino" build.core.parentfolder.vmresolved="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores" build.core.coresparentfolder.vmresolved="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" build.core.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores\arduino" vm.core.include="Arduino.h" vm.boardsource.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" runtime.platform.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" vm.platformname.name="avr" build.arch="AVR" builder.noino="false" build.architecture="4.9.2-atmel3.5.3-arduino2" vmresolved.compiler.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2\bin\" vmresolved.tools.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2" build.variant.vmresolved.name="standard" build.variant.vmresolved.full_path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\variants\standard" build.path="C:\Users\Geek\AppData\Local\Temp\VMBuilds\open_evse\uno\Debug" build.project_name="open_evse.ino" build.project_path="D:\git\open_evse\firmware\open_evse" ProjectDir="D:\git\open_evse\firmware\open_evse\" vm.runtime.compiler.showwarnings="false" vm.runtime.upload.verbose="false" vm.runtime.upload.verify="false" serial.port.file="COM5" serial.port="COM5" serial.port.num="5" vm.runtime.compiler.auto_discover_includes="true" vm.runtime.compiler.auto_discover_includes_cache="true" build.vm.build.vmdebug="1" build.vm.build.isgdb="0" build.vm.build.optimised="1" vm.last.buildpath="C:\Users\Geek\AppData\Local\Temp\VMBuilds\open_evse\uno\Debug" />
-    </Platform>
-    <Debug EnableBreak="1" DebugEnabled="1" />
-  </Program>
-</VisualMicro>
\ No newline at end of file
diff --git a/firmware/open_evse/__vm/Configuration.Release.vmps.xml b/firmware/open_evse/__vm/Configuration.Release.vmps.xml
deleted file mode 100644
index 52468bef..00000000
--- a/firmware/open_evse/__vm/Configuration.Release.vmps.xml
+++ /dev/null
@@ -1,9 +0,0 @@
-<VisualMicro>
-  <Program Name="open_evse" Ext=".ino" Location="D:\git\open_evse\firmware\open_evse">
-    <Compile ReCompileIfSourceIsNewer="1" IsDebugStart="1" IsGdb="0" IsCompiled="0" CompilerErrors="0" ConfigurationName="Release" UseConfigurationNameInBuildFolder="True" StopOnError="False" OptimiseLibs="True" OptimiseCore="True" BuildPath="C:\Users\Geek\AppData\Local\Temp\VMBuilds\open_evse\diecimila_atmega328\Release" />
-    <Platform Name="arduino16x" Package="arduino" Platform="avr" Architecture="4.9.2-atmel3.5.3-arduino2">
-      <Board Name="diecimila_atmega328" Description="Arduino Duemilanove or Diecimila w/ ATmega328" CoreFolder="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores\arduino" VariantFullPath="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\variants\standard" McuIdePath="D:\hacking\arduino\arduino-1.6.3" McuSketchBookPath="D:\Geek\Google Drive\arduino\sketchbook" name="Arduino Duemilanove or Diecimila w/ ATmega328" upload.tool="avrdude" upload.protocol="arduino" bootloader.tool="avrdude" bootloader.low_fuses="0xFF" bootloader.unlock_bits="0x3F" bootloader.lock_bits="0x0F" build.f_cpu="16000000L" build.board="AVR_DUEMILANOVE" build.core="arduino" build.variant="standard" menu.cpu.atmega328="ATmega328" menu.cpu.atmega328.upload.maximum_size="30720" menu.cpu.atmega328.upload.maximum_data_size="2048" menu.cpu.atmega328.upload.speed="57600" menu.cpu.atmega328.bootloader.high_fuses="0xDA" menu.cpu.atmega328.bootloader.extended_fuses="0x05" menu.cpu.atmega328.bootloader.file="atmega/ATmegaBOOT_168_atmega328.hex" menu.cpu.atmega328.build.mcu="atmega328p" menu.cpu.atmega168="ATmega168" menu.cpu.atmega168.upload.maximum_size="14336" menu.cpu.atmega168.upload.maximum_data_size="1024" menu.cpu.atmega168.upload.speed="19200" menu.cpu.atmega168.bootloader.high_fuses="0xdd" menu.cpu.atmega168.bootloader.extended_fuses="0x00" menu.cpu.atmega168.bootloader.file="atmega/ATmegaBOOT_168_diecimila.hex" menu.cpu.atmega168.build.mcu="atmega168" runtime.ide.path="D:\hacking\arduino\arduino-1.6.3" runtime.os="windows" build.system.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\system" runtime.ide.version="10603" target_package="arduino" target_platform="avr" runtime.hardware.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr" originalid="diecimila" intellisense.tools.path="{runtime.tools.avr-gcc.path}\" intellisense.include.paths="{intellisense.tools.path}avr\include\;{intellisense.tools.path}avr\include\avr\;{intellisense.tools.path}lib\gcc\avr\4.8.1\include;{intellisense.tools.path}lib\gcc\avr\4.9.2\include;{intellisense.tools.path}lib\gcc\avr\4.9.3\include" tools.atprogram.cmd.path="%AVRSTUDIO_EXE_PATH%\atbackend\atprogram" tools.atprogram.cmd.setwinpath="true" tools.atprogram.program.params.verbose="-v" tools.atprogram.program.params.quiet="-q" tools.atprogram.program.pattern="&quot;{cmd.path}&quot; -d {build.mcu} {program.verbose} {program.extra_params} program -c -f &quot;{build.path}\{build.project_name}.hex&quot;" tools.atprogram.program.xpattern="&quot;{cmd.path}&quot; {AVRSTUDIO_BACKEND_CONNECTION} -d {build.mcu} {program.verbose} {program.extra_params} program -c -f &quot;{build.path}\{build.project_name}.hex&quot;" tools.atprogram.erase.params.verbose="-v" tools.atprogram.erase.params.quiet="-q" tools.atprogram.bootloader.params.verbose="-v" tools.atprogram.bootloader.params.quiet="-q" tools.atprogram.bootloader.pattern="&quot;{cmd.path}&quot; -d {build.mcu} {bootloader.verbose}  program -c -f &quot;{runtime.ide.path}\hardware\arduino\avr\bootloaders\{bootloader.file}&quot;" version="1.6.15" compiler.warning_flags="-w" compiler.warning_flags.none="-w" compiler.warning_flags.default="" compiler.warning_flags.more="-Wall" compiler.warning_flags.all="-Wall -Wextra" compiler.path="{runtime.tools.avr-gcc.path}/bin/" compiler.c.cmd="avr-gcc" compiler.c.flags="-c -g -Os {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -MMD -flto -fno-fat-lto-objects" compiler.c.elf.flags="{compiler.warning_flags} -Os -flto -fuse-linker-plugin -Wl,--gc-sections" compiler.c.elf.cmd="avr-gcc" compiler.S.flags="-c -g -x assembler-with-cpp -flto" compiler.cpp.cmd="avr-g++" compiler.cpp.flags="-c -g -Os {compiler.warning_flags} -std=gnu++11 -fpermissive -fno-exceptions -ffunction-sections -fdata-sections -fno-threadsafe-statics -MMD -flto" compiler.ar.cmd="avr-gcc-ar" compiler.ar.flags="rcs" compiler.objcopy.cmd="avr-objcopy" compiler.objcopy.eep.flags="-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0" compiler.elf2hex.flags="-O ihex -R .eeprom" compiler.elf2hex.cmd="avr-objcopy" compiler.ldflags="" compiler.size.cmd="avr-size" build.extra_flags="" compiler.c.extra_flags="" compiler.c.elf.extra_flags="" compiler.S.extra_flags="" compiler.cpp.extra_flags="" compiler.ar.extra_flags="" compiler.objcopy.eep.extra_flags="" compiler.elf2hex.extra_flags="" recipe.c.o.pattern="&quot;{compiler.path}{compiler.c.cmd}&quot; {compiler.c.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{object_file}&quot;" recipe.cpp.o.pattern="&quot;{compiler.path}{compiler.cpp.cmd}&quot; {compiler.cpp.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{object_file}&quot;" recipe.S.o.pattern="&quot;{compiler.path}{compiler.c.cmd}&quot; {compiler.S.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{object_file}&quot;" archive_file_path="{build.path}/{archive_file}" recipe.ar.pattern="&quot;{compiler.path}{compiler.ar.cmd}&quot; {compiler.ar.flags} {compiler.ar.extra_flags} &quot;{archive_file_path}&quot; &quot;{object_file}&quot;" recipe.c.combine.pattern="&quot;{compiler.path}{compiler.c.elf.cmd}&quot; {compiler.c.elf.flags} -mmcu={build.mcu} {compiler.c.elf.extra_flags} -o &quot;{build.path}/{build.project_name}.elf&quot; {object_files} &quot;{build.path}/{archive_file}&quot; &quot;-L{build.path}&quot; -lm" recipe.objcopy.eep.pattern="&quot;{compiler.path}{compiler.objcopy.cmd}&quot; {compiler.objcopy.eep.flags} {compiler.objcopy.eep.extra_flags} &quot;{build.path}/{build.project_name}.elf&quot; &quot;{build.path}/{build.project_name}.eep&quot;" recipe.objcopy.hex.pattern="&quot;{compiler.path}{compiler.elf2hex.cmd}&quot; {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} &quot;{build.path}/{build.project_name}.elf&quot; &quot;{build.path}/{build.project_name}.hex&quot;" recipe.output.tmp_file="{build.project_name}.hex" recipe.output.save_file="{build.project_name}.{build.variant}.hex" recipe.size.pattern="&quot;{compiler.path}{compiler.size.cmd}&quot; -A &quot;{build.path}/{build.project_name}.elf&quot;" recipe.size.regex="^(?:\.text|\.data|\.bootloader)\s+([0-9]+).*" recipe.size.regex.data="^(?:\.data|\.bss|\.noinit)\s+([0-9]+).*" recipe.size.regex.eeprom="^(?:\.eeprom)\s+([0-9]+).*" preproc.includes.flags="-w -x c++ -M -MG -MP" recipe.preproc.includes="&quot;{compiler.path}{compiler.cpp.cmd}&quot; {compiler.cpp.flags} {preproc.includes.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot;" preproc.macros.flags="-w -x c++ -E -CC" recipe.preproc.macros="&quot;{compiler.path}{compiler.cpp.cmd}&quot; {compiler.cpp.flags} {preproc.macros.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} &quot;{source_file}&quot; -o &quot;{preprocessed_file_path}&quot;" tools.avrdude.path="{runtime.tools.avrdude.path}" tools.avrdude.cmd.path="{path}/bin/avrdude" tools.avrdude.config.path="{path}/etc/avrdude.conf" tools.avrdude.upload.params.verbose="-v" tools.avrdude.upload.params.quiet="-q -q" tools.avrdude.upload.verify="" tools.avrdude.upload.params.noverify="-V" tools.avrdude.upload.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {upload.verbose} {upload.verify} -p{build.mcu} -c{upload.protocol} -P{serial.port} -b{upload.speed} -D &quot;-Uflash:w:{build.path}/{build.project_name}.hex:i&quot;" tools.avrdude.program.params.verbose="-v" tools.avrdude.program.params.quiet="-q -q" tools.avrdude.program.verify="" tools.avrdude.program.params.noverify="-V" tools.avrdude.program.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {program.verbose} {program.verify} -p{build.mcu} -c{protocol} {program.extra_params} &quot;-Uflash:w:{build.path}/{build.project_name}.hex:i&quot;" tools.avrdude.erase.params.verbose="-v" tools.avrdude.erase.params.quiet="-q -q" tools.avrdude.erase.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {erase.verbose} -p{build.mcu} -c{protocol} {program.extra_params} -e -Ulock:w:{bootloader.unlock_bits}:m -Uefuse:w:{bootloader.extended_fuses}:m -Uhfuse:w:{bootloader.high_fuses}:m -Ulfuse:w:{bootloader.low_fuses}:m" tools.avrdude.bootloader.params.verbose="-v" tools.avrdude.bootloader.params.quiet="-q -q" tools.avrdude.bootloader.pattern="&quot;{cmd.path}&quot; &quot;-C{config.path}&quot; {bootloader.verbose} -p{build.mcu} -c{protocol} {program.extra_params} &quot;-Uflash:w:{runtime.platform.path}/bootloaders/{bootloader.file}:i&quot; -Ulock:w:{bootloader.lock_bits}:m" tools.avrdude_remote.upload.pattern="/usr/bin/run-avrdude /tmp/sketch.hex {upload.verbose} -p{build.mcu}" build.usb_manufacturer="&quot;Unknown&quot;" build.usb_flags="-DUSB_VID={build.vid} -DUSB_PID={build.pid} '-DUSB_MANUFACTURER={build.usb_manufacturer}' '-DUSB_PRODUCT={build.usb_product}'" vm.platform.root.path="C:\Program Files (x86)\Microsoft Visual Studio 14.0\Common7\IDE\Extensions\bkkxodqu.rgl\Micro Platforms\arduino16x" avrisp.name="AVR ISP" avrisp.communication="serial" avrisp.protocol="stk500v1" avrisp.program.protocol="stk500v1" avrisp.program.tool="avrdude" avrisp.program.extra_params="-P{serial.port}" avrispmkii.name="AVRISP mkII" avrispmkii.communication="usb" avrispmkii.protocol="stk500v2" avrispmkii.program.protocol="stk500v2" avrispmkii.program.tool="avrdude" avrispmkii.program.extra_params="-Pusb" usbtinyisp.name="USBtinyISP" usbtinyisp.protocol="usbtiny" usbtinyisp.program.tool="avrdude" usbtinyisp.program.extra_params="" arduinoisp.name="ArduinoISP" arduinoisp.protocol="arduinoisp" arduinoisp.program.tool="avrdude" arduinoisp.program.extra_params="" usbasp.name="USBasp" usbasp.communication="usb" usbasp.protocol="usbasp" usbasp.program.protocol="usbasp" usbasp.program.tool="avrdude" usbasp.program.extra_params="-Pusb" parallel.name="Parallel Programmer" parallel.protocol="dapa" parallel.force="true" parallel.program.tool="avrdude" parallel.program.extra_params="-F" arduinoasisp.name="Arduino as ISP" arduinoasisp.communication="serial" arduinoasisp.protocol="stk500v1" arduinoasisp.speed="19200" arduinoasisp.program.protocol="stk500v1" arduinoasisp.program.speed="19200" arduinoasisp.program.tool="avrdude" arduinoasisp.program.extra_params="-P{serial.port} -b{program.speed}" usbGemma.name="Arduino Gemma" usbGemma.protocol="arduinogemma" usbGemma.program.tool="avrdude" usbGemma.program.extra_params="" usbGemma.config.path="{runtime.platform.path}/bootloaders/gemma/avrdude.conf" stk500.name="Atmel STK500 development board" stk500.communication="serial" stk500.protocol="stk500" stk500.program.protocol="stk500" stk500.program.tool="avrdude" stk500.program.extra_params="-P{serial.port}" buspirate.name="BusPirate as ISP" buspirate.communication="serial" buspirate.protocol="buspirate" buspirate.program.protocol="buspirate" buspirate.program.tool="avrdude" buspirate.program.extra_params="-P{serial.port}" runtime.tools.avr-gcc.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2" runtime.tools.avr-gcc-4.9.2-atmel3.5.3-arduino2.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2" runtime.tools.avrdude.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avrdude\6.3.0-arduino6" runtime.tools.avrdude-6.3.0-arduino6.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avrdude\6.3.0-arduino6" runtime.tools.avrdude-6.0.1-arduino3.path="D:\hacking\arduino\arduino-1.6.3\hardware\tools\avr" runtime.tools.avr-gcc-4.8.1-arduino3.path="D:\hacking\arduino\arduino-1.6.3\hardware\tools\avr" runtime.tools.tools-avr.path="D:\hacking\arduino\arduino-1.6.3\hardware\tools\avr" upload.maximum_size="30720" upload.maximum_data_size="2048" upload.speed="57600" bootloader.high_fuses="0xDA" bootloader.extended_fuses="0x05" bootloader.file="atmega/ATmegaBOOT_168_atmega328.hex" build.mcu="atmega328p" runtime.vm.boardinfo.id="diecimila_atmega328" runtime.vm.boardinfo.name="diecimila_atmega328" runtime.vm.boardinfo.desc="Arduino Duemilanove or Diecimila w/ ATmega328" runtime.vm.boardinfo.src_location="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" ide.hint="Use installed IDE. Provides built-in hardware, reference/help and libraries." ide.location.key="Arduino16x" ide.location.ide.winreg="Arduino 1.6.x Application" ide.location.sketchbook.winreg="Arduino 1.6.x Sketchbook" ide.location.sketchbook.preferences="sketchbook.path" ide.default.revision_name="1.8.0" ide.default.version="10800" ide.default.package="arduino" ide.default.platform="avr" ide.multiplatform="true" ide.includes="Arduino.h" ide.exe_name="arduino" ide.platformswithoutpackage="false" ide.includes.fallback="wprogram.h" ide.extension="ino" ide.extension.fallback="pde" ide.versionGTEQ="160" ide.exe="arduino.exe" ide.builder.exe="arduinobuilder.exe" ide.builder.name="Arduino Builder" ide.hosts="atmel" ide.url="http://arduino.cc/en/Main/Software" ide.help.reference.path="reference" ide.help.reference.path2="reference\www.arduino.cc\en\Reference" ide.help.reference.serial="reference\www.arduino.cc\en\Serial" ide.location.preferences.portable="{runtime.ide.path}\portable" ide.location.preferences.arduinoData="{runtime.sketchbook.path}\ArduinoData" ide.location.preferences="%VM_APPDATA_LOCAL%\arduino15\preferences.txt" ide.location.preferences_fallback="%VM_APPDATA_ROAMING%\arduino15\preferences.txt" ide.location.contributions="%VM_APPDATA_LOCAL%\arduino15" ide.location.contributions_fallback="%VM_APPDATA_ROAMING%\arduino15" ide.contributions.boards.allow="true" ide.contributions.boards.ignore_unless_rewrite_found="true" ide.contributions.libraries.allow="true" ide.contributions.boards.support.urls.wiki="https://github.com/arduino/Arduino/wiki/Unofficial-list-of-3rd-party-boards-support-urls" ide.create_platforms_from_boardsTXT.teensy="build.core" vm.debug="true" software="ARDUINO" ssh.user.name="root" ssh.user.default.password="arduino" ssh.host.wwwfiles.path="/www/sd" build.working_directory="{runtime.ide.path}\java\bin" ide.appid="arduino16x" location.sketchbook="D:\Geek\Google Drive\arduino\sketchbook" build.core.vmresolved="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores\arduino" build.core.parentfolder.vmresolved="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores" build.core.coresparentfolder.vmresolved="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" build.core.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\cores\arduino" vm.core.include="Arduino.h" vm.boardsource.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" runtime.platform.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15" vm.platformname.name="avr" build.arch="AVR" builder.noino="false" build.architecture="4.9.2-atmel3.5.3-arduino2" vmresolved.compiler.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2\bin\" vmresolved.tools.path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\tools\avr-gcc\4.9.2-atmel3.5.3-arduino2" build.variant.vmresolved.name="standard" build.variant.vmresolved.full_path="C:\Users\Geek\AppData\Local\arduino15\packages\arduino\hardware\avr\1.6.15\variants\standard" vm.runtime.compiler.showwarnings="false" vm.runtime.upload.verbose="false" vm.runtime.upload.verify="false" build.path="C:\Users\Geek\AppData\Local\Temp\VMBuilds\open_evse\diecimila_atmega328\Release" build.project_name="open_evse.ino" build.project_path="D:\git\open_evse\firmware\open_evse" ProjectDir="D:\git\open_evse\firmware\open_evse\" vm.runtime.compiler.auto_discover_includes="true" vm.runtime.compiler.auto_discover_includes_cache="true" build.vm.build.vmdebug="0" build.vm.build.isgdb="0" build.vm.build.optimised="1" vm.last.buildpath="C:\Users\Geek\AppData\Local\Temp\VMBuilds\open_evse\diecimila_atmega328\Release" />
-    </Platform>
-    <Debug DebugEnabled="0" EnableBreak="1" />
-  </Program>
-</VisualMicro>
\ No newline at end of file

From 5068634386c2a329baa6bfdd708fa83007945d2e Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 27 May 2026 15:36:26 -0700
Subject: [PATCH 37/59] autodetect all m328p versions v4/5/6 CGMI

---
 firmware/open_evse/J1772EvseController.cpp | 43 ++++++++--------------
 firmware/open_evse/J1772EvseController.h   |  7 +---
 firmware/open_evse/main.cpp                | 10 ++++-
 firmware/open_evse/open_evse.h             | 15 +++++---
 firmware/targets/m328p/pindefs.h           | 23 ++----------
 firmware/targets/m328p/platformio.ini      | 27 ++++++--------
 firmware/targets/m328p/target.cpp          | 37 ++++++++++++++++++-
 firmware/targets/samd/platformio.ini       |  5 +--
 firmware/targets/samd/target.cpp           |  2 +
 platformio.ini                             |  2 +-
 10 files changed, 93 insertions(+), 78 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index ab0300b4..8301c2ce 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -490,7 +490,7 @@ uint8_t J1772EVSEController::EnableAutoSvcLevel(uint8_t tf)
 {
   int rc = 0;
   if (tf) {
-    if (CGMIisEnabled()) rc = 1;
+    if (hasCGMI()) rc = 1;
     else clrFlags(ECF_AUTO_SVC_LEVEL_DISABLED);
   }
   else {
@@ -693,7 +693,7 @@ uint8_t J1772EVSEController::doPost()
   WDT_RESET();
 
   uint8_t RelayOff;
-#ifndef OPENEVSE_2
+#if !defined(OPENEVSE_2) && defined(AUTOSVCLEVEL)
   uint8_t Relay1, Relay2; //Relay Power status
 #endif
   uint8_t svcState = UD;	// service state = undefined
@@ -896,8 +896,8 @@ uint8_t J1772EVSEController::doPost()
 #endif
     if (StuckRelayChkEnabled()) {
       RelayOff = ReadACPins();
-      if ((CGMIisEnabled() && !(RelayOff & RLY_TEST_PIN_OPEN)) ||
-          (!CGMIisEnabled() && (RelayOff != ACPINS_OPEN))) {
+      if ((hasCGMI() && !(RelayOff & RLY_TEST_PIN_OPEN)) ||
+          (!hasCGMI() && (RelayOff != ACPINS_OPEN))) {
 	svcState = SR;
 #ifdef LCD16X2
 	g_OBD.LcdMsg_P(g_psTestFailed,g_psStuckRelay);
@@ -948,18 +948,6 @@ uint8_t J1772EVSEController::doPost()
 
 void J1772EVSEController::Init()
 {
-#ifdef OEV6
-  DPIN_MODE_INPUT(V6_ID_REG,V6_ID_IDX);
-#ifdef INVERT_V6_DETECTION
-  if (DPIN_READ(V6_ID_REG,V6_ID_IDX)) m_isV6 = 0;
-  else m_isV6 = 1;
-#else
-  if (DPIN_READ(V6_ID_REG,V6_ID_IDX)) m_isV6 = 1;
-  else m_isV6 = 0;
-#endif
-  //  Serial.print("isV6: ");Serial.println(isV6());
-#endif
-
 #ifdef MENNEKES_LOCK
   m_MennekesLock.Init();
 #endif // MENNEKES_LOCK
@@ -1055,11 +1043,12 @@ void J1772EVSEController::Init()
   m_wFlags |= ECF_AUTO_SVC_LEVEL_DISABLED;
 #endif
 
-#ifdef ENABLE_CGMI
-  m_wFlags |= ECF_CGMI;
-#endif // ENABLE_CGMI
-
-  if (CGMIisEnabled() && !flagIsSet(ECF_AUTO_SVC_LEVEL_DISABLED)) {
+#ifdef OEV6
+  if (g_hasCGMI) {
+    m_wFlags |= ECF_CGMI;
+  }
+#endif
+  if (hasCGMI() && !flagIsSet(ECF_AUTO_SVC_LEVEL_DISABLED)) {
     // can't do auto svc level when CGMI enabled, revert to default
     setFlags(ECF_AUTO_SVC_LEVEL_DISABLED);
     svclvl = DEFAULT_SERVICE_LEVEL;
@@ -1372,7 +1361,7 @@ void J1772EVSEController::Update(uint8_t forcetransition)
 #ifdef ADVPWR
   uint8_t acpinstate = ReadACPins();
 
-  if (CGMIisEnabled() && GndChkEnabled() && (acpinstate & GND_TEST_PIN_OPEN)) {
+  if (hasCGMI() && GndChkEnabled() && (acpinstate & GND_TEST_PIN_OPEN)) {
     // bad ground
     tmpevsestate = EVSE_STATE_NO_GROUND;
     m_EvseState = EVSE_STATE_NO_GROUND;
@@ -1390,14 +1379,14 @@ void J1772EVSEController::Update(uint8_t forcetransition)
   
   if (nofault) {
     if (chargingIsOn()) { // relay closed
-      if (StuckRelayChkEnabled() && CGMIisEnabled() && ((curms - m_ChargeOnTimeMS) > GROUND_CHK_DELAY) && (acpinstate & RLY_TEST_PIN_OPEN)) {
+      if (StuckRelayChkEnabled() && hasCGMI() && ((curms - m_ChargeOnTimeMS) > GROUND_CHK_DELAY) && (acpinstate & RLY_TEST_PIN_OPEN)) {
         // relay didn't close
         chargingOff(); // open the relay
         tmpevsestate = EVSE_STATE_RELAY_CLOSURE_FAULT;
         m_EvseState = EVSE_STATE_RELAY_CLOSURE_FAULT;
         nofault = 0;
       }
-      else if (!CGMIisEnabled() && ((curms - m_ChargeOnTimeMS) > GROUND_CHK_DELAY)) {
+      else if (!hasCGMI() && ((curms - m_ChargeOnTimeMS) > GROUND_CHK_DELAY)) {
         // ground check - can only test when relay closed
         if (GndChkEnabled() && (acpinstate == ACPINS_OPEN)) {
           // bad ground
@@ -1428,7 +1417,7 @@ void J1772EVSEController::Update(uint8_t forcetransition)
       }
     }
     else { // !chargingIsOn() - relay open
-      if (!CGMIisEnabled() && (prevevsestate == EVSE_STATE_NO_GROUND)) {
+      if (!hasCGMI() && (prevevsestate == EVSE_STATE_NO_GROUND)) {
         // check to see if EV disconnected
         if (!EvConnected()) {
           // EV disconnected - cancel fault
@@ -1448,8 +1437,8 @@ void J1772EVSEController::Update(uint8_t forcetransition)
         }
       }
       else if (StuckRelayChkEnabled()) {    // stuck relay check - can test only when relay open
-        if ((CGMIisEnabled() && !(acpinstate & RLY_TEST_PIN_OPEN)) ||
-            (!CGMIisEnabled() && (acpinstate != ACPINS_OPEN))) { // Stuck Relay reading
+        if ((hasCGMI() && !(acpinstate & RLY_TEST_PIN_OPEN)) ||
+            (!hasCGMI() && (acpinstate != ACPINS_OPEN))) { // Stuck Relay reading
           if ((prevevsestate != EVSE_STATE_STUCK_RELAY) && !m_StuckRelayStartTimeMS) { //check for first occurence
             m_StuckRelayStartTimeMS = curms; // mark start state
           }
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index e20a6d61..5e487afb 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -206,9 +206,6 @@ class J1772EVSEController {
 #ifdef OVERCURRENT_THRESHOLD
   unsigned long m_OverCurrentStartMs;
 #endif // OVERCURRENT_THRESHOLD
-#ifdef OEV6
-  uint8_t m_isV6;
-#endif
 
 
   void setFlags(uint16_t flags) { 
@@ -234,7 +231,7 @@ class J1772EVSEController {
   }
 
 #ifdef OEV6
-  uint8_t isV6() { return m_isV6; }
+  uint8_t isV6() { return g_isV6; }
 #endif
 
 #ifdef ADVPWR
@@ -329,7 +326,7 @@ class J1772EVSEController {
   void SetHardFault() { setVFlags(ECVF_HARD_FAULT); }
   void ClrHardFault() { clrVFlags(ECVF_HARD_FAULT); }
   int8_t InHardFault() { return vFlagIsSet(ECVF_HARD_FAULT); }
-  int8_t CGMIisEnabled() { return flagIsSet(ECF_CGMI); }
+  int8_t hasCGMI() { return flagIsSet(ECF_CGMI); }
   int8_t BootLockIsEnabled() { return !flagIsSet(ECF_BOOT_LOCK_DISABLED); }
   void EnableBootLock(uint8_t tf) {
     if (!tf) setFlags(ECF_BOOT_LOCK_DISABLED); 
diff --git a/firmware/open_evse/main.cpp b/firmware/open_evse/main.cpp
index 9e75a4c1..9657d105 100644
--- a/firmware/open_evse/main.cpp
+++ b/firmware/open_evse/main.cpp
@@ -142,6 +142,14 @@ BtnHandler g_BtnHandler;
 
 //-- begin global variables
 
+
+#ifdef OEV6
+// set by autodetection code in target.cpp initTarget()
+bool g_isV6 = false;
+#endif // OEV6
+bool g_hasCGMI = false;
+
+
 char g_sTmp[TMP_BUF_SIZE];
 
 OnboardDisplay g_OBD;
@@ -661,7 +669,7 @@ void OnboardDisplay::Update(int8_t updmode)
 #ifdef LCD16X2 //Adafruit RGB LCD
       LcdSetBacklightColor(RED);
       if (updmode == OBD_UPD_HARDFAULT) {
-        LcdMsg_P(g_EvseController.CGMIisEnabled() ? g_psSvcReq : g_psEvseError,g_psNoGround);
+        LcdMsg_P(g_EvseController.hasCGMI() ? g_psSvcReq : g_psEvseError,g_psNoGround);
       }
       else {
 	// 2nd line will be updated below with auto retry count
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index a4e5d216..03b72f0a 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -50,6 +50,15 @@
 //Language preferences: Add your custom languagefile here. See Language_default.h for more info.
 //#include "Language_norwegian.h"
 
+
+#ifdef OEV6
+// set by autodetection code in target.cpp initTarget()
+extern bool g_isV6;
+#endif // OEV6
+extern bool g_hasCGMI;
+
+
+
 //-- begin features
 
 #ifndef PLATFORMIO
@@ -57,13 +66,10 @@
 // support V6 hardware
 #define OEV6
 #ifdef OEV6
-//#define INVERT_V6_DETECTION // DO NOT USE: ONLY FOR lincomatic's BETA V6 board
 #define RELAY_PWM
 #define RELAY_HOLD_DELAY_TUNING // enable Z0
-#endif // OEV6
 
-// enable CGMI support
-//#define ENABLE_CGMI
+#endif // OEV6
 
 // auto detect L1/L2
 #ifndef NO_AUTOSVCLEVEL
@@ -1289,6 +1295,5 @@ extern TempMonitor g_TempMonitor;
 char *GetFirmwareVersion(char *str);
 void wdt_delay(uint32_t ms);
 
-
 #include "strings.h"
 #include "rapi_proc.h"
diff --git a/firmware/targets/m328p/pindefs.h b/firmware/targets/m328p/pindefs.h
index d3d04d79..b4bf6e78 100644
--- a/firmware/targets/m328p/pindefs.h
+++ b/firmware/targets/m328p/pindefs.h
@@ -3,10 +3,6 @@
 //#define PZEM_RX_PIN 9 // AUX_B = PB1
 //#define PZEM_TX_PIN A3 // AUX_A = PC3
 
-// V6 has PD7 tied to ground
-#define V6_ID_REG D
-#define V6_ID_IDX 7
-
 #define GFI_INTERRUPT 0 // interrupt number 0 = PD2, 1 = PD3
 // interrupt number 0 = PD2, 1 = PD3
 #define GFI_REG &PIND
@@ -38,22 +34,6 @@
 #define ACLINE2_REG &PIND
 #define ACLINE2_IDX 4
 
-#ifdef OEV6
-// digital Relay trigger pin
-#define CHARGING_REG &PIND
-#define CHARGING_IDX 5
-// digital Relay trigger pin for second relay
-//#define CHARGING2_REG &PIND
-//#define CHARGING2_IDX 6
-#else // !OEV6
-// digital Relay trigger pin
-#define CHARGING_REG &PINB
-#define CHARGING_IDX 0
-// digital Relay trigger pin for second relay - OE1 only
-//#define CHARGING2_REG &PIND
-//#define CHARGING2_IDX 7
-#endif // OEV6
-
 #ifdef VOLTMETER
 // N.B. Note, ADC2 is already used as PP_PIN so beware of potential clashes
 // voltmeter pin is ADC2 on OPENEVSE_2
@@ -82,6 +62,9 @@
 #define V6_CHARGING_PIN  5
 #define V6_CHARGING_PIN2 6
 
+// digital Relay trigger pin
+#define CHARGING_REG &PINB
+#define CHARGING_IDX 0
 // digital Relay trigger pin for second relay
 #define CHARGING2_REG &PIND
 #define CHARGING2_IDX 7
diff --git a/firmware/targets/m328p/platformio.ini b/firmware/targets/m328p/platformio.ini
index e03f4ddb..2001235f 100644
--- a/firmware/targets/m328p/platformio.ini
+++ b/firmware/targets/m328p/platformio.ini
@@ -6,8 +6,8 @@ lib_deps = ${common.lib_deps}
 build_src_flags =
   ${common.build_flags}
   -D TARGET_M328P
-  -D RAPI_SERIAL_PORT=Serial
   -D OEV6
+  -D RAPI_SERIAL_PORT=Serial
   -D RELAY_PWM
   -D SHOW_DISABLED_TESTS
   -I firmware/targets/m328p
@@ -15,8 +15,8 @@ build_src_filter =
   ${common.build_src_filter}
   +<../targets/m328p>
 
-# v5 OpenEVSE
-[env:m328p_v5]
+# autodetect V5/6 and CGMI
+[env:m328p_autodetect]
 platform = atmelavr@3.4.0
 board = openevse
 framework = arduino
@@ -29,17 +29,12 @@ build_src_flags=
   ${m328p.build_src_flags}
  -D 'VERSION="${common.version}"'
 
- # v6 CGMI OpenEVSE
-[env:m328p_v6]
-extends = env:m328p_v5
-build_src_flags=
-  ${m328p.build_src_flags}
-  -D ENABLE_CGMI
-  -D 'VERSION="${common.version}.CGMI"'
-
  # v5 OpenEVSE RTC LCD BTN
 [env:m328p_v5_RTC_BTN_LCD]
-extends = env:m328p_v5
+extends = env:m328p_autodetect
+platform = atmelavr@3.4.0
+board = openevse
+framework = arduino
 build_src_flags=
   ${m328p.build_src_flags}
   -D AUTOSVCLEVEL
@@ -54,10 +49,12 @@ build_src_flags=
 
 # openevse v6 with 16x2 RGBLCD and front panel button
 [env:m328p_v6_RTC_BTN_LCD]
-extends = env:m328p_v6
+extends = env:m328p_autodetect
+platform = atmelavr@3.4.0
+board = openevse
+framework = arduino
 build_src_flags=
   ${m328p.build_src_flags}
-  -D ENABLE_CGMI
   -D BTN_MENU
   -D HAVE_RTC
   -D DELAY_TIMER
@@ -65,7 +62,7 @@ build_src_flags=
   -D CHARGE_LIMIT
   -D TIME_LIMIT
   -D TEMPERATURE_THROTTLING
-  -D 'VERSION="${common.version}.CGMI_RTCRGBLCD"'
+  -D 'VERSION="${common.version}.RTCRGBLCD"'
 
    
 
diff --git a/firmware/targets/m328p/target.cpp b/firmware/targets/m328p/target.cpp
index 51facb69..93e9b91f 100644
--- a/firmware/targets/m328p/target.cpp
+++ b/firmware/targets/m328p/target.cpp
@@ -1,6 +1,5 @@
 #include "open_evse.h"
 
-
 // wdt_init turns off the watchdog timer after we use it
 // to reboot
 
@@ -126,4 +125,40 @@ uint16_t AdcPin::read()
 void initTarget()
 {
 
+/* detect the board
+ * Board ID
+PD7 | ADC6 |
+  0 | 0 | OpenEVSE v1-v5
+  1 | 0 | OEV6 v5.5
+  0 | 1 | n/a
+  1 | 1 | OEV6 + CGMI v6.5+
+  *
+  N.B. lincomatic's BETA V6 board inverts PD7 so V6 is PD7=0
+ */
+  DigitalPin pinPD7;
+  pinPD7.init(&PIND,7,DigitalPin::INP);
+  int pd7 = pinPD7.read();
+
+  // ADC - fake as a digital pin
+  int adc6 = analogRead(A6);
+  if (adc6 > 512) adc6 = 1;
+  else adc6 = 0;
+
+  if (pd7 && !adc6) {
+    g_isV6 = true;
+    g_hasCGMI = false;
+  }
+  else if (pd7 && adc6) {
+    g_isV6 = true;
+    g_hasCGMI = true;
+  }
+  else {
+    g_isV6 = false;
+    g_hasCGMI = false;
+  }
+
+  extern char g_sTmp[];
+  sprintf(g_sTmp,"isV6: %c  hasCGMI %c",g_isV6 ? '1':'0',g_hasCGMI ? '1':'0');
+  Serial.println(g_sTmp);
+
 }
diff --git a/firmware/targets/samd/platformio.ini b/firmware/targets/samd/platformio.ini
index f8637d44..87320309 100644
--- a/firmware/targets/samd/platformio.ini
+++ b/firmware/targets/samd/platformio.ini
@@ -6,14 +6,13 @@ build_src_flags =
   -D TARGET_SAMD
   -D EEPROM_FLASH_STORE_KB=48
   -D RAPI_SERIAL_PORT=Serial1
-  -D ENABLE_CGMI
   -I firmware/targets/samd
 build_src_filter =
   ${common.build_src_filter}
   +<../targets/samd>
 
 
-# SAMD CGMI OpenEVSE
+# SAMD OpenEVSE NXT
 [env:samd]
 platform = atmelsam
 framework = arduino
@@ -29,7 +28,7 @@ build_src_flags=
   ${common.build_flags}
   -D 'VERSION="${common.version}.SAMD"'
 
-# # SAMD CGMI OpenEVSE (Atmel-ICE upload/programming)
+# SAMD OpenEVSE NXT (Atmel-ICE upload/programming)
 [env:samd_ice]
 extends = env:samd
 upload_protocol = atmel-ice
diff --git a/firmware/targets/samd/target.cpp b/firmware/targets/samd/target.cpp
index 3349b0fa..01f88d30 100644
--- a/firmware/targets/samd/target.cpp
+++ b/firmware/targets/samd/target.cpp
@@ -53,6 +53,8 @@ void DigitalPin::init(uint32_t pinnum,int idxjunk,PinMode mode)
 // platform-specific init
 void initTarget()
 {
+  g_hasCGMI = true;
+
   Wire.begin();
   g_eeprom.setMemoryType(512);
   if (g_eeprom.begin() == false) {
diff --git a/platformio.ini b/platformio.ini
index bab61191..0b96aa36 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -16,7 +16,7 @@ extra_configs =
 
 [common]
 lib_deps =
-version = D8.5.0
+version = D9.0.0
 build_src_filter =
    +<*.cpp>
 build_flags =

From fbf25d3eaa8833106b9eb24d766c000446fbdc4c Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 27 May 2026 19:05:25 -0700
Subject: [PATCH 38/59] SetCurrentCapacity() - PP shouldn't override if nosave

---
 firmware/open_evse/J1772EvseController.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 8301c2ce..42d70f5e 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -2076,16 +2076,17 @@ int J1772EVSEController::SetCurrentCapacity(uint8_t amps,uint8_t updatelcd,uint8
   if (nosave) {
     // temporary amps can't be > max set in EEPROM
     maxcurrentcap = GetMaxCurrentCapacity();
-  }
 
 #ifdef PP_AUTO_AMPACITY
   if ((GetState() >= EVSE_STATE_B) && (GetState() <= EVSE_STATE_C)) {
     uint8_t mcc = g_ACCController.ReadPPMaxAmps();
-    if (mcc && (mcc < maxcurrentcap)) {
+    if (mcc && (mcc != PP_AMPS_ABSENT) && (mcc < maxcurrentcap)) {
       maxcurrentcap = mcc;
     }
   }
 #endif // PP_AUTO_AMPACITY
+  }
+
 
   if ((amps >= MIN_CURRENT_CAPACITY_J1772) && (amps <= maxcurrentcap)) {
     m_CurrentCapacity = amps;

From a647e76914f95d59f09bce8306fdbc7ebf2887c6 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 27 May 2026 19:07:39 -0700
Subject: [PATCH 39/59] add PP support for 12-bit ADC

---
 firmware/open_evse/AutoCurrentCapacityController.cpp | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/firmware/open_evse/AutoCurrentCapacityController.cpp b/firmware/open_evse/AutoCurrentCapacityController.cpp
index 7532adde..718ab0f3 100644
--- a/firmware/open_evse/AutoCurrentCapacityController.cpp
+++ b/firmware/open_evse/AutoCurrentCapacityController.cpp
@@ -16,6 +16,7 @@
 
 #ifdef PP_AUTO_AMPACITY
 
+#if (ADC_RESOLUTION_BITS == 10)
 static PP_AMPS s_ppAmps[] = {
   {0,0},
   {93,63},  // 100 = 93
@@ -24,6 +25,16 @@ static PP_AMPS s_ppAmps[] = {
   {615,13}, // 1.5K = 615
   {1023,0}
 };
+#elif (ADC_RESOLUTION_BITS == 12)
+static PP_AMPS s_ppAmps[] = {
+  {0,0},
+  {93*4,63},   // 100 = 93
+  {185*4,32},  // 220 = 185
+  {415*4,20},  // 680 = 415
+  {615*4,13},  // 1.5K = 615
+  {4095,0}
+};
+#endif
 
 AutoCurrentCapacityController::AutoCurrentCapacityController() :
   adcPP(PP_PIN)

From b8e0eeb396d88fe318b924ef36d7ca800dc26f21 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 27 May 2026 19:13:50 -0700
Subject: [PATCH 40/59] detect no PP resistor case

---
 firmware/open_evse/AutoCurrentCapacityController.cpp | 9 +++++++--
 firmware/open_evse/AutoCurrentCapacityController.h   | 3 +++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/firmware/open_evse/AutoCurrentCapacityController.cpp b/firmware/open_evse/AutoCurrentCapacityController.cpp
index 718ab0f3..bb365e62 100644
--- a/firmware/open_evse/AutoCurrentCapacityController.cpp
+++ b/firmware/open_evse/AutoCurrentCapacityController.cpp
@@ -46,7 +46,7 @@ uint8_t AutoCurrentCapacityController::ReadPPMaxAmps()
   // n.b. should probably sample a few times and average it
   uint16_t adcval = adcPP.read();
 
-  uint8_t amps = 0;
+  uint8_t amps = PP_AMPS_ABSENT;
   for (uint8_t i=1;i < sizeof(s_ppAmps)/sizeof(s_ppAmps[0]);i++) {
     if (adcval <= (s_ppAmps[i].adcVal - (s_ppAmps[i].adcVal - s_ppAmps[i-1].adcVal)/2)) {
       amps = s_ppAmps[i-1].amps;
@@ -65,13 +65,18 @@ uint8_t AutoCurrentCapacityController::AutoSetCurrentCapacity()
 {
   uint8_t amps = ReadPPMaxAmps();
 
-  if (amps) {
+  if (amps == PP_AMPS_ABSENT) {
+    // open circuit - no cable present, charge at configured capacity
+    return 0;
+  }
+  else if (amps) {
     if (g_EvseController.GetCurrentCapacity() > ppMaxAmps) {
       g_EvseController.SetCurrentCapacity(ppMaxAmps,1,1);
     }
     return 0;
   }
   else {
+    // ADC near zero - short on PP pin, block charging
     return 1;
   }
 }
diff --git a/firmware/open_evse/AutoCurrentCapacityController.h b/firmware/open_evse/AutoCurrentCapacityController.h
index ce58f4cf..6f8c405a 100644
--- a/firmware/open_evse/AutoCurrentCapacityController.h
+++ b/firmware/open_evse/AutoCurrentCapacityController.h
@@ -15,6 +15,9 @@
 
 #include "open_evse.h"
 
+// fake value denoting no resistor present
+#define PP_AMPS_ABSENT 0xFF
+
 typedef struct pp_amps {
   uint16_t adcVal;
   uint8_t amps;

From 9de2ae466a73545397818461a173757a4b085c1c Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Wed, 27 May 2026 20:09:30 -0700
Subject: [PATCH 41/59] add EVSE_STATE_PP_SHORTED

---
 firmware/CHANGELOG                         |  7 +++++++
 firmware/open_evse/J1772EvseController.cpp | 24 ++++++++++++++++++++++
 firmware/open_evse/J1772EvseController.h   |  7 ++++++-
 firmware/open_evse/Language_default.h      |  2 ++
 firmware/open_evse/main.cpp                | 20 ++++++++++++++----
 firmware/targets/m328p/strings.cpp         |  5 +++++
 firmware/targets/m328p/strings.h           |  5 +++++
 7 files changed, 65 insertions(+), 5 deletions(-)

diff --git a/firmware/CHANGELOG b/firmware/CHANGELOG
index 06fbb417..60d514dd 100644
--- a/firmware/CHANGELOG
+++ b/firmware/CHANGELOG
@@ -3,6 +3,13 @@ Change Log
 20260527 SCL
 - get rid of old V6 detection code (and INVERT_V6_DETECTION)
   -> new globals g_isV6 and g_hasCGMI initialized in initTarget()
+- PP
+  -> if no resistor present, disable auto ampacity
+  -> add EVSE_STATE_PP_SHORTED
+     -> if shorted PP detected on boot, spin until the cable is removed
+     -> if cable isn't present at boot, shorted PP will only be detected
+	on transition to STATE B/C
+     -> LCD: CABLE FAULT/PP SHORTED
 
 20260219 SCL
 - added $FF L 0|1 command to enable/disable boot lock feature
diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 42d70f5e..e7c536f2 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -367,6 +367,23 @@ void J1772EVSEController::chargingOff()
 #endif
 }
 
+#ifdef PP_AUTO_AMPACITY
+void J1772EVSEController::DoPPShorted()
+{
+  m_EvseState = EVSE_STATE_PP_SHORTED;
+  g_OBD.Update(OBD_UPD_FORCE);
+#ifdef RAPI
+  RapiSendEvseState();
+#endif
+  while (g_ACCController.ReadPPMaxAmps() == 0) {
+    ProcessInputs();
+    WDT_RESET();
+    delay(100);
+  }
+  m_EvseState = EVSE_STATE_UNKNOWN;
+}
+#endif // PP_AUTO_AMPACITY
+
 void J1772EVSEController::HardFault(int8_t recoverable)
 {
   SetHardFault();
@@ -1785,6 +1802,13 @@ if (TempChkEnabled()) {
       chargingOff(); // turn off charging current
       m_Pilot.SetState(PILOT_STATE_P12);
     }
+#ifdef PP_AUTO_AMPACITY
+    else if (m_EvseState == EVSE_STATE_PP_SHORTED) {
+      // Ground not detected
+      chargingOff(); // turn off charging current
+      m_Pilot.SetState(PILOT_STATE_P12);
+    }
+#endif // PP_AUTO_AMPACITY
     else if (m_EvseState == EVSE_STATE_STUCK_RELAY) {
       // Stuck relay detected
       chargingOff(); // turn off charging current
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index 5e487afb..82a5ae3e 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -38,7 +38,8 @@
 //reserved #define EVSE_STATE_PILOT_ERROR 0x0C // pilot self test error
 //reserved #define EVSE_STATE_TEMP_SENSOR_FAULT 0x0D // temp sensor dead
 #define EVSE_STATE_RELAY_CLOSURE_FAULT 0x0E
-#define EVSE_STATE_EEPROM_FAILURE 0x0F // SAMD only
+#define EVSE_STATE_PP_SHORTED 0x0F // PP pin shorted
+#define EVSE_STATE_EEPROM_FAILURE 0x10 // SAMD only
 #define EVSE_FAULT_STATE_END EVSE_STATE_EEPROM_FAILURE
            
 #define EVSE_STATE_SLEEPING 0xfe // waiting for timer
@@ -616,6 +617,10 @@ int GetHearbeatTrigger();
     eeprom_write_byte((uint8_t*)EOFS_NOGND_TRIP_CNT,0xff);
     eeprom_write_byte((uint8_t*)EOFS_STUCK_RELAY_TRIP_CNT,0xff);
   }
+#ifdef PP_AUTO_AMPACITY
+  void DoPPShorted();
+#endif // PP_AUTO_AMPACITY
+
 };
 
 #ifdef FT_ENDURANCE
diff --git a/firmware/open_evse/Language_default.h b/firmware/open_evse/Language_default.h
index f43a10f1..699c9efe 100644
--- a/firmware/open_evse/Language_default.h
+++ b/firmware/open_evse/Language_default.h
@@ -79,4 +79,6 @@
 #define STR_L1						     "L1"  
 #define STR_L2						     "L2"  
 #define STR_OVER_CURRENT "OVERCURRENT"
+#define STR_CABLE_FAULT "CABLE FAULT"
+#define STR_PP_SHORTED "PP SHORTED"
 //#endif
diff --git a/firmware/open_evse/main.cpp b/firmware/open_evse/main.cpp
index 9657d105..b1990c72 100644
--- a/firmware/open_evse/main.cpp
+++ b/firmware/open_evse/main.cpp
@@ -663,6 +663,17 @@ void OnboardDisplay::Update(int8_t updmode)
 #endif
       break;
 #endif // OVERCURRENT_THRESHOLD   
+#ifdef PP_AUTO_AMPACITY
+    case EVSE_STATE_PP_SHORTED:
+      SetGreenLed(0);
+      SetRedLed(1);
+#ifdef LCD16X2 //Adafruit RGB LCD
+      LcdSetBacklightColor(RED);
+      LcdPrint_P(0,g_psCableFault);
+      LcdPrint_P(1,g_psPPShorted);
+#endif
+      break;
+#endif // PP_AUTO_AMPACITY
     case EVSE_STATE_NO_GROUND:
       SetGreenLed(0);
       SetRedLed(1);
@@ -2418,7 +2429,9 @@ void EvseReset()
 #endif  // DELAYTIMER
 
 #ifdef PP_AUTO_AMPACITY
-  g_ACCController.AutoSetCurrentCapacity();
+  if (g_ACCController.AutoSetCurrentCapacity() == 1) {
+    g_EvseController.DoPPShorted();
+  }
 #endif
 }
 
@@ -2432,9 +2445,8 @@ uint8_t StateTransitionReqFunc(uint8_t curPilotState,uint8_t newPilotState,uint8
     // already debounces before requesting the state transition, so we can
     // be absolutely sure that the PP pin has firm contact by the time we
     // get here
-    if (g_ACCController.AutoSetCurrentCapacity()) {
-      // invalid PP so 0 amps - force to stay in State A
-      retEvseState = EVSE_STATE_A;
+    if (g_ACCController.AutoSetCurrentCapacity() == 1) {
+      retEvseState = EVSE_STATE_PP_SHORTED;
     }
   }
   /*  else { // EVSE_STATE_A
diff --git a/firmware/targets/m328p/strings.cpp b/firmware/targets/m328p/strings.cpp
index 024a4ab7..e44777ac 100644
--- a/firmware/targets/m328p/strings.cpp
+++ b/firmware/targets/m328p/strings.cpp
@@ -122,3 +122,8 @@ const char *g_DelayMenuItems[] = STR_YESNO_SETSTART_SETSTOP;
 #ifdef OVERCURRENT_THRESHOLD
 const char g_psOverCurrent[] PROGMEM = STR_OVER_CURRENT;
 #endif // OVERCURRENT_THRESHOLD
+
+#ifdef PP_AUTO_AMPACITY
+const char g_psCableFault[] PROGMEM = STR_CABLE_FAULT;
+const char g_psPPShorted[] PROGMEM = STR_PP_SHORTED;
+#endif //PP_AUTO_AMPACITY
diff --git a/firmware/targets/m328p/strings.h b/firmware/targets/m328p/strings.h
index 01f1b3a6..ad2c54ac 100644
--- a/firmware/targets/m328p/strings.h
+++ b/firmware/targets/m328p/strings.h
@@ -127,3 +127,8 @@ extern const char *g_DelayMenuItems[];
 #ifdef OVERCURRENT_THRESHOLD
 extern const char g_psOverCurrent[] PROGMEM;
 #endif // OVERCURRENT_THRESHOLD
+
+#ifdef PP_AUTO_AMPACITY
+extern const char g_psCableFault[] PROGMEM;
+extern const char g_psPPShorted[] PROGMEM;
+#endif //PP_AUTO_AMPACITY

From a9c7b6b017e0cf1e15cd6c90da32a69c7adad959 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Thu, 28 May 2026 12:25:51 -0400
Subject: [PATCH 42/59] Fix CGMI autodetect false positive and V6 relay not
 firing

- Raise ADC6 CGMI detection threshold from 512 to 1000; CGMI boards
  pull A6 to VCC via 330 ohm (~1023), floating pin on non-CGMI boards
  was falsely triggering above 512
- Move pinChargingAC.write(1) outside OEV6 if/else in chargingOn() so
  PB1 (AC relay) is driven HIGH for V6 boards, matching master behavior
- Update platformio.ini and prepare-release.sh for unified autodetect envs

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 firmware/open_evse/J1772EvseController.cpp |  7 +++----
 firmware/targets/m328p/platformio.ini      | 23 ++++------------------
 firmware/targets/m328p/target.cpp          | 11 ++++++-----
 prepare-release.sh                         | 14 ++++---------
 4 files changed, 17 insertions(+), 38 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index e7c536f2..5eb11b1b 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -302,10 +302,6 @@ void J1772EVSEController::chargingOn()
   }
   else {
 #endif // OEV6
-
-#ifdef CHARGINGAC_REG
-    pinChargingAC.write(1);
-#endif
 #ifdef CHARGING_REG
     pinCharging.write(1);
 #endif
@@ -315,6 +311,9 @@ void J1772EVSEController::chargingOn()
 #ifdef OEV6
   }
 #endif // OEV6
+#ifdef CHARGINGAC_REG
+  pinChargingAC.write(1);
+#endif
 
   setVFlags(ECVF_CHARGING_ON);
   
diff --git a/firmware/targets/m328p/platformio.ini b/firmware/targets/m328p/platformio.ini
index 2001235f..5a449527 100644
--- a/firmware/targets/m328p/platformio.ini
+++ b/firmware/targets/m328p/platformio.ini
@@ -29,8 +29,8 @@ build_src_flags=
   ${m328p.build_src_flags}
  -D 'VERSION="${common.version}"'
 
- # v5 OpenEVSE RTC LCD BTN
-[env:m328p_v5_RTC_BTN_LCD]
+ # v5/ v6 and CGMI plus legacy RTC LCD BTN
+[env:m328p_RTC_BTN_LCD]
 extends = env:m328p_autodetect
 platform = atmelavr@3.4.0
 board = openevse
@@ -45,25 +45,10 @@ build_src_flags=
   -D CHARGE_LIMIT
   -D TIME_LIMIT
   -D TEMPERATURE_THROTTLING
-  -D 'VERSION="${common.version}.v5RTCRGBLCD"'
-
-# openevse v6 with 16x2 RGBLCD and front panel button
-[env:m328p_v6_RTC_BTN_LCD]
-extends = env:m328p_autodetect
-platform = atmelavr@3.4.0
-board = openevse
-framework = arduino
-build_src_flags=
-  ${m328p.build_src_flags}
-  -D BTN_MENU
-  -D HAVE_RTC
-  -D DELAY_TIMER
-  -D RGBLCD
-  -D CHARGE_LIMIT
-  -D TIME_LIMIT
-  -D TEMPERATURE_THROTTLING
   -D 'VERSION="${common.version}.RTCRGBLCD"'
 
+
+
    
 
 
diff --git a/firmware/targets/m328p/target.cpp b/firmware/targets/m328p/target.cpp
index 93e9b91f..b9beb9f5 100644
--- a/firmware/targets/m328p/target.cpp
+++ b/firmware/targets/m328p/target.cpp
@@ -128,10 +128,10 @@ void initTarget()
 /* detect the board
  * Board ID
 PD7 | ADC6 |
-  0 | 0 | OpenEVSE v1-v5
-  1 | 0 | OEV6 v5.5
-  0 | 1 | n/a
-  1 | 1 | OEV6 + CGMI v6.5+
+  0 | 0   | OpenEVSE v1-v5
+  1 | 0   | OEV6 v5.5
+  0 | 1   | n/a
+  1 | 1   | OEV6 + CGMI v6.5+  (ADC6 tied to VCC via 330 ohm -> reads ~1023; floating = no CGMI)
   *
   N.B. lincomatic's BETA V6 board inverts PD7 so V6 is PD7=0
  */
@@ -140,8 +140,9 @@ PD7 | ADC6 |
   int pd7 = pinPD7.read();
 
   // ADC - fake as a digital pin
+  // CGMI boards tie A6 to VCC via 330 ohm -> reads ~1023; floating reads mid-rail or lower
   int adc6 = analogRead(A6);
-  if (adc6 > 512) adc6 = 1;
+  if (adc6 > 1000) adc6 = 1;
   else adc6 = 0;
 
   if (pd7 && !adc6) {
diff --git a/prepare-release.sh b/prepare-release.sh
index 96449ded..e97ec9b0 100755
--- a/prepare-release.sh
+++ b/prepare-release.sh
@@ -4,17 +4,11 @@
 
 mkdir -p firmware/targets
 
-pio run -e m328p_v6
-cp .pio/build/m328p_v6/firmware.hex firmware/targets/m328p_openevse_v6_CGMI.hex
+pio run -e m328p_autodetect
+cp .pio/build/m328p_v6/firmware.hex firmware/targets/m328p_openevse.hex
 
-pio run -e m328p_v5
-cp .pio/build/m328p_v5/firmware.hex firmware/targets/m328p_openevse_v5.hex
-
-pio run -e m328p_v6_RTC_BTN_LCD
-cp .pio/build/m328p_v6_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_v6_RTC_BTN_LCD.hex
-
-pio run -e m328p_v5_RTC_BTN_LCD
-cp .pio/build/m328p_v5_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_v5_RTC_BTN_LCD.hex
+pio run -e m328p_RTC_BTN_LCD
+cp .pio/build/m328p_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_RTC_BTN_LCD.hex
 
 pio run -e samd
 cp .pio/build/samd_us/firmware.bin firmware/targets/arm_samd_openevse_nxt.bin

From 4e7a039b8dba3bb6b69ec6ace6b45242e801ab6c Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Thu, 28 May 2026 12:34:22 -0400
Subject: [PATCH 43/59] Update CI to use unified autodetect build envs

Replace separate m328p_v5/v6 matrix entries with m328p_autodetect
and m328p_RTC_BTN_LCD to match consolidated platformio.ini envs.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 .github/workflows/build_platformio.yml | 14 ++------------
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/.github/workflows/build_platformio.yml b/.github/workflows/build_platformio.yml
index bfbe6df6..53b95723 100644
--- a/.github/workflows/build_platformio.yml
+++ b/.github/workflows/build_platformio.yml
@@ -12,22 +12,12 @@ jobs:
       fail-fast: false
       matrix:
         include:
-          - env: m328p_v5
+          - env: m328p_autodetect
             python: 3.x
             platformio: 6.1.5
             arch: avr
             artifact: firmware.hex
-          - env: m328p_v6
-            python: 3.x
-            platformio: 6.1.5
-            arch: avr
-            artifact: firmware.hex
-          - env: m328p_v5_RTC_BTN_LCD
-            python: 3.x
-            platformio: 6.1.5
-            arch: avr
-            artifact: firmware.hex
-          - env: m328p_v6_RTC_BTN_LCD
+          - env: m328p_RTC_BTN_LCD
             python: 3.x
             platformio: 6.1.5
             arch: avr

From c8b7674b60dd09a40a87568751d52dc0e03ffab9 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Thu, 28 May 2026 17:47:45 -0700
Subject: [PATCH 44/59] use mode of A6 for board detection since it floats in
 v1-5

---
 firmware/targets/m328p/target.cpp | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/firmware/targets/m328p/target.cpp b/firmware/targets/m328p/target.cpp
index b9beb9f5..2e4c946b 100644
--- a/firmware/targets/m328p/target.cpp
+++ b/firmware/targets/m328p/target.cpp
@@ -141,15 +141,21 @@ PD7 | ADC6 |
 
   // ADC - fake as a digital pin
   // CGMI boards tie A6 to VCC via 330 ohm -> reads ~1023; floating reads mid-rail or lower
-  int adc6 = analogRead(A6);
-  if (adc6 > 1000) adc6 = 1;
-  else adc6 = 0;
 
-  if (pd7 && !adc6) {
+  // loop and sample ADC6 a few times to get the statisical mode, since it's floating
+  int adc6Count[2] = {0,0};
+  for (int i = 0; i < 5; i++) {
+    int adc6 = analogRead(A6);
+    adc6Count[adc6 > 1000 ? 1 : 0]++;
+    delay(10);
+  }
+  int adc6Mode = (adc6Count[1] > adc6Count[0]) ? 1 : 0;
+
+  if (pd7 && !adc6Mode) {
     g_isV6 = true;
     g_hasCGMI = false;
   }
-  else if (pd7 && adc6) {
+  else if (pd7 && adc6Mode) {
     g_isV6 = true;
     g_hasCGMI = true;
   }
@@ -158,8 +164,11 @@ PD7 | ADC6 |
     g_hasCGMI = false;
   }
 
+  /*
   extern char g_sTmp[];
+  sprintf(g_sTmp,"pd7: %c  adc6Mode: %c",pd7 ? '1':'0',adc6Mode ? '1':'0');
+  Serial.println(g_sTmp);
   sprintf(g_sTmp,"isV6: %c  hasCGMI %c",g_isV6 ? '1':'0',g_hasCGMI ? '1':'0');
   Serial.println(g_sTmp);
-
+  */
 }

From def925c4cef2656c836ff3c83010d10a43813308 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Fri, 29 May 2026 16:46:20 -0700
Subject: [PATCH 45/59] add AdcPin default constructor

---
 firmware/open_evse/J1772EvseController.h | 8 +++++++-
 firmware/open_evse/rapi_proc.cpp         | 5 +++++
 firmware/open_evse/rapi_proc.h           | 1 +
 firmware/targets/m328p/target.h          | 1 +
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index 82a5ae3e..132cdbb6 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -79,7 +79,7 @@ typedef uint8_t (*EvseStateTransitionReqFunc)(uint8_t prevPilotState,uint8_t cur
 #define ECF_GND_CHK_DISABLED   0x0008 // no chk for ground fault
 #define ECF_STUCK_RELAY_CHK_DISABLED 0x0010 // no chk for stuck relay
 #define ECF_AUTO_SVC_LEVEL_DISABLED  0x0020 // auto detect svc level - requires ADVPWR
-//obsolete #define ECF_AUTO_START_DISABLED 0x0040  // no auto start charging
+#define ECF_PP_AUTO_AMPACITY 0x0040  // PP autoampacity enabled
 #define ECF_SERIAL_DBG         0x0080 // enable debugging messages via serial
 #define ECF_MONO_LCD           0x0100 // monochrome LCD backlight
 #define ECF_GFI_TEST_DISABLED  0x0200 // no GFI self test
@@ -340,6 +340,12 @@ class J1772EVSEController {
     else clrFlags(ECF_OVERCURRENT_DISABLED);
     SaveEvseFlags();
   }
+  int8_t PPAutoAmpacityIsEnabled() { return flagIsSet(ECF_PP_AUTO_AMPACITY); }
+  void EnablePPAutoAmpacity(uint8_t tf) {
+    if (tf) setFlags(ECF_PP_AUTO_AMPACITY); 
+    else clrFlags(ECF_PP_AUTO_AMPACITY);
+    SaveEvseFlags();
+  }
   unsigned long GetResetMs();
 
   uint8_t SetMaxHwCurrentCapacity(uint8_t amps);
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index 95d39680..c3f424f2 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -339,6 +339,11 @@ int EvseRapiProcessor::processCmd()
 	    g_EvseController.EnableOverCurrentCheck(u1.u8);
 	    break;
 #endif // OVERCURRENT_THRESHOLD
+#ifdef PP_AUTO_AMPACITY
+	  case 'P': // PP auto ampacity 
+	    g_EvseController.EnablePPAutoAmpacity(u1.u8);
+	    break;
+#endif // PP_AUTO_AMPACITY
 #ifdef TEMPERATURE_MONITORING
 	  case 'T': // temperature monitoring
 	    g_EvseController.EnableTempChk(u1.u8);
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index 9c36f5a0..ca512cb2 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -147,6 +147,7 @@ FF - enable/disable feature
   G = Ground check
   L = boot Lock
   O = overcurrent check
+  P = PP auto ampacity
   R = stuck Relay check
   T = temperature monitoring
   V = Vent required check
diff --git a/firmware/targets/m328p/target.h b/firmware/targets/m328p/target.h
index c8d5a1f8..8a5c23b5 100644
--- a/firmware/targets/m328p/target.h
+++ b/firmware/targets/m328p/target.h
@@ -219,6 +219,7 @@ class AdcPin {
 public:
   enum PinMode { INP,INP_PU,OUT };
 
+  AdcPin() {}
   AdcPin(uint8_t _adcNum) {
     init(_adcNum);
   }

From 45495bcacdb9f077848901afe3a9181882d3f7ad Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Fri, 29 May 2026 16:50:11 -0700
Subject: [PATCH 46/59] added EVSE_STATE_PP_MISSING

---
 .../AutoCurrentCapacityController.cpp         |  8 ++++++--
 .../open_evse/AutoCurrentCapacityController.h |  3 +++
 firmware/open_evse/J1772EvseController.cpp    | 20 +++++++++++++------
 firmware/open_evse/J1772EvseController.h      |  8 ++++++--
 firmware/open_evse/Language_default.h         |  2 ++
 firmware/open_evse/main.cpp                   | 19 ++++++++++++++++--
 firmware/targets/m328p/strings.cpp            |  1 +
 firmware/targets/m328p/strings.h              |  1 +
 8 files changed, 50 insertions(+), 12 deletions(-)

diff --git a/firmware/open_evse/AutoCurrentCapacityController.cpp b/firmware/open_evse/AutoCurrentCapacityController.cpp
index bb365e62..09d80bdf 100644
--- a/firmware/open_evse/AutoCurrentCapacityController.cpp
+++ b/firmware/open_evse/AutoCurrentCapacityController.cpp
@@ -37,12 +37,14 @@ static PP_AMPS s_ppAmps[] = {
 #endif
 
 AutoCurrentCapacityController::AutoCurrentCapacityController() :
-  adcPP(PP_PIN)
+  adcPP(PP_PIN),enabled(false)
 {
 }
 
 uint8_t AutoCurrentCapacityController::ReadPPMaxAmps()
 {
+  if (!enabled) return PP_AMPS_ABSENT;
+
   // n.b. should probably sample a few times and average it
   uint16_t adcval = adcPP.read();
 
@@ -63,11 +65,13 @@ uint8_t AutoCurrentCapacityController::ReadPPMaxAmps()
 
 uint8_t AutoCurrentCapacityController::AutoSetCurrentCapacity()
 {
+  if (!enabled) return 0;
+
   uint8_t amps = ReadPPMaxAmps();
 
   if (amps == PP_AMPS_ABSENT) {
     // open circuit - no cable present, charge at configured capacity
-    return 0;
+    return PP_AMPS_ABSENT;
   }
   else if (amps) {
     if (g_EvseController.GetCurrentCapacity() > ppMaxAmps) {
diff --git a/firmware/open_evse/AutoCurrentCapacityController.h b/firmware/open_evse/AutoCurrentCapacityController.h
index 6f8c405a..bb22e89b 100644
--- a/firmware/open_evse/AutoCurrentCapacityController.h
+++ b/firmware/open_evse/AutoCurrentCapacityController.h
@@ -26,12 +26,15 @@ typedef struct pp_amps {
 class AutoCurrentCapacityController {
   AdcPin adcPP;
   uint8_t ppMaxAmps;
+  bool enabled;
 
 public:
   AutoCurrentCapacityController();
   uint8_t GetPPMaxAmps() { return ppMaxAmps; }
   uint8_t ReadPPMaxAmps();
   uint8_t AutoSetCurrentCapacity();
+  bool IsEnabled() { return enabled; }
+  void Enable(bool tf) { enabled = tf; }
 };
 
 
diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 5eb11b1b..129775c5 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -367,18 +367,26 @@ void J1772EVSEController::chargingOff()
 }
 
 #ifdef PP_AUTO_AMPACITY
-void J1772EVSEController::DoPPShorted()
+void J1772EVSEController::DoPPError(bool shorted)
 {
-  m_EvseState = EVSE_STATE_PP_SHORTED;
+  if (shorted) {
+    m_EvseState = EVSE_STATE_PP_SHORTED;
+  }
+  else {
+    m_EvseState = EVSE_STATE_PP_MISSING;
+  }
   g_OBD.Update(OBD_UPD_FORCE);
 #ifdef RAPI
   RapiSendEvseState();
 #endif
-  while (g_ACCController.ReadPPMaxAmps() == 0) {
+  int ppmaxamps;
+   do {
+    ppmaxamps = g_ACCController.ReadPPMaxAmps();
     ProcessInputs();
     WDT_RESET();
     delay(100);
-  }
+   } while ((shorted && !ppmaxamps) || // shorted
+            (!shorted && (ppmaxamps < PP_AMPS_ABSENT))); // missing
   m_EvseState = EVSE_STATE_UNKNOWN;
 }
 #endif // PP_AUTO_AMPACITY
@@ -1802,8 +1810,8 @@ if (TempChkEnabled()) {
       m_Pilot.SetState(PILOT_STATE_P12);
     }
 #ifdef PP_AUTO_AMPACITY
-    else if (m_EvseState == EVSE_STATE_PP_SHORTED) {
-      // Ground not detected
+    else if ((m_EvseState == EVSE_STATE_PP_SHORTED) || (m_EvseState == EVSE_STATE_PP_MISSING)) {
+      // PP pin shorted
       chargingOff(); // turn off charging current
       m_Pilot.SetState(PILOT_STATE_P12);
     }
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index 132cdbb6..f49fd3b7 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -39,7 +39,8 @@
 //reserved #define EVSE_STATE_TEMP_SENSOR_FAULT 0x0D // temp sensor dead
 #define EVSE_STATE_RELAY_CLOSURE_FAULT 0x0E
 #define EVSE_STATE_PP_SHORTED 0x0F // PP pin shorted
-#define EVSE_STATE_EEPROM_FAILURE 0x10 // SAMD only
+#define EVSE_STATE_PP_MISSING 0x10 // PP resistor missing
+#define EVSE_STATE_EEPROM_FAILURE 0x11 // SAMD only
 #define EVSE_FAULT_STATE_END EVSE_STATE_EEPROM_FAILURE
            
 #define EVSE_STATE_SLEEPING 0xfe // waiting for timer
@@ -340,12 +341,15 @@ class J1772EVSEController {
     else clrFlags(ECF_OVERCURRENT_DISABLED);
     SaveEvseFlags();
   }
+  #ifdef PP_AUTO_AMPACITY
   int8_t PPAutoAmpacityIsEnabled() { return flagIsSet(ECF_PP_AUTO_AMPACITY); }
   void EnablePPAutoAmpacity(uint8_t tf) {
     if (tf) setFlags(ECF_PP_AUTO_AMPACITY); 
     else clrFlags(ECF_PP_AUTO_AMPACITY);
     SaveEvseFlags();
+    g_ACCController.Enable(tf);
   }
+  #endif // PP_AUTO_AMPACITY
   unsigned long GetResetMs();
 
   uint8_t SetMaxHwCurrentCapacity(uint8_t amps);
@@ -624,7 +628,7 @@ int GetHearbeatTrigger();
     eeprom_write_byte((uint8_t*)EOFS_STUCK_RELAY_TRIP_CNT,0xff);
   }
 #ifdef PP_AUTO_AMPACITY
-  void DoPPShorted();
+  void DoPPError(bool shorted);
 #endif // PP_AUTO_AMPACITY
 
 };
diff --git a/firmware/open_evse/Language_default.h b/firmware/open_evse/Language_default.h
index 699c9efe..affa7757 100644
--- a/firmware/open_evse/Language_default.h
+++ b/firmware/open_evse/Language_default.h
@@ -81,4 +81,6 @@
 #define STR_OVER_CURRENT "OVERCURRENT"
 #define STR_CABLE_FAULT "CABLE FAULT"
 #define STR_PP_SHORTED "PP SHORTED"
+#define STR_PP_MISSING "PP MISSING"
+
 //#endif
diff --git a/firmware/open_evse/main.cpp b/firmware/open_evse/main.cpp
index b1990c72..f994bfa3 100644
--- a/firmware/open_evse/main.cpp
+++ b/firmware/open_evse/main.cpp
@@ -671,6 +671,15 @@ void OnboardDisplay::Update(int8_t updmode)
       LcdSetBacklightColor(RED);
       LcdPrint_P(0,g_psCableFault);
       LcdPrint_P(1,g_psPPShorted);
+#endif
+      break;
+    case EVSE_STATE_PP_MISSING:
+      SetGreenLed(0);
+      SetRedLed(1);
+#ifdef LCD16X2 //Adafruit RGB LCD
+      LcdSetBacklightColor(RED);
+      LcdPrint_P(0,g_psCableFault);
+      LcdPrint_P(1,g_psPPMissing);
 #endif
       break;
 #endif // PP_AUTO_AMPACITY
@@ -2429,8 +2438,10 @@ void EvseReset()
 #endif  // DELAYTIMER
 
 #ifdef PP_AUTO_AMPACITY
+  g_ACCController.Enable(g_EvseController.PPAutoAmpacityIsEnabled());
+  Serial.println(g_ACCController.IsEnabled());
   if (g_ACCController.AutoSetCurrentCapacity() == 1) {
-    g_EvseController.DoPPShorted();
+    g_EvseController.DoPPError(true); // shorted
   }
 #endif
 }
@@ -2445,9 +2456,13 @@ uint8_t StateTransitionReqFunc(uint8_t curPilotState,uint8_t newPilotState,uint8
     // already debounces before requesting the state transition, so we can
     // be absolutely sure that the PP pin has firm contact by the time we
     // get here
-    if (g_ACCController.AutoSetCurrentCapacity() == 1) {
+    uint8_t ascret = g_ACCController.AutoSetCurrentCapacity();
+    if (ascret == 1) {
       retEvseState = EVSE_STATE_PP_SHORTED;
     }
+    else if (ascret == PP_AMPS_ABSENT) {
+      retEvseState = EVSE_STATE_PP_MISSING;
+    }
   }
   /*  else { // EVSE_STATE_A
     // reset back to default max current
diff --git a/firmware/targets/m328p/strings.cpp b/firmware/targets/m328p/strings.cpp
index e44777ac..95898c2f 100644
--- a/firmware/targets/m328p/strings.cpp
+++ b/firmware/targets/m328p/strings.cpp
@@ -126,4 +126,5 @@ const char g_psOverCurrent[] PROGMEM = STR_OVER_CURRENT;
 #ifdef PP_AUTO_AMPACITY
 const char g_psCableFault[] PROGMEM = STR_CABLE_FAULT;
 const char g_psPPShorted[] PROGMEM = STR_PP_SHORTED;
+const char g_psPPMissing[] PROGMEM = STR_PP_MISSING;
 #endif //PP_AUTO_AMPACITY
diff --git a/firmware/targets/m328p/strings.h b/firmware/targets/m328p/strings.h
index ad2c54ac..195ae5f8 100644
--- a/firmware/targets/m328p/strings.h
+++ b/firmware/targets/m328p/strings.h
@@ -131,4 +131,5 @@ extern const char g_psOverCurrent[] PROGMEM;
 #ifdef PP_AUTO_AMPACITY
 extern const char g_psCableFault[] PROGMEM;
 extern const char g_psPPShorted[] PROGMEM;
+extern const char g_psPPMissing[] PROGMEM;
 #endif //PP_AUTO_AMPACITY

From c39a757a7de0d477e8c60cc2b968cbb6e9378d7e Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Fri, 29 May 2026 16:52:23 -0700
Subject: [PATCH 47/59] add n.b. regarding #ifndef PLATFORMIO

---
 firmware/open_evse/open_evse.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index 03b72f0a..8246c3c5 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -62,6 +62,10 @@ extern bool g_hasCGMI;
 //-- begin features
 
 #ifndef PLATFORMIO
+//
+// n.b. the items in this block are active only when building w/ Arduino IDE
+// when using PlatformIO, all features must be configured via platformio.ini
+//
 //#define OCPP
 // support V6 hardware
 #define OEV6

From a963f2e16172dbe649cc8db05efbb6fbf5a38960 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Fri, 29 May 2026 16:52:40 -0700
Subject: [PATCH 48/59] refactor platformio.ini

---
 firmware/targets/m328p/platformio.ini | 33 +++++++++++++++++----------
 platformio.ini                        |  2 +-
 2 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/firmware/targets/m328p/platformio.ini b/firmware/targets/m328p/platformio.ini
index 5a449527..2d4d82b4 100644
--- a/firmware/targets/m328p/platformio.ini
+++ b/firmware/targets/m328p/platformio.ini
@@ -15,8 +15,8 @@ build_src_filter =
   ${common.build_src_filter}
   +<../targets/m328p>
 
-# autodetect V5/6 and CGMI
-[env:m328p_autodetect]
+ # WiFi with TFT
+[env:m328p_TFT_WIFI]
 platform = atmelavr@3.4.0
 board = openevse
 framework = arduino
@@ -27,28 +27,37 @@ build_src_filter =
   ${m328p.build_src_filter}
 build_src_flags=
   ${m328p.build_src_flags}
- -D 'VERSION="${common.version}"'
+  -D AUTOSVCLEVEL
+  -D 'VERSION="${common.version}.TFTWIFI"'
 
- # v5/ v6 and CGMI plus legacy RTC LCD BTN
-[env:m328p_RTC_BTN_LCD]
-extends = env:m328p_autodetect
+ # WiFi with LCD
+[env:m328p_LCD_WIFI]
+extends = env:m328p_TFT_WIFI
 platform = atmelavr@3.4.0
 board = openevse
 framework = arduino
 build_src_flags=
   ${m328p.build_src_flags}
-  -D AUTOSVCLEVEL
+  -D RGBLCD
+  -D 'VERSION="${common.version}.LCDWIFI"'
+
+ # legacy RTC LCD BTN no WiFi
+[env:m328p_noWiFi_RTC_BTN_LCD]
+extends = env:m328p_LCD_WIFI
+platform = atmelavr@3.4.0
+board = openevse
+framework = arduino
+build_src_flags=
+  ${m328p.build_src_flags}
+  -UHEARTBEAT_SUPERVISION
+  -UBOOTLOCK
   -D BTN_MENU
   -D HAVE_RTC
   -D DELAY_TIMER
   -D RGBLCD
   -D CHARGE_LIMIT
   -D TIME_LIMIT
-  -D TEMPERATURE_THROTTLING
-  -D 'VERSION="${common.version}.RTCRGBLCD"'
-
-
-
+  -D 'VERSION="${common.version}.noWIFI"'
    
 
 
diff --git a/platformio.ini b/platformio.ini
index 0b96aa36..29ed8fd1 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -31,7 +31,7 @@ build_flags =
   -D PP_AUTO_AMPACITY
   -D BOOTLOCK
   -D HEARTBEAT_SUPERVISION
-  -D NO_AUTOSVCLEVEL
+  -D TEMPERATURE_THROTTLING
   -D DEFAULT_SERVICE_LEVEL=2
   -D DEFAULT_CURRENT_CAPACITY_L2=24
   -D MAX_CURRENT_CAPACITY_L2=80

From 2577bd40ca2bf283be9142287537d8b8bce5cc86 Mon Sep 17 00:00:00 2001
From: lincomatic <lincomatic@hotmail.com>
Date: Fri, 29 May 2026 16:52:53 -0700
Subject: [PATCH 49/59] update CHANGELOG

---
 firmware/CHANGELOG | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/firmware/CHANGELOG b/firmware/CHANGELOG
index 60d514dd..e6bcb64e 100644
--- a/firmware/CHANGELOG
+++ b/firmware/CHANGELOG
@@ -1,6 +1,16 @@
 Change Log
 
-20260527 SCL
+
+20260528-29 SCL vD9.0.1
+- m328p: since A6 is floating in v1-5, read it 5x and use its statistical mode
+	when detecting board type
+- added ECF_PP_AUTO_AMPACITY - when set, PP ampacity detection is enabled
+  -> added RAPI command $FF P 0|1 to enable disable PP detection
+- added EVSE_STATE_PP_MISSING - cable is missing PP resistor
+     -> detected only on transition to state B/C
+     -> LCD: CABLE FAULT/PP SHORTED
+
+20260527 SCL vD9.0.0
 - get rid of old V6 detection code (and INVERT_V6_DETECTION)
   -> new globals g_isV6 and g_hasCGMI initialized in initTarget()
 - PP

From 04148c6755c6098739c4ef4b7d6c98f29d130360 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sat, 30 May 2026 16:53:20 -0400
Subject: [PATCH 50/59] Add UF2 bootloader build, firmware UF2 conversion, and
 Atmel-ICE bootloader upload

- Copy uf2-samdx1 bootloader source into repo (SAMD21/OpenEVSE_NXT board)
- Add PlatformIO pre-build extra_script (build_bootloader.py) that compiles the
  bootloader using PlatformIO's own arm-none-eabi toolchain (no make required),
  copies the .bin to the PlatformIO build dir, and converts firmware.bin to .uf2
- Add post-upload extra_script (upload_bootloader.py) for env:samd_ice that
  flashes the bootloader to 0x0 via Atmel-ICE after the firmware upload
- Update GitHub Actions: fix renamed m328p env names, upload firmware.uf2 and
  bootloader-*.bin as artifacts, add *.uf2 to release assets
- Fix env names throughout: m328p_autodetect -> m328p_TFT_WIFI,
  m328p_RTC_BTN_LCD -> m328p_noWiFi_RTC_BTN_LCD

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 .github/workflows/build_platformio.yml        |    23 +-
 .github/workflows/release.yml                 |    11 +-
 firmware/targets/m328p/platformio.ini         |    18 +-
 firmware/targets/samd/build_bootloader.py     |   249 +
 firmware/targets/samd/platformio.ini          |     6 +-
 firmware/targets/samd/upload_bootloader.py    |    71 +
 prepare-release.sh                            |     8 +-
 uf2-samdx1/.clang-format                      |     5 +
 uf2-samdx1/.gdbinit                           |     1 +
 uf2-samdx1/.gitattributes                     |    29 +
 uf2-samdx1/.github/workflows/ci.yml           |    38 +
 uf2-samdx1/.gitignore                         |    38 +
 uf2-samdx1/.gitignore.bk                      |    10 +
 uf2-samdx1/.gitmodules                        |     3 +
 uf2-samdx1/LICENSE                            |    60 +
 uf2-samdx1/Makefile                           |   242 +
 uf2-samdx1/README.md                          |   199 +
 uf2-samdx1/THIRD-PARTY-NOTICES.txt            |   161 +
 uf2-samdx1/bin-README.md                      |    79 +
 uf2-samdx1/boards/OpenEVSE_NXT/board.mk       |     2 +
 uf2-samdx1/boards/OpenEVSE_NXT/board_config.h |    15 +
 uf2-samdx1/inc/cdc_enumerate.h                |   140 +
 uf2-samdx1/inc/configkeys.h                   |   149 +
 uf2-samdx1/inc/main.h                         |    46 +
 uf2-samdx1/inc/neopixel.h                     |    92 +
 uf2-samdx1/inc/preprocessor/mrecursion.h      |   581 +
 uf2-samdx1/inc/preprocessor/mrepeat.h         |   321 +
 uf2-samdx1/inc/preprocessor/preprocessor.h    |    38 +
 uf2-samdx1/inc/preprocessor/stringz.h         |    67 +
 uf2-samdx1/inc/preprocessor/tpaste.h          |    85 +
 uf2-samdx1/inc/sam_ba_monitor.h               |    69 +
 uf2-samdx1/inc/uart_driver.h                  |   107 +
 uf2-samdx1/inc/uf2.h                          |   369 +
 uf2-samdx1/inc/uf2format.h                    |   120 +
 uf2-samdx1/inc/uf2hid.h                       |   107 +
 uf2-samdx1/inc/usart_sam_ba.h                 |   158 +
 uf2-samdx1/lib/README.txt                     |     8 +
 uf2-samdx1/lib/cmsis/ARM.CMSIS.pdsc           |  1340 ++
 .../CMSIS_END_USER_LICENCE_AGREEMENT.pdf      |   Bin 0 -> 172641 bytes
 .../CMSIS_END_USER_LICENCE_AGREEMENT.rtf      |   793 +
 .../Driver/DriverTemplates/Driver_ETH_MAC.c   |   189 +
 .../Driver/DriverTemplates/Driver_ETH_PHY.c   |   119 +
 .../Driver/DriverTemplates/Driver_Flash.c     |   111 +
 .../CMSIS/Driver/DriverTemplates/Driver_I2C.c |   133 +
 .../CMSIS/Driver/DriverTemplates/Driver_MCI.c |   206 +
 .../CMSIS/Driver/DriverTemplates/Driver_SPI.c |   138 +
 .../Driver/DriverTemplates/Driver_USART.c     |   108 +
 .../Driver/DriverTemplates/Driver_USBD.c      |   144 +
 .../Driver/DriverTemplates/Driver_USBH.c      |   193 +
 .../CMSIS/Driver/Include/Driver_Common.h      |    72 +
 .../cmsis/CMSIS/Driver/Include/Driver_ETH.h   |    85 +
 .../CMSIS/Driver/Include/Driver_ETH_MAC.h     |   301 +
 .../CMSIS/Driver/Include/Driver_ETH_PHY.h     |   133 +
 .../cmsis/CMSIS/Driver/Include/Driver_Flash.h |   194 +
 .../cmsis/CMSIS/Driver/Include/Driver_I2C.h   |   207 +
 .../cmsis/CMSIS/Driver/Include/Driver_MCI.h   |   350 +
 .../cmsis/CMSIS/Driver/Include/Driver_NAND.h  |   403 +
 .../cmsis/CMSIS/Driver/Include/Driver_SPI.h   |   237 +
 .../cmsis/CMSIS/Driver/Include/Driver_USART.h |   328 +
 .../cmsis/CMSIS/Driver/Include/Driver_USB.h   |    95 +
 .../cmsis/CMSIS/Driver/Include/Driver_USBD.h  |   263 +
 .../cmsis/CMSIS/Driver/Include/Driver_USBH.h  |   406 +
 .../cmsis/CMSIS/Include/arm_common_tables.h   |   136 +
 .../cmsis/CMSIS/Include/arm_const_structs.h   |    79 +
 uf2-samdx1/lib/cmsis/CMSIS/Include/arm_math.h |  7544 ++++++
 uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm0.h |   711 +
 .../lib/cmsis/CMSIS/Include/core_cm0plus.h    |   822 +
 uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm3.h |  1650 ++
 uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm4.h |  1802 ++
 uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm7.h |  2221 ++
 .../lib/cmsis/CMSIS/Include/core_cmFunc.h     |   638 +
 .../lib/cmsis/CMSIS/Include/core_cmInstr.h    |   880 +
 .../lib/cmsis/CMSIS/Include/core_cmSimd.h     |   697 +
 .../lib/cmsis/CMSIS/Include/core_sc000.h      |   842 +
 .../lib/cmsis/CMSIS/Include/core_sc300.h      |  1630 ++
 uf2-samdx1/lib/cmsis/CMSIS/README.txt         |    42 +
 uf2-samdx1/lib/cmsis/CMSIS/index.html         |    14 +
 uf2-samdx1/lib/samd21/Atmel.SAMD21_DFP.pdsc   |  6324 +++++
 uf2-samdx1/lib/samd21/package.content         |  1722 ++
 .../Device/SAMD21/Source/ARM/startup_SAMD21.s |   247 +
 .../Device/SAMD21/Source/system_samd21.c      |    78 +
 .../lib/samd21/samd21a/atdf/ATSAMD21E15A.atdf |  4997 ++++
 .../lib/samd21/samd21a/atdf/ATSAMD21E16A.atdf |  4997 ++++
 .../lib/samd21/samd21a/atdf/ATSAMD21E17A.atdf |  4997 ++++
 .../lib/samd21/samd21a/atdf/ATSAMD21E18A.atdf |  4997 ++++
 .../lib/samd21/samd21a/atdf/ATSAMD21G15A.atdf |  5086 ++++
 .../lib/samd21/samd21a/atdf/ATSAMD21G16A.atdf |  5086 ++++
 .../lib/samd21/samd21a/atdf/ATSAMD21G17A.atdf |  5086 ++++
 .../samd21/samd21a/atdf/ATSAMD21G17AU.atdf    |  5106 ++++
 .../lib/samd21/samd21a/atdf/ATSAMD21G18A.atdf |  5086 ++++
 .../samd21/samd21a/atdf/ATSAMD21G18AU.atdf    |  5106 ++++
 .../lib/samd21/samd21a/atdf/ATSAMD21J15A.atdf |  5227 +++++
 .../lib/samd21/samd21a/atdf/ATSAMD21J16A.atdf |  5294 +++++
 .../lib/samd21/samd21a/atdf/ATSAMD21J17A.atdf |  5294 +++++
 .../lib/samd21/samd21a/atdf/ATSAMD21J18A.atdf |  5294 +++++
 .../config/debugger/Atmel/ATSAMD21E15A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21E16A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21E17A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21E18A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21G15A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21G16A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21G17A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21G17AU.ddf   |    25 +
 .../config/debugger/Atmel/ATSAMD21G18A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21G18AU.ddf   |    25 +
 .../config/debugger/Atmel/ATSAMD21J15A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21J16A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21J17A.ddf    |    25 +
 .../config/debugger/Atmel/ATSAMD21J18A.ddf    |    25 +
 .../config/debugger/Atmel/Trace_SAMD21.dmac   |    78 +
 .../devices/Atmel/ATSAMD21/ATSAMD21E15A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21E15A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21E16A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21E16A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21E17A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21E17A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21E18A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21E18A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G15A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G15A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G16A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G16A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G17A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G17A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G17AU.i79  |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G17AU.menu |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G18A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G18A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G18AU.i79  |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21G18AU.menu |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21J15A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21J15A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21J16A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21J16A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21J17A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21J17A.menu  |     7 +
 .../devices/Atmel/ATSAMD21/ATSAMD21J18A.i79   |    41 +
 .../devices/Atmel/ATSAMD21/ATSAMD21J18A.menu  |     7 +
 .../Atmel/samd21e15a/samd21e15a-flash.board   |     9 +
 .../Atmel/samd21e15a/samd21e15a-flash.flash   |    13 +
 .../Atmel/samd21e15a/samd21e15a-flash.out     |   Bin 0 -> 32040 bytes
 .../Atmel/samd21e16a/samd21e16a-flash.board   |     9 +
 .../Atmel/samd21e16a/samd21e16a-flash.flash   |    13 +
 .../Atmel/samd21e16a/samd21e16a-flash.out     |   Bin 0 -> 32040 bytes
 .../Atmel/samd21e17a/samd21e17a-flash.board   |     9 +
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 .../Atmel/samd21e17a/samd21e17a-flash.out     |   Bin 0 -> 32172 bytes
 .../Atmel/samd21e18a/samd21e18a-flash.board   |     9 +
 .../Atmel/samd21e18a/samd21e18a-flash.flash   |    13 +
 .../Atmel/samd21e18a/samd21e18a-flash.out     |   Bin 0 -> 32172 bytes
 .../Atmel/samd21g15a/samd21g15a-flash.board   |     9 +
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 .../Atmel/samd21g15a/samd21g15a-flash.out     |   Bin 0 -> 32040 bytes
 .../Atmel/samd21g16a/samd21g16a-flash.board   |     9 +
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 .../Atmel/samd21g17a/samd21g17a-flash.board   |     9 +
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 .../Atmel/samd21g17a/samd21g17a-flash.out     |   Bin 0 -> 32172 bytes
 .../Atmel/samd21g17au/samd21g17au-flash.board |     9 +
 .../Atmel/samd21g17au/samd21g17au-flash.flash |    13 +
 .../Atmel/samd21g17au/samd21g17au-flash.out   |   Bin 0 -> 32172 bytes
 .../Atmel/samd21g18a/samd21g18a-flash.board   |     9 +
 .../Atmel/samd21g18a/samd21g18a-flash.flash   |    13 +
 .../Atmel/samd21g18a/samd21g18a-flash.out     |   Bin 0 -> 32172 bytes
 .../Atmel/samd21g18au/samd21g18au-flash.board |     9 +
 .../Atmel/samd21g18au/samd21g18au-flash.flash |    13 +
 .../Atmel/samd21g18au/samd21g18au-flash.out   |   Bin 0 -> 32172 bytes
 .../Atmel/samd21j15a/samd21j15a-flash.board   |     9 +
 .../Atmel/samd21j15a/samd21j15a-flash.flash   |    13 +
 .../Atmel/samd21j15a/samd21j15a-flash.out     |   Bin 0 -> 32040 bytes
 .../Atmel/samd21j16a/samd21j16a-flash.board   |     9 +
 .../Atmel/samd21j16a/samd21j16a-flash.flash   |    13 +
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 .../Atmel/samd21j17a/samd21j17a-flash.board   |     9 +
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 .../Atmel/samd21j18a/samd21j18a-flash.board   |     9 +
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 .../Atmel/samd21j18a/samd21j18a-flash.out     |   Bin 0 -> 32172 bytes
 .../samd21a/iar/iar/samd21e15a_flash.icf      |    61 +
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 .../samd21/samd21a/include/component/adc.h    |   684 +
 .../samd21/samd21a/include/component/dac.h    |   271 +
 .../samd21/samd21a/include/component/dmac.h   |  1072 +
 .../samd21/samd21a/include/component/dsu.h    |   536 +
 .../samd21/samd21a/include/component/eic.h    |   666 +
 .../samd21/samd21a/include/component/evsys.h  |   589 +
 .../samd21/samd21a/include/component/gclk.h   |   295 +
 .../samd21a/include/component/hmatrixb.h      |   103 +
 .../samd21/samd21a/include/component/i2s.h    |   624 +
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 .../samd21/samd21a/include/component/pac.h    |    89 +
 .../lib/samd21/samd21a/include/component/pm.h |   518 +
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 .../samd21/samd21a/include/component/rtc.h    |  1053 +
 .../samd21/samd21a/include/component/sercom.h |  1493 ++
 .../samd21a/include/component/sysctrl.h       |   933 +
 .../lib/samd21/samd21a/include/component/tc.h |   669 +
 .../samd21/samd21a/include/component/tcc.h    |  1802 ++
 .../samd21/samd21a/include/component/usb.h    |  1790 ++
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 .../samd21/samd21a/include/instance/nvmctrl.h |    76 +
 .../samd21/samd21a/include/instance/pac0.h    |    44 +
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 .../samd21/samd21a/include/instance/sercom3.h |   128 +
 .../samd21/samd21a/include/instance/sercom4.h |   128 +
 .../samd21/samd21a/include/instance/sercom5.h |   128 +
 .../samd21/samd21a/include/instance/sysctrl.h |   106 +
 .../lib/samd21/samd21a/include/instance/tc3.h |    96 +
 .../lib/samd21/samd21a/include/instance/tc4.h |    96 +
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 .../lib/samd21/samd21a/include/instance/tc6.h |    96 +
 .../lib/samd21/samd21a/include/instance/tc7.h |    96 +
 .../samd21/samd21a/include/instance/tcc0.h    |   116 +
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 uf2-samdx1/lib/samd21/samd21a/include/sam.h   |    64 +
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 .../samd21/samd21a/include/system_samd21.h    |    47 +
 .../samd21a/keil/Flash/ATSAMD21_128.FLM       |   Bin 0 -> 12652 bytes
 .../samd21a/keil/Flash/ATSAMD21_256.FLM       |   Bin 0 -> 12652 bytes
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 .../lib/samd21/samd21a/svd/ATSAMD21E15A.svd   | 19401 +++++++++++++++
 .../lib/samd21/samd21a/svd/ATSAMD21E16A.svd   | 19401 +++++++++++++++
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 uf2-samdx1/lib/uf2/uf2tool/tool.c             |   359 +
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 uf2-samdx1/src/usart_sam_ba.c                 |   505 +
 uf2-samdx1/src/utils.c                        |   263 +
 449 files changed, 449174 insertions(+), 25 deletions(-)
 create mode 100644 firmware/targets/samd/build_bootloader.py
 create mode 100644 firmware/targets/samd/upload_bootloader.py
 create mode 100644 uf2-samdx1/.clang-format
 create mode 100644 uf2-samdx1/.gdbinit
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 create mode 100644 uf2-samdx1/.github/workflows/ci.yml
 create mode 100644 uf2-samdx1/.gitignore
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 create mode 100644 uf2-samdx1/LICENSE
 create mode 100644 uf2-samdx1/Makefile
 create mode 100644 uf2-samdx1/README.md
 create mode 100644 uf2-samdx1/THIRD-PARTY-NOTICES.txt
 create mode 100644 uf2-samdx1/bin-README.md
 create mode 100644 uf2-samdx1/boards/OpenEVSE_NXT/board.mk
 create mode 100644 uf2-samdx1/boards/OpenEVSE_NXT/board_config.h
 create mode 100644 uf2-samdx1/inc/cdc_enumerate.h
 create mode 100644 uf2-samdx1/inc/configkeys.h
 create mode 100644 uf2-samdx1/inc/main.h
 create mode 100644 uf2-samdx1/inc/neopixel.h
 create mode 100644 uf2-samdx1/inc/preprocessor/mrecursion.h
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 create mode 100644 uf2-samdx1/inc/sam_ba_monitor.h
 create mode 100644 uf2-samdx1/inc/uart_driver.h
 create mode 100644 uf2-samdx1/inc/uf2.h
 create mode 100644 uf2-samdx1/inc/uf2format.h
 create mode 100644 uf2-samdx1/inc/uf2hid.h
 create mode 100644 uf2-samdx1/inc/usart_sam_ba.h
 create mode 100644 uf2-samdx1/lib/README.txt
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diff --git a/.github/workflows/build_platformio.yml b/.github/workflows/build_platformio.yml
index 53b95723..c00e3b31 100644
--- a/.github/workflows/build_platformio.yml
+++ b/.github/workflows/build_platformio.yml
@@ -12,12 +12,12 @@ jobs:
       fail-fast: false
       matrix:
         include:
-          - env: m328p_autodetect
+          - env: m328p_TFT_WIFI
             python: 3.x
             platformio: 6.1.5
             arch: avr
             artifact: firmware.hex
-          - env: m328p_RTC_BTN_LCD
+          - env: m328p_noWiFi_RTC_BTN_LCD
             python: 3.x
             platformio: 6.1.5
             arch: avr
@@ -26,7 +26,6 @@ jobs:
             python: 3.x
             platformio: 6.1.5
             arch: samd
-            artifact: firmware.bin
 
     steps:
     - uses: actions/checkout@v5
@@ -74,19 +73,33 @@ jobs:
       if: matrix.arch == 'samd'
       run: |
         BIN_SIZE=$(ls -l .pio/build/${{ matrix.env }}/firmware.bin | awk '{ print $5 }')
+        UF2_SIZE=$(ls -l .pio/build/${{ matrix.env }}/firmware.uf2 | awk '{ print $5 }')
         cat <<EOF >info.json
         {
           "name": "${{ matrix.env }}",
           "built_tool": "Platform IO",
           "arch": "samd",
-          "bin_size": $BIN_SIZE
+          "bin_size": $BIN_SIZE,
+          "uf2_size": $UF2_SIZE
         }
         EOF
 
-    - name: Upload output to GitHub
+    - name: Upload output to GitHub (AVR)
+      if: matrix.arch == 'avr'
       uses: actions/upload-artifact@v6
       with:
         name: ${{ matrix.env }}
         path: |
           .pio/build/${{ matrix.env }}/${{ matrix.artifact }}
           info.json
+
+    - name: Upload output to GitHub (SAMD)
+      if: matrix.arch == 'samd'
+      uses: actions/upload-artifact@v6
+      with:
+        name: ${{ matrix.env }}
+        path: |
+          .pio/build/${{ matrix.env }}/firmware.bin
+          .pio/build/${{ matrix.env }}/firmware.uf2
+          .pio/build/${{ matrix.env }}/bootloader-*.bin
+          info.json
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml
index 233d0454..a8c5ae4e 100644
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -19,14 +19,20 @@ jobs:
 
     - name: Rename images to something more sensible
       run: |
-        for ext in hex bin; do
-          find artifacts -name "*.$ext" | while read -r image; do
+        # Rename firmware outputs: firmware.{hex,bin,uf2} -> <board>.{hex,bin,uf2}
+        for ext in hex bin uf2; do
+          find artifacts -name "firmware.$ext" | while read -r image; do
             dir=$(dirname "${image}")
             board=$(basename "${dir}")
             echo mv "$image" "$board.$ext"
             mv "$image" "$board.$ext"
           done
         done
+        # Move bootloader binaries to the top level keeping their descriptive name
+        find artifacts -name "bootloader-*.bin" | while read -r image; do
+          echo mv "$image" "$(basename "$image")"
+          mv "$image" "$(basename "$image")"
+        done
         jq -s . $(find -name info.json) > build_info.json
         jq -r '(map(keys) | add | unique) as $cols | map(. as $row | $cols | map($row[.])) as $rows | $cols, $rows[] | @csv' build_info.json > build_info.csv
 
@@ -40,5 +46,6 @@ jobs:
         files: |
           *.hex
           *.bin
+          *.uf2
           build_info.json
           build_info.csv
diff --git a/firmware/targets/m328p/platformio.ini b/firmware/targets/m328p/platformio.ini
index 2d4d82b4..55b27e13 100644
--- a/firmware/targets/m328p/platformio.ini
+++ b/firmware/targets/m328p/platformio.ini
@@ -27,23 +27,14 @@ build_src_filter =
   ${m328p.build_src_filter}
 build_src_flags=
   ${m328p.build_src_flags}
-  -D AUTOSVCLEVEL
-  -D 'VERSION="${common.version}.TFTWIFI"'
+  # RGBLCD Minimal code for legacy LCD support, not used for TFT Removing can save 4Kb builds but needed for some shared code
+  -D RGBLCD 
+  -D 'VERSION="${common.version}"'
 
- # WiFi with LCD
-[env:m328p_LCD_WIFI]
-extends = env:m328p_TFT_WIFI
-platform = atmelavr@3.4.0
-board = openevse
-framework = arduino
-build_src_flags=
-  ${m328p.build_src_flags}
-  -D RGBLCD
-  -D 'VERSION="${common.version}.LCDWIFI"'
 
  # legacy RTC LCD BTN no WiFi
 [env:m328p_noWiFi_RTC_BTN_LCD]
-extends = env:m328p_LCD_WIFI
+extends = env:m328p_TFT_WIFI
 platform = atmelavr@3.4.0
 board = openevse
 framework = arduino
@@ -51,6 +42,7 @@ build_src_flags=
   ${m328p.build_src_flags}
   -UHEARTBEAT_SUPERVISION
   -UBOOTLOCK
+  -D AUTOSVCLEVEL
   -D BTN_MENU
   -D HAVE_RTC
   -D DELAY_TIMER
diff --git a/firmware/targets/samd/build_bootloader.py b/firmware/targets/samd/build_bootloader.py
new file mode 100644
index 00000000..a76a97a1
--- /dev/null
+++ b/firmware/targets/samd/build_bootloader.py
@@ -0,0 +1,249 @@
+"""
+PlatformIO extra_script for the OpenEVSE NXT SAMD21 build.
+
+Pre-build : compile the uf2-samdx1 bootloader using PlatformIO's own
+            arm-none-eabi toolchain (no external 'make' required).
+            Output: uf2-samdx1/build/OpenEVSE_NXT/bootloader-*.bin  (+.uf2)
+
+Post-build: convert the PlatformIO firmware binary to UF2 format so it can
+            be drag-and-drop flashed via the UF2 bootloader's USB drive.
+            Output: $BUILD_DIR/firmware.uf2
+
+The uf2-samdx1 directory must exist inside this project root.
+"""
+
+Import("env")  # noqa: F821 — SCons-injected global
+
+import shutil
+import subprocess
+import sys
+from pathlib import Path
+
+BOARD = "OpenEVSE_NXT"
+CHIP_VARIANT = "SAMD21G18A"
+BOOTLOADER_SIZE = 8192  # bytes — SAMD21 bootloader partition
+
+# Main bootloader sources (mirrors SOURCES in the Makefile)
+SOURCES = [
+    "src/flash_samd21.c",
+    "src/init_samd21.c",
+    "src/startup_samd21.c",
+    "src/usart_sam_ba.c",
+    "src/screen.c",
+    "src/images.c",
+    "src/utils.c",
+    "src/cdc_enumerate.c",
+    "src/fat.c",
+    "src/main.c",
+    "src/msc.c",
+    "src/sam_ba_monitor.c",
+    "src/uart_driver.c",
+    "src/hid.c",
+]
+
+
+def _run(cmd, cwd=None):
+    result = subprocess.run(
+        [str(c) for c in cmd],
+        capture_output=True, text=True, cwd=cwd
+    )
+    if result.returncode != 0:
+        print(f"\nFailed: {' '.join(str(c) for c in cmd)}")
+        if result.stdout:
+            print(result.stdout)
+        if result.stderr:
+            print(result.stderr)
+        raise RuntimeError(f"Exit code {result.returncode}")
+    return result.stdout.strip()
+
+
+def _needs_rebuild(output: Path, sources):
+    if not output.exists():
+        return True
+    out_mtime = output.stat().st_mtime
+    return any(s.exists() and s.stat().st_mtime > out_mtime for s in sources)
+
+
+def build_bootloader(source, target, env):
+    project_dir = Path(env.subst("$PROJECT_DIR"))
+    bl_dir = project_dir / "uf2-samdx1"
+    build_path = bl_dir / "build" / BOARD
+
+    if not bl_dir.exists():
+        print(f"WARNING: bootloader directory not found: {bl_dir}")
+        print("  Clone https://github.com/adafruit/uf2-samdx1 next to this project.")
+        return
+
+    # PlatformIO sets $CC to the full path of arm-none-eabi-gcc it installed.
+    cc = Path(env.subst("$CC"))
+    objcopy = cc.parent / "arm-none-eabi-objcopy"
+
+    # Version string from the bootloader repo's git history.
+    try:
+        version = _run(
+            ["git", "describe", "--dirty=+", "--always", "--tags"],
+            cwd=str(bl_dir),
+        )
+    except Exception:
+        version = "unknown"
+
+    name = f"bootloader-{BOARD}-{version}"
+    bin_path = build_path / f"{name}.bin"
+
+    # Rebuild check — same logic as make's file dependency tracking.
+    watch = (
+        list((bl_dir / "src").glob("*.c"))
+        + list((bl_dir / "inc").glob("**/*.h"))
+        + list((bl_dir / f"boards/{BOARD}").glob("*.h"))
+        + [bl_dir / "Makefile"]
+    )
+    if not _needs_rebuild(bin_path, watch):
+        print(f"Bootloader up to date: {bin_path.name}")
+        return
+
+    print(f"\n--- Building bootloader for {BOARD} ---")
+    build_path.mkdir(parents=True, exist_ok=True)
+
+    # Generate uf2_version.h (replaces the make rule that echo-writes the file).
+    (build_path / "uf2_version.h").write_text(
+        f'#define UF2_VERSION_BASE "{version}"\n'
+    )
+
+    common = ["-mthumb", "-mcpu=cortex-m0plus", "-Os", "-g", "-DSAMD21"]
+
+    cflags = common + [
+        "-x", "c", "-c", "-pipe", "-nostdlib",
+        "-fno-strict-aliasing", "-fdata-sections", "-ffunction-sections",
+        f"-D__{CHIP_VARIANT}__",
+        "-fno-jump-tables",
+        # Warning flags from the Makefile WFLAGS variable.
+        "-Werror", "-Wall", "-Wstrict-prototypes",
+        "-Werror-implicit-function-declaration", "-Wpointer-arith", "-std=gnu99",
+        "-Wchar-subscripts", "-Wcomment", "-Wformat=2",
+        "-Wimplicit-int", "-Wmain", "-Wparentheses", "-Wsequence-point",
+        "-Wreturn-type", "-Wswitch", "-Wtrigraphs", "-Wunused", "-Wuninitialized",
+        "-Wunknown-pragmas", "-Wfloat-equal", "-Wno-undef", "-Wbad-function-cast",
+        "-Wwrite-strings", "-Waggregate-return", "-Wmissing-format-attribute",
+        "-Wno-deprecated-declarations", "-Wpacked", "-Wredundant-decls",
+        "-Wnested-externs", "-Wlong-long", "-Wunreachable-code", "-Wcast-align",
+        "-Wno-missing-braces", "-Wno-overflow", "-Wno-shadow", "-Wno-attributes",
+        "-Wno-packed", "-Wno-pointer-sign",
+    ]
+
+    includes = [
+        f"-I{bl_dir}",
+        f"-I{bl_dir / 'inc'}",
+        f"-I{bl_dir / 'inc' / 'preprocessor'}",
+        f"-I{bl_dir / 'boards' / BOARD}",
+        f"-I{bl_dir / 'lib' / 'cmsis' / 'CMSIS' / 'Include'}",
+        f"-I{bl_dir / 'lib' / 'usb_msc'}",
+        f"-I{bl_dir / 'lib' / 'samd21' / 'samd21a' / 'include'}",
+        f"-I{build_path}",
+    ]
+
+    # Compile each source file.
+    objects = []
+    for src in SOURCES:
+        src_path = bl_dir / src
+        obj_path = build_path / (Path(src).stem + ".o")
+        try:
+            _run([cc] + cflags + includes + [src_path, "-o", obj_path])
+        except RuntimeError:
+            env.Exit(1)
+            return
+        objects.append(obj_path)
+
+    # Link.
+    elf_path = build_path / f"{name}.elf"
+    linker_script = bl_dir / "scripts" / "samd21j18a.ld"
+    map_path = build_path / f"{name}.map"
+
+    ldflags = common + [
+        "-Wall",
+        "-Wl,--cref", "-Wl,--check-sections", "-Wl,--gc-sections",
+        "-Wl,--unresolved-symbols=report-all", "-Wl,--warn-common",
+        "-Wl,--warn-section-align",
+        "-nostartfiles",
+        "--specs=nano.specs", "--specs=nosys.specs",
+        f"-L{build_path}",
+        f"-T{linker_script}",
+        f"-Wl,-Map,{map_path}",
+        "-o", elf_path,
+    ]
+
+    try:
+        _run([cc] + ldflags + objects, cwd=str(build_path))
+    except RuntimeError:
+        env.Exit(1)
+        return
+
+    # Produce the flat binary.
+    try:
+        _run([objcopy, "-O", "binary", elf_path, bin_path])
+    except RuntimeError:
+        env.Exit(1)
+        return
+
+    # Produce the self-update UF2 (optional — needs the uf2 submodule).
+    uf2conv = bl_dir / "lib" / "uf2" / "utils" / "uf2conv.py"
+    if uf2conv.exists():
+        uf2_path = build_path / f"update-{name}.uf2"
+        try:
+            _run([
+                sys.executable, str(uf2conv),
+                "-b", str(BOOTLOADER_SIZE), "-c",
+                "-o", str(uf2_path),
+                str(bin_path),
+            ])
+            print(f"  UF2 self-update : {uf2_path.name}")
+        except RuntimeError:
+            pass  # UF2 generation is nice-to-have, not required for flashing
+
+    # Copy bootloader .bin to the PlatformIO build directory alongside firmware.
+    build_dir = Path(env.subst("$BUILD_DIR"))
+    dest = build_dir / bin_path.name
+    build_dir.mkdir(parents=True, exist_ok=True)
+    shutil.copy2(bin_path, dest)
+
+    print(f"  Bootloader .bin : {bin_path.name}")
+    print(f"  Copied to       : {dest}")
+
+    # Clean the bootloader build tree now that the .bin is safely copied.
+    shutil.rmtree(build_path, ignore_errors=True)
+    print(f"  Cleaned         : {build_path}")
+    print(f"--- Bootloader build complete ---\n")
+
+
+def convert_firmware_to_uf2(source, target, env):
+    build_dir = Path(env.subst("$BUILD_DIR"))
+    prog_name = env.subst("$PROGNAME")
+    bin_path = build_dir / f"{prog_name}.bin"
+    uf2_path = build_dir / f"{prog_name}.uf2"
+
+    project_dir = Path(env.subst("$PROJECT_DIR"))
+    uf2conv = project_dir / "uf2-samdx1" / "lib" / "uf2" / "utils" / "uf2conv.py"
+
+    if not uf2conv.exists():
+        print(f"WARNING: uf2conv.py not found at {uf2conv}, skipping UF2 conversion")
+        return
+
+    print(f"\n--- Converting firmware to UF2 ---")
+    try:
+        # -b 0x2000 : application base address (after 8 KB SAMD21 bootloader)
+        # -f 0x68ed2b88 : SAMD21 family ID
+        # -c : convert only, do not flash
+        _run([
+            sys.executable, str(uf2conv),
+            "-b", "0x2000",
+            "-f", "0x68ed2b88",
+            "-c",
+            "-o", str(uf2_path),
+            str(bin_path),
+        ])
+        print(f"  Firmware UF2    : {uf2_path}")
+    except RuntimeError:
+        print("WARNING: UF2 conversion failed — .bin is still available for JLink/ICE flashing")
+
+
+env.AddPreAction("$BUILD_DIR/${PROGNAME}.elf", build_bootloader)
+env.AddPostAction("$BUILD_DIR/${PROGNAME}.bin", convert_firmware_to_uf2)
diff --git a/firmware/targets/samd/platformio.ini b/firmware/targets/samd/platformio.ini
index 87320309..aa1e7731 100644
--- a/firmware/targets/samd/platformio.ini
+++ b/firmware/targets/samd/platformio.ini
@@ -1,4 +1,5 @@
 [samd]
+extra_scripts = pre:firmware/targets/samd/build_bootloader.py
 lib_deps = ${common.lib_deps}
   https://github.com/lincomatic/Adafruit_SleepyDog.git
   https://github.com/sparkfun/SparkFun_External_EEPROM_Arduino_Library.git
@@ -19,7 +20,7 @@ framework = arduino
 board = zeroUSB
 build_type = release
 monitor_speed=115200
-;extra_scripts = ${samd.extra_scripts}
+extra_scripts = ${samd.extra_scripts}
 lib_deps = ${samd.lib_deps}
 build_src_filter =
   ${samd.build_src_filter}
@@ -33,6 +34,9 @@ build_src_flags=
 extends = env:samd
 upload_protocol = atmel-ice
 build_type = release
+extra_scripts =
+  ${samd.extra_scripts}
+  post:firmware/targets/samd/upload_bootloader.py
 
 [env:samd_ice_dev] ; don't use this.. for dev/debug only
 extends = env:samd
diff --git a/firmware/targets/samd/upload_bootloader.py b/firmware/targets/samd/upload_bootloader.py
new file mode 100644
index 00000000..3ccf936c
--- /dev/null
+++ b/firmware/targets/samd/upload_bootloader.py
@@ -0,0 +1,71 @@
+"""
+PlatformIO post-upload extra_script: after flashing firmware, also flash the
+bootloader binary to address 0x0 via the same Atmel-ICE / OpenOCD session.
+
+Reuses PlatformIO's UPLOADER and UPLOADERFLAGS (correct interface cfg, target
+cfg, script paths, speed).  The flags are kept as a list the whole time so that
+multi-word -c arguments (e.g. "set CHIPNAME at91samd21g18") are never split by
+shell parsing — that was the cause of the "Unexpected command line argument:
+CHIPNAME" error when they were joined into a flat string.
+
+Only the -c argument that contains 'program' is replaced; all other flags
+(scripts dir, interface, target, CHIPNAME setup, etc.) are passed through
+unchanged.
+"""
+
+Import("env")  # noqa: F821 — SCons-injected global
+
+import subprocess
+from pathlib import Path
+
+
+def upload_bootloader_ice(source, target, env):
+    build_dir = Path(env.subst("$BUILD_DIR"))
+
+    bl_bins = sorted(build_dir.glob("bootloader-*.bin"))
+    if not bl_bins:
+        print("WARNING: No bootloader-*.bin found in build dir — run a full build first")
+        return
+    bl_bin = bl_bins[0]
+
+    # Forward slashes required inside OpenOCD's { } program argument on all OSes.
+    bl_str = str(bl_bin).replace("\\", "/")
+
+    uploader = env.subst("$UPLOADER")
+
+    # Resolve each flag element individually (they may be SCons nodes or contain
+    # unexpanded variables like $SOURCE).  env.Flatten() handles nested lists.
+    raw_flags = [env.subst(str(f)) for f in env.Flatten(env["UPLOADERFLAGS"])]
+
+    # Walk the flag list and swap out only the -c argument whose value contains
+    # 'program'.  Every other flag is kept verbatim so PlatformIO's interface /
+    # target / CHIPNAME configuration is preserved.
+    new_flags = []
+    i = 0
+    while i < len(raw_flags):
+        if raw_flags[i] == "-c" and i + 1 < len(raw_flags) and "program" in raw_flags[i + 1]:
+            new_flags += [
+                "-c",
+                f"telnet_port disabled; program {{{bl_str}}} 0x0 verify reset; shutdown;",
+            ]
+            i += 2
+        else:
+            new_flags.append(raw_flags[i])
+            i += 1
+
+    cmd = [uploader] + new_flags
+
+    print(f"\n--- Uploading bootloader via Atmel-ICE ---")
+    print(f"  {bl_bin.name}  →  0x0")
+    result = subprocess.run(cmd, capture_output=True, text=True)
+    if result.stdout:
+        print(result.stdout)
+    if result.returncode != 0:
+        if result.stderr:
+            print(result.stderr)
+        print("ERROR: Bootloader upload failed")
+    else:
+        print("--- Bootloader upload complete ---\n")
+
+
+env.AddPostAction("upload", upload_bootloader_ice)
diff --git a/prepare-release.sh b/prepare-release.sh
index e97ec9b0..b778c035 100755
--- a/prepare-release.sh
+++ b/prepare-release.sh
@@ -4,11 +4,11 @@
 
 mkdir -p firmware/targets
 
-pio run -e m328p_autodetect
-cp .pio/build/m328p_v6/firmware.hex firmware/targets/m328p_openevse.hex
+pio run -e m328p_noWiFi_RTC_BTN_LCD
+cp .pio/build/m328p_noWiFi_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_noWiFi.hex
 
-pio run -e m328p_RTC_BTN_LCD
-cp .pio/build/m328p_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_RTC_BTN_LCD.hex
+pio run -e m328p_TFT_WIFI
+cp .pio/build/m328p_TFT_WIFI/firmware.hex firmware/targets/m328p_openevse.hex
 
 pio run -e samd
 cp .pio/build/samd_us/firmware.bin firmware/targets/arm_samd_openevse_nxt.bin
diff --git a/uf2-samdx1/.clang-format b/uf2-samdx1/.clang-format
new file mode 100644
index 00000000..e1f3d46e
--- /dev/null
+++ b/uf2-samdx1/.clang-format
@@ -0,0 +1,5 @@
+BasedOnStyle: LLVM
+IndentWidth: 4
+UseTab: Never
+ColumnLimit: 100
+SortIncludes: false
diff --git a/uf2-samdx1/.gdbinit b/uf2-samdx1/.gdbinit
new file mode 100644
index 00000000..782c767c
--- /dev/null
+++ b/uf2-samdx1/.gdbinit
@@ -0,0 +1 @@
+target extended-remote localhost:3333
diff --git a/uf2-samdx1/.gitattributes b/uf2-samdx1/.gitattributes
new file mode 100644
index 00000000..94ef06d4
--- /dev/null
+++ b/uf2-samdx1/.gitattributes
@@ -0,0 +1,29 @@
+# enforce unix style line endings
+*.ts text eol=lf
+*.tsx text eol=lf
+*.md text eol=lf
+*.txt text eol=lf
+*.js text eol=lf
+*.json text eol=lf
+*.xml text eol=lf
+*.svg text eol=lf
+*.yaml text eol=lf
+*.css text eol=lf
+*.html text eol=lf
+*.py text eol=lf
+*.exp text eol=lf
+*.manifest text eol=lf
+*.cpp text eol=lf
+*.c text eol=lf
+*.h text eol=lf
+*.hpp text eol=lf
+*.sh text eol=lf
+Makefile text eol=lf
+
+# do not enforce text for everything - it causes issues with random binary files
+
+*.sln text eol=crlf
+
+*.png binary
+*.jpg binary
+*.jpeg binary
diff --git a/uf2-samdx1/.github/workflows/ci.yml b/uf2-samdx1/.github/workflows/ci.yml
new file mode 100644
index 00000000..a91e7b5e
--- /dev/null
+++ b/uf2-samdx1/.github/workflows/ci.yml
@@ -0,0 +1,38 @@
+name: Build CI
+
+on:
+  push:
+  pull_request:
+  release:
+    types: [published]
+
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+    - name: Set up repository
+      uses: actions/checkout@v6
+      with:
+        fetch-depth: 0
+        filter: "blob:none"
+        show-progress: false
+        submodules: false
+    - name: Set up compiler
+      uses: carlosperate/arm-none-eabi-gcc-action@v1
+      with:
+        # When changing this update what Windows grabs too!
+        release: '14.3.Rel1'
+    - name: Extract version identifier
+      run: |
+        echo >> $GITHUB_ENV "UF2_VERSION_BASE=`git describe --dirty --always --tags`"
+    - name: Build
+      run: make submodules && make -j$(nproc) all-boards && mv build/drop build/uf2-samdx1-$UF2_VERSION_BASE
+    - name: Upload artifact
+      uses: actions/upload-artifact@v4
+      with:
+        path: build/uf2-samdx1-${{ env.UF2_VERSION_BASE }}/*
+        name: uf2-samdx1-${{ env.UF2_VERSION_BASE }}
diff --git a/uf2-samdx1/.gitignore b/uf2-samdx1/.gitignore
new file mode 100644
index 00000000..61a1f31a
--- /dev/null
+++ b/uf2-samdx1/.gitignore
@@ -0,0 +1,38 @@
+build/
+.vs/
+uf2-bootloader.elf
+tmp
+*.sw?
+Makefile.user
+node_modules
+scripts/clean-ifaces/*.plist
+.vscode/c_cpp_properties.json
+TAGS
+dist
+
+# CMSIS — only CMSIS/Include/ is needed for compilation
+lib/cmsis/CMSIS/Lib/
+lib/cmsis/CMSIS/Documentation/
+lib/cmsis/CMSIS/DSP_Lib/
+lib/cmsis/CMSIS/Pack/
+lib/cmsis/CMSIS/RTOS/
+lib/cmsis/CMSIS/SVD/
+lib/cmsis/CMSIS/Utilities/
+lib/cmsis/CMSIS/UserCodeTemplates/
+lib/cmsis/CMSIS_RTX/
+lib/cmsis/Device/
+
+# Unused chip-family libraries (OpenEVSE NXT is SAMD21 only)
+lib/samd51/
+lib/same51/
+lib/same54/
+
+# samd21 — only samd21a/include/ is used
+lib/samd21/samd21a/gcc/
+lib/samd21/samd21a/license/
+lib/samd21/samd21b/
+lib/samd21/samd21c/
+lib/samd21/samd21d/
+lib/samd21/samd21e/
+lib/samd21/samd21g/
+lib/samd21/samd21j/
diff --git a/uf2-samdx1/.gitignore.bk b/uf2-samdx1/.gitignore.bk
new file mode 100644
index 00000000..e0e9abe9
--- /dev/null
+++ b/uf2-samdx1/.gitignore.bk
@@ -0,0 +1,10 @@
+build/
+.vs/
+uf2-bootloader.elf
+tmp
+*.sw?
+Makefile.user
+node_modules
+scripts/clean-ifaces/*.plist
+.vscode/c_cpp_properties.json
+TAGS
diff --git a/uf2-samdx1/.gitmodules b/uf2-samdx1/.gitmodules
new file mode 100644
index 00000000..c13d46a2
--- /dev/null
+++ b/uf2-samdx1/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "lib/uf2"]
+	path = lib/uf2
+	url = https://github.com/Microsoft/uf2.git
diff --git a/uf2-samdx1/LICENSE b/uf2-samdx1/LICENSE
new file mode 100644
index 00000000..7fffbab2
--- /dev/null
+++ b/uf2-samdx1/LICENSE
@@ -0,0 +1,60 @@
+The MIT License (MIT)
+
+Copyright (c) Microsoft
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
+Third Party Programs: The software may include third party programs that
+Microsoft, not the third party, licenses to you under this agreement.
+Notices, if any, for the third party programs are included for your
+information only.
+
+
+
+Otherwise, where noted:
+
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
diff --git a/uf2-samdx1/Makefile b/uf2-samdx1/Makefile
new file mode 100644
index 00000000..2fa21c8d
--- /dev/null
+++ b/uf2-samdx1/Makefile
@@ -0,0 +1,242 @@
+BOARD=OpenEVSE_NXT
+
+ifeq ($(VERBOSE), 1)
+Q=
+else
+Q=@
+endif
+
+-include Makefile.user
+include boards/$(BOARD)/board.mk
+CC=arm-none-eabi-gcc
+ifeq ($(CHIP_FAMILY), samd21)
+COMMON_FLAGS = -mthumb -mcpu=cortex-m0plus -Os -g -DSAMD21
+endif
+ifeq ($(CHIP_FAMILY), samd51)
+COMMON_FLAGS = -mthumb -mcpu=cortex-m4 -O2 -g -DSAMD51
+endif
+WFLAGS = \
+-Werror -Wall -Wstrict-prototypes \
+-Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 \
+-ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 \
+-Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch \
+-Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wno-undef \
+-Wbad-function-cast -Wwrite-strings -Waggregate-return \
+-Wformat -Wmissing-format-attribute \
+-Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs \
+-Wlong-long -Wunreachable-code -Wcast-align \
+-Wno-missing-braces -Wno-overflow -Wno-shadow -Wno-attributes -Wno-packed -Wno-pointer-sign
+
+CFLAGS = $(COMMON_FLAGS) \
+-x c -c -pipe -nostdlib \
+-fno-strict-aliasing -fdata-sections -ffunction-sections \
+-D__$(CHIP_VARIANT)__ \
+$(WFLAGS)
+
+# Use "+" instead of "-dirty" to save a few bytes.
+UF2_VERSION_BASE = $(shell git describe --dirty=+ --always --tags)
+
+ifeq ($(CHIP_FAMILY), samd21)
+LINKER_SCRIPT=scripts/samd21j18a.ld
+BOOTLOADER_SIZE=8192
+SELF_LINKER_SCRIPT=scripts/samd21j18a_self.ld
+# Code squeezing.
+CFLAGS += -fno-jump-tables
+endif
+
+ifeq ($(CHIP_FAMILY), samd51)
+LINKER_SCRIPT=scripts/samd51j19a.ld
+BOOTLOADER_SIZE=16384
+SELF_LINKER_SCRIPT=scripts/samd51j19a_self.ld
+endif
+
+LDFLAGS= $(COMMON_FLAGS) \
+-Wall -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common \
+-Wl,--warn-section-align \
+-save-temps -nostartfiles \
+--specs=nano.specs --specs=nosys.specs
+BUILD_PATH=build/$(BOARD)
+INCLUDES = -I. -I./inc -I./inc/preprocessor
+INCLUDES += -I./boards/$(BOARD) -Ilib/cmsis/CMSIS/Include -Ilib/usb_msc
+INCLUDES += -I$(BUILD_PATH)
+
+
+ifeq ($(CHIP_FAMILY), samd21)
+INCLUDES += -Ilib/samd21/samd21a/include/
+endif
+
+ifeq ($(CHIP_FAMILY), samd51)
+ifeq ($(findstring SAME51,$(CHIP_VARIANT)),SAME51)
+INCLUDES += -Ilib/same51/include/
+else
+ifeq ($(findstring SAME54,$(CHIP_VARIANT)),SAME54)
+INCLUDES += -Ilib/same54/include/
+else
+INCLUDES += -Ilib/samd51/include/
+endif
+endif
+endif
+
+COMMON_SRC = \
+	src/flash_$(CHIP_FAMILY).c \
+	src/init_$(CHIP_FAMILY).c \
+	src/startup_$(CHIP_FAMILY).c \
+	src/usart_sam_ba.c \
+	src/screen.c \
+	src/images.c \
+	src/utils.c
+
+SOURCES = $(COMMON_SRC) \
+	src/cdc_enumerate.c \
+	src/fat.c \
+	src/main.c \
+	src/msc.c \
+	src/sam_ba_monitor.c \
+	src/uart_driver.c \
+	src/hid.c \
+
+SELF_SOURCES = $(COMMON_SRC) \
+	src/selfmain.c
+
+OBJECTS = $(patsubst src/%.c,$(BUILD_PATH)/%.o,$(SOURCES))
+SELF_OBJECTS = $(patsubst src/%.c,$(BUILD_PATH)/%.o,$(SELF_SOURCES)) $(BUILD_PATH)/selfdata.o
+
+NAME=bootloader-$(BOARD)-$(UF2_VERSION_BASE)
+EXECUTABLE=$(BUILD_PATH)/$(NAME).bin
+SELF_EXECUTABLE=$(BUILD_PATH)/update-$(NAME).uf2
+SELF_EXECUTABLE_INO=$(BUILD_PATH)/update-$(NAME).ino
+
+SUBMODULES = lib/uf2/README.md
+
+all: submodules dirs $(EXECUTABLE) $(SELF_EXECUTABLE)
+submodules: $(SUBMODULES)
+
+r: run
+b: burn
+l: logs
+
+burn: all
+	node scripts/dbgtool.js fuses
+	node scripts/dbgtool.js $(BUILD_PATH)/$(NAME).bin
+
+run: burn wait logs
+
+# This currently only works on macOS with a BMP debugger attached.
+# It's meant to flash the bootloader in a loop.
+BMP = $(shell ls -1 /dev/cu.usbmodem* | head -1)
+BMP_ARGS = --nx -ex "set mem inaccessible-by-default off" -ex "set confirm off" -ex "target extended-remote $(BMP)" -ex "mon tpwr enable" -ex "mon swdp_scan" -ex "attach 1"
+GDB = arm-none-eabi-gdb
+
+bmp-flash: $(BUILD_PATH)/$(NAME).bin
+	@test "X$(BMP)" != "X"
+	$(GDB) $(BMP_ARGS) -ex "load" -ex "quit" $(BUILD_PATH)/$(NAME).elf | tee build/flash.log
+	@grep -q "Transfer rate" build/flash.log
+
+bmp-flashone:
+	while : ; do $(MAKE) bmp-flash && exit 0 ; sleep 1 ; done
+	afplay /System/Library/PrivateFrameworks/ScreenReader.framework/Versions/A/Resources/Sounds/Error.aiff
+
+bmp-loop:
+	while : ; do $(MAKE) bmp-flashone ; sleep 5 ; done
+
+bmp-gdb: $(BUILD_PATH)/$(NAME).bin
+	$(GDB) $(BMP_ARGS) $(BUILD_PATH)/$(NAME).elf
+
+$(BUILD_PATH)/flash.jlink: $(BUILD_PATH)/$(NAME).bin
+	echo " \n\
+r \n\
+h \n\
+loadbin \"$(BUILD_PATH)/$(NAME).bin\", 0x0 \n\
+verifybin \"$(BUILD_PATH)/$(NAME).bin\", 0x0 \n\
+r \n\
+qc \n\
+" > $(BUILD_PATH)/flash.jlink
+
+jlink-flash: $(BUILD_PATH)/$(NAME).bin $(BUILD_PATH)/flash.jlink
+	JLinkExe -if swd -device AT$(CHIP_VARIANT) -speed 4000 -CommanderScript $(BUILD_PATH)/flash.jlink
+
+wait:
+	sleep 5
+
+logs:
+	node scripts/dbgtool.js $(BUILD_PATH)/$(NAME).map
+
+selflogs:
+	node scripts/dbgtool.js $(BUILD_PATH)/update-$(NAME).map
+
+dirs:
+	@echo
+	@echo "--- Building $(BOARD) ---"
+	-@mkdir -p $(BUILD_PATH)
+
+$(EXECUTABLE): $(OBJECTS)
+	$(Q)$(CC) -L$(BUILD_PATH) $(LDFLAGS) \
+		 -T$(LINKER_SCRIPT) \
+		 -Wl,-Map,$(BUILD_PATH)/$(NAME).map -o $(BUILD_PATH)/$(NAME).elf $(OBJECTS)
+	$(Q)arm-none-eabi-objcopy -O binary $(BUILD_PATH)/$(NAME).elf $@
+	@echo
+	-@arm-none-eabi-size $(BUILD_PATH)/$(NAME).elf | awk '{ s=$$1+$$2; print } END { print ""; print "Space left: " ($(BOOTLOADER_SIZE)-s) }'
+	@echo
+
+$(BUILD_PATH)/uf2_version.h: Makefile | dirs
+	@echo "#define UF2_VERSION_BASE \"$(UF2_VERSION_BASE)\""> $@
+
+$(SELF_EXECUTABLE): $(SELF_OBJECTS)
+	$(Q)$(CC) -L$(BUILD_PATH) $(LDFLAGS) \
+		 -T$(SELF_LINKER_SCRIPT) \
+		 -Wl,-Map,$(BUILD_PATH)/update-$(NAME).map -o $(BUILD_PATH)/update-$(NAME).elf $(SELF_OBJECTS)
+	$(Q)arm-none-eabi-objcopy -O binary $(BUILD_PATH)/update-$(NAME).elf $(BUILD_PATH)/update-$(NAME).bin
+	$(Q)python3 lib/uf2/utils/uf2conv.py -b $(BOOTLOADER_SIZE) -c -o $@ $(BUILD_PATH)/update-$(NAME).bin
+
+$(BUILD_PATH)/%.o: src/%.c $(wildcard inc/*.h boards/*/*.h) $(BUILD_PATH)/uf2_version.h
+	$(Q)$(CC) $(CFLAGS) $(BLD_EXTA_FLAGS) $(INCLUDES) $< -o $@
+
+$(BUILD_PATH)/%.o: $(BUILD_PATH)/%.c
+	$(Q)$(CC) $(CFLAGS) $(BLD_EXTA_FLAGS) $(INCLUDES) $< -o $@
+
+$(BUILD_PATH)/selfdata.c: $(EXECUTABLE) scripts/gendata.py src/sketch.cpp
+	$(Q)python3 scripts/gendata.py $(BOOTLOADER_SIZE) $(EXECUTABLE)
+
+clean:
+	rm -rf build
+
+gdb:
+	arm-none-eabi-gdb $(BUILD_PATH)/$(NAME).elf
+
+tui:
+	arm-none-eabi-gdb -tui $(BUILD_PATH)/$(NAME).elf
+
+%.asmdump: %.o
+	arm-none-eabi-objdump -d $< > $@
+
+applet0: $(BUILD_PATH)/flash.asmdump
+	node scripts/genapplet.js $< flash_write
+
+applet1: $(BUILD_PATH)/utils.asmdump
+	node scripts/genapplet.js $< resetIntoApp
+
+drop-board: all
+	@mkdir -p build/drop
+	@rm -rf build/drop/$(BOARD)
+	@mkdir -p build/drop/$(BOARD)
+	@cp $(SELF_EXECUTABLE) build/drop/$(BOARD)/
+	@cp $(EXECUTABLE) build/drop/$(BOARD)/
+# .ino works only for SAMD21 right now; suppress for SAMD51
+ifeq ($(CHIP_FAMILY),samd21)
+	@cp $(SELF_EXECUTABLE_INO) build/drop/$(BOARD)/
+	@cp boards/$(BOARD)/board_config.h build/drop/$(BOARD)/
+endif
+
+drop-pkg:
+	mv build/drop build/uf2-samdx1-$(UF2_VERSION_BASE)
+	cp bin-README.md build/uf2-samdx1-$(UF2_VERSION_BASE)/README.md
+	cd build; 7z a uf2-samdx1-$(UF2_VERSION_BASE).zip uf2-samdx1-$(UF2_VERSION_BASE)
+	rm -rf build/uf2-samdx1-$(UF2_VERSION_BASE)
+
+all-boards:
+	@for f in `cd boards; ls` ; do "$(MAKE)" --no-print-directory BOARD=$$f drop-board || break 1; done
+
+drop: all-boards drop-pkg
+
+$(SUBMODULES):
+	git submodule update --init --recursive
diff --git a/uf2-samdx1/README.md b/uf2-samdx1/README.md
new file mode 100644
index 00000000..ef956dac
--- /dev/null
+++ b/uf2-samdx1/README.md
@@ -0,0 +1,199 @@
+# UF2 Bootloader
+
+This repository contains a bootloader, derived from Atmel's SAM-BA,
+which in addition to the USB CDC (serial) protocol, also supports
+the USB MSC (mass storage).
+
+[![Build Status](https://travis-ci.org/Microsoft/uf2-samd21.svg?branch=master)](https://travis-ci.org/Microsoft/uf2-samd21)
+
+## UF2
+
+**UF2 (USB Flashing Format)** is a name of a file format, developed by Microsoft, that is particularly
+suitable for flashing devices over MSC devices. The file consists
+of 512 byte blocks, each of which is self-contained and independent
+of others.
+
+Each 512 byte block consist of (see `uf2format.h` for details):
+* magic numbers at the beginning and at the end
+* address where the data should be flashed
+* size of data
+* data (up to 476 bytes; for SAMD it's 256 bytes so it's easy to flash in one go)
+
+Thus, it's really easy for the microcontroller to recognize a block of
+a UF2 file is written and immediately write it to flash.
+
+* **UF2 specification repo:** https://github.com/Microsoft/uf2
+* [#DeskOfLadyada UF24U ! LIVE @adafruit #adafruit #programming](https://youtu.be/WxCuB6jxLs0)
+
+## Features
+
+* USB CDC (Serial emulation) monitor mode compatible with Arduino
+  (including XYZ commands) and BOSSA flashing tool
+* USB MSC interface for writing UF2 files
+* reading of the content of the flash as an UF2 file via USB MSC
+* UART Serial (real serial wire) monitor mode (typically disabled due to space constraints)
+* In-memory logging for debugging - use the `logs` target to extract the logs using `openocd`
+* double-tap reset to stay in the bootloader mode
+* automatic reset after UF2 file is written
+
+## Board identification
+
+Configuration files for board `foo` are in `boards/foo/board_config.h` and `board.mk`. You can
+build it with `make BOARD=foo`. You can also create `Makefile.user` file with `BOARD=foo`
+to change the default.
+
+The board configuration specifies the USB vendor/product name and ID,
+as well as the volume label (main thing that the operating systems show).
+
+There is also `BOARD_ID`, which is meant to be machine-readable and specific
+to a given version of board hardware. The programming environment might use
+this to suggest packages to be imported (i.e., a package for a particular
+external flash chip, SD card etc.).
+
+These configuration values can be read from `INFO_UF2.TXT` file.
+Presence of this file can be tested to see if the board supports `UF2` flashing,
+while the contents, particularly `Board-ID` field, can be used for feature detection.
+
+The current flash contents of the board is exposed as `CURRENT.UF2` file.
+This file includes the bootloader address space. The last word of bootloader
+space points to the string holding the `INFO_UF2.TXT` file, so it can be parsed
+by a programming environment to determine which board does the `.UF2` file comes from.
+
+## Handover
+
+When the user space application implements the USB MSC protocol, it's possible to
+handover execution to the bootloader in the middle of MSC file transfer,
+when the application detects that a UF2 block is written.
+
+Details are being finalized.
+
+## Bootloader update
+
+The bootloader will never write to its own flash area directly.
+However, the user code can write there.
+Thus, to update the bootloader, one can ship a user-space program,
+that contains the new version of the bootloader and copies it to the
+appropriate place in flash.
+
+Such a program is generated during build in files `update-bootloader*.uf2`.
+If you're already running UF2 bootloader, the easiest way to update
+it, is to just copy this file to the exposed MSD drive.
+
+The build also generates `update-bootloader*.ino` with an equivalent Arduino
+sketch. You can copy&paste it into Arduino IDE and upload it to the device.
+
+## Fuses
+
+### SAMD21
+
+The SAMD21 supports a `BOOTPROT` fuse, which write-protects the flash area of
+the bootloader. Changes to this fuse only take effect after device reset.
+
+OpenOCD exposes `at91samd bootloader` command to set this fuse. **This command is buggy.**
+It seems to reset both fuse words to `0xffffffff`, which prevents the device
+from operating correctly (it seems to reboot very frequently).
+In `scripts/fuses.tcl` there is an OpenOCD script
+which correctly sets the fuse. It's invoked by `dbgtool.js fuses`. It can be also
+used to reset the fuses to sane values - just look at the comment at the top.
+
+The bootloader update programs (both the `.uf2` file and the Arduino sketch)
+clear the `BOOTPROT` (i.e., set it to `0x7`) before trying to flash anything.
+After flashing is done, they set `BOOTPROT` to 8 kilobyte bootloader size (i.e, `0x2`).
+
+### SAMD51
+
+The SAMD51s bootloader protection can be temporarily disabled through an NVM
+command rather than a full erase and write of the AUX page. The boot protection
+will be checked and set by the self updaters.
+
+So, if you've used self-updaters but want to load it directly, then you'll need
+to temporarily turn off the protection. In gdb the command is:
+
+`set ((Nvmctrl  *)0x41004000UL)->CTRLB.reg = (0xA5 << 8) | 0x1a`
+
+## Build
+
+### Requirements
+
+* `make` and an Unix environment
+* `node`.js in path (optional)
+* `arm-none-eabi-gcc` in the path (the one coming with Yotta will do just fine). You can get the latest version from ARM: https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads
+* `openocd` - you can use the one coming with Arduino (after your install the M0 board support)
+
+Atmel Studio is not supported.
+
+You will need a board with `openocd` support.
+
+Arduino Zero (or M0 Pro) will work just fine as it has an integrated USB EDBG
+port. You need to connect both USB ports to your machine to debug - one is for
+flashing and getting logs, the other is for the exposed MSC interface.
+
+Otherwise, you can use other SAMD21 board and an external `openocd` compatible
+debugger. IBDAP is cheap and seems to work just fine. Another option is to use
+Raspberry Pi and native bit-banging.
+
+`openocd` will flash 16k, meaning that on SAMD21 the beginning of user program (if any) will
+be overwritten with `0xff`. This also means that after fresh flashing of bootloader
+no double-tap reset is necessary, as the bootloader will not try to start application
+at `0xffffffff`.
+
+### Build commands
+
+The default board is `zero`. You can build a different one using:
+
+```
+make BOARD=metro_m0
+```
+
+If you're working on different board, it's best to create `Makefile.user`
+with say `BOARD=metro` to change the default.
+The names `zero` and `metro` refer to subdirectories of `boards/`.
+
+There are various targets:
+* `all` - just compile the board
+* `burn` or `b` - compile and deploy to the board using openocd
+* `logs` or `l` - shows logs
+* `run` or `r` - burn, wait, and show logs
+
+Typically, you will do:
+
+```
+make r
+```
+
+### Configuration
+
+There is a number of configuration parameters at the top of `uf2.h` file.
+Adjust them to your liking.
+
+By default, you cannot enable all the features, as the bootloader would exceed
+the 8k(SAMD21)/16k(SAMD51) allocated to it by Arduino etc. It will assert on startup that it's not bigger
+than 8k(SAMD21)/16k(SAMD51). Also, the linker script will not allow it.
+
+Three typical configurations are:
+
+* HID, WebUSB, MSC, plus flash reading via FAT; UART and CDC disabled;
+  logging optional; **recommended**
+* USB CDC and MSC, plus flash reading via FAT; UART disabled;
+  logging optional; this may have Windows driver problems
+* USB CDC and MSC, no flash reading via FAT (or at least `index.htm` disabled); UART enabled;
+  logging disabled; no handover; no HID;
+  only this one if you need the UART support in bootloader for whatever reason
+
+CDC and MSC together will work on Linux and Mac with no drivers.
+On Windows, if you have drivers installed for the USB ID chosen,
+then CDC might work and MSC will not work;
+otherwise, if you have no drivers, MSC will work, and CDC will work on Windows 10 only.
+Thus, it's best to set the USB ID to one for which there are no drivers.
+
+The bootloader sits at 0x00000000, and the application starts at 0x00002000 (SAMD21) or 0x00004000 (SAMD51).
+
+## Code of Conduct
+
+This project has adopted the [Microsoft Open Source Code of Conduct](https://opensource.microsoft.com/codeofconduct/). For more information see the [Code of Conduct FAQ](https://opensource.microsoft.com/codeofconduct/faq/) or contact [opencode@microsoft.com](mailto:opencode@microsoft.com) with any additional questions or comments.
+
+## License
+
+See THIRD-PARTY-NOTICES.txt for the original SAM-BA bootloader license from Atmel.
+
+The new code is licensed under MIT.
diff --git a/uf2-samdx1/THIRD-PARTY-NOTICES.txt b/uf2-samdx1/THIRD-PARTY-NOTICES.txt
new file mode 100644
index 00000000..39b8007a
--- /dev/null
+++ b/uf2-samdx1/THIRD-PARTY-NOTICES.txt
@@ -0,0 +1,161 @@
+/*!----------------- UF2-SAMD21 ThirdPartyNotices -------------------------------------------------------
+
+
+
+UF2-SAMD21 uses third party material from the projects listed below.
+
+The original copyright notice and the license under which Microsoft
+
+received such third party material are set forth below. Microsoft
+
+reserves all other rights not expressly granted, whether by
+
+implication, estoppel or otherwise.
+
+
+
+In the event that we accidentally failed to list a required notice, please
+
+bring it to our attention. Post an issue or email us:
+
+
+
+           yelmteam@microsoft.com
+
+
+
+---------------------------------------------
+
+Third Party Code Components
+
+---------------------------------------------
+
+----------------- SAM Software Package License -------------------
+
+Copyright (c) 2011-2014, Atmel Corporation
+
+All rights reserved.
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following condition is met:
+
+Redistributions of source code must retain the above copyright notice,
+this list of conditions and the disclaimer below.
+
+Atmel's name may not be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+----------------------------------------------------------------------------
+
+----------------- Atmel Software Framework (ASF)--------------------------------------
+
+Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+
+\asf_license_start
+
+\page License
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice,
+   this list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+3. The name of Atmel may not be used to endorse or promote products derived
+   from this software without specific prior written permission.
+
+4. This software may only be redistributed and used in connection with an
+   Atmel microcontroller product.
+
+THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+\asf_license_stop
+ ----------------------------------------------------------------------------
+
+----------------- Atmel Software Framework (ASF)--------------------------------------
+Copyright (c) 2016 Atmel Corporation. All rights reserved.
+
+\asf_license_start
+
+\page License
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice,
+   this list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+3. The name of Atmel may not be used to endorse or promote products derived
+   from this software without specific prior written permission.
+
+4. This software may only be redistributed and used in connection with an
+   Atmel microcontroller product.
+
+THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+-------------------------------------------------------
+
+---------------------------ARM-------------------------------------------------
+
+Copyright (c) 2009 - 2014 ARM LIMITED
+
+All rights reserved.
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+- Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+- Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+- Neither the name of ARM nor the names of its contributors may be used
+    to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+---------------------------------------------------------------------------
diff --git a/uf2-samdx1/bin-README.md b/uf2-samdx1/bin-README.md
new file mode 100644
index 00000000..f7125d2a
--- /dev/null
+++ b/uf2-samdx1/bin-README.md
@@ -0,0 +1,79 @@
+# UF2 Bootloader
+
+This archive contains information about the binaries of the bootloader, built from this
+repo for various SAMD21 boards. These are derived from Atmel's SAM-BA, 
+also supports USB MSC (mass storage) and USB HID update protocols.
+
+**UF2 (USB Flashing Format)** is a name of a file format supported by the bootloader, 
+that is particularly suitable for flashing devices over mass storage interfaces. The file 
+consists of 512 byte blocks, each of which is self-contained, easy to identify, and 
+independent of others. For more details, see [UF2 specification repo](https://github.com/Microsoft/uf2).
+
+The binaries here are built based on the [source repository](https://github.com/Microsoft/uf2-samd21).
+
+## Usage
+
+Once the bootloader is flashed to your device, it will react to a double-click
+of the reset button. At that point, the indicator LED of the board should start
+pulsing slowly (about 1 per second).
+
+You should also see a new USB drive appear on the connected computer. 
+The drive should have an `INFO_UF2.TXT` file on it with various information.
+You can drop `.UF2` files on that drive to program the board.
+You can also use USB HID protocol dubbed HF2 to talk to the board.
+
+## Choosing the right bootloader
+
+All the bootloaders in this archive use almost the same code and will generally
+work on most SAMD21 boards. However, the LED might not blink and you may get the 
+device mis-identified by the operating system.
+
+Thus, it's good to pick the bootloader from the right directory.
+
+If you're not sure and you are already running an UF2 bootloader, you can
+look at the `INFO_UF2.TXT` file exposed by the current bootloader. In particular
+look for `Model:` and `Board-ID:`. Then compare that with the comment at
+the beginning of `update-bootloader.ino` in various directories.
+
+As said before, consequences of choosing the wrong one are not too dramatic.
+
+Once you have chosen the right directory, there are three ways to update your bootloader.
+
+## I'm already running a version of UF2
+
+In case you can already see a UF2 drive on your computer (it should have `INFO_UF2.TXT` 
+file on it), you can just drop `update-bootloader.uf2` file there.
+
+## I have Arduino running
+
+If you have Arduino IDE available, copy&paste `update-bootloader.ino` sketch
+and upload it to the device.
+
+Please note, that if you're running an Arduino/Genuino board and 
+Windows 8.1 or earlier, this may prevent Arduino IDE from recognizing 
+the serial emulation on the board.
+
+This does not apply to Adafruit boards, only to Arduino and Genuino.
+It also does not apply to Windows 10, Mac, or Linux.
+
+## I have a SWD or JTAG programmer
+
+In case you have a programmer (like the one that comes built in on Arduino Zero or an 
+external one like IBDAP), you can burn the `bootloader.bin` file. Make sure to use 
+`0x00000000` as the base address.
+
+You may also need to remove bootloader protection.
+There is a script in the [source repository](https://github.com/Microsoft/uf2-samd21) 
+to do it.
+
+Do not use `at91samd bootloader 0` command of OpenOCD - it's buggy.
+
+## Code of Conduct
+
+This project has adopted the [Microsoft Open Source Code of Conduct](https://opensource.microsoft.com/codeofconduct/). For more information see the [Code of Conduct FAQ](https://opensource.microsoft.com/codeofconduct/faq/) or contact [opencode@microsoft.com](mailto:opencode@microsoft.com) with any additional questions or comments.
+
+## License
+
+The original SAM-BA bootloader is licensed under BSD-like license from Atmel.
+
+The new code is licensed under MIT.
diff --git a/uf2-samdx1/boards/OpenEVSE_NXT/board.mk b/uf2-samdx1/boards/OpenEVSE_NXT/board.mk
new file mode 100644
index 00000000..0a90fdf6
--- /dev/null
+++ b/uf2-samdx1/boards/OpenEVSE_NXT/board.mk
@@ -0,0 +1,2 @@
+CHIP_FAMILY = samd21
+CHIP_VARIANT = SAMD21G18A
diff --git a/uf2-samdx1/boards/OpenEVSE_NXT/board_config.h b/uf2-samdx1/boards/OpenEVSE_NXT/board_config.h
new file mode 100644
index 00000000..a8f4dbed
--- /dev/null
+++ b/uf2-samdx1/boards/OpenEVSE_NXT/board_config.h
@@ -0,0 +1,15 @@
+#ifndef BOARD_CONFIG_H
+#define BOARD_CONFIG_H
+
+#define VENDOR_NAME "OpenEVSE"
+#define PRODUCT_NAME "OpenEVSE NXT EVSE Controller"
+#define VOLUME_LABEL "OpenEVSE"
+#define INDEX_URL "https://www.openevse.com"
+#define BOARD_ID "SAMD21G18A-OpenEVSE-NXT"
+
+#define USB_VID 0x1B4F
+#define USB_PID 0x0D22
+
+#define LED_PIN PIN_PA17
+
+#endif
diff --git a/uf2-samdx1/inc/cdc_enumerate.h b/uf2-samdx1/inc/cdc_enumerate.h
new file mode 100644
index 00000000..1261c301
--- /dev/null
+++ b/uf2-samdx1/inc/cdc_enumerate.h
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef CDC_ENUMERATE_H
+#define CDC_ENUMERATE_H
+
+#define PKT_SIZE 64
+
+#define USB_EP_IN 1
+#define USB_EP_OUT 2
+#define USB_EP_COMM 3
+
+#define USB_EP_MSC_IN 4
+#define USB_EP_MSC_OUT 5
+
+#define USB_EP_HID 6
+#define USB_EP_WEB 7
+
+#define MAX_EP 8
+
+#define NVM_USB_PAD_TRANSN_POS 45
+#define NVM_USB_PAD_TRANSN_SIZE 5
+#define NVM_USB_PAD_TRANSP_POS 50
+#define NVM_USB_PAD_TRANSP_SIZE 5
+#define NVM_USB_PAD_TRIM_POS 55
+#define NVM_USB_PAD_TRIM_SIZE 3
+
+typedef struct _USB_CDC {
+    // Private members
+    uint8_t currentConfiguration;
+    uint8_t currentConnection;
+} USB_CDC, *P_USB_CDC;
+
+typedef struct {
+    uint32_t dwDTERate;
+    uint8_t bCharFormat;
+    uint8_t bParityType;
+    uint8_t bDataBits;
+} usb_cdc_line_coding_t;
+
+/**
+ * \brief Initializes the USB module
+ */
+void usb_init(void);
+
+/**
+ * \brief Sends a single byte through USB CDC
+ *
+ * \param Data to send
+ * \return number of data sent
+ */
+int cdc_putc(int value);
+
+/**
+ * \brief Reads a single byte through USB CDC
+ *
+ * \return Data read through USB
+ */
+int cdc_getc(void);
+
+/**
+ * \brief Checks if a character has been received on USB CDC
+ *
+ * \return \c 1 if a byte is ready to be read.
+ */
+bool cdc_is_rx_ready(void);
+
+/**
+ * \brief Sends buffer on USB CDC
+ *
+ * \param data pointer
+ * \param number of data to send
+ * \return number of data sent
+ */
+uint32_t cdc_write_buf(void const *data, uint32_t length);
+uint32_t cdc_write_buf_xmd(void const *data, uint32_t length);
+
+/**
+ * \brief Gets data on USB CDC
+ *
+ * \param data pointer
+ * \param number of data to read
+ * \return number of data read
+ */
+uint32_t cdc_read_buf(void *data, uint32_t length);
+
+/**
+ * \brief Gets specified number of bytes on USB CDC
+ *
+ * \param data pointer
+ * \param number of data to read
+ * \return number of data read
+ */
+uint32_t cdc_read_buf_xmd(void *data, uint32_t length);
+
+void reset_ep(uint8_t ep);
+void stall_ep(uint8_t ep);
+
+typedef struct {
+    uint8_t size;
+    uint8_t ptr;
+    uint8_t read_job;
+    uint8_t padding;
+    uint8_t buf[PKT_SIZE];
+} PacketBuffer __attribute__((aligned(4)));
+
+uint32_t USB_Read(void *pData, uint32_t length, uint32_t ep);
+uint32_t USB_Write(const void *pData, uint32_t length, uint8_t ep_num);
+uint32_t USB_WriteCore(const void *pData, uint32_t length, uint8_t ep_num, bool handoverMode);
+void USB_ReadBlocking(void *dst, uint32_t length, uint32_t ep, PacketBuffer *cache);
+uint32_t USB_ReadCore(void *pData, uint32_t length, uint32_t ep, PacketBuffer *cache);
+bool USB_Ok(void);
+
+#endif // CDC_ENUMERATE_H
diff --git a/uf2-samdx1/inc/configkeys.h b/uf2-samdx1/inc/configkeys.h
new file mode 100644
index 00000000..f975005f
--- /dev/null
+++ b/uf2-samdx1/inc/configkeys.h
@@ -0,0 +1,149 @@
+#ifndef __CONFIGKEYS_H
+#define __CONFIGKEYS_H 1
+
+#define CFG_MAGIC0 0x1e9e10f1
+#define CFG_MAGIC1 0x20227a79
+
+#define CFG_PIN_ACCELEROMETER_INT 1
+#define CFG_PIN_ACCELEROMETER_SCL 2
+#define CFG_PIN_ACCELEROMETER_SDA 3
+#define CFG_PIN_BTN_A 4
+#define CFG_PIN_BTN_B 5
+#define CFG_PIN_BTN_SLIDE 6
+#define CFG_PIN_DOTSTAR_CLOCK 7
+#define CFG_PIN_DOTSTAR_DATA 8
+#define CFG_PIN_FLASH_CS 9
+#define CFG_PIN_FLASH_MISO 10
+#define CFG_PIN_FLASH_MOSI 11
+#define CFG_PIN_FLASH_SCK 12
+#define CFG_PIN_LED 13
+#define CFG_PIN_LIGHT 14
+#define CFG_PIN_MICROPHONE 15
+#define CFG_PIN_MIC_CLOCK 16
+#define CFG_PIN_MIC_DATA 17
+#define CFG_PIN_MISO 18
+#define CFG_PIN_MOSI 19
+#define CFG_PIN_NEOPIXEL 20
+#define CFG_PIN_RX 21
+#define CFG_PIN_RXLED 22
+#define CFG_PIN_SCK 23
+#define CFG_PIN_SCL 24
+#define CFG_PIN_SDA 25
+#define CFG_PIN_SPEAKER_AMP 26
+#define CFG_PIN_TEMPERATURE 27
+#define CFG_PIN_TX 28
+#define CFG_PIN_TXLED 29
+#define CFG_PIN_IR_OUT 30
+#define CFG_PIN_IR_IN 31
+#define CFG_PIN_DISPLAY_SCK 32
+#define CFG_PIN_DISPLAY_MISO 33
+#define CFG_PIN_DISPLAY_MOSI 34
+#define CFG_PIN_DISPLAY_CS 35
+#define CFG_PIN_DISPLAY_DC 36
+#define CFG_DISPLAY_WIDTH 37
+#define CFG_DISPLAY_HEIGHT 38
+#define CFG_DISPLAY_CFG0 39
+#define CFG_DISPLAY_CFG1 40
+#define CFG_DISPLAY_CFG2 41
+#define CFG_DISPLAY_CFG3 42
+#define CFG_PIN_DISPLAY_RST 43
+#define CFG_PIN_DISPLAY_BL 44
+#define CFG_PIN_SERVO_1 45
+#define CFG_PIN_SERVO_2 46
+#define CFG_PIN_BTN_LEFT 47
+#define CFG_PIN_BTN_RIGHT 48
+#define CFG_PIN_BTN_UP 49
+#define CFG_PIN_BTN_DOWN 50
+#define CFG_PIN_BTN_MENU 51
+#define CFG_PIN_LED_R 52
+#define CFG_PIN_LED_G 53
+#define CFG_PIN_LED_B 54
+#define CFG_PIN_LED1 55
+#define CFG_PIN_LED2 56
+#define CFG_PIN_LED3 57
+#define CFG_PIN_LED4 58
+#define CFG_SPEAKER_VOLUME 59
+#define CFG_PIN_JACK_TX 60
+#define CFG_PIN_JACK_SENSE 61
+#define CFG_PIN_JACK_HPEN 62
+#define CFG_PIN_JACK_BZEN 63
+#define CFG_PIN_JACK_PWREN 64
+#define CFG_PIN_JACK_SND 65
+#define CFG_PIN_JACK_BUSLED 66
+#define CFG_PIN_JACK_COMMLED 67
+#define CFG_PIN_BTNMX_LATCH 66
+#define CFG_PIN_BTNMX_CLOCK 67
+#define CFG_PIN_BTNMX_DATA 68
+#define CFG_PIN_BTN_SOFT_RESET 69
+#define CFG_ACCELEROMETER_TYPE 70
+#define CFG_PIN_A0 100
+#define CFG_PIN_A1 101
+#define CFG_PIN_A2 102
+#define CFG_PIN_A3 103
+#define CFG_PIN_A4 104
+#define CFG_PIN_A5 105
+#define CFG_PIN_A6 106
+#define CFG_PIN_A7 107
+#define CFG_PIN_A8 108
+#define CFG_PIN_A9 109
+#define CFG_PIN_A10 110
+#define CFG_PIN_A11 111
+#define CFG_PIN_A12 112
+#define CFG_PIN_A13 113
+#define CFG_PIN_A14 114
+#define CFG_PIN_A15 115
+#define CFG_PIN_D0 150
+#define CFG_PIN_D1 151
+#define CFG_PIN_D2 152
+#define CFG_PIN_D3 153
+#define CFG_PIN_D4 154
+#define CFG_PIN_D5 155
+#define CFG_PIN_D6 156
+#define CFG_PIN_D7 157
+#define CFG_PIN_D8 158
+#define CFG_PIN_D9 159
+#define CFG_PIN_D10 160
+#define CFG_PIN_D11 161
+#define CFG_PIN_D12 162
+#define CFG_PIN_D13 163
+#define CFG_PIN_D14 164
+#define CFG_PIN_D15 165
+#define CFG_NUM_NEOPIXELS 200
+#define CFG_NUM_DOTSTARS 201
+#define CFG_DEFAULT_BUTTON_MODE 202
+#define CFG_SWD_ENABLED 203
+#define CFG_FLASH_BYTES 204
+#define CFG_RAM_BYTES 205
+#define CFG_SYSTEM_HEAP_BYTES 206
+#define CFG_LOW_MEM_SIMULATION_KB 207
+#define CFG_BOOTLOADER_BOARD_ID 208
+#define CFG_UF2_FAMILY 209
+#define CFG_PINS_PORT_SIZE 210
+
+#define ACCELEROMETER_TYPE_LIS3DH 0x32
+#define ACCELEROMETER_TYPE_MMA8453 0x38
+#define ACCELEROMETER_TYPE_FXOS8700 0x3c
+#define ACCELEROMETER_TYPE_MMA8653 0x3a
+#define ACCELEROMETER_TYPE_MSA300 0x4c
+
+#define UF2_FAMILY_ATSAMD21 0x68ed2b88
+#define UF2_FAMILY_ATSAMD51 0x55114460
+#define UF2_FAMILY_NRF52840 0x1b57745f
+#define UF2_FAMILY_STM32F103 0x5ee21072
+#define UF2_FAMILY_STM32F401 0x57755a57
+#define UF2_FAMILY_ATMEGA32 0x16573617
+#define UF2_FAMILY_CYPRESS_FX2 0x5a18069b
+
+#define PINS_PORT_SIZE_PA_16 0x10
+#define PINS_PORT_SIZE_PA_32 0x20
+#define PINS_PORT_SIZE_P0_16 0x1010
+#define PINS_PORT_SIZE_P0_32 0x1020
+
+#define DEFAULT_BUTTON_MODE_ACTIVE_HIGH_PULL_DOWN 0x11
+#define DEFAULT_BUTTON_MODE_ACTIVE_HIGH_PULL_UP 0x21
+#define DEFAULT_BUTTON_MODE_ACTIVE_HIGH_PULL_NONE 0x31
+#define DEFAULT_BUTTON_MODE_ACTIVE_LOW_PULL_DOWN 0x10
+#define DEFAULT_BUTTON_MODE_ACTIVE_LOW_PULL_UP 0x20
+#define DEFAULT_BUTTON_MODE_ACTIVE_LOW_PULL_NONE 0x30
+
+#endif // __CONFIGKEYS_H
diff --git a/uf2-samdx1/inc/main.h b/uf2-samdx1/inc/main.h
new file mode 100644
index 00000000..31f23a8a
--- /dev/null
+++ b/uf2-samdx1/inc/main.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _MAIN_H_
+#define _MAIN_H_
+
+#define CPU_FREQUENCY 48000000
+
+#define FLASH_WAIT_STATES 1
+
+#ifndef BOOT_USART_MODULE
+#define BOOT_USART_MODULE SERCOM3
+#define BOOT_USART_PAD_SETTINGS UART_RX_PAD1_TX_PAD0
+#define BOOT_USART_PAD3 PINMUX_UNUSED
+#define BOOT_USART_PAD2 PINMUX_UNUSED
+#define BOOT_USART_PAD1 PINMUX_PA23C_SERCOM3_PAD1
+#define BOOT_USART_PAD0 PINMUX_PA22C_SERCOM3_PAD0
+#endif
+
+#endif // _MAIN_H_
diff --git a/uf2-samdx1/inc/neopixel.h b/uf2-samdx1/inc/neopixel.h
new file mode 100644
index 00000000..9a89be64
--- /dev/null
+++ b/uf2-samdx1/inc/neopixel.h
@@ -0,0 +1,92 @@
+#ifndef DEVICE_NEOPIXEL_H
+#define DEVICE_NEOPIXEL_H
+
+#ifdef BOARD_NEOPIXEL_PIN
+
+// The timings are taken from Adafruit's NeoPixel library
+
+static void neopixel_send_buffer_core(volatile uint32_t *clraddr, uint32_t pinMask,
+                                      const uint8_t *ptr, int numBytes) __attribute__((naked));
+
+static void neopixel_send_buffer_core(volatile uint32_t *clraddr, uint32_t pinMask,
+                                      const uint8_t *ptr, int numBytes) {
+    asm volatile("        push    {r4, r5, r6, lr};"
+                 "        add     r3, r2, r3;"
+                 "loopLoad:"
+                 "        ldrb r5, [r2, #0];" // r5 := *ptr
+                 "        add  r2, #1;"       // ptr++
+                 "        movs    r4, #128;"  // r4-mask, 0x80
+                 "loopBit:"
+                 "        str r1, [r0, #4];"                    // set
+                 #ifdef SAMD21
+                 "        movs r6, #3; d2: sub r6, #1; bne d2;" // delay 3
+                 #endif
+                 #ifdef SAMD51
+                 "        movs r6, #3; d2: subs r6, #1; bne d2;" // delay 3
+                 #endif
+                 "        tst r4, r5;"                          // mask&r5
+                 "        bne skipclr;"
+                 "        str r1, [r0, #0];" // clr
+                 "skipclr:"
+                 #ifdef SAMD21
+                 "        movs r6, #6; d0: sub r6, #1; bne d0;" // delay 6
+                 #endif
+                 #ifdef SAMD51
+                 "        movs r6, #6; d0: subs r6, #1; bne d0;" // delay 6
+                 #endif
+                 "        str r1, [r0, #0];"   // clr (possibly again, doesn't matter)
+                 #ifdef SAMD21
+                 "        asr     r4, r4, #1;" // mask >>= 1
+                 #endif
+                 #ifdef SAMD51
+                 "        asrs     r4, r4, #1;" // mask >>= 1
+                 #endif
+                 "        beq     nextbyte;"
+                 "        uxtb    r4, r4;"
+                 #ifdef SAMD21
+                 "        movs r6, #2; d1: sub r6, #1; bne d1;" // delay 2
+                 #endif
+                 #ifdef SAMD51
+                 "        movs r6, #2; d1: subs r6, #1; bne d1;" // delay 2
+                 #endif
+                 "        b       loopBit;"
+                 "nextbyte:"
+                 "        cmp r2, r3;"
+                 "        bcs stop;"
+                 "        b loopLoad;"
+                 "stop:"
+                 "        pop {r4, r5, r6, pc};"
+                 "");
+}
+
+// this assumes the pin has been configured correctly
+static inline void neopixel_send_buffer(const uint8_t *ptr, int numBytes) {
+    uint8_t portNum = BOARD_NEOPIXEL_PIN / 32;
+    uint32_t pinMask = 1ul << (BOARD_NEOPIXEL_PIN % 32);
+
+    PINOP(BOARD_NEOPIXEL_PIN, DIRSET);
+
+#if (USB_VID == 0x239a) && (USB_PID == 0x0013)  // Adafruit Metro M0
+    // turn off mux too, needed for metro m0
+    PORT->Group[BOARD_NEOPIXEL_PIN / 32].PINCFG[BOARD_NEOPIXEL_PIN % 32].reg =
+        (uint8_t)(PORT_PINCFG_INEN);
+#endif
+
+    PINOP(BOARD_NEOPIXEL_PIN, OUTCLR);
+    delay(1);
+
+    volatile uint32_t *clraddr = &PORT->Group[portNum].OUTCLR.reg;
+
+    // equivalent to cpu_irq_is_enabled()
+    if (__get_PRIMASK() == 0) {
+        __disable_irq();
+        neopixel_send_buffer_core(clraddr, pinMask, ptr, numBytes);
+        __enable_irq();
+    } else {
+        neopixel_send_buffer_core(clraddr, pinMask, ptr, numBytes);
+    }
+}
+
+#endif
+
+#endif
diff --git a/uf2-samdx1/inc/preprocessor/mrecursion.h b/uf2-samdx1/inc/preprocessor/mrecursion.h
new file mode 100644
index 00000000..1722ab0c
--- /dev/null
+++ b/uf2-samdx1/inc/preprocessor/mrecursion.h
@@ -0,0 +1,581 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _MRECURSION_H_
+#define _MRECURSION_H_
+
+/**
+ * \defgroup group_sam0_utils_mrecursion Preprocessor - Macro Recursion
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+#define DEC_256                                   255
+#define DEC_255                                   254
+#define DEC_254                                   253
+#define DEC_253                                   252
+#define DEC_252                                   251
+#define DEC_251                                   250
+#define DEC_250                                   249
+#define DEC_249                                   248
+#define DEC_248                                   247
+#define DEC_247                                   246
+#define DEC_246                                   245
+#define DEC_245                                   244
+#define DEC_244                                   243
+#define DEC_243                                   242
+#define DEC_242                                   241
+#define DEC_241                                   240
+#define DEC_240                                   239
+#define DEC_239                                   238
+#define DEC_238                                   237
+#define DEC_237                                   236
+#define DEC_236                                   235
+#define DEC_235                                   234
+#define DEC_234                                   233
+#define DEC_233                                   232
+#define DEC_232                                   231
+#define DEC_231                                   230
+#define DEC_230                                   229
+#define DEC_229                                   228
+#define DEC_228                                   227
+#define DEC_227                                   226
+#define DEC_226                                   225
+#define DEC_225                                   224
+#define DEC_224                                   223
+#define DEC_223                                   222
+#define DEC_222                                   221
+#define DEC_221                                   220
+#define DEC_220                                   219
+#define DEC_219                                   218
+#define DEC_218                                   217
+#define DEC_217                                   216
+#define DEC_216                                   215
+#define DEC_215                                   214
+#define DEC_214                                   213
+#define DEC_213                                   212
+#define DEC_212                                   211
+#define DEC_211                                   210
+#define DEC_210                                   209
+#define DEC_209                                   208
+#define DEC_208                                   207
+#define DEC_207                                   206
+#define DEC_206                                   205
+#define DEC_205                                   204
+#define DEC_204                                   203
+#define DEC_203                                   202
+#define DEC_202                                   201
+#define DEC_201                                   200
+#define DEC_200                                   199
+#define DEC_199                                   198
+#define DEC_198                                   197
+#define DEC_197                                   196
+#define DEC_196                                   195
+#define DEC_195                                   194
+#define DEC_194                                   193
+#define DEC_193                                   192
+#define DEC_192                                   191
+#define DEC_191                                   190
+#define DEC_190                                   189
+#define DEC_189                                   188
+#define DEC_188                                   187
+#define DEC_187                                   186
+#define DEC_186                                   185
+#define DEC_185                                   184
+#define DEC_184                                   183
+#define DEC_183                                   182
+#define DEC_182                                   181
+#define DEC_181                                   180
+#define DEC_180                                   179
+#define DEC_179                                   178
+#define DEC_178                                   177
+#define DEC_177                                   176
+#define DEC_176                                   175
+#define DEC_175                                   174
+#define DEC_174                                   173
+#define DEC_173                                   172
+#define DEC_172                                   171
+#define DEC_171                                   170
+#define DEC_170                                   169
+#define DEC_169                                   168
+#define DEC_168                                   167
+#define DEC_167                                   166
+#define DEC_166                                   165
+#define DEC_165                                   164
+#define DEC_164                                   163
+#define DEC_163                                   162
+#define DEC_162                                   161
+#define DEC_161                                   160
+#define DEC_160                                   159
+#define DEC_159                                   158
+#define DEC_158                                   157
+#define DEC_157                                   156
+#define DEC_156                                   155
+#define DEC_155                                   154
+#define DEC_154                                   153
+#define DEC_153                                   152
+#define DEC_152                                   151
+#define DEC_151                                   150
+#define DEC_150                                   149
+#define DEC_149                                   148
+#define DEC_148                                   147
+#define DEC_147                                   146
+#define DEC_146                                   145
+#define DEC_145                                   144
+#define DEC_144                                   143
+#define DEC_143                                   142
+#define DEC_142                                   141
+#define DEC_141                                   140
+#define DEC_140                                   139
+#define DEC_139                                   138
+#define DEC_138                                   137
+#define DEC_137                                   136
+#define DEC_136                                   135
+#define DEC_135                                   134
+#define DEC_134                                   133
+#define DEC_133                                   132
+#define DEC_132                                   131
+#define DEC_131                                   130
+#define DEC_130                                   129
+#define DEC_129                                   128
+#define DEC_128                                   127
+#define DEC_127                                   126
+#define DEC_126                                   125
+#define DEC_125                                   124
+#define DEC_124                                   123
+#define DEC_123                                   122
+#define DEC_122                                   121
+#define DEC_121                                   120
+#define DEC_120                                   119
+#define DEC_119                                   118
+#define DEC_118                                   117
+#define DEC_117                                   116
+#define DEC_116                                   115
+#define DEC_115                                   114
+#define DEC_114                                   113
+#define DEC_113                                   112
+#define DEC_112                                   111
+#define DEC_111                                   110
+#define DEC_110                                   109
+#define DEC_109                                   108
+#define DEC_108                                   107
+#define DEC_107                                   106
+#define DEC_106                                   105
+#define DEC_105                                   104
+#define DEC_104                                   103
+#define DEC_103                                   102
+#define DEC_102                                   101
+#define DEC_101                                   100
+#define DEC_100                                    99
+#define DEC_99                                     98
+#define DEC_98                                     97
+#define DEC_97                                     96
+#define DEC_96                                     95
+#define DEC_95                                     94
+#define DEC_94                                     93
+#define DEC_93                                     92
+#define DEC_92                                     91
+#define DEC_91                                     90
+#define DEC_90                                     89
+#define DEC_89                                     88
+#define DEC_88                                     87
+#define DEC_87                                     86
+#define DEC_86                                     85
+#define DEC_85                                     84
+#define DEC_84                                     83
+#define DEC_83                                     82
+#define DEC_82                                     81
+#define DEC_81                                     80
+#define DEC_80                                     79
+#define DEC_79                                     78
+#define DEC_78                                     77
+#define DEC_77                                     76
+#define DEC_76                                     75
+#define DEC_75                                     74
+#define DEC_74                                     73
+#define DEC_73                                     72
+#define DEC_72                                     71
+#define DEC_71                                     70
+#define DEC_70                                     69
+#define DEC_69                                     68
+#define DEC_68                                     67
+#define DEC_67                                     66
+#define DEC_66                                     65
+#define DEC_65                                     64
+#define DEC_64                                     63
+#define DEC_63                                     62
+#define DEC_62                                     61
+#define DEC_61                                     60
+#define DEC_60                                     59
+#define DEC_59                                     58
+#define DEC_58                                     57
+#define DEC_57                                     56
+#define DEC_56                                     55
+#define DEC_55                                     54
+#define DEC_54                                     53
+#define DEC_53                                     52
+#define DEC_52                                     51
+#define DEC_51                                     50
+#define DEC_50                                     49
+#define DEC_49                                     48
+#define DEC_48                                     47
+#define DEC_47                                     46
+#define DEC_46                                     45
+#define DEC_45                                     44
+#define DEC_44                                     43
+#define DEC_43                                     42
+#define DEC_42                                     41
+#define DEC_41                                     40
+#define DEC_40                                     39
+#define DEC_39                                     38
+#define DEC_38                                     37
+#define DEC_37                                     36
+#define DEC_36                                     35
+#define DEC_35                                     34
+#define DEC_34                                     33
+#define DEC_33                                     32
+#define DEC_32                                     31
+#define DEC_31                                     30
+#define DEC_30                                     29
+#define DEC_29                                     28
+#define DEC_28                                     27
+#define DEC_27                                     26
+#define DEC_26                                     25
+#define DEC_25                                     24
+#define DEC_24                                     23
+#define DEC_23                                     22
+#define DEC_22                                     21
+#define DEC_21                                     20
+#define DEC_20                                     19
+#define DEC_19                                     18
+#define DEC_18                                     17
+#define DEC_17                                     16
+#define DEC_16                                     15
+#define DEC_15                                     14
+#define DEC_14                                     13
+#define DEC_13                                     12
+#define DEC_12                                     11
+#define DEC_11                                     10
+#define DEC_10                                      9
+#define DEC_9                                       8
+#define DEC_8                                       7
+#define DEC_7                                       6
+#define DEC_6                                       5
+#define DEC_5                                       4
+#define DEC_4                                       3
+#define DEC_3                                       2
+#define DEC_2                                       1
+#define DEC_1                                       0
+#define DEC_(n)                                     DEC_##n
+
+
+/** Maximal number of repetitions supported by MRECURSION. */
+#define MRECURSION_LIMIT   256
+
+/** \brief Macro recursion.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count  The number of repetitious calls to macro. Valid values
+ *                   range from 0 to MRECURSION_LIMIT.
+ * \param[in] macro  A binary operation of the form macro(data, n).  This macro
+ *                   is expanded by MRECURSION with the current repetition number
+ *                   and the auxiliary data argument.
+ * \param[in] data   A recursive threshold, building on this to decline by times 
+ *                   defined with param count.
+ *
+ * \return       <tt>macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1)</tt>
+ */
+#define MRECURSION(count, macro, data) TPASTE2(MRECURSION, count) (macro, data)
+
+#define MRECURSION0(  macro, data)
+#define MRECURSION1(  macro, data)    MRECURSION0(  macro, DEC_(data))   macro(data, 0)
+#define MRECURSION2(  macro, data)    MRECURSION1(  macro, DEC_(data))   macro(data, 1)
+#define MRECURSION3(  macro, data)    MRECURSION2(  macro, DEC_(data))   macro(data, 2)
+#define MRECURSION4(  macro, data)    MRECURSION3(  macro, DEC_(data))   macro(data, 3)
+#define MRECURSION5(  macro, data)    MRECURSION4(  macro, DEC_(data))   macro(data, 4)
+#define MRECURSION6(  macro, data)    MRECURSION5(  macro, DEC_(data))   macro(data, 5)
+#define MRECURSION7(  macro, data)    MRECURSION6(  macro, DEC_(data))   macro(data, 6)
+#define MRECURSION8(  macro, data)    MRECURSION7(  macro, DEC_(data))   macro(data, 7)
+#define MRECURSION9(  macro, data)    MRECURSION8(  macro, DEC_(data))   macro(data, 8)
+#define MRECURSION10( macro, data)    MRECURSION9(  macro, DEC_(data))   macro(data, 9)
+#define MRECURSION11( macro, data)    MRECURSION10(  macro, DEC_(data))   macro(data, 10)
+#define MRECURSION12( macro, data)    MRECURSION11(  macro, DEC_(data))   macro(data, 11)
+#define MRECURSION13( macro, data)    MRECURSION12(  macro, DEC_(data))   macro(data, 12)
+#define MRECURSION14( macro, data)    MRECURSION13(  macro, DEC_(data))   macro(data, 13)
+#define MRECURSION15( macro, data)    MRECURSION14(  macro, DEC_(data))   macro(data, 14)
+#define MRECURSION16( macro, data)    MRECURSION15(  macro, DEC_(data))   macro(data, 15)
+#define MRECURSION17( macro, data)    MRECURSION16(  macro, DEC_(data))   macro(data, 16)
+#define MRECURSION18( macro, data)    MRECURSION17(  macro, DEC_(data))   macro(data, 17)
+#define MRECURSION19( macro, data)    MRECURSION18(  macro, DEC_(data))   macro(data, 18)
+#define MRECURSION20( macro, data)    MRECURSION19(  macro, DEC_(data))   macro(data, 19)
+#define MRECURSION21( macro, data)    MRECURSION20(  macro, DEC_(data))   macro(data, 20)
+#define MRECURSION22( macro, data)    MRECURSION21(  macro, DEC_(data))   macro(data, 21)
+#define MRECURSION23( macro, data)    MRECURSION22(  macro, DEC_(data))   macro(data, 22)
+#define MRECURSION24( macro, data)    MRECURSION23(  macro, DEC_(data))   macro(data, 23)
+#define MRECURSION25( macro, data)    MRECURSION24(  macro, DEC_(data))   macro(data, 24)
+#define MRECURSION26( macro, data)    MRECURSION25(  macro, DEC_(data))   macro(data, 25)
+#define MRECURSION27( macro, data)    MRECURSION26(  macro, DEC_(data))   macro(data, 26)
+#define MRECURSION28( macro, data)    MRECURSION27(  macro, DEC_(data))   macro(data, 27)
+#define MRECURSION29( macro, data)    MRECURSION28(  macro, DEC_(data))   macro(data, 28)
+#define MRECURSION30( macro, data)    MRECURSION29(  macro, DEC_(data))   macro(data, 29)
+#define MRECURSION31( macro, data)    MRECURSION30(  macro, DEC_(data))   macro(data, 30)
+#define MRECURSION32( macro, data)    MRECURSION31(  macro, DEC_(data))   macro(data, 31)
+#define MRECURSION33( macro, data)    MRECURSION32(  macro, DEC_(data))   macro(data, 32)
+#define MRECURSION34( macro, data)    MRECURSION33(  macro, DEC_(data))   macro(data, 33)
+#define MRECURSION35( macro, data)    MRECURSION34(  macro, DEC_(data))   macro(data, 34)
+#define MRECURSION36( macro, data)    MRECURSION35(  macro, DEC_(data))   macro(data, 35)
+#define MRECURSION37( macro, data)    MRECURSION36(  macro, DEC_(data))   macro(data, 36)
+#define MRECURSION38( macro, data)    MRECURSION37(  macro, DEC_(data))   macro(data, 37)
+#define MRECURSION39( macro, data)    MRECURSION38(  macro, DEC_(data))   macro(data, 38)
+#define MRECURSION40( macro, data)    MRECURSION39(  macro, DEC_(data))   macro(data, 39)
+#define MRECURSION41( macro, data)    MRECURSION40(  macro, DEC_(data))   macro(data, 40)
+#define MRECURSION42( macro, data)    MRECURSION41(  macro, DEC_(data))   macro(data, 41)
+#define MRECURSION43( macro, data)    MRECURSION42(  macro, DEC_(data))   macro(data, 42)
+#define MRECURSION44( macro, data)    MRECURSION43(  macro, DEC_(data))   macro(data, 43)
+#define MRECURSION45( macro, data)    MRECURSION44(  macro, DEC_(data))   macro(data, 44)
+#define MRECURSION46( macro, data)    MRECURSION45(  macro, DEC_(data))   macro(data, 45)
+#define MRECURSION47( macro, data)    MRECURSION46(  macro, DEC_(data))   macro(data, 46)
+#define MRECURSION48( macro, data)    MRECURSION47(  macro, DEC_(data))   macro(data, 47)
+#define MRECURSION49( macro, data)    MRECURSION48(  macro, DEC_(data))   macro(data, 48)
+#define MRECURSION50( macro, data)    MRECURSION49(  macro, DEC_(data))   macro(data, 49)
+#define MRECURSION51( macro, data)    MRECURSION50(  macro, DEC_(data))   macro(data, 50)
+#define MRECURSION52( macro, data)    MRECURSION51(  macro, DEC_(data))   macro(data, 51)
+#define MRECURSION53( macro, data)    MRECURSION52(  macro, DEC_(data))   macro(data, 52)
+#define MRECURSION54( macro, data)    MRECURSION53(  macro, DEC_(data))   macro(data, 53)
+#define MRECURSION55( macro, data)    MRECURSION54(  macro, DEC_(data))   macro(data, 54)
+#define MRECURSION56( macro, data)    MRECURSION55(  macro, DEC_(data))   macro(data, 55)
+#define MRECURSION57( macro, data)    MRECURSION56(  macro, DEC_(data))   macro(data, 56)
+#define MRECURSION58( macro, data)    MRECURSION57(  macro, DEC_(data))   macro(data, 57)
+#define MRECURSION59( macro, data)    MRECURSION58(  macro, DEC_(data))   macro(data, 58)
+#define MRECURSION60( macro, data)    MRECURSION59(  macro, DEC_(data))   macro(data, 59)
+#define MRECURSION61( macro, data)    MRECURSION60(  macro, DEC_(data))   macro(data, 60)
+#define MRECURSION62( macro, data)    MRECURSION61(  macro, DEC_(data))   macro(data, 61)
+#define MRECURSION63( macro, data)    MRECURSION62(  macro, DEC_(data))   macro(data, 62)
+#define MRECURSION64( macro, data)    MRECURSION63(  macro, DEC_(data))   macro(data, 63)
+#define MRECURSION65( macro, data)    MRECURSION64(  macro, DEC_(data))   macro(data, 64)
+#define MRECURSION66( macro, data)    MRECURSION65(  macro, DEC_(data))   macro(data, 65)
+#define MRECURSION67( macro, data)    MRECURSION66(  macro, DEC_(data))   macro(data, 66)
+#define MRECURSION68( macro, data)    MRECURSION67(  macro, DEC_(data))   macro(data, 67)
+#define MRECURSION69( macro, data)    MRECURSION68(  macro, DEC_(data))   macro(data, 68)
+#define MRECURSION70( macro, data)    MRECURSION69(  macro, DEC_(data))   macro(data, 69)
+#define MRECURSION71( macro, data)    MRECURSION70(  macro, DEC_(data))   macro(data, 70)
+#define MRECURSION72( macro, data)    MRECURSION71(  macro, DEC_(data))   macro(data, 71)
+#define MRECURSION73( macro, data)    MRECURSION72(  macro, DEC_(data))   macro(data, 72)
+#define MRECURSION74( macro, data)    MRECURSION73(  macro, DEC_(data))   macro(data, 73)
+#define MRECURSION75( macro, data)    MRECURSION74(  macro, DEC_(data))   macro(data, 74)
+#define MRECURSION76( macro, data)    MRECURSION75(  macro, DEC_(data))   macro(data, 75)
+#define MRECURSION77( macro, data)    MRECURSION76(  macro, DEC_(data))   macro(data, 76)
+#define MRECURSION78( macro, data)    MRECURSION77(  macro, DEC_(data))   macro(data, 77)
+#define MRECURSION79( macro, data)    MRECURSION78(  macro, DEC_(data))   macro(data, 78)
+#define MRECURSION80( macro, data)    MRECURSION79(  macro, DEC_(data))   macro(data, 79)
+#define MRECURSION81( macro, data)    MRECURSION80(  macro, DEC_(data))   macro(data, 80)
+#define MRECURSION82( macro, data)    MRECURSION81(  macro, DEC_(data))   macro(data, 81)
+#define MRECURSION83( macro, data)    MRECURSION82(  macro, DEC_(data))   macro(data, 82)
+#define MRECURSION84( macro, data)    MRECURSION83(  macro, DEC_(data))   macro(data, 83)
+#define MRECURSION85( macro, data)    MRECURSION84(  macro, DEC_(data))   macro(data, 84)
+#define MRECURSION86( macro, data)    MRECURSION85(  macro, DEC_(data))   macro(data, 85)
+#define MRECURSION87( macro, data)    MRECURSION86(  macro, DEC_(data))   macro(data, 86)
+#define MRECURSION88( macro, data)    MRECURSION87(  macro, DEC_(data))   macro(data, 87)
+#define MRECURSION89( macro, data)    MRECURSION88(  macro, DEC_(data))   macro(data, 88)
+#define MRECURSION90( macro, data)    MRECURSION89(  macro, DEC_(data))   macro(data, 89)
+#define MRECURSION91( macro, data)    MRECURSION90(  macro, DEC_(data))   macro(data, 90)
+#define MRECURSION92( macro, data)    MRECURSION91(  macro, DEC_(data))   macro(data, 91)
+#define MRECURSION93( macro, data)    MRECURSION92(  macro, DEC_(data))   macro(data, 92)
+#define MRECURSION94( macro, data)    MRECURSION93(  macro, DEC_(data))   macro(data, 93)
+#define MRECURSION95( macro, data)    MRECURSION94(  macro, DEC_(data))   macro(data, 94)
+#define MRECURSION96( macro, data)    MRECURSION95(  macro, DEC_(data))   macro(data, 95)
+#define MRECURSION97( macro, data)    MRECURSION96(  macro, DEC_(data))   macro(data, 96)
+#define MRECURSION98( macro, data)    MRECURSION97(  macro, DEC_(data))   macro(data, 97)
+#define MRECURSION99( macro, data)    MRECURSION98(  macro, DEC_(data))   macro(data, 98)
+#define MRECURSION100(macro, data)    MRECURSION99(  macro, DEC_(data))   macro(data, 99)
+#define MRECURSION101(macro, data)    MRECURSION100(  macro, DEC_(data))   macro(data, 100)
+#define MRECURSION102(macro, data)    MRECURSION101(  macro, DEC_(data))   macro(data, 101)
+#define MRECURSION103(macro, data)    MRECURSION102(  macro, DEC_(data))   macro(data, 102)
+#define MRECURSION104(macro, data)    MRECURSION103(  macro, DEC_(data))   macro(data, 103)
+#define MRECURSION105(macro, data)    MRECURSION104(  macro, DEC_(data))   macro(data, 104)
+#define MRECURSION106(macro, data)    MRECURSION105(  macro, DEC_(data))   macro(data, 105)
+#define MRECURSION107(macro, data)    MRECURSION106(  macro, DEC_(data))   macro(data, 106)
+#define MRECURSION108(macro, data)    MRECURSION107(  macro, DEC_(data))   macro(data, 107)
+#define MRECURSION109(macro, data)    MRECURSION108(  macro, DEC_(data))   macro(data, 108)
+#define MRECURSION110(macro, data)    MRECURSION109(  macro, DEC_(data))   macro(data, 109)
+#define MRECURSION111(macro, data)    MRECURSION110(  macro, DEC_(data))   macro(data, 110)
+#define MRECURSION112(macro, data)    MRECURSION111(  macro, DEC_(data))   macro(data, 111)
+#define MRECURSION113(macro, data)    MRECURSION112(  macro, DEC_(data))   macro(data, 112)
+#define MRECURSION114(macro, data)    MRECURSION113(  macro, DEC_(data))   macro(data, 113)
+#define MRECURSION115(macro, data)    MRECURSION114(  macro, DEC_(data))   macro(data, 114)
+#define MRECURSION116(macro, data)    MRECURSION115(  macro, DEC_(data))   macro(data, 115)
+#define MRECURSION117(macro, data)    MRECURSION116(  macro, DEC_(data))   macro(data, 116)
+#define MRECURSION118(macro, data)    MRECURSION117(  macro, DEC_(data))   macro(data, 117)
+#define MRECURSION119(macro, data)    MRECURSION118(  macro, DEC_(data))   macro(data, 118)
+#define MRECURSION120(macro, data)    MRECURSION119(  macro, DEC_(data))   macro(data, 119)
+#define MRECURSION121(macro, data)    MRECURSION120(  macro, DEC_(data))   macro(data, 120)
+#define MRECURSION122(macro, data)    MRECURSION121(  macro, DEC_(data))   macro(data, 121)
+#define MRECURSION123(macro, data)    MRECURSION122(  macro, DEC_(data))   macro(data, 122)
+#define MRECURSION124(macro, data)    MRECURSION123(  macro, DEC_(data))   macro(data, 123)
+#define MRECURSION125(macro, data)    MRECURSION124(  macro, DEC_(data))   macro(data, 124)
+#define MRECURSION126(macro, data)    MRECURSION125(  macro, DEC_(data))   macro(data, 125)
+#define MRECURSION127(macro, data)    MRECURSION126(  macro, DEC_(data))   macro(data, 126)
+#define MRECURSION128(macro, data)    MRECURSION127(  macro, DEC_(data))   macro(data, 127)
+#define MRECURSION129(macro, data)    MRECURSION128(  macro, DEC_(data))   macro(data, 128)
+#define MRECURSION130(macro, data)    MRECURSION129(  macro, DEC_(data))   macro(data, 129)
+#define MRECURSION131(macro, data)    MRECURSION130(  macro, DEC_(data))   macro(data, 130)
+#define MRECURSION132(macro, data)    MRECURSION131(  macro, DEC_(data))   macro(data, 131)
+#define MRECURSION133(macro, data)    MRECURSION132(  macro, DEC_(data))   macro(data, 132)
+#define MRECURSION134(macro, data)    MRECURSION133(  macro, DEC_(data))   macro(data, 133)
+#define MRECURSION135(macro, data)    MRECURSION134(  macro, DEC_(data))   macro(data, 134)
+#define MRECURSION136(macro, data)    MRECURSION135(  macro, DEC_(data))   macro(data, 135)
+#define MRECURSION137(macro, data)    MRECURSION136(  macro, DEC_(data))   macro(data, 136)
+#define MRECURSION138(macro, data)    MRECURSION137(  macro, DEC_(data))   macro(data, 137)
+#define MRECURSION139(macro, data)    MRECURSION138(  macro, DEC_(data))   macro(data, 138)
+#define MRECURSION140(macro, data)    MRECURSION139(  macro, DEC_(data))   macro(data, 139)
+#define MRECURSION141(macro, data)    MRECURSION140(  macro, DEC_(data))   macro(data, 140)
+#define MRECURSION142(macro, data)    MRECURSION141(  macro, DEC_(data))   macro(data, 141)
+#define MRECURSION143(macro, data)    MRECURSION142(  macro, DEC_(data))   macro(data, 142)
+#define MRECURSION144(macro, data)    MRECURSION143(  macro, DEC_(data))   macro(data, 143)
+#define MRECURSION145(macro, data)    MRECURSION144(  macro, DEC_(data))   macro(data, 144)
+#define MRECURSION146(macro, data)    MRECURSION145(  macro, DEC_(data))   macro(data, 145)
+#define MRECURSION147(macro, data)    MRECURSION146(  macro, DEC_(data))   macro(data, 146)
+#define MRECURSION148(macro, data)    MRECURSION147(  macro, DEC_(data))   macro(data, 147)
+#define MRECURSION149(macro, data)    MRECURSION148(  macro, DEC_(data))   macro(data, 148)
+#define MRECURSION150(macro, data)    MRECURSION149(  macro, DEC_(data))   macro(data, 149)
+#define MRECURSION151(macro, data)    MRECURSION150(  macro, DEC_(data))   macro(data, 150)
+#define MRECURSION152(macro, data)    MRECURSION151(  macro, DEC_(data))   macro(data, 151)
+#define MRECURSION153(macro, data)    MRECURSION152(  macro, DEC_(data))   macro(data, 152)
+#define MRECURSION154(macro, data)    MRECURSION153(  macro, DEC_(data))   macro(data, 153)
+#define MRECURSION155(macro, data)    MRECURSION154(  macro, DEC_(data))   macro(data, 154)
+#define MRECURSION156(macro, data)    MRECURSION155(  macro, DEC_(data))   macro(data, 155)
+#define MRECURSION157(macro, data)    MRECURSION156(  macro, DEC_(data))   macro(data, 156)
+#define MRECURSION158(macro, data)    MRECURSION157(  macro, DEC_(data))   macro(data, 157)
+#define MRECURSION159(macro, data)    MRECURSION158(  macro, DEC_(data))   macro(data, 158)
+#define MRECURSION160(macro, data)    MRECURSION159(  macro, DEC_(data))   macro(data, 159)
+#define MRECURSION161(macro, data)    MRECURSION160(  macro, DEC_(data))   macro(data, 160)
+#define MRECURSION162(macro, data)    MRECURSION161(  macro, DEC_(data))   macro(data, 161)
+#define MRECURSION163(macro, data)    MRECURSION162(  macro, DEC_(data))   macro(data, 162)
+#define MRECURSION164(macro, data)    MRECURSION163(  macro, DEC_(data))   macro(data, 163)
+#define MRECURSION165(macro, data)    MRECURSION164(  macro, DEC_(data))   macro(data, 164)
+#define MRECURSION166(macro, data)    MRECURSION165(  macro, DEC_(data))   macro(data, 165)
+#define MRECURSION167(macro, data)    MRECURSION166(  macro, DEC_(data))   macro(data, 166)
+#define MRECURSION168(macro, data)    MRECURSION167(  macro, DEC_(data))   macro(data, 167)
+#define MRECURSION169(macro, data)    MRECURSION168(  macro, DEC_(data))   macro(data, 168)
+#define MRECURSION170(macro, data)    MRECURSION169(  macro, DEC_(data))   macro(data, 169)
+#define MRECURSION171(macro, data)    MRECURSION170(  macro, DEC_(data))   macro(data, 170)
+#define MRECURSION172(macro, data)    MRECURSION171(  macro, DEC_(data))   macro(data, 171)
+#define MRECURSION173(macro, data)    MRECURSION172(  macro, DEC_(data))   macro(data, 172)
+#define MRECURSION174(macro, data)    MRECURSION173(  macro, DEC_(data))   macro(data, 173)
+#define MRECURSION175(macro, data)    MRECURSION174(  macro, DEC_(data))   macro(data, 174)
+#define MRECURSION176(macro, data)    MRECURSION175(  macro, DEC_(data))   macro(data, 175)
+#define MRECURSION177(macro, data)    MRECURSION176(  macro, DEC_(data))   macro(data, 176)
+#define MRECURSION178(macro, data)    MRECURSION177(  macro, DEC_(data))   macro(data, 177)
+#define MRECURSION179(macro, data)    MRECURSION178(  macro, DEC_(data))   macro(data, 178)
+#define MRECURSION180(macro, data)    MRECURSION179(  macro, DEC_(data))   macro(data, 179)
+#define MRECURSION181(macro, data)    MRECURSION180(  macro, DEC_(data))   macro(data, 180)
+#define MRECURSION182(macro, data)    MRECURSION181(  macro, DEC_(data))   macro(data, 181)
+#define MRECURSION183(macro, data)    MRECURSION182(  macro, DEC_(data))   macro(data, 182)
+#define MRECURSION184(macro, data)    MRECURSION183(  macro, DEC_(data))   macro(data, 183)
+#define MRECURSION185(macro, data)    MRECURSION184(  macro, DEC_(data))   macro(data, 184)
+#define MRECURSION186(macro, data)    MRECURSION185(  macro, DEC_(data))   macro(data, 185)
+#define MRECURSION187(macro, data)    MRECURSION186(  macro, DEC_(data))   macro(data, 186)
+#define MRECURSION188(macro, data)    MRECURSION187(  macro, DEC_(data))   macro(data, 187)
+#define MRECURSION189(macro, data)    MRECURSION188(  macro, DEC_(data))   macro(data, 188)
+#define MRECURSION190(macro, data)    MRECURSION189(  macro, DEC_(data))   macro(data, 189)
+#define MRECURSION191(macro, data)    MRECURSION190(  macro, DEC_(data))   macro(data, 190)
+#define MRECURSION192(macro, data)    MRECURSION191(  macro, DEC_(data))   macro(data, 191)
+#define MRECURSION193(macro, data)    MRECURSION192(  macro, DEC_(data))   macro(data, 192)
+#define MRECURSION194(macro, data)    MRECURSION193(  macro, DEC_(data))   macro(data, 193)
+#define MRECURSION195(macro, data)    MRECURSION194(  macro, DEC_(data))   macro(data, 194)
+#define MRECURSION196(macro, data)    MRECURSION195(  macro, DEC_(data))   macro(data, 195)
+#define MRECURSION197(macro, data)    MRECURSION196(  macro, DEC_(data))   macro(data, 196)
+#define MRECURSION198(macro, data)    MRECURSION197(  macro, DEC_(data))   macro(data, 197)
+#define MRECURSION199(macro, data)    MRECURSION198(  macro, DEC_(data))   macro(data, 198)
+#define MRECURSION200(macro, data)    MRECURSION199(  macro, DEC_(data))   macro(data, 199)
+#define MRECURSION201(macro, data)    MRECURSION200(  macro, DEC_(data))   macro(data, 200)
+#define MRECURSION202(macro, data)    MRECURSION201(  macro, DEC_(data))   macro(data, 201)
+#define MRECURSION203(macro, data)    MRECURSION202(  macro, DEC_(data))   macro(data, 202)
+#define MRECURSION204(macro, data)    MRECURSION203(  macro, DEC_(data))   macro(data, 203)
+#define MRECURSION205(macro, data)    MRECURSION204(  macro, DEC_(data))   macro(data, 204)
+#define MRECURSION206(macro, data)    MRECURSION205(  macro, DEC_(data))   macro(data, 205)
+#define MRECURSION207(macro, data)    MRECURSION206(  macro, DEC_(data))   macro(data, 206)
+#define MRECURSION208(macro, data)    MRECURSION207(  macro, DEC_(data))   macro(data, 207)
+#define MRECURSION209(macro, data)    MRECURSION208(  macro, DEC_(data))   macro(data, 208)
+#define MRECURSION210(macro, data)    MRECURSION209(  macro, DEC_(data))   macro(data, 209)
+#define MRECURSION211(macro, data)    MRECURSION210(  macro, DEC_(data))   macro(data, 210)
+#define MRECURSION212(macro, data)    MRECURSION211(  macro, DEC_(data))   macro(data, 211)
+#define MRECURSION213(macro, data)    MRECURSION212(  macro, DEC_(data))   macro(data, 212)
+#define MRECURSION214(macro, data)    MRECURSION213(  macro, DEC_(data))   macro(data, 213)
+#define MRECURSION215(macro, data)    MRECURSION214(  macro, DEC_(data))   macro(data, 214)
+#define MRECURSION216(macro, data)    MRECURSION215(  macro, DEC_(data))   macro(data, 215)
+#define MRECURSION217(macro, data)    MRECURSION216(  macro, DEC_(data))   macro(data, 216)
+#define MRECURSION218(macro, data)    MRECURSION217(  macro, DEC_(data))   macro(data, 217)
+#define MRECURSION219(macro, data)    MRECURSION218(  macro, DEC_(data))   macro(data, 218)
+#define MRECURSION220(macro, data)    MRECURSION219(  macro, DEC_(data))   macro(data, 219)
+#define MRECURSION221(macro, data)    MRECURSION220(  macro, DEC_(data))   macro(data, 220)
+#define MRECURSION222(macro, data)    MRECURSION221(  macro, DEC_(data))   macro(data, 221)
+#define MRECURSION223(macro, data)    MRECURSION222(  macro, DEC_(data))   macro(data, 222)
+#define MRECURSION224(macro, data)    MRECURSION223(  macro, DEC_(data))   macro(data, 223)
+#define MRECURSION225(macro, data)    MRECURSION224(  macro, DEC_(data))   macro(data, 224)
+#define MRECURSION226(macro, data)    MRECURSION225(  macro, DEC_(data))   macro(data, 225)
+#define MRECURSION227(macro, data)    MRECURSION226(  macro, DEC_(data))   macro(data, 226)
+#define MRECURSION228(macro, data)    MRECURSION227(  macro, DEC_(data))   macro(data, 227)
+#define MRECURSION229(macro, data)    MRECURSION228(  macro, DEC_(data))   macro(data, 228)
+#define MRECURSION230(macro, data)    MRECURSION229(  macro, DEC_(data))   macro(data, 229)
+#define MRECURSION231(macro, data)    MRECURSION230(  macro, DEC_(data))   macro(data, 230)
+#define MRECURSION232(macro, data)    MRECURSION231(  macro, DEC_(data))   macro(data, 231)
+#define MRECURSION233(macro, data)    MRECURSION232(  macro, DEC_(data))   macro(data, 232)
+#define MRECURSION234(macro, data)    MRECURSION233(  macro, DEC_(data))   macro(data, 233)
+#define MRECURSION235(macro, data)    MRECURSION234(  macro, DEC_(data))   macro(data, 234)
+#define MRECURSION236(macro, data)    MRECURSION235(  macro, DEC_(data))   macro(data, 235)
+#define MRECURSION237(macro, data)    MRECURSION236(  macro, DEC_(data))   macro(data, 236)
+#define MRECURSION238(macro, data)    MRECURSION237(  macro, DEC_(data))   macro(data, 237)
+#define MRECURSION239(macro, data)    MRECURSION238(  macro, DEC_(data))   macro(data, 238)
+#define MRECURSION240(macro, data)    MRECURSION239(  macro, DEC_(data))   macro(data, 239)
+#define MRECURSION241(macro, data)    MRECURSION240(  macro, DEC_(data))   macro(data, 240)
+#define MRECURSION242(macro, data)    MRECURSION241(  macro, DEC_(data))   macro(data, 241)
+#define MRECURSION243(macro, data)    MRECURSION242(  macro, DEC_(data))   macro(data, 242)
+#define MRECURSION244(macro, data)    MRECURSION243(  macro, DEC_(data))   macro(data, 243)
+#define MRECURSION245(macro, data)    MRECURSION244(  macro, DEC_(data))   macro(data, 244)
+#define MRECURSION246(macro, data)    MRECURSION245(  macro, DEC_(data))   macro(data, 245)
+#define MRECURSION247(macro, data)    MRECURSION246(  macro, DEC_(data))   macro(data, 246)
+#define MRECURSION248(macro, data)    MRECURSION247(  macro, DEC_(data))   macro(data, 247)
+#define MRECURSION249(macro, data)    MRECURSION248(  macro, DEC_(data))   macro(data, 248)
+#define MRECURSION250(macro, data)    MRECURSION249(  macro, DEC_(data))   macro(data, 249)
+#define MRECURSION251(macro, data)    MRECURSION250(  macro, DEC_(data))   macro(data, 250)
+#define MRECURSION252(macro, data)    MRECURSION251(  macro, DEC_(data))   macro(data, 251)
+#define MRECURSION253(macro, data)    MRECURSION252(  macro, DEC_(data))   macro(data, 252)
+#define MRECURSION254(macro, data)    MRECURSION253(  macro, DEC_(data))   macro(data, 253)
+#define MRECURSION255(macro, data)    MRECURSION254(  macro, DEC_(data))   macro(data, 254)
+#define MRECURSION256(macro, data)    MRECURSION255(  macro, DEC_(data))   macro(data, 255)
+
+/** @} */
+
+#endif  /* _MRECURSION_H_ */
diff --git a/uf2-samdx1/inc/preprocessor/mrepeat.h b/uf2-samdx1/inc/preprocessor/mrepeat.h
new file mode 100644
index 00000000..369afa80
--- /dev/null
+++ b/uf2-samdx1/inc/preprocessor/mrepeat.h
@@ -0,0 +1,321 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _MREPEAT_H_
+#define _MREPEAT_H_
+
+/**
+ * \defgroup group_sam0_utils_mrepeat Preprocessor - Macro Repeat
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+#include "preprocessor.h"
+
+/** Maximal number of repetitions supported by MREPEAT. */
+#define MREPEAT_LIMIT   256
+
+/** \brief Macro repeat.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param[in] count  The number of repetitious calls to macro. Valid values
+ *                   range from 0 to MREPEAT_LIMIT.
+ * \param[in] macro  A binary operation of the form macro(n, data). This macro
+ *                   is expanded by MREPEAT with the current repetition number
+ *                   and the auxiliary data argument.
+ * \param[in] data   Auxiliary data passed to macro.
+ *
+ * \return       <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
+ */
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count) (macro, data)
+
+#define MREPEAT0(  macro, data)
+#define MREPEAT1(  macro, data)    MREPEAT0(  macro, data)   macro(  0, data)
+#define MREPEAT2(  macro, data)    MREPEAT1(  macro, data)   macro(  1, data)
+#define MREPEAT3(  macro, data)    MREPEAT2(  macro, data)   macro(  2, data)
+#define MREPEAT4(  macro, data)    MREPEAT3(  macro, data)   macro(  3, data)
+#define MREPEAT5(  macro, data)    MREPEAT4(  macro, data)   macro(  4, data)
+#define MREPEAT6(  macro, data)    MREPEAT5(  macro, data)   macro(  5, data)
+#define MREPEAT7(  macro, data)    MREPEAT6(  macro, data)   macro(  6, data)
+#define MREPEAT8(  macro, data)    MREPEAT7(  macro, data)   macro(  7, data)
+#define MREPEAT9(  macro, data)    MREPEAT8(  macro, data)   macro(  8, data)
+#define MREPEAT10( macro, data)    MREPEAT9(  macro, data)   macro(  9, data)
+#define MREPEAT11( macro, data)    MREPEAT10( macro, data)   macro( 10, data)
+#define MREPEAT12( macro, data)    MREPEAT11( macro, data)   macro( 11, data)
+#define MREPEAT13( macro, data)    MREPEAT12( macro, data)   macro( 12, data)
+#define MREPEAT14( macro, data)    MREPEAT13( macro, data)   macro( 13, data)
+#define MREPEAT15( macro, data)    MREPEAT14( macro, data)   macro( 14, data)
+#define MREPEAT16( macro, data)    MREPEAT15( macro, data)   macro( 15, data)
+#define MREPEAT17( macro, data)    MREPEAT16( macro, data)   macro( 16, data)
+#define MREPEAT18( macro, data)    MREPEAT17( macro, data)   macro( 17, data)
+#define MREPEAT19( macro, data)    MREPEAT18( macro, data)   macro( 18, data)
+#define MREPEAT20( macro, data)    MREPEAT19( macro, data)   macro( 19, data)
+#define MREPEAT21( macro, data)    MREPEAT20( macro, data)   macro( 20, data)
+#define MREPEAT22( macro, data)    MREPEAT21( macro, data)   macro( 21, data)
+#define MREPEAT23( macro, data)    MREPEAT22( macro, data)   macro( 22, data)
+#define MREPEAT24( macro, data)    MREPEAT23( macro, data)   macro( 23, data)
+#define MREPEAT25( macro, data)    MREPEAT24( macro, data)   macro( 24, data)
+#define MREPEAT26( macro, data)    MREPEAT25( macro, data)   macro( 25, data)
+#define MREPEAT27( macro, data)    MREPEAT26( macro, data)   macro( 26, data)
+#define MREPEAT28( macro, data)    MREPEAT27( macro, data)   macro( 27, data)
+#define MREPEAT29( macro, data)    MREPEAT28( macro, data)   macro( 28, data)
+#define MREPEAT30( macro, data)    MREPEAT29( macro, data)   macro( 29, data)
+#define MREPEAT31( macro, data)    MREPEAT30( macro, data)   macro( 30, data)
+#define MREPEAT32( macro, data)    MREPEAT31( macro, data)   macro( 31, data)
+#define MREPEAT33( macro, data)    MREPEAT32( macro, data)   macro( 32, data)
+#define MREPEAT34( macro, data)    MREPEAT33( macro, data)   macro( 33, data)
+#define MREPEAT35( macro, data)    MREPEAT34( macro, data)   macro( 34, data)
+#define MREPEAT36( macro, data)    MREPEAT35( macro, data)   macro( 35, data)
+#define MREPEAT37( macro, data)    MREPEAT36( macro, data)   macro( 36, data)
+#define MREPEAT38( macro, data)    MREPEAT37( macro, data)   macro( 37, data)
+#define MREPEAT39( macro, data)    MREPEAT38( macro, data)   macro( 38, data)
+#define MREPEAT40( macro, data)    MREPEAT39( macro, data)   macro( 39, data)
+#define MREPEAT41( macro, data)    MREPEAT40( macro, data)   macro( 40, data)
+#define MREPEAT42( macro, data)    MREPEAT41( macro, data)   macro( 41, data)
+#define MREPEAT43( macro, data)    MREPEAT42( macro, data)   macro( 42, data)
+#define MREPEAT44( macro, data)    MREPEAT43( macro, data)   macro( 43, data)
+#define MREPEAT45( macro, data)    MREPEAT44( macro, data)   macro( 44, data)
+#define MREPEAT46( macro, data)    MREPEAT45( macro, data)   macro( 45, data)
+#define MREPEAT47( macro, data)    MREPEAT46( macro, data)   macro( 46, data)
+#define MREPEAT48( macro, data)    MREPEAT47( macro, data)   macro( 47, data)
+#define MREPEAT49( macro, data)    MREPEAT48( macro, data)   macro( 48, data)
+#define MREPEAT50( macro, data)    MREPEAT49( macro, data)   macro( 49, data)
+#define MREPEAT51( macro, data)    MREPEAT50( macro, data)   macro( 50, data)
+#define MREPEAT52( macro, data)    MREPEAT51( macro, data)   macro( 51, data)
+#define MREPEAT53( macro, data)    MREPEAT52( macro, data)   macro( 52, data)
+#define MREPEAT54( macro, data)    MREPEAT53( macro, data)   macro( 53, data)
+#define MREPEAT55( macro, data)    MREPEAT54( macro, data)   macro( 54, data)
+#define MREPEAT56( macro, data)    MREPEAT55( macro, data)   macro( 55, data)
+#define MREPEAT57( macro, data)    MREPEAT56( macro, data)   macro( 56, data)
+#define MREPEAT58( macro, data)    MREPEAT57( macro, data)   macro( 57, data)
+#define MREPEAT59( macro, data)    MREPEAT58( macro, data)   macro( 58, data)
+#define MREPEAT60( macro, data)    MREPEAT59( macro, data)   macro( 59, data)
+#define MREPEAT61( macro, data)    MREPEAT60( macro, data)   macro( 60, data)
+#define MREPEAT62( macro, data)    MREPEAT61( macro, data)   macro( 61, data)
+#define MREPEAT63( macro, data)    MREPEAT62( macro, data)   macro( 62, data)
+#define MREPEAT64( macro, data)    MREPEAT63( macro, data)   macro( 63, data)
+#define MREPEAT65( macro, data)    MREPEAT64( macro, data)   macro( 64, data)
+#define MREPEAT66( macro, data)    MREPEAT65( macro, data)   macro( 65, data)
+#define MREPEAT67( macro, data)    MREPEAT66( macro, data)   macro( 66, data)
+#define MREPEAT68( macro, data)    MREPEAT67( macro, data)   macro( 67, data)
+#define MREPEAT69( macro, data)    MREPEAT68( macro, data)   macro( 68, data)
+#define MREPEAT70( macro, data)    MREPEAT69( macro, data)   macro( 69, data)
+#define MREPEAT71( macro, data)    MREPEAT70( macro, data)   macro( 70, data)
+#define MREPEAT72( macro, data)    MREPEAT71( macro, data)   macro( 71, data)
+#define MREPEAT73( macro, data)    MREPEAT72( macro, data)   macro( 72, data)
+#define MREPEAT74( macro, data)    MREPEAT73( macro, data)   macro( 73, data)
+#define MREPEAT75( macro, data)    MREPEAT74( macro, data)   macro( 74, data)
+#define MREPEAT76( macro, data)    MREPEAT75( macro, data)   macro( 75, data)
+#define MREPEAT77( macro, data)    MREPEAT76( macro, data)   macro( 76, data)
+#define MREPEAT78( macro, data)    MREPEAT77( macro, data)   macro( 77, data)
+#define MREPEAT79( macro, data)    MREPEAT78( macro, data)   macro( 78, data)
+#define MREPEAT80( macro, data)    MREPEAT79( macro, data)   macro( 79, data)
+#define MREPEAT81( macro, data)    MREPEAT80( macro, data)   macro( 80, data)
+#define MREPEAT82( macro, data)    MREPEAT81( macro, data)   macro( 81, data)
+#define MREPEAT83( macro, data)    MREPEAT82( macro, data)   macro( 82, data)
+#define MREPEAT84( macro, data)    MREPEAT83( macro, data)   macro( 83, data)
+#define MREPEAT85( macro, data)    MREPEAT84( macro, data)   macro( 84, data)
+#define MREPEAT86( macro, data)    MREPEAT85( macro, data)   macro( 85, data)
+#define MREPEAT87( macro, data)    MREPEAT86( macro, data)   macro( 86, data)
+#define MREPEAT88( macro, data)    MREPEAT87( macro, data)   macro( 87, data)
+#define MREPEAT89( macro, data)    MREPEAT88( macro, data)   macro( 88, data)
+#define MREPEAT90( macro, data)    MREPEAT89( macro, data)   macro( 89, data)
+#define MREPEAT91( macro, data)    MREPEAT90( macro, data)   macro( 90, data)
+#define MREPEAT92( macro, data)    MREPEAT91( macro, data)   macro( 91, data)
+#define MREPEAT93( macro, data)    MREPEAT92( macro, data)   macro( 92, data)
+#define MREPEAT94( macro, data)    MREPEAT93( macro, data)   macro( 93, data)
+#define MREPEAT95( macro, data)    MREPEAT94( macro, data)   macro( 94, data)
+#define MREPEAT96( macro, data)    MREPEAT95( macro, data)   macro( 95, data)
+#define MREPEAT97( macro, data)    MREPEAT96( macro, data)   macro( 96, data)
+#define MREPEAT98( macro, data)    MREPEAT97( macro, data)   macro( 97, data)
+#define MREPEAT99( macro, data)    MREPEAT98( macro, data)   macro( 98, data)
+#define MREPEAT100(macro, data)    MREPEAT99( macro, data)   macro( 99, data)
+#define MREPEAT101(macro, data)    MREPEAT100(macro, data)   macro(100, data)
+#define MREPEAT102(macro, data)    MREPEAT101(macro, data)   macro(101, data)
+#define MREPEAT103(macro, data)    MREPEAT102(macro, data)   macro(102, data)
+#define MREPEAT104(macro, data)    MREPEAT103(macro, data)   macro(103, data)
+#define MREPEAT105(macro, data)    MREPEAT104(macro, data)   macro(104, data)
+#define MREPEAT106(macro, data)    MREPEAT105(macro, data)   macro(105, data)
+#define MREPEAT107(macro, data)    MREPEAT106(macro, data)   macro(106, data)
+#define MREPEAT108(macro, data)    MREPEAT107(macro, data)   macro(107, data)
+#define MREPEAT109(macro, data)    MREPEAT108(macro, data)   macro(108, data)
+#define MREPEAT110(macro, data)    MREPEAT109(macro, data)   macro(109, data)
+#define MREPEAT111(macro, data)    MREPEAT110(macro, data)   macro(110, data)
+#define MREPEAT112(macro, data)    MREPEAT111(macro, data)   macro(111, data)
+#define MREPEAT113(macro, data)    MREPEAT112(macro, data)   macro(112, data)
+#define MREPEAT114(macro, data)    MREPEAT113(macro, data)   macro(113, data)
+#define MREPEAT115(macro, data)    MREPEAT114(macro, data)   macro(114, data)
+#define MREPEAT116(macro, data)    MREPEAT115(macro, data)   macro(115, data)
+#define MREPEAT117(macro, data)    MREPEAT116(macro, data)   macro(116, data)
+#define MREPEAT118(macro, data)    MREPEAT117(macro, data)   macro(117, data)
+#define MREPEAT119(macro, data)    MREPEAT118(macro, data)   macro(118, data)
+#define MREPEAT120(macro, data)    MREPEAT119(macro, data)   macro(119, data)
+#define MREPEAT121(macro, data)    MREPEAT120(macro, data)   macro(120, data)
+#define MREPEAT122(macro, data)    MREPEAT121(macro, data)   macro(121, data)
+#define MREPEAT123(macro, data)    MREPEAT122(macro, data)   macro(122, data)
+#define MREPEAT124(macro, data)    MREPEAT123(macro, data)   macro(123, data)
+#define MREPEAT125(macro, data)    MREPEAT124(macro, data)   macro(124, data)
+#define MREPEAT126(macro, data)    MREPEAT125(macro, data)   macro(125, data)
+#define MREPEAT127(macro, data)    MREPEAT126(macro, data)   macro(126, data)
+#define MREPEAT128(macro, data)    MREPEAT127(macro, data)   macro(127, data)
+#define MREPEAT129(macro, data)    MREPEAT128(macro, data)   macro(128, data)
+#define MREPEAT130(macro, data)    MREPEAT129(macro, data)   macro(129, data)
+#define MREPEAT131(macro, data)    MREPEAT130(macro, data)   macro(130, data)
+#define MREPEAT132(macro, data)    MREPEAT131(macro, data)   macro(131, data)
+#define MREPEAT133(macro, data)    MREPEAT132(macro, data)   macro(132, data)
+#define MREPEAT134(macro, data)    MREPEAT133(macro, data)   macro(133, data)
+#define MREPEAT135(macro, data)    MREPEAT134(macro, data)   macro(134, data)
+#define MREPEAT136(macro, data)    MREPEAT135(macro, data)   macro(135, data)
+#define MREPEAT137(macro, data)    MREPEAT136(macro, data)   macro(136, data)
+#define MREPEAT138(macro, data)    MREPEAT137(macro, data)   macro(137, data)
+#define MREPEAT139(macro, data)    MREPEAT138(macro, data)   macro(138, data)
+#define MREPEAT140(macro, data)    MREPEAT139(macro, data)   macro(139, data)
+#define MREPEAT141(macro, data)    MREPEAT140(macro, data)   macro(140, data)
+#define MREPEAT142(macro, data)    MREPEAT141(macro, data)   macro(141, data)
+#define MREPEAT143(macro, data)    MREPEAT142(macro, data)   macro(142, data)
+#define MREPEAT144(macro, data)    MREPEAT143(macro, data)   macro(143, data)
+#define MREPEAT145(macro, data)    MREPEAT144(macro, data)   macro(144, data)
+#define MREPEAT146(macro, data)    MREPEAT145(macro, data)   macro(145, data)
+#define MREPEAT147(macro, data)    MREPEAT146(macro, data)   macro(146, data)
+#define MREPEAT148(macro, data)    MREPEAT147(macro, data)   macro(147, data)
+#define MREPEAT149(macro, data)    MREPEAT148(macro, data)   macro(148, data)
+#define MREPEAT150(macro, data)    MREPEAT149(macro, data)   macro(149, data)
+#define MREPEAT151(macro, data)    MREPEAT150(macro, data)   macro(150, data)
+#define MREPEAT152(macro, data)    MREPEAT151(macro, data)   macro(151, data)
+#define MREPEAT153(macro, data)    MREPEAT152(macro, data)   macro(152, data)
+#define MREPEAT154(macro, data)    MREPEAT153(macro, data)   macro(153, data)
+#define MREPEAT155(macro, data)    MREPEAT154(macro, data)   macro(154, data)
+#define MREPEAT156(macro, data)    MREPEAT155(macro, data)   macro(155, data)
+#define MREPEAT157(macro, data)    MREPEAT156(macro, data)   macro(156, data)
+#define MREPEAT158(macro, data)    MREPEAT157(macro, data)   macro(157, data)
+#define MREPEAT159(macro, data)    MREPEAT158(macro, data)   macro(158, data)
+#define MREPEAT160(macro, data)    MREPEAT159(macro, data)   macro(159, data)
+#define MREPEAT161(macro, data)    MREPEAT160(macro, data)   macro(160, data)
+#define MREPEAT162(macro, data)    MREPEAT161(macro, data)   macro(161, data)
+#define MREPEAT163(macro, data)    MREPEAT162(macro, data)   macro(162, data)
+#define MREPEAT164(macro, data)    MREPEAT163(macro, data)   macro(163, data)
+#define MREPEAT165(macro, data)    MREPEAT164(macro, data)   macro(164, data)
+#define MREPEAT166(macro, data)    MREPEAT165(macro, data)   macro(165, data)
+#define MREPEAT167(macro, data)    MREPEAT166(macro, data)   macro(166, data)
+#define MREPEAT168(macro, data)    MREPEAT167(macro, data)   macro(167, data)
+#define MREPEAT169(macro, data)    MREPEAT168(macro, data)   macro(168, data)
+#define MREPEAT170(macro, data)    MREPEAT169(macro, data)   macro(169, data)
+#define MREPEAT171(macro, data)    MREPEAT170(macro, data)   macro(170, data)
+#define MREPEAT172(macro, data)    MREPEAT171(macro, data)   macro(171, data)
+#define MREPEAT173(macro, data)    MREPEAT172(macro, data)   macro(172, data)
+#define MREPEAT174(macro, data)    MREPEAT173(macro, data)   macro(173, data)
+#define MREPEAT175(macro, data)    MREPEAT174(macro, data)   macro(174, data)
+#define MREPEAT176(macro, data)    MREPEAT175(macro, data)   macro(175, data)
+#define MREPEAT177(macro, data)    MREPEAT176(macro, data)   macro(176, data)
+#define MREPEAT178(macro, data)    MREPEAT177(macro, data)   macro(177, data)
+#define MREPEAT179(macro, data)    MREPEAT178(macro, data)   macro(178, data)
+#define MREPEAT180(macro, data)    MREPEAT179(macro, data)   macro(179, data)
+#define MREPEAT181(macro, data)    MREPEAT180(macro, data)   macro(180, data)
+#define MREPEAT182(macro, data)    MREPEAT181(macro, data)   macro(181, data)
+#define MREPEAT183(macro, data)    MREPEAT182(macro, data)   macro(182, data)
+#define MREPEAT184(macro, data)    MREPEAT183(macro, data)   macro(183, data)
+#define MREPEAT185(macro, data)    MREPEAT184(macro, data)   macro(184, data)
+#define MREPEAT186(macro, data)    MREPEAT185(macro, data)   macro(185, data)
+#define MREPEAT187(macro, data)    MREPEAT186(macro, data)   macro(186, data)
+#define MREPEAT188(macro, data)    MREPEAT187(macro, data)   macro(187, data)
+#define MREPEAT189(macro, data)    MREPEAT188(macro, data)   macro(188, data)
+#define MREPEAT190(macro, data)    MREPEAT189(macro, data)   macro(189, data)
+#define MREPEAT191(macro, data)    MREPEAT190(macro, data)   macro(190, data)
+#define MREPEAT192(macro, data)    MREPEAT191(macro, data)   macro(191, data)
+#define MREPEAT193(macro, data)    MREPEAT192(macro, data)   macro(192, data)
+#define MREPEAT194(macro, data)    MREPEAT193(macro, data)   macro(193, data)
+#define MREPEAT195(macro, data)    MREPEAT194(macro, data)   macro(194, data)
+#define MREPEAT196(macro, data)    MREPEAT195(macro, data)   macro(195, data)
+#define MREPEAT197(macro, data)    MREPEAT196(macro, data)   macro(196, data)
+#define MREPEAT198(macro, data)    MREPEAT197(macro, data)   macro(197, data)
+#define MREPEAT199(macro, data)    MREPEAT198(macro, data)   macro(198, data)
+#define MREPEAT200(macro, data)    MREPEAT199(macro, data)   macro(199, data)
+#define MREPEAT201(macro, data)    MREPEAT200(macro, data)   macro(200, data)
+#define MREPEAT202(macro, data)    MREPEAT201(macro, data)   macro(201, data)
+#define MREPEAT203(macro, data)    MREPEAT202(macro, data)   macro(202, data)
+#define MREPEAT204(macro, data)    MREPEAT203(macro, data)   macro(203, data)
+#define MREPEAT205(macro, data)    MREPEAT204(macro, data)   macro(204, data)
+#define MREPEAT206(macro, data)    MREPEAT205(macro, data)   macro(205, data)
+#define MREPEAT207(macro, data)    MREPEAT206(macro, data)   macro(206, data)
+#define MREPEAT208(macro, data)    MREPEAT207(macro, data)   macro(207, data)
+#define MREPEAT209(macro, data)    MREPEAT208(macro, data)   macro(208, data)
+#define MREPEAT210(macro, data)    MREPEAT209(macro, data)   macro(209, data)
+#define MREPEAT211(macro, data)    MREPEAT210(macro, data)   macro(210, data)
+#define MREPEAT212(macro, data)    MREPEAT211(macro, data)   macro(211, data)
+#define MREPEAT213(macro, data)    MREPEAT212(macro, data)   macro(212, data)
+#define MREPEAT214(macro, data)    MREPEAT213(macro, data)   macro(213, data)
+#define MREPEAT215(macro, data)    MREPEAT214(macro, data)   macro(214, data)
+#define MREPEAT216(macro, data)    MREPEAT215(macro, data)   macro(215, data)
+#define MREPEAT217(macro, data)    MREPEAT216(macro, data)   macro(216, data)
+#define MREPEAT218(macro, data)    MREPEAT217(macro, data)   macro(217, data)
+#define MREPEAT219(macro, data)    MREPEAT218(macro, data)   macro(218, data)
+#define MREPEAT220(macro, data)    MREPEAT219(macro, data)   macro(219, data)
+#define MREPEAT221(macro, data)    MREPEAT220(macro, data)   macro(220, data)
+#define MREPEAT222(macro, data)    MREPEAT221(macro, data)   macro(221, data)
+#define MREPEAT223(macro, data)    MREPEAT222(macro, data)   macro(222, data)
+#define MREPEAT224(macro, data)    MREPEAT223(macro, data)   macro(223, data)
+#define MREPEAT225(macro, data)    MREPEAT224(macro, data)   macro(224, data)
+#define MREPEAT226(macro, data)    MREPEAT225(macro, data)   macro(225, data)
+#define MREPEAT227(macro, data)    MREPEAT226(macro, data)   macro(226, data)
+#define MREPEAT228(macro, data)    MREPEAT227(macro, data)   macro(227, data)
+#define MREPEAT229(macro, data)    MREPEAT228(macro, data)   macro(228, data)
+#define MREPEAT230(macro, data)    MREPEAT229(macro, data)   macro(229, data)
+#define MREPEAT231(macro, data)    MREPEAT230(macro, data)   macro(230, data)
+#define MREPEAT232(macro, data)    MREPEAT231(macro, data)   macro(231, data)
+#define MREPEAT233(macro, data)    MREPEAT232(macro, data)   macro(232, data)
+#define MREPEAT234(macro, data)    MREPEAT233(macro, data)   macro(233, data)
+#define MREPEAT235(macro, data)    MREPEAT234(macro, data)   macro(234, data)
+#define MREPEAT236(macro, data)    MREPEAT235(macro, data)   macro(235, data)
+#define MREPEAT237(macro, data)    MREPEAT236(macro, data)   macro(236, data)
+#define MREPEAT238(macro, data)    MREPEAT237(macro, data)   macro(237, data)
+#define MREPEAT239(macro, data)    MREPEAT238(macro, data)   macro(238, data)
+#define MREPEAT240(macro, data)    MREPEAT239(macro, data)   macro(239, data)
+#define MREPEAT241(macro, data)    MREPEAT240(macro, data)   macro(240, data)
+#define MREPEAT242(macro, data)    MREPEAT241(macro, data)   macro(241, data)
+#define MREPEAT243(macro, data)    MREPEAT242(macro, data)   macro(242, data)
+#define MREPEAT244(macro, data)    MREPEAT243(macro, data)   macro(243, data)
+#define MREPEAT245(macro, data)    MREPEAT244(macro, data)   macro(244, data)
+#define MREPEAT246(macro, data)    MREPEAT245(macro, data)   macro(245, data)
+#define MREPEAT247(macro, data)    MREPEAT246(macro, data)   macro(246, data)
+#define MREPEAT248(macro, data)    MREPEAT247(macro, data)   macro(247, data)
+#define MREPEAT249(macro, data)    MREPEAT248(macro, data)   macro(248, data)
+#define MREPEAT250(macro, data)    MREPEAT249(macro, data)   macro(249, data)
+#define MREPEAT251(macro, data)    MREPEAT250(macro, data)   macro(250, data)
+#define MREPEAT252(macro, data)    MREPEAT251(macro, data)   macro(251, data)
+#define MREPEAT253(macro, data)    MREPEAT252(macro, data)   macro(252, data)
+#define MREPEAT254(macro, data)    MREPEAT253(macro, data)   macro(253, data)
+#define MREPEAT255(macro, data)    MREPEAT254(macro, data)   macro(254, data)
+#define MREPEAT256(macro, data)    MREPEAT255(macro, data)   macro(255, data)
+
+/** @} */
+
+#endif  /* _MREPEAT_H_ */
diff --git a/uf2-samdx1/inc/preprocessor/preprocessor.h b/uf2-samdx1/inc/preprocessor/preprocessor.h
new file mode 100644
index 00000000..254ad092
--- /dev/null
+++ b/uf2-samdx1/inc/preprocessor/preprocessor.h
@@ -0,0 +1,38 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _PREPROCESSOR_H_
+#define _PREPROCESSOR_H_
+
+#include "tpaste.h"
+#include "stringz.h"
+#include "mrepeat.h"
+#include "mrecursion.h"
+
+#endif  // _PREPROCESSOR_H_
diff --git a/uf2-samdx1/inc/preprocessor/stringz.h b/uf2-samdx1/inc/preprocessor/stringz.h
new file mode 100644
index 00000000..c7317098
--- /dev/null
+++ b/uf2-samdx1/inc/preprocessor/stringz.h
@@ -0,0 +1,67 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _STRINGZ_H_
+#define _STRINGZ_H_
+
+/**
+ * \defgroup group_sam0_utils_stringz Preprocessor - Stringize
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \brief Stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * May be used only within macros with the token passed as an argument if the
+ * token is \#defined.
+ *
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
+ * writing "A0".
+ */
+#define STRINGZ(x)                                #x
+
+/** \brief Absolute stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * No restriction of use if the token is \#defined.
+ *
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
+ * equivalent to writing "A0".
+ */
+#define ASTRINGZ(x)                               STRINGZ(x)
+
+/** @} */
+
+#endif  // _STRINGZ_H_
diff --git a/uf2-samdx1/inc/preprocessor/tpaste.h b/uf2-samdx1/inc/preprocessor/tpaste.h
new file mode 100644
index 00000000..20773ff5
--- /dev/null
+++ b/uf2-samdx1/inc/preprocessor/tpaste.h
@@ -0,0 +1,85 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+#ifndef _TPASTE_H_
+#define _TPASTE_H_
+
+/**
+ * \defgroup group_sam0_utils_tpaste Preprocessor - Token Paste
+ *
+ * \ingroup group_sam0_utils
+ *
+ * @{
+ */
+
+/** \name Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
+ *
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
+ * equivalent to writing U32.
+ *
+ * @{ */
+#define TPASTE2( a, b)                            a##b
+#define TPASTE3( a, b, c)                         a##b##c
+#define TPASTE4( a, b, c, d)                      a##b##c##d
+#define TPASTE5( a, b, c, d, e)                   a##b##c##d##e
+#define TPASTE6( a, b, c, d, e, f)                a##b##c##d##e##f
+#define TPASTE7( a, b, c, d, e, f, g)             a##b##c##d##e##f##g
+#define TPASTE8( a, b, c, d, e, f, g, h)          a##b##c##d##e##f##g##h
+#define TPASTE9( a, b, c, d, e, f, g, h, i)       a##b##c##d##e##f##g##h##i
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j)    a##b##c##d##e##f##g##h##i##j
+/** @} */
+
+/** \name Absolute Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * No restriction of use if the tokens are \#defined.
+ *
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
+ * as 32 is equivalent to writing U32.
+ *
+ * @{ */
+#define ATPASTE2( a, b)                           TPASTE2( a, b)
+#define ATPASTE3( a, b, c)                        TPASTE3( a, b, c)
+#define ATPASTE4( a, b, c, d)                     TPASTE4( a, b, c, d)
+#define ATPASTE5( a, b, c, d, e)                  TPASTE5( a, b, c, d, e)
+#define ATPASTE6( a, b, c, d, e, f)               TPASTE6( a, b, c, d, e, f)
+#define ATPASTE7( a, b, c, d, e, f, g)            TPASTE7( a, b, c, d, e, f, g)
+#define ATPASTE8( a, b, c, d, e, f, g, h)         TPASTE8( a, b, c, d, e, f, g, h)
+#define ATPASTE9( a, b, c, d, e, f, g, h, i)      TPASTE9( a, b, c, d, e, f, g, h, i)
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j)   TPASTE10(a, b, c, d, e, f, g, h, i, j)
+/** @} */
+
+/** @} */
+
+#endif  // _TPASTE_H_
diff --git a/uf2-samdx1/inc/sam_ba_monitor.h b/uf2-samdx1/inc/sam_ba_monitor.h
new file mode 100644
index 00000000..a695543f
--- /dev/null
+++ b/uf2-samdx1/inc/sam_ba_monitor.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _MONITOR_SAM_BA_H_
+#define _MONITOR_SAM_BA_H_
+
+#include <stdint.h>
+
+#define SAM_BA_VERSION "1.1"
+
+/* Selects USART as the communication interface of the monitor */
+#define SAM_BA_INTERFACE_USART 1
+/* Selects USB as the communication interface of the monitor */
+#define SAM_BA_INTERFACE_USBCDC 0
+
+/* Selects USB as the communication interface of the monitor */
+#define SIZEBUFMAX 64
+
+/**
+ * \brief Initialize the monitor
+ *
+ */
+void sam_ba_monitor_init(uint8_t com_interface);
+
+/**
+ * \brief Main function of the SAM-BA Monitor
+ *
+ */
+void sam_ba_monitor_run(void);
+
+/**
+ * \brief
+ *
+ */
+void sam_ba_putdata_term(uint8_t *data, uint32_t length);
+
+/**
+ * \brief
+ *
+ */
+void call_applet(uint32_t address);
+
+#endif // _MONITOR_SAM_BA_H_
diff --git a/uf2-samdx1/inc/uart_driver.h b/uf2-samdx1/inc/uart_driver.h
new file mode 100644
index 00000000..effa7ae0
--- /dev/null
+++ b/uf2-samdx1/inc/uart_driver.h
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef UART_DRIVER_H
+#define UART_DRIVER_H
+#include "sam.h"
+#include <stdbool.h>
+#include <stdio.h>
+
+#define PINMUX_UNUSED 0xFFFFFFFF
+#define GCLK_ID_SERCOM0_CORE 0x14
+
+/* SERCOM UART available pad settings */
+enum uart_pad_settings {
+    UART_RX_PAD0_TX_PAD2 = SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1),
+    UART_RX_PAD1_TX_PAD2 = SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1),
+    UART_RX_PAD2_TX_PAD0 = SERCOM_USART_CTRLA_RXPO(2),
+    UART_RX_PAD3_TX_PAD0 = SERCOM_USART_CTRLA_RXPO(3),
+    UART_RX_PAD1_TX_PAD0 = SERCOM_USART_CTRLA_RXPO(1),
+    UART_RX_PAD3_TX_PAD2 = SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1),
+};
+
+/**
+ * \brief Gets the index of the provided SERCOM instance
+ *
+ * \param Pointer to SERCOM instance
+ * \return Index of the SERCOM module
+ */
+uint32_t uart_get_sercom_index(Sercom *sercom_instance);
+
+/**
+ * \brief Initializes the UART
+ *
+ * \param Pointer to SERCOM instance
+ * \param Baud value corresponding to the desired baudrate
+ * \param SERCOM pad settings
+ */
+void uart_basic_init(Sercom *sercom, uint16_t baud_val, enum uart_pad_settings pad_conf);
+
+/**
+ * \brief Disables UART interface
+ *
+ * \param Pointer to SERCOM instance
+ */
+void uart_disable(Sercom *sercom);
+
+/**
+ * \brief Sends a single byte through UART interface
+ *
+ * \param Pointer to SERCOM instance
+ * \param Data to send
+ */
+void uart_write_byte(Sercom *sercom, uint8_t data);
+
+/**
+ * \brief Reads a single character from UART interface
+ *
+ * \param Pointer to SERCOM instance
+ * \return Data byte read
+ */
+uint8_t uart_read_byte(Sercom *sercom);
+
+/**
+ * \brief Sends buffer on UART interface
+ *
+ * \param Pointer to SERCOM instance
+ * \param Pointer to data to send
+ * \param Number of bytes to send
+ */
+void uart_write_buffer_polled(Sercom *sercom, uint8_t *ptr, uint16_t length);
+
+/**
+ * \brief Reads data on UART interface
+ *
+ * \param Pointer to SERCOM instance
+ * \param Pointer to store read data
+ * \param Number of bytes to read
+ */
+void uart_read_buffer_polled(Sercom *sercom, uint8_t *ptr, uint16_t length);
+
+#endif
diff --git a/uf2-samdx1/inc/uf2.h b/uf2-samdx1/inc/uf2.h
new file mode 100644
index 00000000..91a9f5f3
--- /dev/null
+++ b/uf2-samdx1/inc/uf2.h
@@ -0,0 +1,369 @@
+#ifndef UF2_H
+#define UF2_H 1
+
+#include <stdint.h>
+#include "board_config.h"
+
+#include "sam.h"
+#define UF2_DEFINE_HANDOVER 1 // for testing
+#include "uf2format.h"
+#include "uf2hid.h"
+#include "main.h"
+#include "cdc_enumerate.h"
+#include "sam_ba_monitor.h"
+#include "usart_sam_ba.h"
+#include <stdio.h>
+#include <string.h>
+
+
+#include "configkeys.h"
+
+
+#undef DISABLE
+#undef ENABLE
+
+// always go for crystalless - smaller and more compatible
+#ifndef CRYSTALLESS
+#define CRYSTALLESS 1
+#endif
+
+#ifndef USB_PID
+#define USB_VID 0x03EB // Atmel
+#define USB_PID 0x2402 // Generic HID device
+#endif
+
+#ifndef INDEX_URL
+#define INDEX_URL "https://www.pxt.io/"
+#endif
+
+#include "uf2_version.h"
+
+// needs to be more than ~4200 (to force FAT16)
+#define NUM_FAT_BLOCKS 16000
+
+// 8kB with NeoPixel or DotStar is a tight fit.
+#define SAMD21_MINIMIZE (defined(SAMD21) && (defined(BOARD_NEOPIXEL_PIN) || defined(BOARD_RGBLED_CLOCK_PIN)))
+
+// Logging to help debugging
+#define USE_LOGS 0
+// Check various conditions; best leave on
+#define USE_ASSERT 0 // 188 bytes
+// Enable reading flash via FAT files; otherwise drive will appear empty
+#define USE_FAT 1 // 272 bytes
+
+// Enable URL in INFO_UF2.TXT. Used for boards that are a very tight fit.
+#ifndef USE_URL_IN_INFO
+#define USE_URL_IN_INFO SAMD21_MINIMIZE
+#endif
+
+// Enable index.htm file on the drive.
+// 132 bytes
+#ifndef USE_INDEX_HTM
+#define USE_INDEX_HTM (!USE_URL_IN_INFO)
+#endif
+
+// Enable USB CDC (Communication Device Class; i.e., USB serial) monitor for Arduino style flashing
+#define USE_CDC 1 // 1264 bytes (plus terminal, see below)
+// Support the UART (real serial port, not USB)
+#define USE_UART 0
+// Support Human Interface Device (HID) - serial, flashing and debug
+#define USE_HID 1 // 788 bytes
+// Expose HID via WebUSB
+#define USE_WEBUSB 1
+// Doesn't yet disable code, just enumeration
+#define USE_MSC 1
+
+#ifdef BOARD_SCREEN
+#define USE_SCREEN 1
+#else
+#define USE_SCREEN 0
+#endif
+
+// If enabled, bootloader will start on power-on and every reset. A second reset
+// will start the app. This only happens if the app says it wants that (see SINGLE_RESET() below).
+// If disabled here or by the app, the bootloader will only start with double-click of the reset
+// button.
+#define USE_SINGLE_RESET 1
+
+// Fine-tuning of features
+#define USE_HID_SERIAL 0   // just an example, not really needed; 36 bytes
+#define USE_HID_EXT 1      // extended HID commands (read/write mem); 60 bytes
+#define USE_HID_HANDOVER 1 // allow HID application->bootloader seamless transition; 56 bytes
+#define USE_MSC_HANDOVER 1 // ditto for MSC; 348 bytes
+#define USE_MSC_CHECKS 0   // check validity of MSC commands; 460 bytes
+#define USE_CDC_TERMINAL 0 // enable ASCII mode on CDC loop (not used by BOSSA); 228 bytes
+#define USE_DBG_MSC 0      // output debug info about MSC
+
+#if USE_CDC
+#define CDC_VERSION "S"
+#else
+#define CDC_VERSION ""
+#endif
+
+#if USE_LOGS
+#define LOGS_VERSION "L"
+#else
+#define LOGS_VERSION ""
+#endif
+
+#if USE_FAT
+#define FAT_VERSION "F"
+#else
+#define FAT_VERSION ""
+#endif
+
+#if USE_ASSERT
+#define ASSERT_VERSION "A"
+#else
+#define ASSERT_VERSION ""
+#endif
+
+#if USE_HID
+#define HID_VERSION "H"
+#else
+#define HID_VERSION ""
+#endif
+
+#if USE_SINGLE_RESET
+#define RESET_VERSION "R"
+#else
+#define RESET_VERSION ""
+#endif
+
+#if USE_WEBUSB
+#define WEB_VERSION "W"
+#else
+#define WEB_VERSION ""
+#endif
+
+#if USE_MSC_HANDOVER
+#define MSC_HANDOVER_VERSION "O"
+#else
+#define MSC_HANDOVER_VERSION ""
+#endif
+
+#define UF2_VERSION                                                                                \
+    UF2_VERSION_BASE " " CDC_VERSION LOGS_VERSION FAT_VERSION ASSERT_VERSION HID_VERSION           \
+        WEB_VERSION RESET_VERSION MSC_HANDOVER_VERSION
+
+// End of config
+
+#define USE_MONITOR (USE_CDC || USE_UART)
+
+#ifdef SAMD51
+// 51 also runs at 48MHz in bootloader mode, but it's still faster
+#define TIMER_STEP 2000
+#else
+#define TIMER_STEP 1500
+#endif
+
+#ifdef BOARD_NEOPIXEL_PIN
+#define COLOR_START 0x040000
+#define COLOR_USB 0x000400
+#define COLOR_UART 0x040400
+#define COLOR_LEAVE 0x000000
+#else
+#define COLOR_START 0x000040
+#define COLOR_USB 0x004000
+#define COLOR_UART 0x404000
+#define COLOR_LEAVE 0x000000
+#endif
+
+/*
+From CPU config:
+#define FLASH_SIZE            0x8000UL
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+*/
+
+// These two need to be defined as plain decimal numbers, as we're using # on them
+#define FLASH_ROW_SIZE 256
+#ifndef FLASH_NUM_ROWS
+#define FLASH_NUM_ROWS 1024
+#endif
+
+#define NOOP                                                                                       \
+    do {                                                                                           \
+    } while (0)
+
+#if USE_LOGS
+struct LogStore {
+    int ptr;
+    char buffer[4096];
+};
+extern struct LogStore logStoreUF2;
+void logmsg(const char *msg);
+void logval(const char *lbl, uint32_t v);
+void logwritenum(uint32_t n);
+void logwrite(const char *msg);
+void logreset(void);
+#else
+#define logmsg(...) NOOP
+#define logval(...) NOOP
+#define logwritenum(...) NOOP
+#define logwrite(...) NOOP
+#define logreset() NOOP
+#endif
+
+#if USE_DBG_MSC
+#define DBG_MSC(x) x
+#else
+#define DBG_MSC(x) NOOP
+#endif
+
+void panic(int code);
+
+#if USE_ASSERT
+#define assert(cond)                                                                               \
+    if (!(cond)) {                                                                                 \
+        panic(__LINE__);                                                                           \
+    }
+#else
+#define assert(cond) NOOP
+#endif
+
+extern volatile bool b_sam_ba_interface_usart;
+void flash_write_row(uint32_t *dst, uint32_t *src);
+void flash_erase_to_end(uint32_t *start_address);
+void flash_write_words(uint32_t *dst, uint32_t *src, uint32_t n_words);
+void copy_words(uint32_t *dst, uint32_t *src, uint32_t n_words);
+
+int writeNum(char *buf, uint32_t n, bool full);
+
+void process_hid(void);
+
+// index of highest LUN
+#define MAX_LUN 0
+void process_msc(void);
+void msc_reset(void);
+//! Static block size for all memories
+#define UDI_MSC_BLOCK_SIZE 512L
+
+void read_block(uint32_t block_no, uint8_t *data);
+#define MAX_BLOCKS (FLASH_SIZE / 256 + 100)
+typedef struct {
+    uint32_t numBlocks;
+    uint32_t numWritten;
+    uint8_t writtenMask[MAX_BLOCKS / 8 + 1];
+} WriteState;
+void write_block(uint32_t block_no, uint8_t *data, bool quiet, WriteState *state);
+void padded_memcpy(char *dst, const char *src, int len);
+
+// Last word in RAM
+// Unlike for ordinary applications, our link script doesn't place the stack at the bottom
+// of the RAM, but instead after all allocated BSS.
+// In other words, this word should survive reset.
+#ifdef SAMD21
+#define DBL_TAP_PTR ((volatile uint32_t *)(HMCRAMC0_ADDR + HMCRAMC0_SIZE - 4))
+#endif
+#ifdef SAMD51
+#define DBL_TAP_PTR ((volatile uint32_t *)(HSRAM_ADDR + HSRAM_SIZE - 4))
+#endif
+#define DBL_TAP_MAGIC 0xf01669ef // Randomly selected, adjusted to have first and last bit set
+#define DBL_TAP_MAGIC_QUICK_BOOT 0xf02669ef
+
+#if USE_SINGLE_RESET
+#ifdef SAMD21
+#define SINGLE_RESET() (*((uint32_t *)0x20B4) == 0x87eeb07c)
+#endif
+#ifdef SAMD51
+#define SINGLE_RESET() (*((uint32_t *)0x4268) == 0x87eeb07c)
+#endif
+#endif
+
+void resetIntoApp(void);
+void resetIntoBootloader(void);
+extern uint32_t current_cpu_frequency_MHz;
+extern volatile bool led_tick_on;
+void system_init(void);
+
+#define LED_TICK led_tick
+
+#define PINOP(pin, OP) (PORT->Group[(pin) / 32].OP.reg = (1 << ((pin) % 32)))
+
+void led_tick(void);
+void led_signal(void);
+void led_init(void);
+void RGBLED_set_color(uint32_t color);
+
+// Not all targets have a LED
+#if defined(LED_PIN)
+#if !defined(LED_PIN_PULLUP)
+#define LED_MSC_OFF() PINOP(LED_PIN, OUTCLR)
+#define LED_MSC_ON() PINOP(LED_PIN, OUTSET)
+#else
+#define LED_MSC_OFF() PINOP(LED_PIN, OUTSET)
+#define LED_MSC_ON() PINOP(LED_PIN, OUTCLR)
+#endif
+#define LED_MSC_TGL() PINOP(LED_PIN, OUTTGL)
+#else
+#define LED_MSC_OFF()
+#define LED_MSC_ON()
+#define LED_MSC_TGL()
+#endif
+
+// Not all targets have a TX LED
+#if defined(LED_TX_PIN)
+#if defined(LED_TX_PIN_PULLUP)
+#define LED_TX_OFF() PINOP(LED_TX_PIN, OUTSET)
+#define LED_TX_ON() PINOP(LED_TX_PIN, OUTCLR)
+#else
+#define LED_TX_OFF() PINOP(LED_TX_PIN, OUTCLR)
+#define LED_TX_ON() PINOP(LED_TX_PIN, OUTSET)
+#endif
+#define LED_TX_TGL() PINOP(LED_TX_PIN, OUTTGL)
+#else
+#define LED_TX_OFF()
+#define LED_TX_ON()
+#define LED_TX_TGL()
+#endif
+
+// Not all targets have a RX LED
+#if defined(LED_RX_PIN)
+#if defined(LED_RX_PIN_PULLUP)
+#define LED_RX_OFF() PINOP(LED_RX_PIN, OUTSET)
+#define LED_RX_ON() PINOP(LED_RX_PIN, OUTCLR)
+#else
+#define LED_RX_OFF() PINOP(LED_RX_PIN, OUTCLR)
+#define LED_RX_ON() PINOP(LED_RX_PIN, OUTSET)
+#endif
+#define LED_RX_TGL() PINOP(LED_RX_PIN, OUTTGL)
+#else
+#define LED_RX_OFF()
+#define LED_RX_ON()
+#define LED_RX_TGL()
+#endif
+
+extern uint32_t timerHigh, resetHorizon;
+void timerTick(void);
+void delay(uint32_t ms);
+void hidHandoverLoop(int ep);
+void handoverPrep(void);
+
+// Useful for debugging.
+#ifdef BLINK_DEBUG
+void blink_n(uint32_t pin, uint32_t n, uint32_t interval);
+void blink_n_forever(uint32_t pin, uint32_t n, uint32_t interval);
+#endif
+
+#define CONCAT_1(a, b) a##b
+#define CONCAT_0(a, b) CONCAT_1(a, b)
+#define STATIC_ASSERT(e) enum { CONCAT_0(_static_assert_, __LINE__) = 1 / ((e) ? 1 : 0) }
+
+#ifdef SAMD21
+STATIC_ASSERT(FLASH_ROW_SIZE == FLASH_PAGE_SIZE * 4);
+STATIC_ASSERT(FLASH_ROW_SIZE == NVMCTRL_ROW_SIZE);
+STATIC_ASSERT(FLASH_NUM_ROWS * 4 == FLASH_NB_OF_PAGES);
+#endif
+
+extern const char infoUf2File[];
+
+#if USE_SCREEN
+void draw_screen(void);
+void draw_hf2(void);
+void draw_drag(void);
+void screen_init(void);
+void screen_early_init(void);
+#endif
+
+#endif
diff --git a/uf2-samdx1/inc/uf2format.h b/uf2-samdx1/inc/uf2format.h
new file mode 100644
index 00000000..179f900c
--- /dev/null
+++ b/uf2-samdx1/inc/uf2format.h
@@ -0,0 +1,120 @@
+#ifndef UF2FORMAT_H
+#define UF2FORMAT_H 1
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// All entries are little endian.
+
+// if you increase that, you will also need to update the linker script file
+#ifdef SAMD21
+#define APP_START_ADDRESS 0x00002000
+#define UF2_FAMILY 0x68ed2b88
+#endif
+#ifdef SAMD51
+#define APP_START_ADDRESS 0x00004000
+#define UF2_FAMILY 0x55114460
+#endif
+
+#define UF2_MAGIC_START0 0x0A324655UL // "UF2\n"
+#define UF2_MAGIC_START1 0x9E5D5157UL // Randomly selected
+#define UF2_MAGIC_END 0x0AB16F30UL    // Ditto
+
+// If set, the block is "comment" and should not be flashed to the device
+#define UF2_FLAG_NOFLASH 0x00000001
+#define UF2_FLAG_FAMILYID_PRESENT 0x00002000
+
+#define UF2_IS_MY_FAMILY(bl)                                                                       \
+    (((bl)->flags & UF2_FLAG_FAMILYID_PRESENT) == 0 || (bl)->familyID == UF2_FAMILY)
+
+typedef struct {
+    // 32 byte header
+    uint32_t magicStart0;
+    uint32_t magicStart1;
+    uint32_t flags;
+    uint32_t targetAddr;
+    uint32_t payloadSize;
+    uint32_t blockNo;
+    uint32_t numBlocks;
+    uint32_t familyID;
+
+    // raw data;
+    uint8_t data[476];
+
+    // store magic also at the end to limit damage from partial block reads
+    uint32_t magicEnd;
+} UF2_Block;
+
+typedef struct {
+    uint8_t version;
+    uint8_t ep_in;
+    uint8_t ep_out;
+    uint8_t reserved0;
+    uint32_t cbw_tag;
+    uint32_t blocks_remaining;
+    uint8_t *buffer;
+} UF2_HandoverArgs;
+
+typedef void (*UF2_MSC_Handover_Handler)(UF2_HandoverArgs *handover);
+typedef void (*UF2_HID_Handover_Handler)(int ep);
+
+// this is required to be exactly 16 bytes long by the linker script
+typedef struct {
+    const uint32_t *config_data;
+    UF2_HID_Handover_Handler handoverHID;
+    UF2_MSC_Handover_Handler handoverMSC;
+    const char *info_uf2;
+} UF2_BInfo;
+
+#define UF2_BINFO ((UF2_BInfo *)(APP_START_ADDRESS - sizeof(UF2_BInfo)))
+
+static inline bool is_uf2_block(void *data) {
+    UF2_Block *bl = (UF2_Block *)data;
+    return bl->magicStart0 == UF2_MAGIC_START0 && bl->magicStart1 == UF2_MAGIC_START1 &&
+           bl->magicEnd == UF2_MAGIC_END;
+}
+
+static inline bool in_uf2_bootloader_space(const void *addr) {
+    return 0xb4 <= (uint32_t)addr && (uint32_t)addr < APP_START_ADDRESS;
+}
+
+static inline const char *uf2_info(void) {
+    if (in_uf2_bootloader_space(UF2_BINFO->info_uf2))
+        return UF2_BINFO->info_uf2;
+    return "N/A";
+}
+
+#ifdef UF2_DEFINE_HANDOVER
+static inline void hf2_handover(uint8_t ep) {
+    const char *board_info = UF2_BINFO->info_uf2;
+    UF2_HID_Handover_Handler fn = UF2_BINFO->handoverHID;
+
+    if (in_uf2_bootloader_space(board_info) && in_uf2_bootloader_space((const void *)fn) &&
+        ((uint32_t)fn & 1)) {
+        // Pass control to bootloader; never returns
+        fn(ep & 0xf);
+    }
+}
+
+// the ep_in/ep_out are without the 0x80 mask
+// cbw_tag is in the same bit format as it came
+static inline void check_uf2_handover(uint8_t *buffer, uint32_t blocks_remaining, uint8_t ep_in,
+                                      uint8_t ep_out, uint32_t cbw_tag) {
+    if (!is_uf2_block(buffer))
+        return;
+
+    const char *board_info = UF2_BINFO->info_uf2;
+    UF2_MSC_Handover_Handler fn = UF2_BINFO->handoverMSC;
+
+    if (in_uf2_bootloader_space(board_info) && in_uf2_bootloader_space((const void *)fn) &&
+        ((uint32_t)fn & 1)) {
+        UF2_HandoverArgs hand = {
+            1, ep_in, ep_out, 0, cbw_tag, blocks_remaining, buffer,
+        };
+        // Pass control to bootloader; never returns
+        fn(&hand);
+    }
+}
+#endif
+
+#endif
diff --git a/uf2-samdx1/inc/uf2hid.h b/uf2-samdx1/inc/uf2hid.h
new file mode 100644
index 00000000..90077b7b
--- /dev/null
+++ b/uf2-samdx1/inc/uf2hid.h
@@ -0,0 +1,107 @@
+#ifndef UF2_HID_H
+#define UF2_HID_H 1
+
+#define HF2_CMD_BININFO 0x0001
+// no arguments
+#define HF2_MODE_BOOTLOADER 0x01
+#define HF2_MODE_USERSPACE 0x02
+struct HF2_BININFO_Result {
+    uint32_t mode;
+    uint32_t flash_page_size;
+    uint32_t flash_num_pages;
+    uint32_t max_message_size;
+    uint32_t uf2_family;
+};
+
+#define HF2_CMD_INFO 0x0002
+// no arguments
+// results is utf8 character array
+
+#define HF2_CMD_RESET_INTO_APP 0x0003
+// no arguments, no result
+
+#define HF2_CMD_RESET_INTO_BOOTLOADER 0x0004
+// no arguments, no result
+
+#define HF2_CMD_START_FLASH 0x0005
+// no arguments, no result
+
+#define HF2_CMD_WRITE_FLASH_PAGE 0x0006
+struct HF2_WRITE_FLASH_PAGE_Command {
+    uint32_t target_addr;
+    uint32_t data[0];
+};
+// no result
+
+#define HF2_CMD_CHKSUM_PAGES 0x0007
+struct HF2_CHKSUM_PAGES_Command {
+    uint32_t target_addr;
+    uint32_t num_pages;
+};
+struct HF2_CHKSUM_PAGES_Result {
+    uint16_t chksums[0 /* num_pages */];
+};
+
+#define HF2_CMD_READ_WORDS 0x0008
+struct HF2_READ_WORDS_Command {
+    uint32_t target_addr;
+    uint32_t num_words;
+};
+struct HF2_READ_WORDS_Result {
+    uint32_t words[0 /* num_words */];
+};
+
+#define HF2_CMD_WRITE_WORDS 0x0009
+struct HF2_WRITE_WORDS_Command {
+    uint32_t target_addr;
+    uint32_t num_words;
+    uint32_t words[0 /* num_words */];
+};
+// no result
+
+#define HF2_CMD_DMESG 0x0010
+// no arguments
+// results is utf8 character array
+
+typedef struct {
+    uint32_t command_id;
+    uint16_t tag;
+    uint8_t reserved0;
+    uint8_t reserved1;
+
+    union {
+        struct HF2_WRITE_FLASH_PAGE_Command write_flash_page;
+        struct HF2_WRITE_WORDS_Command write_words;
+        struct HF2_READ_WORDS_Command read_words;
+        struct HF2_CHKSUM_PAGES_Command chksum_pages;
+    };
+} HF2_Command;
+
+typedef struct {
+    uint16_t tag;
+    union {
+        struct {
+            uint8_t status;
+            uint8_t status_info;
+        };
+        uint16_t status16;
+    };
+    union {
+        struct HF2_BININFO_Result bininfo;
+        uint8_t data8[0];
+        uint16_t data16[0];
+        uint32_t data32[0];
+    };
+} HF2_Response;
+
+#define HF2_FLAG_SERIAL_OUT 0x80
+#define HF2_FLAG_SERIAL_ERR 0xC0
+#define HF2_FLAG_CMDPKT_LAST 0x40
+#define HF2_FLAG_CMDPKT_BODY 0x00
+#define HF2_FLAG_MASK 0xC0
+#define HF2_SIZE_MASK 63
+
+#define HF2_STATUS_OK 0x00
+#define HF2_STATUS_INVALID_CMD 0x01
+
+#endif
diff --git a/uf2-samdx1/inc/usart_sam_ba.h b/uf2-samdx1/inc/usart_sam_ba.h
new file mode 100644
index 00000000..f0eca98f
--- /dev/null
+++ b/uf2-samdx1/inc/usart_sam_ba.h
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _USART_SAM_BA_H_
+#define _USART_SAM_BA_H_
+
+#include "stdbool.h"
+#include "stdint.h"
+
+/* USART buffer size (must be a power of two) */
+#define USART_BUFFER_SIZE 128
+
+/* Define the default time-out value for USART. */
+#define USART_DEFAULT_TIMEOUT 1000
+
+/* Xmodem related defines */
+/* CRC16  polynomial */
+#define CRC16POLY 0x1021
+
+#define SHARP_CHARACTER '#'
+
+/* X/Ymodem protocol: */
+#define SOH 0x01
+//#define STX                    0x02
+#define EOT 0x04
+#define ACK 0x06
+#define NAK 0x15
+#define CAN 0x18
+#define ESC 0x1b
+
+#define PKTLEN_128 128
+
+/**
+ * \brief Open the given USART
+ */
+void usart_open(void);
+
+/**
+ * \brief Stops the USART
+ */
+void usart_close(void);
+
+/**
+ * \brief Puts a byte on usart line
+ *
+ * \param value      Value to put
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+int usart_putc(int value);
+
+/**
+ * \brief Waits and gets a value on usart line
+ *
+ * \return value read on usart line
+ */
+int usart_getc(void);
+
+/**
+ * \brief Returns true if the SAM-BA Uart received the sharp char
+ *
+ * \return Returns true if the SAM-BA Uart received the sharp char
+ */
+int usart_sharp_received(void);
+
+/**
+ * \brief This function checks if a character has been received on the usart
+ * line
+ *
+ * \return \c 1 if a byte is ready to be read.
+ */
+bool usart_is_rx_ready(void);
+
+/**
+ * \brief Gets a value on usart line
+ *
+ * \return value read on usart line
+ */
+int usart_readc(void);
+
+/**
+ * \brief Send buffer on usart line
+ *
+ * \param data pointer
+ * \param number of data to send
+ * \return number of data sent
+ */
+uint32_t usart_putdata(void const *data, uint32_t length); // Send given data (polling)
+
+/**
+ * \brief Gets data from usart line
+ *
+ * \param data pointer
+ * \param number of data to get
+ * \return value read on usart line
+ */
+uint32_t usart_getdata(void *data, uint32_t length); // Get data from comm. device
+
+/**
+ * \brief Send buffer on usart line using Xmodem protocol
+ *
+ * \param data pointer
+ * \param number of data to send
+ * \return number of data sent
+ */
+uint32_t
+usart_putdata_xmd(void const *data,
+                  uint32_t length); // Send given data (polling) using xmodem (if necessary)
+
+/**
+ * \brief Gets data from usart line using Xmodem protocol
+ *
+ * \param data pointer
+ * \param number of data to get
+ * \return value read on usart line
+ */
+uint32_t
+usart_getdata_xmd(void *data,
+                  uint32_t length); // Get data from comm. device using xmodem (if necessary)
+
+/**
+ * \brief Gets data from usart line using Xmodem protocol
+ *
+ * \param data pointer
+ * \param number of data to get
+ * \return value read on usart line
+ */
+uint16_t add_crc(uint8_t ch, unsigned short crc0);
+
+uint8_t getPacket(uint8_t *pData, uint8_t sno);
+
+#endif // _USART_SAM_BA_H_
diff --git a/uf2-samdx1/lib/README.txt b/uf2-samdx1/lib/README.txt
new file mode 100644
index 00000000..08daefb3
--- /dev/null
+++ b/uf2-samdx1/lib/README.txt
@@ -0,0 +1,8 @@
+The contents of these directories is sourced from Atmel's http://packs.download.atmel.com/ website.
+
+* cmsis is "
+CMSIS (Cortex Microcontroller Software Interface Standard)"
+* samd21 is "Atmel SAMD21 Series Device Support"
+* samd51 is " Atmel SAMD51 Series Device Support"
+
+The atpack files have been unzipped into each respective directly and unmodified.
diff --git a/uf2-samdx1/lib/cmsis/ARM.CMSIS.pdsc b/uf2-samdx1/lib/cmsis/ARM.CMSIS.pdsc
new file mode 100644
index 00000000..1e153217
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/ARM.CMSIS.pdsc
@@ -0,0 +1,1340 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
+  <name>CMSIS</name>
+  <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>
+  <vendor>ARM</vendor>
+  <!-- <license>CMSIS\CMSIS_END_USER_LICENCE_AGREEMENT.rtf</license> -->
+  <url>http://www.keil.com/pack/</url>
+
+  <taxonomy>
+    <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
+    <description Cclass="CMSIS" doc="CMSIS\Documentation\General\html\index.html">Cortex Microcontroller Software Interface Components</description>
+    <description Cclass="Device" doc="CMSIS\Documentation\Core\html\index.html">Startup, System Setup</description>
+    <description Cclass="CMSIS Driver" doc="CMSIS\Documentation\Driver\html\index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
+    <description Cclass="File System">File Drive Support and File System</description>
+    <description Cclass="Graphics">Graphical User Interface</description>
+    <description Cclass="Network">Network Stack using Internet Protocols</description>
+    <description Cclass="USB">Universal Serial Bus Stack</description>
+  </taxonomy>
+
+  <releases>
+    <release version="4.2.0" date="2014-09-24">
+      Adding Cortex-M7 support
+      - CMSIS-Core     4.00  (Cortex-M7 support, corrected C++ include guards in core header files)
+      - CMSIS-DSP      1.4.4 (Cortex-M7 support and corrected out of bound issues)
+      - CMSIS-PACK     1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
+      - CMSIS-SVD      1.2   (Cortex-M7 extensions)
+      - CMSIS-RTOS RTX 4.75  (see revision history for details)
+    </release>
+    <release version="4.1.1" date="2014-06-30">
+      - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
+    </release>
+    <release version="4.1.0" date="2014-06-12">
+      - CMSIS-Driver   2.02  (incompatible update)
+      - CMSIS-Pack     1.3   (see revision history for details)
+      - CMSIS-DSP      1.4.2 (unchanged)
+      - CMSIS-Core     3.30  (unchanged)
+      - CMSIS-RTOS RTX 4.74  (unchanged)
+      - CMSIS-RTOS API 1.02  (unchanged)
+      - CMSIS-SVD      1.10  (unchanged)
+      PACK:
+      - removed G++ specific files from PACK
+      - added Component Startup variant "C Startup"
+      - added Pack Checking Utility 
+      - updated conditions to reflect tool-chain dependency
+      - added Taxonomy for Graphics
+      - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
+    </release>
+    <release version="4.0.0">
+      - CMSIS-Driver   2.00  Preliminary (incompatible update)
+      - CMSIS-Pack     1.1   Preliminary
+      - CMSIS-DSP      1.4.2 (see revision history for details)
+      - CMSIS-Core     3.30  (see revision history for details)
+      - CMSIS-RTOS RTX 4.74  (see revision history for details)
+      - CMSIS-RTOS API 1.02  (unchanged)
+      - CMSIS-SVD      1.10  (unchanged)
+    </release>
+    <release version="3.20.4">
+      - CMSIS-RTOS 4.74 (see revision history for details)
+      - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
+    </release>
+    <release version="3.20.3">
+      - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
+      - CMSIS-RTOS 4.73 (see revision history for details)
+    </release>
+    <release version="3.20.2">
+      - CMSIS-Pack documentation has been added
+      - CMSIS-Drivers header and documentation have been added to PACK
+      - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
+    </release>
+    <release version="3.20.1">
+      - CMSIS-RTOS Keil RTX V4.72 has been added to PACK
+      - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
+    </release>
+    <release version="3.20.0">
+      The software portions that are deployed in the application program are now under a BSD license which allows usage
+      of CMSIS components in any commercial or open source projects.  The Pack Description file Arm.CMSIS.pdsc describes the use cases
+      The individual components have been update as listed below:
+      - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
+      - CMSIS-DSP library is optimized for more performance and contains several bug fixes.
+      - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
+      - CMSIS-SVD is unchanged.
+    </release>
+  </releases>
+
+  <devices>
+    <!-- ******************************  Cortex-M0  ****************************** -->
+    <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
+      <book      name="Device\ARM\Documents\cortex_m0_dgug.pdf"       title="Cortex-M4 Device Generic Users Guide"/>
+      <description>
+The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed
+for a broad range of embedded applications. It offers significant benefits to developers,
+including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+      </description>
+      <debug     svd="Device\ARM\SVD\ARMCM0.svd"/>
+      <memory    id="IROM1"                                 start="0x00000000"  size="0x40000"  startup="1"   default="1"/>
+      <memory    id="IRAM1"                                 start="0x20000000"  size="0x20000"  init   ="0"   default="1"/>
+      <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM"     start="0x00000000"  size="0x40000"  default="1"/>
+
+      <device Dname="ARMCM0">
+        <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="0" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMCM0\Include\ARMCM0.h"    define="ARMCM0"/>
+      </device>
+    </family>
+
+    <!-- ******************************  Cortex-M0P  ****************************** -->
+    <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
+      <book      name="Device\ARM\Documents\cortex_m0p_dgug.pdf"       title="Cortex-M4 Device Generic Users Guide"/>
+      <description>
+The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed
+for a broad range of embedded applications. It offers significant benefits to developers,
+including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+      </description>
+      <debug     svd="Device\ARM\SVD\ARMCM0P.svd"/>
+      <memory    id="IROM1"                                 start="0x00000000"  size="0x40000"  startup="1"   default="1"/>
+      <memory    id="IRAM1"                                 start="0x20000000"  size="0x20000"  init   ="0"   default="1"/>
+      <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM"     start="0x00000000"  size="0x40000"  default="1"/>
+
+      <device Dname="ARMCM0P">
+        <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="0" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMCM0plus\Include\ARMCM0plus.h"  define="ARMCM0P"/>
+      </device>
+    </family>
+
+    <!-- ******************************  Cortex-M3  ****************************** -->
+    <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
+      <book      name="Device\ARM\Documents\cortex_m3_dgug.pdf"       title="Cortex-M3 Device Generic Users Guide"/>
+      <description>
+The Cortex-M3 processor is an entry-level 32-bit ARM Cortex processor designed
+for a broad range of embedded applications. It offers significant benefits to developers,
+including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+      </description>
+      <debug     svd="Device\ARM\SVD\ARMCM3.svd"/>
+      <memory    id="IROM1"                                 start="0x00000000"  size="0x40000"  startup="1"   default="1"/>
+      <memory    id="IRAM1"                                 start="0x20000000"  size="0x20000"  init   ="0"   default="1"/>
+      <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM"     start="0x00000000"  size="0x40000"  default="1"/>
+
+      <device Dname="ARMCM3">
+        <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="0" Dmpu="1" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMCM3\Include\ARMCM3.h"    define="ARMCM3"/>
+      </device>
+    </family>
+
+    <!-- ******************************  Cortex-M4  ****************************** -->
+    <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
+      <book      name="Device\ARM\Documents\cortex_m4_dgug.pdf"       title="Cortex-M4 Device Generic Users Guide"/>
+      <description>
+The Cortex-M4 processor is an entry-level 32-bit ARM Cortex processor designed
+for a broad range of embedded applications. It offers significant benefits to developers,
+including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+      </description>
+      <debug     svd="Device\ARM\SVD\ARMCM4.svd"/>
+      <memory    id="IROM1"                                 start="0x00000000"  size="0x80000"  startup="1"   default="1"/>
+      <memory    id="IRAM1"                                 start="0x20000000"  size="0x20000"  init   ="0"   default="1"/>
+      <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM"     start="0x00000000"  size="0x80000"  default="1"/>
+
+      <device Dname="ARMCM4">
+        <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="0" Dmpu="1" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMCM4\Include\ARMCM4.h"    define="ARMCM4"/>
+      </device>
+
+      <device Dname="ARMCM4_FP">
+        <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="1" Dmpu="1" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMCM4\Include\ARMCM4_FP.h" define="ARMCM4_FP"/>
+      </device>
+    </family>
+
+    <!-- ******************************  Cortex-M7  ****************************** -->
+    <family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
+      <!-- <book      name="Documents\..."                 title="ARM Cortex-M4 Device Generic Users Guide"/> -->
+      <description>
+The Cortex-M4 processor is an entry-level 32-bit ARM Cortex processor designed
+for a broad range of embedded applications. It offers significant benefits to developers,
+including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+- upward compatibility with the rest of the Cortex-M processor family.
+      </description>
+      <debug     svd="Device\ARM\SVD\ARMCM7.svd"/>
+      <memory    id="IROM1"                                 start="0x00000000"  size="0x80000"  startup="1"   default="1"/>
+      <memory    id="IRAM1"                                 start="0x20000000"  size="0x20000"  init   ="0"   default="1"/>
+      <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM"     start="0x00000000"  size="0x80000"  default="1"/>
+
+      <device Dname="ARMCM7">
+        <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="0" Dmpu="1" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMCM7\Include\ARMCM7.h"    define="ARMCM7"/>
+      </device>
+
+      <device Dname="ARMCM7_SP">
+        <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="1" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMCM7\Include\ARMCM7_SP.h" define="ARMCM7_SP"/>
+      </device>
+
+      <device Dname="ARMCM7_DP">
+        <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="1" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMCM7\Include\ARMCM7_DP.h" define="ARMCM7_DP"/>
+      </device>
+    </family>
+
+    <!-- ******************************  ARMSC000  ****************************** -->
+    <family Dfamily="ARM SC000" Dvendor="ARM:82">
+      <description>
+The ARM SC000 processor is an entry-level 32-bit ARM Cortex processor designed
+for a broad range of secure embedded applications. It offers significant benefits to developers,
+including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+      </description>
+      <debug     svd="Device\ARM\SVD\ARMSC000.svd"/>
+      <memory    id="IROM1"                                 start="0x00000000"  size="0x40000"  startup="1"   default="1"/>
+      <memory    id="IRAM1"                                 start="0x20000000"  size="0x20000"  init   ="0"   default="1"/>
+      <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM"     start="0x00000000"  size="0x40000"  default="1"/>
+
+      <device Dname="ARMSC000">
+        <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="0" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMSC000\Include\ARMSC000.h" define="ARMSC000"/>
+      </device>
+    </family>
+
+
+    <!-- ******************************  ARMSC300  ****************************** -->
+    <family Dfamily="ARM SC300" Dvendor="ARM:82">
+      <description>
+The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed
+for a broad range of secure embedded applications. It offers significant benefits to developers,
+including:
+- simple, easy-to-use programmers model
+- highly efficient ultra-low power operation
+- excellent code density
+- deterministic, high-performance interrupt handling
+      </description>
+      <debug     svd="Device\ARM\SVD\ARMSC300.svd"/>
+      <memory    id="IROM1"                                 start="0x00000000"  size="0x40000"  startup="1"   default="1"/>
+      <memory    id="IRAM1"                                 start="0x20000000"  size="0x20000"  init   ="0"   default="1"/>
+      <algorithm name="Device\ARM\Flash\NEW_DEVICE.FLM"     start="0x00000000"  size="0x40000"  default="1"/>
+
+      <device Dname="ARMSC300">
+        <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="0" Dmpu="0" Dendian="Configurable" Dclock="10000000"/>
+        <compile   header="Device\ARM\ARMSC300\Include\ARMSC300.h" define="ARMSC300"/>
+      </device>
+    </family>
+
+  </devices>
+
+
+  <apis>
+    <!-- CMSIS-RTOS API -->
+    <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0" exclusive="1">
+      <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
+      <files>
+        <file category="doc" name="CMSIS\Documentation\RTOS\html\index.html"/>
+      </files>
+    </api>
+    <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.01" exclusive="0">
+        <description>USART Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__usart__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_USART.h" />
+        </files>
+      </api>
+    <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.01" exclusive="0">
+        <description>SPI Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__spi__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_SPI.h" />
+        </files>
+      </api>
+      <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.02" exclusive="0">
+        <description>I2C Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__i2c__interface__gr.html"/>
+          <file category="header" name="CMSIS\Driver\Include\Driver_I2C.h" />
+        </files>
+      </api>
+    <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.00" exclusive="0">
+        <description>Flash Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__flash__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_Flash.h" />
+        </files>
+      </api>
+      <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.02" exclusive="0">
+        <description>MCI Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__mci__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_MCI.h" />
+        </files>
+      </api>
+    <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.01" exclusive="0">
+        <description>NAND Flash Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__nand__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_NAND.h" />
+        </files>
+      </api>
+    <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.01" exclusive="0">
+        <description>Ethernet MAC and PHY Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__eth__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_ETH_MAC.h" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_ETH_PHY.h" />
+        </files>
+      </api>
+    <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.01" exclusive="0">
+        <description>Ethernet MAC Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__eth__mac__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_ETH_MAC.h" />
+        </files>
+      </api>
+    <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.00" exclusive="0">
+        <description>Ethernet PHY Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__eth__phy__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_ETH_PHY.h" />
+        </files>
+      </api>
+    <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.01" exclusive="0">
+        <description>USB Device Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__usbd__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_USBD.h" />
+        </files>
+      </api>
+    <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.01" exclusive="0">
+        <description>USB Host Driver API for Cortex-M</description>
+        <files>
+          <file category="doc" name="CMSIS\Documentation\Driver\html\group__usbh__interface__gr.html" />
+          <file category="header" name="CMSIS\Driver\Include\Driver_USBH.h" />
+        </files>
+      </api>
+  </apis>
+
+  <!-- conditions are dependency rules that can apply to a component or an individual file -->
+  <conditions>
+    <condition id="ARMCC">
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="GCC">
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="IAR">
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="Cortex-M Device">
+      <description>Cortex-M processor based device: one of CM0, CM0+, CM3, CM4, CM7, SC000, SC3000</description>
+      <accept Dcore="Cortex-M0"/>
+      <accept Dcore="Cortex-M0+"/>
+      <accept Dcore="Cortex-M3"/>
+      <accept Dcore="Cortex-M4"/>
+      <accept Dcore="Cortex-M7"/>
+      <accept Dcore="SC000"/>
+      <accept Dcore="SC300"/>
+    </condition>
+
+    <condition id="Cortex-M CMSIS Device">
+      <description>ARM Cortex-M device</description>
+      <require condition="Cortex-M Device"/>
+      <require Cclass="CMSIS" Cgroup="CORE"/>
+    </condition>
+
+    <condition id="CMSIS Core">
+      <description>CMSIS CORE processor and device specific Startup files</description>
+      <require condition="Cortex-M Device"/>
+      <require Cclass="Device" Cgroup="Startup"/>
+    </condition>
+
+    <condition id="ARMCM0 CMSIS">
+      <!-- conditions selecting Devices -->
+      <description>Generic ARM Cortex-M0 device and CMSIS Core</description>
+      <require Dvendor="ARM:82" Dname="ARMCM0"/>
+      <require Cclass="CMSIS" Cgroup="CORE"/>
+    </condition>
+
+    <condition id="ARMCM0 CMSIS GCC">
+      <!-- conditions selecting Devices -->
+      <description>Generic ARM Cortex-M0 device and CMSIS Core requiring GCC</description>
+      <require condition="ARMCM0 CMSIS"/>
+      <require condition="GCC"/>
+    </condition>
+
+    <condition id="ARMCM0+ CMSIS">
+      <description>Generic ARM Cortex-M0+ device and CMSIS Core</description>
+      <require Dvendor="ARM:82" Dname="ARMCM0P"/>
+      <require Cclass="CMSIS" Cgroup="CORE"/>
+    </condition>
+
+    <condition id="ARMCM0+ CMSIS GCC">
+      <description>Generic ARM Cortex-M0+ device and CMSIS Core requiring GCC</description>
+      <require condition="ARMCM0+ CMSIS"/>
+      <require condition="GCC"/>
+    </condition>
+
+    <condition id="ARMCM3 CMSIS">
+      <description>Generic ARM Cortex-M3 device and CMSIS Core</description>
+      <require Dvendor="ARM:82" Dname="ARMCM3"/>
+      <require Cclass="CMSIS" Cgroup="CORE"/>
+    </condition>
+
+    <condition id="ARMCM3 CMSIS GCC">
+      <description>Generic ARM Cortex-M3 device and CMSIS Core requiring GCC</description>
+      <require condition="ARMCM3 CMSIS"/>
+      <require condition="GCC"/>
+    </condition>
+
+    <condition id="ARMCM4 CMSIS">
+      <description>Generic ARM Cortex-M4 device and CMSIS Core</description>
+      <require Dvendor="ARM:82" Dname="ARMCM4*"/>
+      <require Cclass="CMSIS" Cgroup="CORE"/>
+    </condition>
+
+    <condition id="ARMCM4 CMSIS GCC">
+      <description>Generic ARM Cortex-M4 device and CMSIS Core requiring GCC</description>
+      <require condition="ARMCM4 CMSIS"/>
+      <require condition="GCC"/>
+    </condition>
+
+    <condition id="ARMCM7 CMSIS">
+      <description>Generic ARM Cortex-M7 device and CMSIS Core</description>
+      <require Dvendor="ARM:82" Dname="ARMCM7*"/>
+      <require Cclass="CMSIS" Cgroup="CORE"/>
+    </condition>
+
+    <condition id="ARMCM7 CMSIS GCC">
+      <description>Generic ARM Cortex-M7 device and CMSIS Core requiring GCC</description>
+      <require condition="ARMCM7 CMSIS"/>
+      <require condition="GCC"/>
+    </condition>
+
+    <condition id="ARMSC000 CMSIS">
+      <description>Generic ARM SC000 device and CMSIS Core</description>
+      <require Dvendor="ARM:82" Dname="ARMSC000"/>
+      <require Cclass="CMSIS" Cgroup="CORE"/>
+    </condition>
+
+    <condition id="ARMSC000 CMSIS GCC">
+      <description>Generic ARM SC000 device and CMSIS Core requiring GCC</description>
+      <require condition="ARMSC000 CMSIS"/>
+      <require condition="GCC"/>
+    </condition>
+
+    <condition id="ARMSC300 CMSIS">
+      <description>Generic ARM SC300 device and CMSIS Core</description>
+      <require Dvendor="ARM:82" Dname="ARMSC300"/>
+      <require Cclass="CMSIS" Cgroup="CORE"/>
+    </condition>
+
+    <condition id="ARMSC300 CMSIS GCC">
+      <description>Generic ARM SC300 device and CMSIS Core requiring GCC</description>
+      <require condition="ARMSC300 CMSIS"/>
+      <require condition="GCC"/>
+    </condition>
+
+    <condition id="CMSIS DSP">
+      <description>CMSIS DSP Library is for ARM Cortex-M Devices only and is prebuild for one of the compilers ARMCC, GCC or IAR</description>
+      <require condition="Cortex-M CMSIS Device"/>
+      <accept Tcompiler="GCC"/>
+      <accept Tcompiler="ARMCC"/>
+      <accept Tcompiler="IAR"/>
+    </condition>
+
+    <!-- ARMCC compiler -->
+    <condition id="CM0_LE_ARMCC">
+      <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M0"/>
+      <accept Dcore="Cortex-M0+"/>
+      <accept Dcore="SC000"/>
+      <require Dendian="Little-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM0_BE_ARMCC">
+      <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M0"/>
+      <accept Dcore="Cortex-M0+"/>
+      <accept Dcore="SC000"/>
+      <require Dendian="Big-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM3_LE_ARMCC">
+      <description>Cortex-M3 or SC300 processor based device in little endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M3"/>
+      <accept Dcore="SC300"/>
+      <require Dendian="Little-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM3_BE_ARMCC">
+      <description>Cortex-M3 or SC300 processor based device in big endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M3"/>
+      <accept Dcore="SC300"/>
+      <require Dendian="Big-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM4_LE_ARMCC">
+      <description>Cortex-M4 processor based device in little endian mode for the ARM Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM4_BE_ARMCC">
+      <description>Cortex-M4 processor based device in big endian mode for the ARM Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM4F_LE_ARMCC">
+      <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM4F_BE_ARMCC">
+      <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Big-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+    
+    <!-- XMC 4000 Series devices from Infineon require a special library -->
+    <condition id="CM4_LE_ARMCC_STD">
+      <description>Cortex-M4 processor based device in little endian mode for the ARM Compiler without Infineon devices</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>
+      <deny Dvendor="Infineon:7" Dname="XMC4*"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+    <condition id="CM4_LE_ARMCC_IFX">
+      <description>Cortex-M4 processor based device in little endian mode for the ARM Compiler and Infineon devices</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+    <condition id="CM4F_LE_ARMCC_STD">
+      <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the ARM Compiler without Infineon devices</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>
+      <deny Dvendor="Infineon:7" Dname="XMC4*"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+    <condition id="CM4F_LE_ARMCC_IFX">
+      <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the ARM Compiler and Infineon devices</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM7_LE_ARMCC">
+      <description>Cortex-M7 processor based device in little endian mode for the ARM Compiler</description>
+      <require Dcore="Cortex-M7" Dfpu="NO_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM7_BE_ARMCC">
+      <description>Cortex-M7 processor based device in big endian mode for the ARM Compiler</description>
+      <require Dcore="Cortex-M7" Dfpu="NO_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM7F_LE_ARMCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Little-endian"/>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM7F_BE_ARMCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Big-endian"/>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM7FSP_LE_ARMCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM7FSP_BE_ARMCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM7FDP_LE_ARMCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <condition id="CM7FDP_BE_ARMCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the ARM Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="ARMCC"/>
+    </condition>
+
+    <!-- GCC compiler -->
+    <condition id="CM0_LE_GCC">
+      <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M0"/>
+      <accept Dcore="Cortex-M0+"/>
+      <accept Dcore="SC000"/>
+      <require Dendian="Little-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM0_BE_GCC">
+      <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M0"/>
+      <accept Dcore="Cortex-M0+"/>
+      <accept Dcore="SC000"/>
+      <require Dendian="Big-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM3_LE_GCC">
+      <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M3"/>
+      <accept Dcore="SC300"/>
+      <require Dendian="Little-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM3_BE_GCC">
+      <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M3"/>
+      <accept Dcore="SC300"/>
+      <require Dendian="Big-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM4_LE_GCC">
+      <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM4_BE_GCC">
+      <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM4F_LE_GCC">
+      <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM4F_BE_GCC">
+      <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Big-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <!-- XMC 4000 Series devices from Infineon require a special library -->
+    <condition id="CM4_LE_GCC_STD">
+      <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler without Infineon devices</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>
+      <deny Dvendor="Infineon:7" Dname="XMC4*"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+    <condition id="CM4_LE_GCC_IFX">
+      <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler and Infineon devices</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+    <condition id="CM4F_LE_GCC_STD">
+      <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler without Infineon devices</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>
+      <deny Dvendor="Infineon:7" Dname="XMC4*"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+    <condition id="CM4F_LE_GCC_IFX">
+      <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler and Infineon devices</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian" Dvendor="Infineon:7" Dname="XMC4*"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM7_LE_GCC">
+      <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description>
+      <require Dcore="Cortex-M7" Dfpu="NO_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM7_BE_GCC">
+      <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description>
+      <require Dcore="Cortex-M7" Dfpu="NO_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM7F_LE_GCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Little-endian"/>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM7F_BE_GCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Big-endian"/>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM7FSP_LE_GCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM7FSP_BE_GCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM7FDP_LE_GCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <condition id="CM7FDP_BE_GCC">
+      <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="GCC"/>
+    </condition>
+
+    <!-- IAR compiler -->
+    <condition id="CM0_LE_IAR">
+      <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M0"/>
+      <accept Dcore="Cortex-M0+"/>
+      <accept Dcore="SC000"/>
+      <require Dendian="Little-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM0_BE_IAR">
+      <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M0"/>
+      <accept Dcore="Cortex-M0+"/>
+      <accept Dcore="SC000"/>
+      <require Dendian="Big-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM3_LE_IAR">
+      <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M3"/>
+      <accept Dcore="SC300"/>
+      <require Dendian="Little-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM3_BE_IAR">
+      <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M3"/>
+      <accept Dcore="SC300"/>
+      <require Dendian="Big-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM4_LE_IAR">
+      <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM4_BE_IAR">
+      <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="NO_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM4F_LE_IAR">
+      <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Little-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM4F_BE_IAR">
+      <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
+      <require Dcore="Cortex-M4" Dfpu="FPU" Dendian="Big-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM7_LE_IAR">
+      <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description>
+      <require Dcore="Cortex-M7" Dfpu="NO_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM7_BE_IAR">
+      <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description>
+      <require Dcore="Cortex-M7" Dfpu="NO_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM7F_LE_IAR">
+      <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Little-endian"/>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM7F_BE_IAR">
+      <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Big-endian"/>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM7FSP_LE_IAR">
+      <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM7FSP_BE_IAR">
+      <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="SP_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM7FDP_LE_IAR">
+      <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Little-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+
+    <condition id="CM7FDP_BE_IAR">
+      <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
+      <accept Dcore="Cortex-M7" Dfpu="DP_FPU" Dendian="Big-endian"/>
+      <require Tcompiler="IAR"/>
+    </condition>
+  </conditions>
+  
+  <components>
+    <!-- CMSIS-Core component -->
+    <component Cclass="CMSIS" Cgroup="CORE" Cversion="3.40.0" condition="CMSIS Core">
+      <description>CMSIS-CORE for Cortex-M, SC000, and SC300</description>
+      <files>
+        <!-- templates -->
+        <file category="source" attr="template" name="CMSIS\UserCodeTemplates\ARM\ITM_Retarget.c" select="CMSIS-CORE 'ITM Printf Debug'" condition="ARMCC"/>
+        <!-- CPU independent -->
+        <file category="doc"     name="CMSIS\Documentation\Core\html\index.html"/>
+        <file category="include" name="CMSIS\Include\"/>
+      </files>
+    </component>
+
+    <!-- CMSIS-Startup components -->
+    <!-- Cortex-M0 -->
+    <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS">
+      <description>System and Startup for Generic ARM Cortex-M0 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMCM0\Include\ARMCM0.h"/>
+        <!-- startup / system file -->
+        <file category="sourceAsm"    name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM0\Source\GCC\startup_ARMCM0.S" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM0\Source\GCC\gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM0\Source\IAR\startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM0\Source\system_ARMCM0.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup"   Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
+      <description>System and Startup for Generic ARM Cortex-M0 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMCM0\Include\ARMCM0.h"/>
+        <!-- startup / system file -->
+        <file category="sourceC"      name="Device\ARM\ARMCM0\Source\GCC\startup_ARMCM0.c" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM0\Source\GCC\gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM0\Source\system_ARMCM0.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+
+    <!-- Cortex-M0+ -->
+    <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS">
+      <description>System and Startup for Generic ARM Cortex-M0+ device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMCM0plus\Include\ARMCM0plus.h"/>
+        <!-- startup / system file -->
+        <file category="sourceAsm"    name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM0plus\Source\GCC\startup_ARMCM0plus.S" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM0plus\Source\GCC\gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM0plus\Source\IAR\startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup"   Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
+      <description>System and Startup for Generic ARM Cortex-M0+ device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMCM0plus\Include\ARMCM0plus.h"/>
+        <!-- startup / system file -->
+        <file category="sourceC"      name="Device\ARM\ARMCM0plus\Source\GCC\startup_ARMCM0plus.c" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM0plus\Source\GCC\gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+
+    <!-- Cortex-M3 -->
+    <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS">
+      <description>System and Startup for Generic ARM Cortex-M3 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMCM3\Include\ARMCM3.h"/>
+        <!-- startup / system file -->
+        <file category="sourceAsm"    name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.S" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM3\Source\IAR\startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM3\Source\system_ARMCM3.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup"   Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
+      <description>System and Startup for Generic ARM Cortex-M3 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMCM3\Include\ARMCM3.h"/>
+        <!-- startup / system file -->
+        <file category="sourceC"      name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM3\Source\system_ARMCM3.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+
+    <!-- Cortex-M4 -->
+    <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS">
+      <description>System and Startup for Generic ARM Cortex-M4 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="include" name="Device\ARM\ARMCM4\Include\"/>
+        <!-- startup / system file -->
+        <file category="sourceAsm"    name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.S" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM4\Source\IAR\startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM4\Source\system_ARMCM4.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup"   Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
+      <description>System and Startup for Generic ARM Cortex-M4 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="include" name="Device\ARM\ARMCM4\Include\"/>
+        <!-- startup / system file -->
+        <file category="sourceC"      name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM4\Source\system_ARMCM4.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+
+    <!-- Cortex-M7 -->
+    <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS">
+      <description>System and Startup for Generic ARM Cortex-M7 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="include"  name="Device\ARM\ARMCM7\Include\"/>
+        <!-- startup / system file -->
+        <file category="sourceAsm"    name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0" attr="config" condition="ARMCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM7\Source\GCC\startup_ARMCM7.S" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM7\Source\GCC\gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMCM7\Source\IAR\startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM7\Source\system_ARMCM7.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup"   Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
+      <description>System and Startup for Generic ARM Cortex-M4 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="include"  name="Device\ARM\ARMCM7\Include\"/>
+        <!-- startup / system file -->
+        <file category="sourceC"      name="Device\ARM\ARMCM7\Source\GCC\startup_ARMCM7.c" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMCM7\Source\GCC\gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceC"      name="Device\ARM\ARMCM7\Source\system_ARMCM7.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+
+    <!-- Cortex-SC000 -->
+    <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS">
+      <description>System and Startup for Generic ARM SC000 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMSC000\Include\ARMSC000.h"/>
+        <!-- startup / system file -->
+        <file category="sourceAsm"    name="Device\ARM\ARMSC000\Source\ARM\startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMSC000\Source\GCC\startup_ARMSC000.S" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMSC000\Source\GCC\gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMSC000\Source\IAR\startup_ARMSC000.s" version="1.0.0" attr="config" condition="IAR"/>
+        <file category="sourceC"      name="Device\ARM\ARMSC000\Source\system_ARMSC000.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup"   Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">
+      <description>System and Startup for Generic ARM SC000 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMSC000\Include\ARMSC000.h"/>
+        <!-- startup / system file -->
+        <file category="sourceC"      name="Device\ARM\ARMSC000\Source\GCC\startup_ARMSC000.c" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMSC000\Source\GCC\gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceC"      name="Device\ARM\ARMSC000\Source\system_ARMSC000.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+
+    <!-- Cortex-SC300 -->
+    <component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS">
+      <description>System and Startup for Generic ARM SC300 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMSC300\Include\ARMSC300.h"/>
+        <!-- startup / system file -->
+        <file category="sourceAsm"    name="Device\ARM\ARMSC300\Source\ARM\startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMSC300\Source\GCC\startup_ARMSC300.S" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMSC300\Source\GCC\gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceAsm"    name="Device\ARM\ARMSC300\Source\IAR\startup_ARMSC300.s" version="1.0.0" attr="config" condition="IAR"/>
+        <file category="sourceC"      name="Device\ARM\ARMSC300\Source\system_ARMSC300.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+    <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup"   Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">
+      <description>System and Startup for Generic ARM SC300 device</description>
+      <files>
+        <!-- include folder / device header file -->
+        <file category="header"  name="Device\ARM\ARMSC300\Include\ARMSC300.h"/>
+        <!-- startup / system file -->
+        <file category="sourceC"      name="Device\ARM\ARMSC300\Source\GCC\startup_ARMSC300.c" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="linkerScript" name="Device\ARM\ARMSC300\Source\GCC\gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
+        <file category="sourceC"      name="Device\ARM\ARMSC300\Source\system_ARMSC300.c"      version="1.0.0" attr="config"/>
+      </files>
+    </component>
+
+    <!-- CMSIS-DSP component -->
+    <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.4.2" condition="CMSIS DSP">
+      <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
+      <files>
+        <!-- CPU independent -->
+        <file category="doc" name="CMSIS\Documentation\DSP\html\index.html"/>
+        <!-- <file category="header" name="CMSIS\Include\arm_common_tables.h"/> -->
+        <file category="header" name="CMSIS\Include\arm_math.h"/>
+        <!-- CPU and Compiler dependent -->
+        <!-- ARMCC -->
+        <file category="library" condition="CM0_LE_ARMCC"     name="CMSIS\Lib\ARM\arm_cortexM0l_math.lib"      src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM0_BE_ARMCC"     name="CMSIS\Lib\ARM\arm_cortexM0b_math.lib"      src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM3_LE_ARMCC"     name="CMSIS\Lib\ARM\arm_cortexM3l_math.lib"      src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM3_BE_ARMCC"     name="CMSIS\Lib\ARM\arm_cortexM3b_math.lib"      src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM4_LE_ARMCC"     name="CMSIS\Lib\ARM\arm_cortexM4l_math.lib"      src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM4_BE_ARMCC"     name="CMSIS\Lib\ARM\arm_cortexM4b_math.lib"      src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM4F_LE_ARMCC"    name="CMSIS\Lib\ARM\arm_cortexM4lf_math.lib"     src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM4F_BE_ARMCC"    name="CMSIS\Lib\ARM\arm_cortexM4bf_math.lib"     src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM7_LE_ARMCC"     name="CMSIS\Lib\ARM\arm_cortexM7l_math.lib"      src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM7_BE_ARMCC"     name="CMSIS\Lib\ARM\arm_cortexM7b_math.lib"      src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM7FSP_LE_ARMCC"  name="CMSIS\Lib\ARM\arm_cortexM7lfsp_math.lib"   src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM7FSP_BE_ARMCC"  name="CMSIS\Lib\ARM\arm_cortexM7bfsp_math.lib"   src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM7FDP_LE_ARMCC"  name="CMSIS\Lib\ARM\arm_cortexM7lfdp_math.lib"   src="CMSIS\DSP_Lib\Source\ARM"/>
+        <file category="library" condition="CM7FDP_BE_ARMCC"  name="CMSIS\Lib\ARM\arm_cortexM7bfdp_math.lib"   src="CMSIS\DSP_Lib\Source\ARM"/>
+        <!-- GCC -->
+        <file category="library" condition="CM0_LE_GCC"       name="CMSIS\Lib\GCC\libarm_cortexM0l_math.a"     src="CMSIS\DSP_Lib\Source\GCC"/>
+        <file category="library" condition="CM3_LE_GCC"       name="CMSIS\Lib\GCC\libarm_cortexM3l_math.a"     src="CMSIS\DSP_Lib\Source\GCC"/>
+        <file category="library" condition="CM4_LE_GCC"       name="CMSIS\Lib\GCC\libarm_cortexM4l_math.a"     src="CMSIS\DSP_Lib\Source\GCC"/>
+        <file category="library" condition="CM4F_LE_GCC"      name="CMSIS\Lib\GCC\libarm_cortexM4lf_math.a"    src="CMSIS\DSP_Lib\Source\GCC"/>
+        <!--file category="library" condition="CM7_LE_GCC"       name="CMSIS\Lib\GCC\libarm_cortexM7l_math.a"     src="CMSIS\DSP_Lib\Source\GCC"/-->
+        <!--file category="library" condition="CM7FSP_LE_GCC"    name="CMSIS\Lib\GCC\libarm_cortexM7lfsp_math.a"  src="CMSIS\DSP_Lib\Source\GCC"/-->
+        <!--file category="library" condition="CM7FDP_LE_GCC"    name="CMSIS\Lib\GCC\libarm_cortexM7lfdp_math.a"  src="CMSIS\DSP_Lib\Source\GCC"/-->
+      </files>
+    </component>
+
+    <!-- CMSIS-RTOS Keil RTX component -->
+    <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.75.0" condition="CMSIS Core">
+      <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
+      <RTE_Components_h>
+        <!-- the following content goes into file 'RTE_Components.h' -->
+        #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
+        #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
+      </RTE_Components_h>
+      <files>
+        <!-- CPU independent -->
+        <file category="doc" name="CMSIS_RTX\Doc\index.html"/>
+        <file category="header" name="CMSIS_RTX\INC\cmsis_os.h"/>
+        <file category="source" attr="config"   name="CMSIS_RTX\Templates\RTX_Conf_CM.c" version="4.70"/>
+        
+        <!-- RTX templates -->
+        <file category="header" attr="template" name="CMSIS_RTX\UserCodeTemplates\osObjects.h" select="CMSIS-RTOS 'main' function"/>
+        <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\main.c"      select="CMSIS-RTOS 'main' function"/>
+        <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
+        <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
+        <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
+        <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Mutex.c"     select="CMSIS-RTOS Mutex"/>
+        <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Semaphore.c" select="CMSIS-RTOS Semaphore"/>
+        <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Thread.c"    select="CMSIS-RTOS Thread"/>
+        <file category="source" attr="template" name="CMSIS_RTX\UserCodeTemplates\Timer.c"     select="CMSIS-RTOS Timer"/>
+        <!-- tool-chain specific template file -->
+        <file category="source" attr="template" condition="ARMCC" name="CMSIS_RTX\SRC\ARM\SVC_Table.s" select="CMSIS-RTOS User SVC"/>
+        <file category="source" attr="template" condition="GCC"   name="CMSIS_RTX\SRC\GCC\SVC_Table.S" select="CMSIS-RTOS User SVC"/>
+        <file category="source" attr="template" condition="IAR"   name="CMSIS_RTX\SRC\IAR\SVC_Table.s" select="CMSIS-RTOS User SVC"/>
+
+        <!-- CPU and Compiler dependent -->
+        <!-- ARMCC -->
+        <file category="library" condition="CM0_LE_ARMCC"      name="CMSIS_RTX\LIB\ARM\RTX_CM0.lib"      src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM0_BE_ARMCC"      name="CMSIS_RTX\LIB\ARM\RTX_CM0_B.lib"    src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM3_LE_ARMCC"      name="CMSIS_RTX\LIB\ARM\RTX_CM3.lib"      src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM3_BE_ARMCC"      name="CMSIS_RTX\LIB\ARM\RTX_CM3_B.lib"    src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM4_LE_ARMCC_STD"  name="CMSIS_RTX\LIB\ARM\RTX_CM3.lib"      src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM4_LE_ARMCC_IFX"  name="CMSIS_RTX\LIB\ARM\RTX_CM3_IFX.lib"  src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM4_BE_ARMCC"      name="CMSIS_RTX\LIB\ARM\RTX_CM3_B.lib"    src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM4F_LE_ARMCC_STD" name="CMSIS_RTX\LIB\ARM\RTX_CM4.lib"      src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM4F_LE_ARMCC_IFX" name="CMSIS_RTX\LIB\ARM\RTX_CM4_IFX.lib"  src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM4F_BE_ARMCC"     name="CMSIS_RTX\LIB\ARM\RTX_CM4_B.lib"    src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM7_LE_ARMCC"      name="CMSIS_RTX\LIB\ARM\RTX_CM3.lib"      src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM7_BE_ARMCC"      name="CMSIS_RTX\LIB\ARM\RTX_CM3_B.lib"    src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM7F_LE_ARMCC"     name="CMSIS_RTX\LIB\ARM\RTX_CM4.lib"      src="CMSIS_RTX\SRC\ARM"/>
+        <file category="library" condition="CM7F_BE_ARMCC"     name="CMSIS_RTX\LIB\ARM\RTX_CM4_B.lib"    src="CMSIS_RTX\SRC\ARM"/>
+        <!-- GCC -->
+        <file category="library" condition="CM0_LE_GCC"        name="CMSIS_RTX\LIB\GCC\libRTX_CM0.a"     src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM0_BE_GCC"        name="CMSIS_RTX\LIB\GCC\libRTX_CM0_B.a"   src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM3_LE_GCC"        name="CMSIS_RTX\LIB\GCC\libRTX_CM3.a"     src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM3_BE_GCC"        name="CMSIS_RTX\LIB\GCC\libRTX_CM3_B.a"   src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM4_LE_GCC_STD"    name="CMSIS_RTX\LIB\GCC\libRTX_CM3.a"     src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM4_LE_GCC_IFX"    name="CMSIS_RTX\LIB\GCC\libRTX_CM3_IFX.a" src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM4_BE_GCC"        name="CMSIS_RTX\LIB\GCC\libRTX_CM3_B.a"   src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM4F_LE_GCC_STD"   name="CMSIS_RTX\LIB\GCC\libRTX_CM4.a"     src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM4F_LE_GCC_IFX"   name="CMSIS_RTX\LIB\GCC\libRTX_CM4_IFX.a" src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM4F_BE_GCC"       name="CMSIS_RTX\LIB\GCC\libRTX_CM4_B.a"   src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM7_LE_GCC"        name="CMSIS_RTX\LIB\GCC\libRTX_CM3.a"     src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM7_BE_GCC"        name="CMSIS_RTX\LIB\GCC\libRTX_CM3_B.a"   src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM7F_LE_GCC"       name="CMSIS_RTX\LIB\GCC\libRTX_CM4.a"     src="CMSIS_RTX\SRC\GCC"/>
+        <file category="library" condition="CM7F_BE_GCC"       name="CMSIS_RTX\LIB\GCC\libRTX_CM4_B.a"   src="CMSIS_RTX\SRC\GCC"/>
+        <!-- IAR -->
+        <file category="library" condition="CM0_LE_IAR"        name="CMSIS_RTX\LIB\IAR\RTX_CM0.a"        src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM0_BE_IAR"        name="CMSIS_RTX\LIB\IAR\RTX_CM0_B.a"      src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM3_LE_IAR"        name="CMSIS_RTX\LIB\IAR\RTX_CM3.a"        src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM3_BE_IAR"        name="CMSIS_RTX\LIB\IAR\RTX_CM3_B.a"      src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM4_LE_IAR"        name="CMSIS_RTX\LIB\IAR\RTX_CM3.a"        src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM4_BE_IAR"        name="CMSIS_RTX\LIB\IAR\RTX_CM3_B.a"      src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM4F_LE_IAR"       name="CMSIS_RTX\LIB\IAR\RTX_CM4.a"        src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM4F_BE_IAR"       name="CMSIS_RTX\LIB\IAR\RTX_CM4_B.a"      src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM7_LE_IAR"        name="CMSIS_RTX\LIB\IAR\RTX_CM3.a"        src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM7_BE_IAR"        name="CMSIS_RTX\LIB\IAR\RTX_CM3_B.a"      src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM7F_LE_IAR"       name="CMSIS_RTX\LIB\IAR\RTX_CM4.a"        src="CMSIS_RTX\SRC\IAR"/>
+        <file category="library" condition="CM7F_BE_IAR"       name="CMSIS_RTX\LIB\IAR\RTX_CM4_B.a"      src="CMSIS_RTX\SRC\IAR"/>
+      </files>
+    </component>
+  </components>
+ 
+  <boards>
+    <board name="uVision Simulator" vendor="Keil">
+      <description>uVision Simulator</description>
+      <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
+      <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
+      <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
+      <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
+    </board>
+  </boards>
+
+  <examples>
+    <example name="DSP_Lib Class Marks example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_class_marks_example\ARM">
+      <description>DSP_Lib Class Marks example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_class_marks_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+    <example name="DSP_Lib Convolution example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_convolution_example\ARM">
+      <description>DSP_Lib Convolution example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_convolution_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+    <example name="DSP_Lib Dotproduct example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_dotproduct_example\ARM">
+      <description>DSP_Lib Dotproduct example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_dotproduct_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+    <example name="DSP_Lib FFT Bin example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_fft_bin_example\ARM">
+      <description>DSP_Lib FFT Bin example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_fft_bin_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+    <example name="DSP_Lib FIR example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_fir_example\ARM">
+      <description>DSP_Lib FIR example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_fir_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+    <example name="DSP_Lib Graphic Equalizer example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_graphic_equalizer_example\ARM">
+      <description>DSP_Lib Graphic Equalizer example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_graphic_equalizer_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+    <example name="DSP_Lib Linear Interpolation example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_linear_interp_example\ARM">
+      <description>DSP_Lib Linear Interpolation example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_linear_interp_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+    <example name="DSP_Lib Matrix example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_matrix_example\ARM">
+      <description>DSP_Lib Matrix example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_matrix_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+    <example name="DSP_Lib Signal Convergence example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_signal_converge_example\ARM">
+      <description>DSP_Lib Signal Convergence example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_signal_converge_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+    <example name="DSP_Lib Sinus/Cosinus example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_sin_cos_example\ARM">
+      <description>DSP_Lib Sinus/Cosinus example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_sin_cos_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+
+
+    <example name="DSP_Lib Variance example" doc="Abstract.txt" folder="CMSIS\DSP_Lib\Examples\arm_variance_example\ARM">
+      <description>DSP_Lib Variance example</description>
+      <board name="uVision Simulator" vendor="Keil"/>
+      <project>
+        <environment name="uv" load="arm_variance_example.uvprojx"/>
+      </project>
+      <attributes>
+        <component Cclass="CMSIS" Cgroup="CORE"/>
+        <component Cclass="CMSIS" Cgroup="DSP"/>
+        <component Cclass="Device" Cgroup="Startup"/>
+        <category>Getting Started</category>
+      </attributes>
+    </example>
+  </examples>
+
+</package>
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/uf2-samdx1/lib/cmsis/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf
new file mode 100644
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diff --git a/uf2-samdx1/lib/cmsis/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf b/uf2-samdx1/lib/cmsis/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf
new file mode 100644
index 00000000..fb44cda0
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf
@@ -0,0 +1,793 @@
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+{\f2\fbidi \fmodern\fcharset0\fprq1{\*\panose 02070309020205020404}Courier New;}{\f3\fbidi \froman\fcharset2\fprq2{\*\panose 05050102010706020507}Symbol;}{\f10\fbidi \fnil\fcharset2\fprq2{\*\panose 05000000000000000000}Wingdings;}
+{\f14\fbidi \froman\fcharset136\fprq2{\*\panose 02020500000000000000}PMingLiU{\*\falt \'b7\'73\'b2\'d3\'a9\'fa\'c5\'e9};}{\f34\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria Math;}
+{\f37\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;}{\f38\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604030504040204}Tahoma;}{\f39\fbidi \fmodern\fcharset0\fprq1{\*\panose 020b0609020204030204}Consolas;}
+{\f40\fbidi \froman\fcharset136\fprq2{\*\panose 02020500000000000000}@PMingLiU;}{\flomajor\f31500\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}
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+{\f44\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\f45\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\f46\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\f47\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
+{\f48\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\f49\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\f51\fbidi \fswiss\fcharset238\fprq2 Arial CE;}{\f52\fbidi \fswiss\fcharset204\fprq2 Arial Cyr;}
+{\f54\fbidi \fswiss\fcharset161\fprq2 Arial Greek;}{\f55\fbidi \fswiss\fcharset162\fprq2 Arial Tur;}{\f56\fbidi \fswiss\fcharset177\fprq2 Arial (Hebrew);}{\f57\fbidi \fswiss\fcharset178\fprq2 Arial (Arabic);}
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+{\fbimajor\f31544\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbimajor\f31545\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fbimajor\f31546\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}
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+{\flominor\f31552\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\flominor\f31553\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\flominor\f31554\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
+{\flominor\f31555\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\flominor\f31556\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fdbminor\f31558\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
+{\fdbminor\f31559\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fdbminor\f31561\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fdbminor\f31562\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
+{\fdbminor\f31563\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fdbminor\f31564\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fdbminor\f31565\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
+{\fdbminor\f31566\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fhiminor\f31568\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}{\fhiminor\f31569\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}
+{\fhiminor\f31571\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;}{\fhiminor\f31572\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}{\fhiminor\f31575\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}
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+{\title LEC-PRE-00489 ~ EULA for CMSIS Deliverables}{\author emidre01}{\operator Joachim Krech}{\creatim\yr2014\mo6\dy2\hr8\min46}{\revtim\yr2014\mo6\dy2\hr8\min48}{\printim\yr2014\mo6\dy2\hr8\min46}{\version3}{\edmins4}{\nofpages4}{\nofwords1696}
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+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+\par THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 
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+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING OR OTHERWISE USING OR COPYING THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 OF }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  AND YOU MAY NOT INSTALL, USE OR COPY THE }{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 .
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93
+CMSIS Deliverables\'94 means the following components: (i) CMSIS-CORE; (ii) CMSIS-DRIVER; (iii) CMSIS-DSP; (iv) CMSIS-PACK; (v) CMSIS-RTOS API; and (vi) CMSIS-SVD . 
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-CORE
+\'94 means the specification defining the application programming interface, naming and coding conventions for the Cortex-M processor cores.
+\par \'94}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 CMSIS-DRIVER}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 
+\insrsid11754636 \hich\af37\dbch\af37\loch\f37  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 means the specification defining }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\hich\af1\dbch\af37\loch\f1 a generic}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 p}{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 eripheral }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 d}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 river application programming interface, naming and coding conventions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 .
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  \'93CMSIS-DSP\'94
+ means the digital signal process (DSP) library specification defining the application programming interface of a DSP library implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93}{
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 CMSIS-PACK}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 
+\insrsid11754636\charrsid13240697 \hich\af37\dbch\af37\loch\f37  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 means the specification defining a software pack file format}{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 , verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 and the associated XML schema file}{\rtlch\fcs1 
+\af0 \ltrch\fcs0 \insrsid11754636\charrsid13240697 .}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-RTOS API\'94 means the
+ real-time operating system (RTOS) specification defining a generic application programming interface layer for a RTOS system}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 
+Notwithstanding the foregoing, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1 the CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1  shall not}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1  include}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1  (i) the implementation of other published specification
+\hich\af1\dbch\af37\loch\f1 s }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 referenced }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 in th}{
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 
+; (ii) any enabling technologies that may be necessary to make or use any product or portion thereof that }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 complies with the }{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 , but are not themselves expressly set forth in the }{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1  (e.\hich\af1\dbch\af37\loch\f1 
+g. compiler front ends, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; applications, operating system or driver software; RISC architecture; processor microarchitecture)
+\hich\af1\dbch\af37\loch\f1 ;\hich\af1\dbch\af37\loch\f1  (iii) maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 
+\hich\af1\dbch\af37\loch\f1  level representations of integrated circuit designs.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  \'93CMSIS-SVD\'94 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 means }{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 the specification defining the System View Description (SVD), verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407 and associated XML}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636  schema}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407  files. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  \'93Separate Files\'94 means the components in }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid10227990 the CMSIS reference implementation identified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+ in the Schedule that demonstrate the usage of the CMSIS-CORE, CMSIS-DRIVER, CMSIS-DSP, CMSIS-PACK and CMSIS-RTOS API, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid3618484  for microprocessors 
+or device specific software applications that are for use with microprocessors.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  
+\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 1. LICENCE GRANTS.
+\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES 
+\par 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable }{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 licence, to use and copy the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 for the purpose of: }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
+\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 (i) subject to clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 , developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the }{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ; and 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 (ii) distributing and having distributed (directly or through your customers and authorised distributors) the CMSIS-D}{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547  unmodified, with the products}{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135  you have developed under }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Clause 1.1 (i) }{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 provided you preserve any copyright notices which are included with the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 . 
+\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  CONDITIONS ON REDISTRIBUTION}{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+\par 
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 
+\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 
+If you distribute (directly or through your customers and authorised distributors) the products you have created pursuant to Clauses 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1  
+}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (i) you agree: (a) not to use ARM\hich\f1 \rquote \loch\f1 s name\hich\af1\dbch\af37\loch\f1 
+, logo or trademarks to market any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1928237 products created under Clause 1.1 (i); }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (b) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 to }{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 pr}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 serve any copyright notices included in the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 
+\hich\af1\dbch\af37\loch\f1 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 
+\hich\af1\dbch\af37\loch\f1 ; and (c) to ensure your customers and authorised distributors comply with this Clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 2}{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1     }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 2. RESTRICTIONS ON USE OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+ CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 .
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 
+\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 PERMITTED USERS: The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 shall be used only by you (either a single individual, or single legal entity) your employees, or by your }{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 on-site }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+bona fide sub-contractors for whose acts and omissions you hereby agree to be responsible to ARM}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  for}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  to the same extent as }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 you are for }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 your employees, and provided always that such sub-contractors}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 :}{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  (i) are contractually obligated to use the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 only for your benefit}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+;}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  and (i}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 i}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 ) agree to assign all their work product and any rights they create therein in the supply of such work to you.
+\par COPYRIGHT AND RESERVATION OF RIGHTS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 : The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 
+ are owned by ARM or its licensors and are protected by copyright and other intellectual property laws and international treaties. The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502  are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the }{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 
+ or any intellectual property therein. In no event shall the licences granted herein be construed as granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 3}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . SUPPORT.
+\par ARM is not obligated to support the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables but}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  may do so entirely at ARM's discretion. 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 4}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 NO }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 WARRANT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Y.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+\par YOU AGREE THAT THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES ARE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+ LICENSED "AS IS", AND THAT ARM EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARR
+ANTIES OF NON-INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  THE CMSIS DELIVERABLES MAY CONTAIN ERRORS.  }{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . LIMITATION OF LIABILITY.
+\par THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE SHALL NOT EXCEED }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE GREATER OF (I) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+THE TOTAL OF SUMS PAID BY YOU TO ARM (IF ANY) FOR THIS LICENCE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  AND (II) US$10.00}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636   THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN THIS LICEN
+CE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 6
+}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 . THIRD PARTY RIGHTS.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13830602 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 
+The Separate Files are delivered subject to and your use is governed by their own separate licence agreements. This Licence does not apply to such Separate Files and the\hich\af1\dbch\af37\loch\f1 \hich\f1 y are not included in the term \'93}{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 
+\loch\af1\dbch\af37\hich\f1 \'94\loch\f1 \hich\f1  under this Licence. You agree to comply with all terms and conditions imposed on you in respect of such Separate Files including those identified in the Schedule (\'93\loch\f1 \hich\f1 Third Party Terms
+\'94\loch\f1 ).  
+\par \hich\af1\dbch\af37\loch\f1 ARM HEREBY DISCLA\hich\af1\dbch\af37\loch\f1 \hich\f1 
+IMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY \'93\loch\f1 \hich\f1 
+OTHER CODE\'94\loch\f1 ), AND THE USE OF\hich\af1\dbch\af37\loch\f1  \hich\af1\dbch\af37\loch\f1 
+ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.
+\par \hich\af1\dbch\af37\loch\f1 NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, \hich\af1\dbch\af37\loch\f1 
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EX
+\hich\af1\dbch\af37\loch\f1 E\hich\af1\dbch\af37\loch\f1 RCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 7}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . U.S. GOVERNMENT END USERS.
+\par US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . TERM AND TERMINATION.
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+This Licence shall remain in force until terminated }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 in accordance with the terms of Clause 8.2 or Clause 8.3 below}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+\par 8.2 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon giving written notice to you}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 .  You may terminate this Licence at any time. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 
+8.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you asserts any patents against ARM, ARM affiliates, third parties who have a valid licence fro\hich\af1\dbch\af37\loch\f1 
+m ARM for the CMSIS Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate) patent is Necessary to implement the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 . In this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1  (i) "affiliate" means any entity controlling, contr\hich\af1\dbch\af37\loch\f1 
+olled by or under common control with a party (in fact or in law, via voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert" means to allege infringement in legal or administrative proceedings, o
+\hich\af1\dbch\af37\loch\f1 r\hich\af1\dbch\af37\loch\f1  proceedings before any other competent trade, arbitral or international authority; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 \hich\f1 (iii) \'93\loch\f1 \hich\f1 Necessary\'94\loch\f1 
+ means with respect to any claims of any patent, those claims which, without the appropriate permission of the patent owner, will be infringed when imp\hich\af1\dbch\af37\loch\f1 lementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 
+because no alternative, commercially reasonable, non-infringing way of implementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 is known.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid5900444 \hich\af1\dbch\af37\loch\f1  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.4 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 Upon termination of this Licence,}{
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  you shall stop }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 
+using the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 
+ and destroy all copies of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396  in your possession. The provisions of clauses 5, 6, 7, 8 and 9 shall survive termination of this Licence.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636   
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 9}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . GENERAL.
+\par This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by you and ARM, this is the only agreement between you and ARM relating to the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
+ and it may only be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence may not be modified by purchase orders, ad
+vertising or other representation by any person. If any clause or sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this Licence shall not be affected thereby. The failure by ARM to enforce any o
+f the provisions of this Licence, unless waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of this Licence in the future.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636   This Licence may not be assigned without the prior written consent of ARM.
+\par }\pard \ltrpar\qc \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \page SCHEDULE
+\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Separate Files
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 The }{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 package }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 also }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 includes the components}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  contained in the following directories}{\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
+\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (a)\tab}}\pard \ltrpar
+\qj \fi-360\li720\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\ls16\adjustright\rin0\lin720\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 
+\hich\af1\dbch\af37\loch\f1 DSP_Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  -  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 
+DSP Library sources and examples}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; 
+\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (b)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 
+\hich\af1\dbch\af37\loch\f1 Include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  - Header files; 
+\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (c)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 
+\hich\af1\dbch\af37\loch\f1 Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 
+DSP Library build for various toolchains}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; 
+\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (d)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 
+\hich\af1\dbch\af37\loch\f1 RTOS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 
+Header file template for CMSIS-RTOS implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; and 
+\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (e)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 .}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /Device - T}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid14488502 \hich\af1\dbch\af37\loch\f1 emplate files and implementations for Cortex-M class processors}{
+\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 . 
+\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\par \hich\af1\dbch\af37\loch\f1 All of the above components (a\hich\f1 \endash \loch\f1  e) are licensed to you under the terms of the BSD licence, which is incorp\hich\af1\dbch\af37\loch\f1 orated within or alongside the above components.  
+\par }\pard \ltrpar\qj \li284\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin284\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1   }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
+\f1\fs18\insrsid11754636\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (f)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1    }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13975144 
+\hich\af1\dbch\af37\loch\f1 ./CMSIS/Driver \hich\f1 \endash \loch\f1  CMSIS-Driver header files}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13975144 \hich\af1\dbch\af37\loch\f1   (g)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 
+\hich\af37\dbch\af37\loch\f37  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ./CMSIS/Pack \hich\f1 \endash \loch\f1  Example Device Family Pack}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636\charrsid13975144 
+
+\par }\pard\plain \ltrpar\s32\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \rtlch\fcs1 \af0\afs21\alang1025 \ltrch\fcs0 \f39\fs21\lang2057\langfe1033\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 
+\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\par The above components (f \endash  g) are licensed to you under the terms of the zlib licence, which is incorporated within or alongside the above components.
+\par 
+\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid14488502        }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
+\par 
+\par 
+\par }\pard\plain \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 
+\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid2958685 \hich\af1\dbch\af37\loch\f1 ARM contract reference LEC-PRE-00489}{\rtlch\fcs1 \af1\afs18 
+\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - v3.0}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid2958685 
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\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c
new file mode 100644
index 00000000..4f8d3c6b
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c
@@ -0,0 +1,189 @@
+#include "Driver_ETH_MAC.h"
+
+#include "RTE_Components.h"
+
+#define ARM_ETH_MAC_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 00) /* driver version */
+
+#if (defined(RTE_Drivers_ETH_MAC0) && !RTE_ENET)
+#error "Ethernet not configured in RTE_Device.h!"
+#endif
+
+ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion(void)
+{
+}
+
+ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities(void)
+{
+}
+
+int32_t ARM_ETH_MAC_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_ETH_MAC_Uninitialize(void)
+{
+}
+
+int32_t ARM_ETH_MAC_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_ETH_MAC_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr)
+{
+}
+
+int32_t ARM_ETH_MAC_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr)
+{
+}
+
+int32_t ARM_ETH_MAC_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)
+{
+}
+
+int32_t ARM_ETH_MAC_SendFrame(const uint8_t *frame, uint32_t len, uint32_t flags)
+{
+}
+
+int32_t ARM_ETH_MAC_ReadFrame(uint8_t *frame, uint32_t len)
+{
+}
+
+uint32_t ARM_ETH_MAC_GetRxFrameSize(void)
+{
+}
+
+int32_t ARM_ETH_MAC_GetRxFrameTime(ARM_ETH_MAC_TIME *time)
+{
+}
+
+int32_t ARM_ETH_MAC_GetTxFrameTime(ARM_ETH_MAC_TIME *time)
+{
+}
+
+int32_t ARM_ETH_MAC_Control(uint32_t control, uint32_t arg)
+{
+    switch (control)
+    {
+    case ARM_ETH_MAC_CONFIGURE:
+
+        switch (arg & ARM_ETH_MAC_SPEED_Msk)
+        {
+        case ARM_ETH_MAC_SPEED_10M:
+            break;
+        case ARM_ETH_SPEED_100M:
+            break;
+        default:
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+
+        switch (arg & ARM_ETH_MAC_DUPLEX_Msk)
+        {
+        case ARM_ETH_MAC_DUPLEX_FULL:
+            break;
+        }
+
+        if (arg & ARM_ETH_MAC_LOOPBACK)
+        {
+        }
+
+        if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) ||
+            (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX))
+        {
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+
+        if (!(arg & ARM_ETH_MAC_ADDRESS_BROADCAST))
+        {
+        }
+
+        if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST)
+        {
+        }
+
+        if (arg & ARM_ETH_MAC_ADDRESS_ALL)
+        {
+        }
+
+        break;
+
+    case ARM_ETH_MAC_CONTROL_TX:
+        break;
+
+    case ARM_ETH_MAC_CONTROL_RX:
+        break;
+
+    case ARM_ETH_MAC_FLUSH:
+        if (arg & ARM_ETH_MAC_FLUSH_RX)
+        {
+        }
+        if (arg & ARM_ETH_MAC_FLUSH_TX)
+        {
+        }
+        break;
+
+    case ARM_ETH_MAC_SLEEP:
+        break;
+
+    case ARM_ETH_MAC_VLAN_FILTER:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_ETH_MAC_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time)
+{
+}
+
+int32_t ARM_ETH_MAC_PHY_Read(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+{
+}
+
+int32_t ARM_ETH_MAC_PHY_Write(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+{
+}
+
+void ARM_ETH_MAC_SignalEvent(uint32_t event)
+{
+}
+
+// end group eth_mac_control
+
+// End ETH MAC Interface
+
+ARM_DRIVER_ETH_MAC Driver_ETH_MAC =
+{
+    ARM_ETH_MAC_GetVersion,
+    ARM_ETH_MAC_GetCapabilities,
+    ARM_ETH_MAC_Initialize,
+    ARM_ETH_MAC_Uninitialize,
+    ARM_ETH_MAC_PowerControl,
+    ARM_ETH_MAC_GetMacAddress,
+    ARM_ETH_MAC_SetMacAddress,
+    ARM_ETH_MAC_SetAddressFilter,
+    ARM_ETH_MAC_SendFrame,
+    ARM_ETH_MAC_ReadFrame,
+    ARM_ETH_MAC_GetRxFrameSize,
+    ARM_ETH_MAC_GetRxFrameTime,
+    ARM_ETH_MAC_GetTxFrameTime,
+    ARM_ETH_MAC_ControlTimer,
+    ARM_ETH_MAC_Control,
+    ARM_ETH_MAC_PHY_Read,
+    ARM_ETH_MAC_PHY_Write
+};
+
\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c
new file mode 100644
index 00000000..9d0f3126
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c
@@ -0,0 +1,119 @@
+#include "Driver_ETH_PHY.h"
+
+#define ARM_ETH_PHY_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(5, 10) /* driver version */
+
+#ifndef ETH_PHY_NUM
+#define ETH_PHY_NUM                0 /* Default driver number */
+#endif
+
+#ifndef ETH_PHY_ADDR
+#define ETH_PHY_ADDR    0x01     /* Default device address */
+#endif
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_ETH_PHY_API_VERSION,
+    ARM_ETH_PHY_DRV_VERSION
+};
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion(void)
+{
+}
+
+int32_t ARM_ETH_PHY_Initialize(ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write)
+{
+}
+
+int32_t ARM_ETH_PHY_Uninitialize(void)
+{
+}
+
+int32_t ARM_ETH_PHY_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_ETH_PHY_SetInterface(uint32_t interface)
+{
+    switch (interface)
+    {
+    case ARM_ETH_INTERFACE_MII:
+
+        break;
+    case ARM_ETH_INTERFACE_RMII:
+        break;
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_ETH_PHY_SetMode(uint32_t mode)
+{
+    switch (mode & ARM_ETH_PHY_SPEED_Msk)
+    {
+    case ARM_ETH_PHY_SPEED_10M:
+        break;
+    case ARM_ETH_PHY_SPEED_100M:
+        break;
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+
+    switch (mode & ARM_ETH_PHY_DUPLEX_Msk)
+    {
+    case ARM_ETH_PHY_DUPLEX_HALF:
+        break;
+    case ARM_ETH_PHY_DUPLEX_FULL:
+        break;
+    }
+
+    if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE)
+    {
+    }
+
+    if (mode & ARM_ETH_PHY_LOOPBACK)
+    {
+    }
+
+    if (mode & ARM_ETH_PHY_ISOLATE)
+    {
+    }
+}
+
+ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState(void)
+{
+}
+
+ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo(void)
+{
+}
+
+ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY_(ETH_PHY_NUM) =
+{
+    ARM_ETH_PHY_GetVersion,
+    ARM_ETH_PHY_Initialize,
+    ARM_ETH_PHY_Uninitialize,
+    ARM_ETH_PHY_PowerControl,
+    ARM_ETH_PHY_SetInterface,
+    ARM_ETH_PHY_SetMode,
+    ARM_ETH_PHY_GetLinkState,
+    ARM_ETH_PHY_GetLinkInfo,
+};
+
\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_Flash.c b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_Flash.c
new file mode 100644
index 00000000..ca26726b
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_Flash.c
@@ -0,0 +1,111 @@
+#include "Driver_Flash.h"
+
+#define ARM_FLASH_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 00) /* driver version */
+
+#ifndef DRIVER_FLASH_NUM
+#define DRIVER_FLASH_NUM         0      /* Default driver number */
+#endif
+
+/* Sector Information */
+#ifdef FLASH_SECTORS
+static ARM_FLASH_SECTOR FLASH_SECTOR_INFO[FLASH_SECTOR_COUNT] = {
+    FLASH_SECTORS
+};
+#else
+#define FLASH_SECTOR_INFO    NULL
+#endif
+
+/* Flash Information */
+static ARM_FLASH_INFO FlashInfo = {
+    0, //FLASH_SECTOR_INFO,
+    0, //FLASH_SECTOR_COUNT,
+    0, //FLASH_SECTOR_SIZE,
+    0, //FLASH_PAGE_SIZE,
+    0, //FLASH_PROGRAM_UNIT,
+    0  //FLASH_ERASED_VALUE
+};
+
+/* Flash Status */
+static ARM_FLASH_STATUS FlashStatus;
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_FLASH_API_VERSION,
+    ARM_FLASH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
+    0,  /* event_ready */
+    0,  /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
+    0   /* erase_chip */
+};
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
+{
+}
+
+ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
+{
+}
+
+int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_Flash_Uninitialize(void)
+{
+}
+
+int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
+{
+}
+
+int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt)
+{
+}
+
+int32_t ARM_Flash_EraseSector(uint32_t addr)
+{
+}
+
+int32_t ARM_Flash_EraseChip(void)
+{
+}
+
+ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
+{
+}
+
+ARM_FLASH_INFO * ARM_Flash_GetInfo(void)
+{
+}
+
+void ARM_Flash_SignalEvent(uint32_t event)
+{
+}
+
+
+
\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_I2C.c b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_I2C.c
new file mode 100644
index 00000000..6a2a4302
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_I2C.c
@@ -0,0 +1,133 @@
+
+#include "Driver_I2C.h"
+
+#include "RTE_Components.h"
+
+#define ARM_I2C_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 00) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_I2C_API_VERSION,
+    ARM_I2C_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_I2C_CAPABILITIES DriverCapabilities = {
+    0          /* supports 10-bit addressing */
+};
+
+//
+//  Functions
+//
+
+ARM_DRIVER_VERSION ARM_I2C_GetVersion(void)
+{
+}
+
+ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities(void)
+{
+}
+
+int32_t ARM_I2C_Initialize(ARM_I2C_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_I2C_Uninitialize(void)
+{
+}
+
+int32_t ARM_I2C_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_I2C_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+}
+
+int32_t ARM_I2C_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+}
+
+int32_t ARM_I2C_SlaveTransmit(const uint8_t *data, uint32_t num)
+{
+}
+
+int32_t ARM_I2C_SlaveReceive(uint8_t *data, uint32_t num)
+{
+}
+
+int32_t ARM_I2C_GetDataCount(void)
+{
+}
+
+int32_t ARM_I2C_Control(uint32_t control, uint32_t arg)
+{
+    switch (control)
+    {
+    case ARM_I2C_OWN_ADDRESS:
+        break;
+
+    case ARM_I2C_BUS_SPEED:
+        switch (arg)
+        {
+        case ARM_I2C_BUS_SPEED_STANDARD:
+            break;
+        case ARM_I2C_BUS_SPEED_FAST:
+            break;
+        case ARM_I2C_BUS_SPEED_FAST_PLUS:
+            break;
+        default:
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+        break;
+
+    case ARM_I2C_BUS_CLEAR:
+        break;
+
+    case ARM_I2C_ABORT_TRANSFER:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+ARM_I2C_STATUS ARM_I2C_GetStatus(void)
+{
+}
+
+void ARM_I2C_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End I2C Interface
+
+ARM_DRIVER_I2C Driver_I2C = {
+    ARM_I2C_GetVersion,
+    ARM_I2C_GetCapabilities,
+    ARM_I2C_Initialize,
+    ARM_I2C_Uninitialize,
+    ARM_I2C_PowerControl,
+    ARM_I2C_MasterTransmit,
+    ARM_I2C_MasterReceive,
+    ARM_I2C_SlaveTransmit,
+    ARM_I2C_SlaveReceive,
+    ARM_I2C_GetDataCount,
+    ARM_I2C_Control,
+    ARM_I2C_GetStatus
+}; 
\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_MCI.c b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_MCI.c
new file mode 100644
index 00000000..7a2afd7a
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_MCI.c
@@ -0,0 +1,206 @@
+#include "RTE_Components.h"
+#include "Driver_MCI.h"
+
+#define ARM_MCI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 00) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_MCI_API_VERSION,
+    ARM_MCI_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_MCI_CAPABILITIES DriverCapabilities = {
+    0,                 /* cd_state          */
+    0,                 /* cd_event          */
+    0,                 /* vdd               */
+    0,                 /* vdd_1v8           */
+    0,                 /* vccq              */
+    0,                 /* vccq_1v8          */
+    0,                 /* vccq_1v2          */
+    1,                 /* data_width_4      */
+    1,                 /* data_width_8      */
+    0,                 /* data_width_4_ddr  */
+    0,                 /* data_width_8_ddr  */
+    0,                 /* high_speed        */
+    0,                 /* uhs_signaling     */
+    0,                 /* uhs_tuning        */
+    0,                 /* uhs_sdr50         */
+    0,                 /* uhs_sdr104        */
+    0,                 /* uhs_ddr50         */
+    0,                 /* uhs_driver_type_a */
+    0,                 /* uhs_driver_type_c */
+    0,                 /* uhs_driver_type_d */
+    1,                 /* sdio_interrupt    */
+    1,                 /* read_wait         */
+    0,                 /* suspend_resume    */
+    0,                 /* mmc_interrupt     */
+    0,                 /* mmc_boot          */
+    0,                 /* ccs               */
+    0                  /* ccs_timeout       */
+};
+
+//open mci_contorl_gr
+
+// close group mci_control_gr
+
+//
+//   Functions
+//
+ARM_DRIVER_VERSION ARM_MCI_GetVersion(void)
+{
+}
+
+ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities(void)
+{
+}
+
+int32_t ARM_MCI_Initialize(ARM_MCI_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_MCI_Uninitialize(void)
+{
+}
+
+int32_t ARM_MCI_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_MCI_CardPower(uint32_t voltage)
+{
+    switch (voltage & ARM_MCI_POWER_VDD_Msk)
+    {
+    case ARM_MCI_POWER_VDD_OFF:
+        return ARM_DRIVER_OK;
+
+    case ARM_MCI_POWER_VDD_3V3:
+        return ARM_DRIVER_OK;
+
+    default:
+        break;
+    }
+}
+
+int32_t ARM_MCI_ReadCD(void)
+{
+}
+
+int32_t ARM_MCI_ReadWP(void)
+{
+}
+
+int32_t ARM_MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response)
+{
+}
+
+int32_t ARM_MCI_SetupTransfer(uint8_t  *data, uint32_t block_count, uint32_t block_size, uint32_t mode)
+{
+}
+
+int32_t ARM_MCI_AbortTransfer(void)
+{
+}
+
+int32_t ARM_MCI_Control(uint32_t control, uint32_t arg)
+{
+    switch (control)
+    {
+    case ARM_MCI_BUS_SPEED:
+        break;
+
+    case ARM_MCI_BUS_SPEED_MODE:
+        break;
+
+    case ARM_MCI_BUS_CMD_MODE:
+        /* Implement external pull-up control to support MMC cards in open-drain mode */
+        /* Default mode is push-pull and is configured in Driver_MCI0.Initialize()    */
+        if (arg == ARM_MCI_BUS_CMD_PUSH_PULL)
+        {
+            /* Configure external circuit to work in push-pull mode */
+        }
+        else if (arg == ARM_MCI_BUS_CMD_OPEN_DRAIN)
+        {
+            /* Configure external circuit to work in open-drain mode */
+        }
+        else
+        {
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+        break;
+
+    case ARM_MCI_BUS_DATA_WIDTH:
+        switch (arg)
+        {
+        case ARM_MCI_BUS_DATA_WIDTH_1:
+            break;
+        case ARM_MCI_BUS_DATA_WIDTH_4:
+            break;
+        case ARM_MCI_BUS_DATA_WIDTH_8:
+            break;
+        default:
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+        break;
+
+    case ARM_MCI_CONTROL_RESET:
+        break;
+
+    case ARM_MCI_CONTROL_CLOCK_IDLE:
+        break;
+
+    case ARM_MCI_DATA_TIMEOUT:
+        break;
+
+    case ARM_MCI_MONITOR_SDIO_INTERRUPT:
+        break;
+
+    case ARM_MCI_CONTROL_READ_WAIT:
+        break;
+
+    case ARM_MCI_DRIVER_STRENGTH:
+    default: return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+ARM_MCI_STATUS ARM_MCI_GetStatus(void)
+{
+}
+
+void ARM_MCI_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End MCI Interface
+
+ARM_DRIVER_MCI Driver_MCI = {
+    ARM_MCI_GetVersion,
+    ARM_MCI_GetCapabilities,
+    ARM_MCI_Initialize,
+    ARM_MCI_Uninitialize,
+    ARM_MCI_PowerControl,
+    ARM_MCI_CardPower,
+    ARM_MCI_ReadCD,
+    ARM_MCI_ReadWP,
+    ARM_MCI_SendCommand,
+    ARM_MCI_SetupTransfer,
+    ARM_MCI_AbortTransfer,
+    ARM_MCI_Control,
+    ARM_MCI_GetStatus
+};
+
\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_SPI.c b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_SPI.c
new file mode 100644
index 00000000..fa7b40d6
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_SPI.c
@@ -0,0 +1,138 @@
+#include "Driver_SPI.h"
+
+#include "RTE_Components.h"
+
+#define ARM_SPI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 00) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_SPI_API_VERSION,
+    ARM_SPI_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_SPI_CAPABILITIES DriverCapabilities = {
+    1, /* Simplex Mode (Master and Slave) */
+    1, /* TI Synchronous Serial Interface */
+    1, /* Microwire Interface */
+    0  /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
+};
+
+//
+//  Functions
+//
+
+ARM_DRIVER_VERSION ARM_SPI_GetVersion(void)
+{
+}
+
+ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities(void)
+{
+}
+
+int32_t ARM_SPI_Initialize(ARM_SPI_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_SPI_Uninitialize(void)
+{
+}
+
+int32_t ARM_SPI_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_SPI_Send(const void *data, uint32_t num)
+{
+}
+
+int32_t ARM_SPI_Receive(void *data, uint32_t num)
+{
+}
+
+int32_t ARM_SPI_Transfer(const void *data_out, void *data_in, uint32_t num)
+{
+}
+
+uint32_t ARM_SPI_GetDataCount(void)
+{
+}
+
+int32_t ARM_SPI_Control(uint32_t control, uint32_t arg)
+{
+    switch (control & ARM_SPI_CONTROL_Msk)
+    {
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_SPI_MODE_INACTIVE:             // SPI Inactive
+        return ARM_DRIVER_OK;
+
+    case ARM_SPI_MODE_MASTER:               // SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
+        break;
+
+    case ARM_SPI_MODE_SLAVE:                // SPI Slave  (Output on MISO, Input on MOSI)
+        break;
+
+    case ARM_SPI_MODE_MASTER_SIMPLEX:       // SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
+    case ARM_SPI_MODE_SLAVE_SIMPLEX:        // SPI Slave  (Output/Input on MISO)
+        return ARM_SPI_ERROR_MODE;
+
+    case ARM_SPI_SET_BUS_SPEED:             // Set Bus Speed in bps; arg = value
+        break;
+
+    case ARM_SPI_GET_BUS_SPEED:             // Get Bus Speed in bps
+        break;
+
+    case ARM_SPI_SET_DEFAULT_TX_VALUE:      // Set default Transmit value; arg = value
+        break;
+
+    case ARM_SPI_CONTROL_SS:                // Control Slave Select; arg = 0:inactive, 1:active
+        break;
+
+    case ARM_SPI_ABORT_TRANSFER:            // Abort current data transfer
+        break;
+    }
+}
+
+ARM_SPI_STATUS ARM_SPI_GetStatus(void)
+{
+}
+
+void ARM_SPI_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// end group SPI_control
+
+// End SPI Interface
+
+ARM_DRIVER_SPI Driver_SPI1 = {
+    ARM_SPI_GetVersion,
+    ARM_SPI_GetCapabilities,
+    ARM_SPI_Initialize,
+    ARM_SPI_Uninitialize,
+    ARM_SPI_PowerControl,
+    ARM_SPI_Send,
+    ARM_SPI_Receive,
+    ARM_SPI_Transfer,
+    ARM_SPI_GetDataCount,
+    ARM_SPI_Control,
+    ARM_SPI_GetStatus
+};
+
\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_USART.c b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_USART.c
new file mode 100644
index 00000000..661d796b
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_USART.c
@@ -0,0 +1,108 @@
+#include "Driver_USART.h"
+#include "RTE_Components.h"
+
+#define ARM_USART_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 00)
+
+// Driver Version
+static const ARM_DRIVER_VERSION usart_driver_version = { ARM_USART_API_VERSION, ARM_USART_DRV_VERSION };
+
+// end group USART_control
+
+//
+//   Functions
+//
+
+ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+}
+
+ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+}
+
+int32_t ARM_USART_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_USART_Uninitialize(void)
+{
+}
+
+int32_t ARM_USART_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_USART_Send(const void *data, uint32_t num)
+{
+}
+
+int32_t ARM_USART_Receive(void *data, uint32_t num)
+{
+}
+
+int32_t ARM_USART_Transfer(const void *data_out, void *data_in, uint32_t num)
+{
+}
+
+uint32_t ARM_USART_GetTxCount(void)
+{
+}
+
+uint32_t ARM_USART_GetRxCount(void)
+{
+}
+
+int32_t ARM_USART_Control(uint32_t control, uint32_t arg)
+{
+}
+
+ARM_USART_STATUS ARM_USART_GetStatus(void)
+{
+}
+
+int32_t ARM_USART_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+}
+
+ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void)
+{
+}
+
+void ARM_USART_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End USART Interface
+
+ARM_DRIVER_USART Driver_USART = {
+    ARM_USART_GetVersion,
+    ARM_USART_GetCapabilities,
+    ARM_USART_Initialize,
+    ARM_USART_Uninitialize,
+    ARM_USART_PowerControl,
+    ARM_USART_Send,
+    ARM_USART_Receive,
+    ARM_USART_Transfer,
+    ARM_USART_GetTxCount,
+    ARM_USART_GetRxCount,
+    ARM_USART_Control,
+    ARM_USART_GetStatus,
+    ARM_USART_SetModemControl,
+    ARM_USART_GetModemStatus
+};
+
\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_USBD.c b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_USBD.c
new file mode 100644
index 00000000..b1bcc1e7
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_USBD.c
@@ -0,0 +1,144 @@
+#include "Driver_USBD.h"
+
+#include "RTE_Components.h"
+
+/* USBD Driver ****************************************************************/
+
+#define ARM_USBD_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* USBD driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION usbd_driver_version = { ARM_USBD_API_VERSION, ARM_USBD_DRV_VERSION };
+
+/* Driver Capabilities */
+static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = {
+    0, // vbus_detection
+    0, // event_vbus_on
+    0, // event_vbus_off
+};
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_USBD_GetVersion(void)
+{
+}
+
+ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities(void)
+{
+}
+
+int32_t ARM_USBD_Initialize(ARM_USBD_SignalDeviceEvent_t cb_device_event,
+                            ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+{
+}
+
+int32_t ARM_USBD_Uninitialize(void)
+{
+}
+
+int32_t ARM_USBD_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_USBD_DeviceConnect(void)
+{
+}
+
+int32_t ARM_USBD_DeviceDisconnect(void)
+{
+}
+
+ARM_USBD_STATE ARM_USBD_DeviceGetState(void)
+{
+}
+
+int32_t ARM_USBD_DeviceRemoteWakeup(void)
+{
+}
+
+int32_t ARM_USBD_DeviceSetAddress(uint8_t dev_addr)
+{
+}
+
+int32_t ARM_USBD_ReadSetupPacket(uint8_t *setup)
+{
+}
+
+int32_t ARM_USBD_EndpointConfigure(uint8_t ep_addr,
+                                   uint8_t ep_type,
+                                   uint16_t ep_max_packet_size)
+{
+}
+
+int32_t ARM_USBD_EndpointUnconfigure(uint8_t ep_addr)
+{
+}
+
+int32_t ARM_USBD_EndpointStall(uint8_t ep_addr, bool stall)
+{
+}
+
+int32_t ARM_USBD_EndpointTransfer(uint8_t ep_addr, uint8_t *data, uint32_t num)
+{
+}
+
+uint32_t ARM_USBD_EndpointTransferGetResult(uint8_t ep_addr)
+{
+}
+
+int32_t ARM_USBD_EndpointTransferAbort(uint8_t ep_addr)
+{
+}
+
+uint16_t ARM_USBD_GetFrameNumber(void)
+{
+}
+
+void ARM_USBD_SignalDeviceEvent(uint32_t event)
+{
+    // function body
+}
+
+void ARM_USBD_SignalEndpointEvent(uint8_t ep_addr, uint32_t ep_event)
+{
+    // function body
+}
+
+// End USBD Interface
+
+ARM_DRIVER_USBD Driver_USBD0 =
+{
+    ARM_USBD_GetVersion,
+    ARM_USBD_GetCapabilities,
+    ARM_USBD_Initialize,
+    ARM_USBD_Uninitialize,
+    ARM_USBD_PowerControl,
+    ARM_USBD_DeviceConnect,
+    ARM_USBD_DeviceDisconnect,
+    ARM_USBD_DeviceGetState,
+    ARM_USBD_DeviceRemoteWakeup,
+    ARM_USBD_DeviceSetAddress,
+    ARM_USBD_EndpointConfigure,
+    ARM_USBD_EndpointUnconfigure,
+    ARM_USBD_EndpointStall,
+    ARM_USBD_EndpointTransfer,
+    ARM_USBD_EndpointTransferGetResult,
+    ARM_USBD_EndpointTransferAbort,
+    ARM_USBD_GetFrameNumber
+};
+
\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_USBH.c b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_USBH.c
new file mode 100644
index 00000000..7e44d083
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/DriverTemplates/Driver_USBH.c
@@ -0,0 +1,193 @@
+#include <stdint.h>
+#include <string.h>
+
+#include "Driver_USBH.h"
+
+#include "RTE_Components.h"
+
+#define ARM_USBH_EHCI_DRIVER_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 00)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION usbh_ehci_driver_version = { ARM_USBH_API_VERSION, ARM_USBH_EHCI_DRIVER_VERSION };
+
+/* Driver Capabilities */
+static const ARM_USBH_HCI_CAPABILITIES usbh_ehci_driver_capabilities = {
+    0x0001, /* Root HUB available Ports Mask   */
+};
+
+static ARM_USBH_HCI_Interrupt_t        handle_interrupt;
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_USBH_GetVersion(void)
+{
+}
+
+ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities(void)
+{
+}
+
+int32_t ARM_USBH_Initialize(ARM_USBH_SignalPortEvent_t cb_port_event,
+                            ARM_USBH_SignalEndpointEvent_t cb_endpoint_event)
+{
+}
+
+int32_t ARM_USBH_Uninitialize(void)
+{
+}
+
+int32_t ARM_USBH_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_USBH_PortVbusOnOff(uint8_t port, bool vbus)
+{
+}
+
+int32_t ARM_USBH_PortReset(uint8_t port)
+{
+}
+
+int32_t ARM_USBH_PortSuspend(uint8_t port)
+{
+}
+
+int32_t ARM_USBH_PortResume(uint8_t port)
+{
+}
+
+ARM_USBH_PORT_STATE ARM_USBH_PortGetState(uint8_t port)
+{
+}
+
+ARM_USBH_EP_HANDLE ARM_USBH_EndpointCreate(uint8_t dev_addr,
+                                           uint8_t dev_speed,
+                                           uint8_t hub_addr,
+                                           uint8_t hub_port,
+                                           uint8_t ep_addr,
+                                           uint8_t ep_type,
+                                           uint16_t ep_max_packet_size,
+                                           uint8_t ep_interval)
+{
+}
+
+int32_t ARM_USBH_EndpointModify(ARM_USBH_EP_HANDLE ep_hndl,
+                                uint8_t dev_addr,
+                                uint8_t dev_speed,
+                                uint8_t hub_addr,
+                                uint8_t hub_port,
+                                uint16_t ep_max_packet_size)
+{
+}
+
+int32_t ARM_USBH_EndpointDelete(ARM_USBH_EP_HANDLE ep_hndl)
+{
+}
+
+int32_t ARM_USBH_EndpointReset(ARM_USBH_EP_HANDLE ep_hndl)
+{
+}
+
+int32_t ARM_USBH_EndpointTransfer(ARM_USBH_EP_HANDLE ep_hndl,
+                                  uint32_t packet,
+                                  uint8_t *data,
+                                  uint32_t num)
+{
+}
+
+uint32_t ARM_USBH_EndpointTransferGetResult(ARM_USBH_EP_HANDLE ep_hndl)
+{
+}
+
+int32_t ARM_USBH_EndpointTransferAbort(ARM_USBH_EP_HANDLE ep_hndl)
+{
+}
+
+uint16_t ARM_USBH_GetFrameNumber(void)
+{
+}
+
+void ARM_USBH_SignalPortEvent(uint8_t port, uint32_t event)
+{
+    // function body
+}
+
+void ARM_USBH_SignalEndpointEvent(ARM_USBH_EP_HANDLE ep_hndl, uint32_t event)
+{
+    // function body
+}
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion(void)
+{
+}
+
+ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities(void)
+{
+}
+
+int32_t ARM_USBH_HCI_Initialize(ARM_USBH_HCI_Interrupt_t *cb_interrupt)
+{
+}
+
+int32_t ARM_USBH_HCI_Uninitialize(void)
+{
+}
+
+int32_t ARM_USBH_HCI_PowerControl(ARM_POWER_STATE state)
+{
+	    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }	
+}
+
+int32_t ARM_USBH_HCI_PortVbusOnOff(uint8_t port, bool vbus)
+{
+}
+
+void ARM_USBH_HCI_Interrupt(void)
+{
+    // function body
+}
+
+// End USBH Interface
+
+ARM_DRIVER_USBH_HCI Driver_USBH_HCI = {
+    ARM_USBH_HCI_GetVersion,
+    ARM_USBH_HCI_GetCapabilities,
+    ARM_USBH_HCI_Initialize,
+    ARM_USBH_HCI_Uninitialize,
+    ARM_USBH_HCI_PowerControl,
+    ARM_USBH_HCI_PortVbusOnOff
+};
+
\ No newline at end of file
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_Common.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_Common.h
new file mode 100644
index 00000000..b11a115c
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_Common.h
@@ -0,0 +1,72 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        2. Jan 2014
+ * $Revision:    V2.00
+ *
+ * Project:      Common Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.00
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Added General return codes definitions
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_COMMON_H
+#define __DRIVER_COMMON_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+  uint16_t api;                         ///< API version
+  uint16_t drv;                         ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK                 0 ///< Operation succeeded 
+#define ARM_DRIVER_ERROR             -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors 
+
+/**
+\brief General power states
+*/ 
+typedef enum _ARM_POWER_STATE {
+  ARM_POWER_OFF,                        ///< Power off: no operation possible
+  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* __DRIVER_COMMON_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_ETH.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_ETH.h
new file mode 100644
index 00000000..ca087b6f
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_ETH.h
@@ -0,0 +1,85 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        7. Mar 2014
+ * $Revision:    V2.00
+ *
+ * Project:      Ethernet PHY and MAC Driver common definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.00
+ *    Removed ARM_ETH_STATUS enumerator
+ *    Removed ARM_ETH_MODE enumerator
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_ETH_H
+#define __DRIVER_ETH_H
+
+#include "Driver_Common.h"
+
+/**
+\brief Ethernet Media Interface type
+*/
+#define ARM_ETH_INTERFACE_MII           0       ///< Media Independent Interface (MII)
+#define ARM_ETH_INTERFACE_RMII          1       ///< Reduced Media Independent Interface (RMII)
+#define ARM_ETH_INTERFACE_SMII          2       ///< Serial Media Independent Interface (SMII)
+
+/**
+\brief Ethernet link speed
+*/
+#define ARM_ETH_SPEED_10M               0       ///< 10 Mbps link speed
+#define ARM_ETH_SPEED_100M              1       ///< 100 Mbps link speed
+#define ARM_ETH_SPEED_1G                2       ///< 1 Gpbs link speed
+
+/**
+\brief Ethernet duplex mode
+*/
+#define ARM_ETH_DUPLEX_HALF             0       ///< Half duplex link
+#define ARM_ETH_DUPLEX_FULL             1       ///< Full duplex link
+
+/**
+\brief Ethernet link state
+*/
+typedef enum _ARM_ETH_LINK_STATE {
+  ARM_ETH_LINK_DOWN,                    ///< Link is down
+  ARM_ETH_LINK_UP                       ///< Link is up
+} ARM_ETH_LINK_STATE;
+
+/**
+\brief Ethernet link information
+*/
+typedef struct _ARM_ETH_LINK_INFO {
+  uint32_t speed  : 2;                  ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
+  uint32_t duplex : 1;                  ///< Duplex mode: 0= Half, 1= Full
+} ARM_ETH_LINK_INFO;
+
+/**
+\brief Ethernet MAC Address
+*/
+typedef struct _ARM_ETH_MAC_ADDR {
+  uint8_t b[6];                         ///< MAC Address (6 bytes), MSB first
+} ARM_ETH_MAC_ADDR;
+
+#endif /* __DRIVER_ETH_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_ETH_MAC.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_ETH_MAC.h
new file mode 100644
index 00000000..ad8bc2d6
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_ETH_MAC.h
@@ -0,0 +1,301 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        30. May 2014
+ * $Revision:    V2.01
+ *
+ * Project:      Ethernet MAC (Media Access Control) Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.01
+ *    Added ARM_ETH_MAC_SLEEP Control
+ *  Version 2.00
+ *    Changed MAC Address handling:
+ *      moved from ARM_ETH_MAC_Initialize
+ *      to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress
+ *    Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter
+ *    Extended ARM_ETH_MAC_SendFrame function with flags
+ *    Added ARM_ETH_MAC_Control function:
+ *      more control options (Broadcast, Multicast, Checksum offload, VLAN, ...)
+ *      replaces ARM_ETH_MAC_SetMode
+ *      replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx
+ *    Added optional event on transmitted frame
+ *    Added support for PTP (Precision Time Protocol) through new functions:
+ *       ARM_ETH_MAC_ControlTimer
+ *       ARM_ETH_MAC_GetRxFrameTime
+ *       ARM_ETH_MAC_GetTxFrameTime
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Name space prefix ARM_ added
+ *  Version 1.01
+ *    Renamed capabilities items for checksum offload
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_ETH_MAC_H
+#define __DRIVER_ETH_MAC_H
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01)  /* API version */
+
+
+#define _ARM_Driver_ETH_MAC_(n)      Driver_ETH_MAC##n
+#define  ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n)
+
+
+/****** Ethernet MAC Control Codes *****/
+
+#define ARM_ETH_MAC_CONFIGURE           (0x01)      ///< Configure MAC; arg = configuration
+#define ARM_ETH_MAC_CONTROL_TX          (0x02)      ///< Transmitter; arg: 0=disabled, 1=enabled
+#define ARM_ETH_MAC_CONTROL_RX          (0x03)      ///< Receiver; arg: 0=disabled, 1=enabled
+#define ARM_ETH_MAC_FLUSH               (0x04)      ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_...
+#define ARM_ETH_MAC_SLEEP               (0x05)      ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
+#define ARM_ETH_MAC_VLAN_FILTER         (0x06)      ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY
+
+/*----- Ethernet MAC Configuration -----*/
+#define ARM_ETH_MAC_SPEED_Pos            0
+#define ARM_ETH_MAC_SPEED_Msk           (3UL                 << ARM_ETH_MAC_SPEED_Pos)
+#define ARM_ETH_MAC_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_MAC_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_MAC_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_MAC_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_MAC_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_MAC_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_MAC_DUPLEX_Pos           2
+#define ARM_ETH_MAC_DUPLEX_Msk          (1UL                 << ARM_ETH_MAC_DUPLEX_Pos)
+#define ARM_ETH_MAC_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_MAC_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_MAC_LOOPBACK            (1UL << 4)  ///< Loop-back test mode
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5)  ///< Receiver Checksum offload
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6)  ///< Transmitter Checksum offload
+#define ARM_ETH_MAC_ADDRESS_BROADCAST   (1UL << 7)  ///< Accept frames with Broadcast address
+#define ARM_ETH_MAC_ADDRESS_MULTICAST   (1UL << 8)  ///< Accept frames with any Multicast address
+#define ARM_ETH_MAC_ADDRESS_ALL         (1UL << 9)  ///< Accept frames with any address (Promiscuous Mode)
+
+/*----- Ethernet MAC Flush Flags -----*/
+#define ARM_ETH_MAC_FLUSH_RX            (1UL << 0)  ///< Flush Receive buffer
+#define ARM_ETH_MAC_FLUSH_TX            (1UL << 1)  ///< Flush Transmit buffer
+
+/*----- Ethernet MAC VLAN Filter Flag -----*/
+#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit)
+
+
+/****** Ethernet MAC Frame Transmit Flags *****/
+#define ARM_ETH_MAC_TX_FRAME_FRAGMENT   (1UL << 0)  ///< Indicate frame fragment
+#define ARM_ETH_MAC_TX_FRAME_EVENT      (1UL << 1)  ///< Generate event when frame is transmitted
+#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP  (1UL << 2)  ///< Capture frame time stamp
+
+
+/****** Ethernet MAC Timer Control Codes *****/
+#define ARM_ETH_MAC_TIMER_GET_TIME      (0x01)      ///< Get current time
+#define ARM_ETH_MAC_TIMER_SET_TIME      (0x02)      ///< Set new time
+#define ARM_ETH_MAC_TIMER_INC_TIME      (0x03)      ///< Increment current time
+#define ARM_ETH_MAC_TIMER_DEC_TIME      (0x04)      ///< Decrement current time
+#define ARM_ETH_MAC_TIMER_SET_ALARM     (0x05)      ///< Set alarm time
+#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK  (0x06)      ///< Adjust clock frequency; time->ns: correction factor * 2^31
+
+
+/**
+\brief Ethernet MAC Time
+*/
+typedef struct _ARM_ETH_MAC_TIME {
+  uint32_t ns;                          ///< Nano seconds
+  uint32_t sec;                         ///< Seconds
+} ARM_ETH_MAC_TIME;
+
+
+/****** Ethernet MAC Event *****/
+#define ARM_ETH_MAC_EVENT_RX_FRAME      (1UL << 0)  ///< Frame Received
+#define ARM_ETH_MAC_EVENT_TX_FRAME      (1UL << 1)  ///< Frame Transmitted
+#define ARM_ETH_MAC_EVENT_WAKEUP        (1UL << 2)  ///< Wake-up (on Magic Packet)
+#define ARM_ETH_MAC_EVENT_TIMER_ALARM   (1UL << 3)  ///< Timer Alarm
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_ETH_MAC_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)
+  \brief       Initialize Ethernet MAC Device.
+  \param[in]   cb_event  Pointer to \ref ARM_ETH_MAC_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Uninitialize (void)
+  \brief       De-initialize Ethernet MAC Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet MAC Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Get Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Set Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr,
+                                                           uint32_t          num_addr)
+  \brief       Configure Address Filter.
+  \param[in]   ptr_addr  Pointer to addresses
+  \param[in]   num_addr  Number of addresses to configure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)
+  \brief       Send Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer with data to send
+  \param[in]   len    Frame buffer length in bytes
+  \param[in]   flags  Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)
+  \brief       Read data of received Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer for data to read into
+  \param[in]   len    Frame buffer length in bytes
+  \return      number of data bytes read or execution status
+                 - value >= 0: number of data bytes read
+                 - value < 0: error occurred, value is execution status as defined with \ref execution_status 
+*/
+/**
+  \fn          uint32_t ARM_ETH_MAC_GetRxFrameSize (void)
+  \brief       Get size of received Ethernet frame.
+  \return      number of bytes in received frame
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of received Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of transmitted Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)
+  \brief       Control Ethernet Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)
+  \brief       Control Precision Timer.
+  \param[in]   control  Operation
+  \param[in]   time     Pointer to time structure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+  \brief       Read Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[out]  data      Pointer where the result is written to
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+  \brief       Write Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[in]   data      16-bit data to write
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_ETH_MAC_SignalEvent (uint32_t event)
+  \brief       Callback function that signals a Ethernet Event.
+  \param[in]   event  event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event.
+
+
+/**
+\brief Ethernet MAC Capabilities
+*/
+typedef struct _ARM_ETH_MAC_CAPABILITIES {
+  uint32_t checksum_offload_rx_ip4  : 1;        ///< 1 = IPv4 header checksum verified on receive
+  uint32_t checksum_offload_rx_ip6  : 1;        ///< 1 = IPv6 checksum verification supported on receive
+  uint32_t checksum_offload_rx_udp  : 1;        ///< 1 = UDP payload checksum verified on receive
+  uint32_t checksum_offload_rx_tcp  : 1;        ///< 1 = TCP payload checksum verified on receive
+  uint32_t checksum_offload_rx_icmp : 1;        ///< 1 = ICMP payload checksum verified on receive
+  uint32_t checksum_offload_tx_ip4  : 1;        ///< 1 = IPv4 header checksum generated on transmit
+  uint32_t checksum_offload_tx_ip6  : 1;        ///< 1 = IPv6 checksum generation supported on transmit
+  uint32_t checksum_offload_tx_udp  : 1;        ///< 1 = UDP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_tcp  : 1;        ///< 1 = TCP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_icmp : 1;        ///< 1 = ICMP payload checksum generated on transmit
+  uint32_t media_interface          : 2;        ///< Ethernet Media Interface type
+  uint32_t mac_address              : 1;        ///< 1 = driver provides serialized MAC address
+  uint32_t event_rx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated
+  uint32_t event_tx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated
+  uint32_t event_wakeup             : 1;        ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated
+  uint32_t precision_timer          : 1;        ///< 1 = Precision Timer supported
+} ARM_ETH_MAC_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Ethernet MAC Driver
+*/
+typedef struct _ARM_DRIVER_ETH_MAC {
+  ARM_DRIVER_VERSION       (*GetVersion)      (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version.
+  ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities.
+  int32_t                  (*Initialize)      (ARM_ETH_MAC_SignalEvent_t cb_event);                  ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device.
+  int32_t                  (*Uninitialize)    (void);                                                ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device.
+  int32_t                  (*PowerControl)    (ARM_POWER_STATE state);                               ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power.
+  int32_t                  (*GetMacAddress)   (      ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address.
+  int32_t                  (*SetMacAddress)   (const ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address.
+  int32_t                  (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter.
+  int32_t                  (*SendFrame)       (const uint8_t *frame, uint32_t len, uint32_t flags);  ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame.
+  int32_t                  (*ReadFrame)       (      uint8_t *frame, uint32_t len);                  ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame.
+  uint32_t                 (*GetRxFrameSize)  (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame.
+  int32_t                  (*GetRxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame.
+  int32_t                  (*GetTxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame.
+  int32_t                  (*ControlTimer)    (uint32_t control, ARM_ETH_MAC_TIME *time);            ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer.
+  int32_t                  (*Control)         (uint32_t control, uint32_t arg);                      ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface.
+  int32_t                  (*PHY_Read)        (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface.
+  int32_t                  (*PHY_Write)       (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface.
+} const ARM_DRIVER_ETH_MAC;
+
+#endif /* __DRIVER_ETH_MAC_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_ETH_PHY.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_ETH_PHY.h
new file mode 100644
index 00000000..d0216902
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_ETH_PHY.h
@@ -0,0 +1,133 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        7. Mar 2014
+ * $Revision:    V2.00
+ *
+ * Project:      Ethernet PHY (Physical Transceiver) Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.00
+ *    changed parameter "mode" in function ARM_ETH_PHY_SetMode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_ETH_PHY_H
+#define __DRIVER_ETH_PHY_H
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,00)  /* API version */
+
+
+#define _ARM_Driver_ETH_PHY_(n)      Driver_ETH_PHY##n
+#define  ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n)
+
+
+/****** Ethernet PHY Mode *****/
+#define ARM_ETH_PHY_SPEED_Pos            0
+#define ARM_ETH_PHY_SPEED_Msk           (3UL                 << ARM_ETH_PHY_SPEED_Pos)
+#define ARM_ETH_PHY_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_PHY_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_PHY_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_PHY_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_PHY_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_PHY_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_PHY_DUPLEX_Pos           2
+#define ARM_ETH_PHY_DUPLEX_Msk          (1UL                 << ARM_ETH_PHY_DUPLEX_Pos)
+#define ARM_ETH_PHY_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_PHY_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_PHY_AUTO_NEGOTIATE      (1UL << 3)                                      ///< Auto Negotiation mode
+#define ARM_ETH_PHY_LOOPBACK            (1UL << 4)                                      ///< Loop-back test mode
+#define ARM_ETH_PHY_ISOLATE             (1UL << 5)                                      ///< Isolate PHY from MII interface
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t  fn_read,
+                                               ARM_ETH_PHY_Write_t fn_write)
+  \brief       Initialize Ethernet PHY Device.
+  \param[in]   fn_read   Pointer to \ref ARM_ETH_MAC_PHY_Read
+  \param[in]   fn_write  Pointer to \ref ARM_ETH_MAC_PHY_Write
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Uninitialize (void)
+  \brief       De-initialize Ethernet PHY Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet PHY Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetInterface (uint32_t interface)
+  \brief       Set Ethernet Media Interface.
+  \param[in]   interface  Media Interface type
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetMode (uint32_t mode)
+  \brief       Set Ethernet PHY Device Operation mode.
+  \param[in]   mode  Operation Mode
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)
+  \brief       Get Ethernet PHY Device Link state.
+  \return      current link status \ref ARM_ETH_LINK_STATE
+*/
+/**
+  \fn          ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)
+  \brief       Get Ethernet PHY Device Link information.
+  \return      current link parameters \ref ARM_ETH_LINK_INFO
+*/
+
+
+typedef int32_t (*ARM_ETH_PHY_Read_t)  (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register.
+typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register.
+
+
+/**
+\brief Access structure of the Ethernet PHY Driver
+*/
+typedef struct _ARM_DRIVER_ETH_PHY {
+  ARM_DRIVER_VERSION (*GetVersion)   (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version.
+  int32_t            (*Initialize)   (ARM_ETH_PHY_Read_t  fn_read,
+                                      ARM_ETH_PHY_Write_t fn_write);  ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device.
+  int32_t            (*Uninitialize) (void);                          ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device.
+  int32_t            (*PowerControl) (ARM_POWER_STATE state);         ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power.
+  int32_t            (*SetInterface) (uint32_t interface);            ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface.
+  int32_t            (*SetMode)      (uint32_t mode);                 ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode.
+  ARM_ETH_LINK_STATE (*GetLinkState) (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state.
+  ARM_ETH_LINK_INFO  (*GetLinkInfo)  (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information.
+} const ARM_DRIVER_ETH_PHY;
+
+#endif /* __DRIVER_ETH_PHY_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_Flash.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_Flash.h
new file mode 100644
index 00000000..0223299b
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_Flash.h
@@ -0,0 +1,194 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        31. Mar 2014
+ * $Revision:    V2.00
+ *
+ * Project:      Flash Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.00
+ *    Renamed driver NOR -> Flash (more generic)
+ *    Non-blocking operation
+ *    Added Events, Status and Capabilities
+ *    Linked Flash information (GetInfo)
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_FLASH_H
+#define __DRIVER_FLASH_H
+
+#include "Driver_Common.h"
+
+#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,00)  /* API version */
+
+
+#define _ARM_Driver_Flash_(n)      Driver_Flash##n
+#define  ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n)
+
+
+#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 }
+
+/**
+\brief Flash Sector information
+*/
+typedef struct _ARM_FLASH_SECTOR {
+  uint32_t start;                       ///< Sector Start address
+  uint32_t end;                         ///< Sector End address (start+size-1)
+} const ARM_FLASH_SECTOR;
+
+/**
+\brief Flash information
+*/
+typedef struct _ARM_FLASH_INFO {
+  ARM_FLASH_SECTOR *sector_info;        ///< Sector layout information (NULL=Uniform sectors)
+  uint32_t          sector_count;       ///< Number of sectors
+  uint32_t          sector_size;        ///< Uniform sector size in bytes (0=sector_info used) 
+  uint32_t          page_size;          ///< Optimal programming page size in bytes
+  uint32_t          program_unit;       ///< Smallest programmable unit in bytes
+  uint8_t           erased_value;       ///< Contents of erased memory (usually 0xFF)
+} const ARM_FLASH_INFO;
+
+
+/**
+\brief Flash Status
+*/
+typedef struct _ARM_FLASH_STATUS {
+  uint32_t busy  : 1;                   ///< Flash busy flag
+  uint32_t error : 1;                   ///< Read/Program/Erase error flag (cleared on start of next operation)
+} ARM_FLASH_STATUS;
+
+
+/****** Flash Event *****/
+#define ARM_FLASH_EVENT_READY           (1UL << 0)  ///< Flash Ready
+#define ARM_FLASH_EVENT_ERROR           (1UL << 1)  ///< Read/Program/Erase Error
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_FLASH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)
+  \brief       Initialize the Flash Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_Flash_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_Uninitialize (void)
+  \brief       De-initialize the Flash Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)
+  \brief       Control the Flash interface power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)
+  \brief       Read data from Flash.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Flash.
+  \param[in]   cnt   Number of data items to read.
+  \return      number of data items read or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)
+  \brief       Program data to Flash.
+  \param[in]   addr  Data address.
+  \param[in]   data  Pointer to a buffer containing the data to be programmed to Flash.
+  \param[in]   cnt   Number of data items to program.
+  \return      number of data items programmed or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseSector (uint32_t addr)
+  \brief       Erase Flash Sector.
+  \param[in]   addr  Sector address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseChip (void)
+  \brief       Erase complete Flash.
+               Optional function for faster full chip erase.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_FLASH_STATUS ARM_Flash_GetStatus (void)
+  \brief       Get Flash status.
+  \return      Flash status \ref ARM_FLASH_STATUS
+*/
+/**
+  \fn          ARM_FLASH_INFO * ARM_Flash_GetInfo (void)
+  \brief       Get Flash information.
+  \return      Pointer to Flash information \ref ARM_FLASH_INFO
+*/
+
+/**
+  \fn          void ARM_Flash_SignalEvent (uint32_t event)
+  \brief       Signal Flash event.
+  \param[in]   event  Event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event);    ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event.
+
+
+/**
+\brief Flash Driver Capabilities.
+*/
+typedef struct _ARM_FLASH_CAPABILITIES {
+  uint32_t event_ready  : 1;            ///< Signal Flash Ready event
+  uint32_t data_width   : 2;            ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
+  uint32_t erase_chip   : 1;            ///< Supports EraseChip operation
+} ARM_FLASH_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Flash Driver
+*/
+typedef struct _ARM_DRIVER_FLASH {
+  ARM_DRIVER_VERSION     (*GetVersion)     (void);                                          ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version.
+  ARM_FLASH_CAPABILITIES (*GetCapabilities)(void);                                          ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)     (ARM_Flash_SignalEvent_t cb_event);              ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface.
+  int32_t                (*Uninitialize)   (void);                                          ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface.
+  int32_t                (*PowerControl)   (ARM_POWER_STATE state);                         ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power.
+  int32_t                (*ReadData)       (uint32_t addr,       void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash.
+  int32_t                (*ProgramData)    (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash.
+  int32_t                (*EraseSector)    (uint32_t addr);                                 ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector.
+  int32_t                (*EraseChip)      (void);                                          ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash.
+  ARM_FLASH_STATUS       (*GetStatus)      (void);                                          ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status.
+  ARM_FLASH_INFO *       (*GetInfo)        (void);                                          ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information.
+} const ARM_DRIVER_FLASH;
+
+#endif /* __DRIVER_FLASH_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_I2C.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_I2C.h
new file mode 100644
index 00000000..da05f982
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_I2C.h
@@ -0,0 +1,207 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        9. May 2014
+ * $Revision:    V2.02
+ *
+ * Project:      I2C (Inter-Integrated Circuit) Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.02
+ *    Removed function ARM_I2C_MasterTransfer in order to simplify drivers
+ *      and added back parameter "xfer_pending" to functions
+ *      ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *  Version 2.01
+ *    Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending"
+ *      from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *    Added function ARM_I2C_GetDataCount
+ *    Removed flag "address_nack" from ARM_I2C_STATUS
+ *    Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE
+ *      with event ARM_I2C_EVENT_TRANSFER_DONE
+ *    Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE
+ *    Removed parameter "arg" from function ARM_I2C_SignalEvent
+ *  Version 2.00
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_I2C_H
+#define __DRIVER_I2C_H
+
+#include "Driver_Common.h"
+
+#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02)  /* API version */
+
+
+/****** I2C Control Codes *****/
+
+#define ARM_I2C_OWN_ADDRESS             (0x01)      ///< Set Own Slave Address; arg = address 
+#define ARM_I2C_BUS_SPEED               (0x02)      ///< Set Bus Speed; arg = speed
+#define ARM_I2C_BUS_CLEAR               (0x03)      ///< Execute Bus clear: send nine clock pulses
+#define ARM_I2C_ABORT_TRANSFER          (0x04)      ///< Abort Master/Slave Transmit/Receive
+
+/*----- I2C Bus Speed -----*/
+#define ARM_I2C_BUS_SPEED_STANDARD      (0x01)      ///< Standard Speed (100kHz)
+#define ARM_I2C_BUS_SPEED_FAST          (0x02)      ///< Fast Speed     (400kHz)
+#define ARM_I2C_BUS_SPEED_FAST_PLUS     (0x03)      ///< Fast+ Speed    (  1MHz)
+#define ARM_I2C_BUS_SPEED_HIGH          (0x04)      ///< High Speed     (3.4MHz)
+
+
+/****** I2C Address Flags *****/
+
+#define ARM_I2C_ADDRESS_10BIT           0x0400      ///< 10-bit address flag
+#define ARM_I2C_ADDRESS_GC              0x8000      ///< General Call flag
+
+
+/**
+\brief I2C Status
+*/
+typedef struct _ARM_I2C_STATUS {
+  uint32_t busy             : 1;        ///< Busy flag
+  uint32_t mode             : 1;        ///< Mode: 0=Slave, 1=Master
+  uint32_t direction        : 1;        ///< Direction: 0=Transmitter, 1=Receiver
+  uint32_t general_call     : 1;        ///< General Call indication (cleared on start of next Slave operation)
+  uint32_t arbitration_lost : 1;        ///< Master lost arbitration (cleared on start of next Master operation)
+  uint32_t bus_error        : 1;        ///< Bus error detected (cleared on start of next Master/Slave operation)
+} ARM_I2C_STATUS;
+
+
+/****** I2C Event *****/
+#define ARM_I2C_EVENT_TRANSFER_DONE       (1UL << 0)  ///< Master/Slave Transmit/Receive finished
+#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1)  ///< Master/Slave Transmit/Receive incomplete transfer
+#define ARM_I2C_EVENT_SLAVE_TRANSMIT      (1UL << 2)  ///< Slave Transmit operation requested
+#define ARM_I2C_EVENT_SLAVE_RECEIVE       (1UL << 3)  ///< Slave Receive operation requested
+#define ARM_I2C_EVENT_ADDRESS_NACK        (1UL << 4)  ///< Address not acknowledged from Slave
+#define ARM_I2C_EVENT_GENERAL_CALL        (1UL << 5)  ///< General Call indication
+#define ARM_I2C_EVENT_ARBITRATION_LOST    (1UL << 6)  ///< Master lost arbitration
+#define ARM_I2C_EVENT_BUS_ERROR           (1UL << 7)  ///< Bus error detected (START/STOP at illegal position)
+#define ARM_I2C_EVENT_BUS_CLEAR           (1UL << 8)  ///< Bus clear finished
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_I2C_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_I2C_CAPABILITIES
+
+  \fn          int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
+  \brief       Initialize I2C Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_I2C_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_Uninitialize (void)
+  \brief       De-initialize I2C Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)
+  \brief       Control I2C Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start transmitting data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[in]   data          Pointer to buffer with data to transmit to I2C Slave
+  \param[in]   num           Number of data bytes to transmit
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start receiving data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[out]  data          Pointer to buffer for data to receive from I2C Slave
+  \param[in]   num           Number of data bytes to receive
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)
+  \brief       Start transmitting data as I2C Slave.
+  \param[in]   data  Pointer to buffer with data to transmit to I2C Master
+  \param[in]   num   Number of data bytes to transmit
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)
+  \brief       Start receiving data as I2C Slave.
+  \param[out]  data  Pointer to buffer for data to receive from I2C Master
+  \param[in]   num   Number of data bytes to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data bytes transferred; -1 when Slave is not addressed by Master
+
+  \fn          int32_t ARM_I2C_Control (uint32_t control, uint32_t arg)
+  \brief       Control I2C Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+
+  \fn          ARM_I2C_STATUS ARM_I2C_GetStatus (void)
+  \brief       Get I2C status.
+  \return      I2C status \ref ARM_I2C_STATUS
+
+  \fn          void ARM_I2C_SignalEvent (uint32_t event)
+  \brief       Signal I2C Events.
+  \param[in]   event  \ref I2C_events notification mask
+*/
+
+typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event.
+
+
+/**
+\brief I2C Driver Capabilities.
+*/
+typedef struct _ARM_I2C_CAPABILITIES {
+  uint32_t address_10_bit : 1;          ///< supports 10-bit addressing
+} ARM_I2C_CAPABILITIES;
+
+
+/**
+\brief Access structure of the I2C Driver.
+*/
+typedef struct _ARM_DRIVER_I2C {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                                                                ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version.
+  ARM_I2C_CAPABILITIES (*GetCapabilities)(void);                                                                ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_I2C_SignalEvent_t cb_event);                                      ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface.
+  int32_t              (*Uninitialize)   (void);                                                                ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);                                               ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power.
+  int32_t              (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master.
+  int32_t              (*MasterReceive)  (uint32_t addr,       uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master.
+  int32_t              (*SlaveTransmit)  (               const uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave.
+  int32_t              (*SlaveReceive)   (                     uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave.
+  int32_t              (*GetDataCount)   (void);                                                                ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg);                                      ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface.
+  ARM_I2C_STATUS       (*GetStatus)      (void);                                                                ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status.
+} const ARM_DRIVER_I2C;
+
+#endif /* __DRIVER_I2C_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_MCI.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_MCI.h
new file mode 100644
index 00000000..93375d07
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_MCI.h
@@ -0,0 +1,350 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        16. May 2014
+ * $Revision:    V2.02
+ *
+ * Project:      MCI (Memory Card Interface) Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.02
+ *    Added timeout and error flags to ARM_MCI_STATUS
+ *    Added support for controlling optional RST_n pin (eMMC)
+ *    Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK)
+ *    Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT
+ *  Version 2.01
+ *    Decoupled SPI mode from MCI driver
+ *    Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP
+ *  Version 2.00
+ *    Added support for:
+ *      SD UHS-I (Ultra High Speed)
+ *      SD I/O Interrupt
+ *      Read Wait (SD I/O)
+ *      Suspend/Resume (SD I/O)
+ *      MMC Interrupt
+ *      MMC Boot
+ *      Stream Data transfer (MMC)
+ *      VCCQ Power Supply Control (eMMC)
+ *      Command Completion Signal (CCS) for CE-ATA
+ *    Added ARM_MCI_Control function
+ *    Added ARM_MCI_GetStatus function
+ *    Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions
+ *      (replaced by ARM_MCI_Control)
+ *    Changed ARM_MCI_CardPower function (voltage parameter)
+ *    Changed ARM_MCI_SendCommnad function (flags parameter)
+ *    Changed ARM_MCI_SetupTransfer function (mode parameter)
+ *    Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_MCI_H
+#define __DRIVER_MCI_H
+
+#include "Driver_Common.h"
+
+#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02)  /* API version */
+
+
+/****** MCI Send Command Flags *****/
+#define ARM_MCI_RESPONSE_Pos             0
+#define ARM_MCI_RESPONSE_Msk            (3UL << ARM_MCI_RESPONSE_Pos)
+#define ARM_MCI_RESPONSE_NONE           (0UL << ARM_MCI_RESPONSE_Pos)   ///< No response expected (default)
+#define ARM_MCI_RESPONSE_SHORT          (1UL << ARM_MCI_RESPONSE_Pos)   ///< Short response (48-bit)
+#define ARM_MCI_RESPONSE_SHORT_BUSY     (2UL << ARM_MCI_RESPONSE_Pos)   ///< Short response with busy signal (48-bit)
+#define ARM_MCI_RESPONSE_LONG           (3UL << ARM_MCI_RESPONSE_Pos)   ///< Long response (136-bit)
+
+#define ARM_MCI_RESPONSE_INDEX          (1UL << 2)  ///< Check command index in response
+#define ARM_MCI_RESPONSE_CRC            (1UL << 3)  ///< Check CRC in response
+
+#define ARM_MCI_WAIT_BUSY               (1UL << 4)  ///< Wait until busy before sending the command
+
+#define ARM_MCI_TRANSFER_DATA           (1UL << 5)  ///< Activate Data transfer
+
+#define ARM_MCI_CARD_INITIALIZE         (1UL << 6)  ///< Execute Memory Card initialization sequence
+
+#define ARM_MCI_INTERRUPT_COMMAND       (1UL << 7)  ///< Send Interrupt command (CMD40 - MMC only)
+#define ARM_MCI_INTERRUPT_RESPONSE      (1UL << 8)  ///< Send Interrupt response (CMD40 - MMC only)
+
+#define ARM_MCI_BOOT_OPERATION          (1UL << 9)  ///< Execute Boot operation (MMC only)
+#define ARM_MCI_BOOT_ALTERNATIVE        (1UL << 10) ///< Execute Alternative Boot operation (MMC only)
+#define ARM_MCI_BOOT_ACK                (1UL << 11) ///< Expect Boot Acknowledge (MMC only)
+
+#define ARM_MCI_CCSD                    (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device
+#define ARM_MCI_CCS                     (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device
+
+
+/****** MCI Setup Transfer Mode *****/
+#define ARM_MCI_TRANSFER_READ           (0UL << 0)  ///< Data Read Transfer (from MCI)
+#define ARM_MCI_TRANSFER_WRITE          (1UL << 0)  ///< Data Write Transfer (to MCI)
+#define ARM_MCI_TRANSFER_BLOCK          (0UL << 1)  ///< Block Data transfer (default)
+#define ARM_MCI_TRANSFER_STREAM         (1UL << 1)  ///< Stream Data transfer (MMC only)
+
+
+/****** MCI Control Codes *****/
+#define ARM_MCI_BUS_SPEED               (0x01)      ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s
+#define ARM_MCI_BUS_SPEED_MODE          (0x02)      ///< Set Bus Speed Mode as specified with arg
+#define ARM_MCI_BUS_CMD_MODE            (0x03)      ///< Set CMD Line Mode as specified with arg
+#define ARM_MCI_BUS_DATA_WIDTH          (0x04)      ///< Set Bus Data Width as specified with arg
+#define ARM_MCI_DRIVER_STRENGTH         (0x05)      ///< Set SD UHS-I Driver Strength as specified with arg 
+#define ARM_MCI_CONTROL_RESET           (0x06)      ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active 
+#define ARM_MCI_CONTROL_CLOCK_IDLE      (0x07)      ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled
+#define ARM_MCI_UHS_TUNING_OPERATION    (0x08)      ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute
+#define ARM_MCI_UHS_TUNING_RESULT       (0x09)      ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error
+#define ARM_MCI_DATA_TIMEOUT            (0x0A)      ///< Set Data timeout; arg = timeout in bus cycles
+#define ARM_MCI_CSS_TIMEOUT             (0x0B)      ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles
+#define ARM_MCI_MONITOR_SDIO_INTERRUPT  (0x0C)      ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled
+#define ARM_MCI_CONTROL_READ_WAIT       (0x0D)      ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled
+#define ARM_MCI_SUSPEND_TRANSFER        (0x0E)      ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer
+#define ARM_MCI_RESUME_TRANSFER         (0x0F)      ///< Resume Data transfer (SD I/O)
+
+/*----- MCI Bus Speed Mode -----*/
+#define ARM_MCI_BUS_DEFAULT_SPEED       (0x00)      ///< SD/MMC: Default Speed mode up to 25/26MHz
+#define ARM_MCI_BUS_HIGH_SPEED          (0x01)      ///< SD/MMC: High    Speed mode up to 50/52MHz
+#define ARM_MCI_BUS_UHS_SDR12           (0x02)      ///< SD: SDR12  (Single Data Rate) up to  25MHz,  12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR25           (0x03)      ///< SD: SDR25  (Single Data Rate) up to  50MHz,  25  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR50           (0x04)      ///< SD: SDR50  (Single Data Rate) up to 100MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR104          (0x05)      ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_DDR50           (0x06)      ///< SD: DDR50  (Dual Data Rate)   up to  50MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+
+/*----- MCI CMD Line Mode -----*/
+#define ARM_MCI_BUS_CMD_PUSH_PULL       (0x00)      ///< Push-Pull CMD line (default)
+#define ARM_MCI_BUS_CMD_OPEN_DRAIN      (0x01)      ///< Open Drain CMD line (MMC only)
+
+/*----- MCI Bus Data Width -----*/
+#define ARM_MCI_BUS_DATA_WIDTH_1        (0x00)      ///< Bus data width: 1 bit (default)
+#define ARM_MCI_BUS_DATA_WIDTH_4        (0x01)      ///< Bus data width: 4 bits
+#define ARM_MCI_BUS_DATA_WIDTH_8        (0x02)      ///< Bus data width: 8 bits
+#define ARM_MCI_BUS_DATA_WIDTH_4_DDR    (0x03)      ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only
+#define ARM_MCI_BUS_DATA_WIDTH_8_DDR    (0x04)      ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only
+
+/*----- MCI Driver Strength -----*/
+#define ARM_MCI_DRIVER_TYPE_A           (0x01)      ///< SD UHS-I Driver Type A
+#define ARM_MCI_DRIVER_TYPE_B           (0x00)      ///< SD UHS-I Driver Type B (default)
+#define ARM_MCI_DRIVER_TYPE_C           (0x02)      ///< SD UHS-I Driver Type C
+#define ARM_MCI_DRIVER_TYPE_D           (0x03)      ///< SD UHS-I Driver Type D
+
+
+/****** MCI Card Power *****/
+#define ARM_MCI_POWER_VDD_Pos            0
+#define ARM_MCI_POWER_VDD_Msk           (0x0FUL << ARM_MCI_POWER_VDD_Pos)
+#define ARM_MCI_POWER_VDD_OFF           (0x01UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) turned off
+#define ARM_MCI_POWER_VDD_3V3           (0x02UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 3.3V
+#define ARM_MCI_POWER_VDD_1V8           (0x03UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 1.8V
+#define ARM_MCI_POWER_VCCQ_Pos           4
+#define ARM_MCI_POWER_VCCQ_Msk          (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)
+#define ARM_MCI_POWER_VCCQ_OFF          (0x01UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ turned off
+#define ARM_MCI_POWER_VCCQ_3V3          (0x02UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 3.3V
+#define ARM_MCI_POWER_VCCQ_1V8          (0x03UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.8V
+#define ARM_MCI_POWER_VCCQ_1V2          (0x04UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.2V
+
+
+/**
+\brief MCI Status
+*/
+typedef struct _ARM_MCI_STATUS {
+  uint32_t command_active   : 1;        ///< Command active flag
+  uint32_t command_timeout  : 1;        ///< Command timeout flag (cleared on start of next command)
+  uint32_t command_error    : 1;        ///< Command error flag (cleared on start of next command)
+  uint32_t transfer_active  : 1;        ///< Transfer active flag
+  uint32_t transfer_timeout : 1;        ///< Transfer timeout flag (cleared on start of next command)
+  uint32_t transfer_error   : 1;        ///< Transfer error flag (cleared on start of next command)
+  uint32_t sdio_interrupt   : 1;        ///< SD I/O Interrupt flag (cleared on start of monitoring)
+  uint32_t ccs              : 1;        ///< CCS flag (cleared on start of next command)
+} ARM_MCI_STATUS;
+
+
+/****** MCI Card Event *****/
+#define ARM_MCI_EVENT_CARD_INSERTED     (1UL << 0)  ///< Memory Card inserted
+#define ARM_MCI_EVENT_CARD_REMOVED      (1UL << 1)  ///< Memory Card removed
+#define ARM_MCI_EVENT_COMMAND_COMPLETE  (1UL << 2)  ///< Command completed
+#define ARM_MCI_EVENT_COMMAND_TIMEOUT   (1UL << 3)  ///< Command timeout
+#define ARM_MCI_EVENT_COMMAND_ERROR     (1UL << 4)  ///< Command response error (CRC error or invalid response)
+#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5)  ///< Data transfer completed
+#define ARM_MCI_EVENT_TRANSFER_TIMEOUT  (1UL << 6)  ///< Data transfer timeout
+#define ARM_MCI_EVENT_TRANSFER_ERROR    (1UL << 7)  ///< Data transfer CRC failed
+#define ARM_MCI_EVENT_SDIO_INTERRUPT    (1UL << 8)  ///< SD I/O Interrupt
+#define ARM_MCI_EVENT_CCS               (1UL << 9)  ///< Command Completion Signal (CCS)
+#define ARM_MCI_EVENT_CCS_TIMEOUT       (1UL << 10) ///< Command Completion Signal (CCS) Timeout
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_MCI_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_MCI_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)
+  \brief         Initialize the Memory Card Interface
+  \param[in]     cb_event  Pointer to \ref ARM_MCI_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Uninitialize (void)
+  \brief         De-initialize Memory Card Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)
+  \brief         Control Memory Card Interface Power.
+  \param[in]     state   Power state \ref ARM_POWER_STATE
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_CardPower (uint32_t voltage)
+  \brief         Set Memory Card Power supply voltage.
+  \param[in]     voltage  Memory Card Power supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadCD (void)
+  \brief         Read Card Detect (CD) state.
+  \return        1:card detected, 0:card not detected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadWP (void)
+  \brief         Read Write Protect (WP) state.
+  \return        1:write protected, 0:not write protected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_SendCommand (uint32_t  cmd,
+                                              uint32_t  arg,
+                                              uint32_t  flags,
+                                              uint32_t *response)
+  \brief         Send Command to card and get the response.
+  \param[in]     cmd       Memory Card command
+  \param[in]     arg       Command argument
+  \param[in]     flags     Command flags
+  \param[out]    response  Pointer to buffer for response
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_SetupTransfer (uint8_t *data,
+                                                uint32_t block_count,
+                                                uint32_t block_size,
+                                                uint32_t mode)
+  \brief         Setup read or write transfer operation.
+  \param[in,out] data         Pointer to data block(s) to be written or read
+  \param[in]     block_count  Number of blocks
+  \param[in]     block_size   Size of a block in bytes
+  \param[in]     mode         Transfer mode
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_AbortTransfer (void)
+  \brief         Abort current read/write data transfer.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Control (uint32_t control, uint32_t arg)
+  \brief         Control MCI Interface.
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation (optional)
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_MCI_STATUS ARM_MCI_GetStatus (void)
+  \brief         Get MCI status.
+  \return        MCI status \ref ARM_MCI_STATUS
+*/
+
+/**
+  \fn            void ARM_MCI_SignalEvent (uint32_t event)
+  \brief         Callback function that signals a MCI Card Event.
+  \param[in]     event \ref mci_event_gr
+  \return        none
+*/
+
+typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event.
+
+
+/**
+\brief  MCI Driver Capabilities.
+*/
+typedef struct _ARM_MCI_CAPABILITIES {
+  uint32_t cd_state          : 1;       ///< Card Detect State available
+  uint32_t cd_event          : 1;       ///< Signal Card Detect change event
+  uint32_t wp_state          : 1;       ///< Write Protect State available
+  uint32_t vdd               : 1;       ///< Supports VDD Card Power Supply Control
+  uint32_t vdd_1v8           : 1;       ///< Supports 1.8 VDD Card Power Supply
+  uint32_t vccq              : 1;       ///< Supports VCCQ Card Power Supply Control (eMMC)
+  uint32_t vccq_1v8          : 1;       ///< Supports 1.8 VCCQ Card Power Supply (eMMC)
+  uint32_t vccq_1v2          : 1;       ///< Supports 1.2 VCCQ Card Power Supply (eMMC)
+  uint32_t data_width_4      : 1;       ///< Supports 4-bit data
+  uint32_t data_width_8      : 1;       ///< Supports 8-bit data
+  uint32_t data_width_4_ddr  : 1;       ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t data_width_8_ddr  : 1;       ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t high_speed        : 1;       ///< Supports SD/MMC High Speed Mode
+  uint32_t uhs_signaling     : 1;       ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling 
+  uint32_t uhs_tuning        : 1;       ///< Supports SD UHS-I tuning 
+  uint32_t uhs_sdr50         : 1;       ///< Supports SD UHS-I SDR50  (Single Data Rate) up to  50MB/s
+  uint32_t uhs_sdr104        : 1;       ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s
+  uint32_t uhs_ddr50         : 1;       ///< Supports SD UHS-I DDR50  (Dual   Data Rate) up to  50MB/s
+  uint32_t uhs_driver_type_a : 1;       ///< Supports SD UHS-I Driver Type A
+  uint32_t uhs_driver_type_c : 1;       ///< Supports SD UHS-I Driver Type C
+  uint32_t uhs_driver_type_d : 1;       ///< Supports SD UHS-I Driver Type D 
+  uint32_t sdio_interrupt    : 1;       ///< Supports SD I/O Interrupt 
+  uint32_t read_wait         : 1;       ///< Supports Read Wait (SD I/O)
+  uint32_t suspend_resume    : 1;       ///< Supports Suspend/Resume (SD I/O)
+  uint32_t mmc_interrupt     : 1;       ///< Supports MMC Interrupt 
+  uint32_t mmc_boot          : 1;       ///< Supports MMC Boot 
+  uint32_t rst_n             : 1;       ///< Supports RST_n Pin Control (eMMC)
+  uint32_t ccs               : 1;       ///< Supports Command Completion Signal (CCS) for CE-ATA
+  uint32_t ccs_timeout       : 1;       ///< Supports Command Completion Signal (CCS) timeout for CE-ATA
+} ARM_MCI_CAPABILITIES;
+
+
+/**
+\brief  Access structure of the MCI Driver.
+*/
+typedef struct _ARM_DRIVER_MCI {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                           ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version.
+  ARM_MCI_CAPABILITIES (*GetCapabilities)(void);                           ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface.
+  int32_t              (*Uninitialize)   (void);                           ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);          ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power.
+  int32_t              (*CardPower)      (uint32_t voltage);               ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage.
+  int32_t              (*ReadCD)         (void);                           ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state.
+  int32_t              (*ReadWP)         (void);                           ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state.
+  int32_t              (*SendCommand)    (uint32_t cmd, 
+                                          uint32_t arg, 
+                                          uint32_t flags,
+                                          uint32_t *response);             ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response.
+  int32_t              (*SetupTransfer)  (uint8_t *data,
+                                          uint32_t block_count,
+                                          uint32_t block_size,
+                                          uint32_t mode);                  ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation.
+  int32_t              (*AbortTransfer)  (void);                           ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface.
+  ARM_MCI_STATUS       (*GetStatus)      (void);                           ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status.
+} const ARM_DRIVER_MCI;
+
+#endif /* __DRIVER_MCI_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_NAND.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_NAND.h
new file mode 100644
index 00000000..dc6ba864
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_NAND.h
@@ -0,0 +1,403 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        30. May 2014
+ * $Revision:    V2.01
+ *
+ * Project:      NAND Flash Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.01
+ *    Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions
+ *  Version 2.00
+ *    New simplified driver:
+ *      complexity moved to upper layer (command agnostic)
+ *    Added support for:
+ *      NV-DDR & NV-DDR2 Interface (ONFI specification)
+ *      VCC, VCCQ and VPP Power Supply Control
+ *      WP (Write Protect) Control
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_NAND_H
+#define __DRIVER_NAND_H
+
+#include "Driver_Common.h"
+
+#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01)  /* API version */
+
+
+/****** NAND Device Power *****/
+#define ARM_NAND_POWER_VCC_Pos           0
+#define ARM_NAND_POWER_VCC_Msk          (0x07UL << ARM_NAND_POWER_VCC_Pos)
+#define ARM_NAND_POWER_VCC_OFF          (0x01UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC Power off
+#define ARM_NAND_POWER_VCC_3V3          (0x02UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 3.3V
+#define ARM_NAND_POWER_VCC_1V8          (0x03UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 1.8V
+#define ARM_NAND_POWER_VCCQ_Pos          3
+#define ARM_NAND_POWER_VCCQ_Msk         (0x07UL << ARM_NAND_POWER_VCCQ_Pos)
+#define ARM_NAND_POWER_VCCQ_OFF         (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off
+#define ARM_NAND_POWER_VCCQ_3V3         (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V
+#define ARM_NAND_POWER_VCCQ_1V8         (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V
+#define ARM_NAND_POWER_VPP_OFF          (1UL << 6)                          ///< VPP off
+#define ARM_NAND_POWER_VPP_ON           (1Ul << 7)                          ///< VPP on
+
+
+/****** NAND Control Codes *****/
+#define ARM_NAND_BUS_MODE               (0x01)      ///< Set Bus Mode as specified with arg
+#define ARM_NAND_BUS_DATA_WIDTH         (0x02)      ///< Set Bus Data Width as specified with arg
+#define ARM_NAND_DRIVER_STRENGTH        (0x03)      ///< Set Driver Strength as specified with arg
+#define ARM_NAND_DEVICE_READY_EVENT     (0x04)      ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled 
+#define ARM_NAND_DRIVER_READY_EVENT     (0x05)      ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled 
+
+/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_BUS_INTERFACE_Pos       4
+#define ARM_NAND_BUS_INTERFACE_Msk      (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)
+#define ARM_NAND_BUS_SDR                (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface:    SDR  (Single Data Rate) - Traditional interface (default)
+#define ARM_NAND_BUS_DDR                (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR  (Double Data Rate)
+#define ARM_NAND_BUS_DDR2               (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR2 (Double Data Rate)
+#define ARM_NAND_BUS_TIMING_MODE_Pos     0
+#define ARM_NAND_BUS_TIMING_MODE_Msk    (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)
+#define ARM_NAND_BUS_TIMING_MODE_0      (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 0 (default)
+#define ARM_NAND_BUS_TIMING_MODE_1      (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 1
+#define ARM_NAND_BUS_TIMING_MODE_2      (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 2
+#define ARM_NAND_BUS_TIMING_MODE_3      (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 3
+#define ARM_NAND_BUS_TIMING_MODE_4      (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 4 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_5      (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 5 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_6      (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 6 (NV-DDR2 only)
+#define ARM_NAND_BUS_TIMING_MODE_7      (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 7 (NV-DDR2 only)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos    8
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warmup cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warmup cycles: 1
+#define ARM_NAND_BUS_DDR2_DO_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warmup cycles: 2
+#define ARM_NAND_BUS_DDR2_DO_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warmup cycles: 4
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos    12
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warmup cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warmup cycles: 1
+#define ARM_NAND_BUS_DDR2_DI_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warmup cycles: 2
+#define ARM_NAND_BUS_DDR2_DI_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warmup cycles: 4
+#define ARM_NAND_BUS_DDR2_VEN           (1UL << 16)                               ///< DDR2 Enable external VREFQ as reference
+#define ARM_NAND_BUS_DDR2_CMPD          (1UL << 17)                               ///< DDR2 Enable complementary DQS (DQS_c) signal
+#define ARM_NAND_BUS_DDR2_CMPR          (1UL << 18)                               ///< DDR2 Enable complementary RE_n (RE_c) signal
+
+/*----- NAND Data Bus Width -----*/
+#define ARM_NAND_BUS_DATA_WIDTH_8       (0x00)      ///< Bus Data Width:  8 bit (default)
+#define ARM_NAND_BUS_DATA_WIDTH_16      (0x01)      ///< Bus Data Width: 16 bit
+
+/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_DRIVER_STRENGTH_18     (0x00)      ///< Driver Strength 2.0x = 18 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_25     (0x01)      ///< Driver Strength 1.4x = 25 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_35     (0x02)      ///< Driver Strength 1.0x = 35 Ohms (default)
+#define ARM_NAND_DRIVER_STRENGTH_50     (0x03)      ///< Driver Strength 0.7x = 50 Ohms
+
+
+/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_ECC_INDEX_Pos           0
+#define ARM_NAND_ECC_INDEX_Msk          (0xFFUL << ARM_NAND_ECC_INDEX_Pos)
+#define ARM_NAND_ECC(n)                 ((n) & ARM_NAND_ECC_INDEX_Msk)     ///< Select ECC
+#define ARM_NAND_ECC0                   (1UL << 8)                         ///< Use ECC0 of selected ECC
+#define ARM_NAND_ECC1                   (1UL << 9)                         ///< Use ECC1 of selected ECC
+
+/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_DRIVER_DONE_EVENT      (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE
+
+/****** NAND Sequence Execution Code *****/
+#define ARM_NAND_CODE_SEND_CMD1         (1UL << 17) ///< Send Command 1
+#define ARM_NAND_CODE_SEND_ADDR_COL1    (1UL << 18) ///< Send Column Address 1
+#define ARM_NAND_CODE_SEND_ADDR_COL2    (1UL << 19) ///< Send Column Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW1    (1UL << 20) ///< Send Row Address 1
+#define ARM_NAND_CODE_SEND_ADDR_ROW2    (1UL << 21) ///< Send Row Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW3    (1UL << 22) ///< Send Row Address 3
+#define ARM_NAND_CODE_INC_ADDR_ROW      (1UL << 23) ///< Auto-increment Row Address
+#define ARM_NAND_CODE_WRITE_DATA        (1UL << 24) ///< Write Data
+#define ARM_NAND_CODE_SEND_CMD2         (1UL << 25) ///< Send Command 2
+#define ARM_NAND_CODE_WAIT_BUSY         (1UL << 26) ///< Wait while R/Bn busy
+#define ARM_NAND_CODE_READ_DATA         (1UL << 27) ///< Read Data
+#define ARM_NAND_CODE_SEND_CMD3         (1UL << 28) ///< Send Command 3
+#define ARM_NAND_CODE_READ_STATUS       (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0)
+
+/*----- NAND Sequence Execution Code: Command -----*/
+#define ARM_NAND_CODE_CMD1_Pos           0
+#define ARM_NAND_CODE_CMD1_Msk          (0xFFUL << ARM_NAND_CODE_CMD1_Pos)
+#define ARM_NAND_CODE_CMD2_Pos           8
+#define ARM_NAND_CODE_CMD2_Msk          (0xFFUL << ARM_NAND_CODE_CMD2_Pos)
+#define ARM_NAND_CODE_CMD3_Pos           16
+#define ARM_NAND_CODE_CMD3_Msk          (0xFFUL << ARM_NAND_CODE_CMD3_Pos)
+
+/*----- NAND Sequence Execution Code: Column Address -----*/
+#define ARM_NAND_CODE_ADDR_COL1_Pos      0
+#define ARM_NAND_CODE_ADDR_COL1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)
+#define ARM_NAND_CODE_ADDR_COL2_Pos      8
+#define ARM_NAND_CODE_ADDR_COL2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)
+
+/*----- NAND Sequence Execution Code: Row Address -----*/
+#define ARM_NAND_CODE_ADDR_ROW1_Pos      0
+#define ARM_NAND_CODE_ADDR_ROW1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)
+#define ARM_NAND_CODE_ADDR_ROW2_Pos      8
+#define ARM_NAND_CODE_ADDR_ROW2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)
+#define ARM_NAND_CODE_ADDR_ROW3_Pos      16
+#define ARM_NAND_CODE_ADDR_ROW3_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)
+
+
+/****** NAND specific error codes *****/
+#define ARM_NAND_ERROR_ECC              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< ECC generation/correction failed
+
+
+/**
+\brief NAND ECC (Error Correction Code) Information
+*/
+typedef struct _ARM_NAND_ECC_INFO {
+  uint32_t type             :  2;       ///< Type: 1=ECC0 over Data, 2=ECC0 over Data+Spare, 3=ECC0 over Data and ECC1 over Spare
+  uint32_t page_layout      :  1;       ///< Page layout: 0=|Data0|Spare0|...|DataN-1|SpareN-1|, 1=|Data0|...|DataN-1|Spare0|...|SpareN-1|
+  uint32_t page_count       :  3;       ///< Number of virtual pages: N = 2 ^ page_count
+  uint32_t page_size        :  4;       ///< Virtual Page size (Data+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448
+  uint32_t reserved         : 14;       ///< Reserved (must be zero)
+  uint32_t correctable_bits :  8;       ///< Number of correctable bits (based on 512 byte codeword size)
+  uint16_t codeword_size [2];           ///< Number of bytes over which ECC is calculated
+  uint16_t ecc_size      [2];           ///< ECC size in bytes (rounded up)
+  uint16_t ecc_offset    [2];           ///< ECC offset in bytes (where ECC starts in Spare area) 
+} ARM_NAND_ECC_INFO;
+
+
+/**
+\brief NAND Status
+*/
+typedef struct _ARM_NAND_STATUS {
+  uint32_t busy      : 1;               ///< Driver busy flag
+  uint32_t ecc_error : 1;               ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence)
+} ARM_NAND_STATUS;
+
+
+/****** NAND Event *****/
+#define ARM_NAND_EVENT_DEVICE_READY     (1UL << 0)  ///< Device Ready: R/Bn rising edge
+#define ARM_NAND_EVENT_DRIVER_READY     (1UL << 1)  ///< Driver Ready
+#define ARM_NAND_EVENT_DRIVER_DONE      (1UL << 2)  ///< Driver operation done
+#define ARM_NAND_EVENT_ECC_ERROR        (1UL << 3)  ///< ECC could not correct data
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_NAND_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event)
+  \brief         Initialize the NAND Interface.
+  \param[in]     cb_event  Pointer to \ref ARM_NAND_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Uninitialize (void)
+  \brief         De-initialize the NAND Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)
+  \brief         Control the NAND interface power.
+  \param[in]     state  Power state
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_DevicePower (uint32_t voltage)
+  \brief         Set device power supply voltage.
+  \param[in]     voltage  NAND Device supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)
+  \brief         Control WPn (Write Protect).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Write Protect off
+                - \b true  Write Protect on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)
+  \brief         Control CEn (Chip Enable).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Chip Enable off
+                - \b true  Chip Enable on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)
+  \brief         Get Device Busy pin state.
+  \param[in]     dev_num  Device number
+  \return        1=busy, 0=not busy, or error
+*/
+/**
+  \fn            int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)
+  \brief         Send command to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     cmd      Command
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)
+  \brief         Send address to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     addr     Address
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)
+  \brief         Read data from NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer for data to read from NAND device
+  \param[in]     cnt      Number of data items to read
+  \param[in]     mode     Operation mode
+  \return        number of data items read or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)
+  \brief         Write data to NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer with data to write to NAND device
+  \param[in]     cnt      Number of data items to write
+  \param[in]     mode     Operation mode
+  \return        number of data items written or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                                   uint32_t addr_col, uint32_t addr_row,
+                                                   void *data, uint32_t data_cnt,
+                                                   uint8_t *status, uint32_t *count)
+  \brief         Execute sequence of operations.
+  \param[in]     dev_num  Device number
+  \param[in]     code     Sequence code
+  \param[in]     cmd      Command(s)
+  \param[in]     addr_col Column address
+  \param[in]     addr_row Row address
+  \param[in,out] data     Pointer to data to be written or read 
+  \param[in]     data_cnt Number of data items in one iteration
+  \param[out]    status   Pointer to status read
+  \param[in,out] count    Number of iterations
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_AbortSequence (uint32_t dev_num)
+  \brief         Abort sequence execution.
+  \param[in]     dev_num  Device number
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)
+  \brief         Control NAND Interface.
+  \param[in]     dev_num  Device number
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)
+  \brief         Get NAND status.
+  \param[in]     dev_num  Device number
+  \return        NAND status \ref ARM_NAND_STATUS
+*/
+/**
+  \fn            int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)
+  \brief         Inquire about available ECC.
+  \param[in]     index   Device number
+  \param[out]    info    Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved
+  \return        \ref execution_status
+*/
+
+/**
+  \fn            void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)
+  \brief         Signal NAND event.
+  \param[in]     dev_num  Device number
+  \param[in]     event    Event notification mask
+  \return        none
+*/
+
+typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event);    ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event.
+
+
+/**
+\brief NAND Driver Capabilities.
+*/
+typedef struct _ARM_NAND_CAPABILITIES {
+  uint32_t event_device_ready  : 1;     ///< Signal Device Ready event (R/Bn rising edge)
+  uint32_t reentrant_operation : 1;     ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData)
+  uint32_t sequence_operation  : 1;     ///< Supports Sequence operation (ExecuteSequence, AbortSequence)
+  uint32_t vcc                 : 1;     ///< Supports VCC Power Supply Control
+  uint32_t vcc_1v8             : 1;     ///< Supports 1.8 VCC Power Supply
+  uint32_t vccq                : 1;     ///< Supports VCCQ I/O Power Supply Control
+  uint32_t vccq_1v8            : 1;     ///< Supports 1.8 VCCQ I/O Power Supply
+  uint32_t vpp                 : 1;     ///< Supports VPP High Voltage Power Supply Control
+  uint32_t wp                  : 1;     ///< Supports WPn (Write Protect) Control
+  uint32_t ce_lines            : 4;     ///< Number of CEn (Chip Enable) lines: ce_lines + 1
+  uint32_t ce_manual           : 1;     ///< Supports manual CEn (Chip Enable) Control
+  uint32_t rb_monitor          : 1;     ///< Supports R/Bn (Ready/Busy) Monitoring
+  uint32_t data_width_16       : 1;     ///< Supports 16-bit data
+  uint32_t ddr                 : 1;     ///< Supports NV-DDR  Data Interface (ONFI)
+  uint32_t ddr2                : 1;     ///< Supports NV-DDR2 Data Interface (ONFI)
+  uint32_t sdr_timing_mode     : 3;     ///< Fastest (highest) SDR     Timing Mode supported (ONFI)
+  uint32_t ddr_timing_mode     : 3;     ///< Fastest (highest) NV_DDR  Timing Mode supported (ONFI)
+  uint32_t ddr2_timing_mode    : 3;     ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)
+  uint32_t driver_strength_18  : 1;     ///< Supports Driver Strength 2.0x = 18 Ohms
+  uint32_t driver_strength_25  : 1;     ///< Supports Driver Strength 1.4x = 25 Ohms
+  uint32_t driver_strength_50  : 1;     ///< Supports Driver Strength 0.7x = 50 Ohms
+} ARM_NAND_CAPABILITIES;
+
+
+/**
+\brief Access structure of the NAND Driver.
+*/
+typedef struct _ARM_DRIVER_NAND {
+  ARM_DRIVER_VERSION    (*GetVersion)     (void);                                                             ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version.
+  ARM_NAND_CAPABILITIES (*GetCapabilities)(void);                                                             ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)     (ARM_NAND_SignalEvent_t cb_event);                                  ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface.
+  int32_t               (*Uninitialize)   (void);                                                             ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface.
+  int32_t               (*PowerControl)   (ARM_POWER_STATE state);                                            ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power.
+  int32_t               (*DevicePower)    (uint32_t voltage);                                                 ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage.
+  int32_t               (*WriteProtect)   (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect).
+  int32_t               (*ChipEnable)     (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable).
+  int32_t               (*GetDeviceBusy)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state.
+  int32_t               (*SendCommand)    (uint32_t dev_num, uint8_t cmd);                                    ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device.
+  int32_t               (*SendAddress)    (uint32_t dev_num, uint8_t addr);                                   ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device.
+  int32_t               (*ReadData)       (uint32_t dev_num,       void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device.
+  int32_t               (*WriteData)      (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device.
+  int32_t               (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                           uint32_t addr_col, uint32_t addr_row,
+                                           void *data, uint32_t data_cnt,
+                                           uint8_t *status, uint32_t *count);                                 ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations.
+  int32_t               (*AbortSequence)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution. 
+  int32_t               (*Control)        (uint32_t dev_num, uint32_t control, uint32_t arg);                 ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface.
+  ARM_NAND_STATUS       (*GetStatus)      (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status.
+  int32_t               (*InquireECC)     ( int32_t index, ARM_NAND_ECC_INFO *info);                          ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC. 
+} const ARM_DRIVER_NAND;
+
+#endif /* __DRIVER_NAND_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_SPI.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_SPI.h
new file mode 100644
index 00000000..28bd10af
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_SPI.h
@@ -0,0 +1,237 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        17. Apr 2014
+ * $Revision:    V2.01
+ *
+ * Project:      SPI (Serial Peripheral Interface) Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.01
+ *    Renamed status flag "tx_rx_busy" to "busy"
+ *  Version 2.00
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *      Half-duplex Modes
+ *      Configurable number of data bits
+ *      Support for TI Mode and Microwire
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added "send_done_event" to Capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_SPI_H
+#define __DRIVER_SPI_H
+
+#include "Driver_Common.h"
+
+#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,00)  /* API version */
+
+
+/****** SPI Control Codes *****/
+
+#define ARM_SPI_CONTROL_Pos              0
+#define ARM_SPI_CONTROL_Msk             (0xFFUL << ARM_SPI_CONTROL_Pos)
+
+/*----- SPI Control Codes: Mode -----*/
+#define ARM_SPI_MODE_INACTIVE           (0x00UL << ARM_SPI_CONTROL_Pos)     ///< SPI Inactive
+#define ARM_SPI_MODE_MASTER             (0x01UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
+#define ARM_SPI_MODE_SLAVE              (0x02UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output on MISO, Input on MOSI)
+#define ARM_SPI_MODE_MASTER_SIMPLEX     (0x03UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
+#define ARM_SPI_MODE_SLAVE_SIMPLEX      (0x04UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output/Input on MISO)
+
+/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
+#define ARM_SPI_FRAME_FORMAT_Pos         8
+#define ARM_SPI_FRAME_FORMAT_Msk        (7UL << ARM_SPI_FRAME_FORMAT_Pos)
+#define ARM_SPI_CPOL0_CPHA0             (0UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 0 (default)
+#define ARM_SPI_CPOL0_CPHA1             (1UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 1
+#define ARM_SPI_CPOL1_CPHA0             (2UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 0
+#define ARM_SPI_CPOL1_CPHA1             (3UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 1
+#define ARM_SPI_TI_SSI                  (4UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Texas Instruments Frame Format
+#define ARM_SPI_MICROWIRE               (5UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< National Microwire Frame Format
+
+/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_SPI_DATA_BITS_Pos            12
+#define ARM_SPI_DATA_BITS_Msk           (0x3FUL << ARM_SPI_DATA_BITS_Pos)
+#define ARM_SPI_DATA_BITS(n)            (((n) & 0x3F) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits
+
+/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
+#define ARM_SPI_BIT_ORDER_Pos            18
+#define ARM_SPI_BIT_ORDER_Msk           (1UL << ARM_SPI_BIT_ORDER_Pos)
+#define ARM_SPI_MSB_LSB                 (0UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from MSB to LSB (default)
+#define ARM_SPI_LSB_MSB                 (1UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from LSB to MSB
+
+/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
+#define ARM_SPI_SS_MASTER_MODE_Pos       19
+#define ARM_SPI_SS_MASTER_MODE_Msk      (3UL << ARM_SPI_SS_MASTER_MODE_Pos)
+#define ARM_SPI_SS_MASTER_UNUSED        (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default)
+#define ARM_SPI_SS_MASTER_SW            (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled
+#define ARM_SPI_SS_MASTER_HW_OUTPUT     (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output
+#define ARM_SPI_SS_MASTER_HW_INPUT      (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input
+#define ARM_SPI_SS_SLAVE_MODE_Pos        21
+#define ARM_SPI_SS_SLAVE_MODE_Msk       (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)
+#define ARM_SPI_SS_SLAVE_HW             (0UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Hardware monitored (default)
+#define ARM_SPI_SS_SLAVE_SW             (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Software controlled
+
+
+/*----- SPI Control Codes: Miscellaneous Controls  -----*/
+#define ARM_SPI_SET_BUS_SPEED           (0x10UL << ARM_SPI_CONTROL_Pos)     ///< Set Bus Speed in bps; arg = value
+#define ARM_SPI_GET_BUS_SPEED           (0x11UL << ARM_SPI_CONTROL_Pos)     ///< Get Bus Speed in bps
+#define ARM_SPI_SET_DEFAULT_TX_VALUE    (0x12UL << ARM_SPI_CONTROL_Pos)     ///< Set default Transmit value; arg = value
+#define ARM_SPI_CONTROL_SS              (0x13UL << ARM_SPI_CONTROL_Pos)     ///< Control Slave Select; arg: 0=inactive, 1=active 
+#define ARM_SPI_ABORT_TRANSFER          (0x14UL << ARM_SPI_CONTROL_Pos)     ///< Abort current data transfer
+
+
+/****** SPI Slave Select Signal definitions *****/
+#define ARM_SPI_SS_INACTIVE              0                                  ///< SPI Slave Select Signal Inactive
+#define ARM_SPI_SS_ACTIVE                1                                  ///< SPI Slave Select Signal Active
+
+
+/****** SPI specific error codes *****/
+#define ARM_SPI_ERROR_MODE              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_SPI_ERROR_FRAME_FORMAT      (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Frame Format not supported
+#define ARM_SPI_ERROR_DATA_BITS         (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_SPI_ERROR_BIT_ORDER         (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported
+#define ARM_SPI_ERROR_SS_MODE           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Slave Select Mode not supported
+
+
+/**
+\brief SPI Status
+*/
+typedef struct _ARM_SPI_STATUS {
+  uint32_t busy       : 1;              ///< Transmitter/Receiver busy flag
+  uint32_t data_lost  : 1;              ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
+  uint32_t mode_fault : 1;              ///< Mode fault detected; optional (cleared on start of transfer operation)
+} ARM_SPI_STATUS;
+
+
+/****** SPI Event *****/
+#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0)  ///< Data Transfer completed
+#define ARM_SPI_EVENT_DATA_LOST         (1UL << 1)  ///< Data lost: Receive overflow / Transmit underflow
+#define ARM_SPI_EVENT_MODE_FAULT        (1UL << 2)  ///< Master Mode Fault (SS deactivated when Master)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_SPI_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SPI_CAPABILITIES
+
+  \fn          int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)
+  \brief       Initialize SPI Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SPI_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Uninitialize (void)
+  \brief       De-initialize SPI Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control SPI Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Send (const void *data, uint32_t num)
+  \brief       Start sending data to SPI transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SPI transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from SPI receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Transfer (const void *data_out,
+                                               void *data_in,
+                                         uint32_t    num)
+  \brief       Start sending/receiving data to/from SPI transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to SPI transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_SPI_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data items transferred
+
+  \fn          int32_t ARM_SPI_Control (uint32_t control, uint32_t arg)
+  \brief       Control SPI Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref spi_execution_status
+
+  \fn          ARM_SPI_STATUS ARM_SPI_GetStatus (void)
+  \brief       Get SPI status.
+  \return      SPI status \ref ARM_SPI_STATUS
+
+  \fn          void ARM_SPI_SignalEvent (uint32_t event)
+  \brief       Signal SPI Events.
+  \param[in]   event \ref SPI_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event.
+
+
+/**
+\brief SPI Driver Capabilities.
+*/
+typedef struct _ARM_SPI_CAPABILITIES {
+  uint32_t simplex          : 1;        ///< supports Simplex Mode (Master and Slave)
+  uint32_t ti_ssi           : 1;        ///< supports TI Synchronous Serial Interface
+  uint32_t microwire        : 1;        ///< supports Microwire Interface
+  uint32_t event_mode_fault : 1;        ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT
+} ARM_SPI_CAPABILITIES;
+
+
+/**
+\brief Access structure of the SPI Driver.
+*/
+typedef struct _ARM_DRIVER_SPI {
+  ARM_DRIVER_VERSION   (*GetVersion)      (void);                             ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version.
+  ARM_SPI_CAPABILITIES (*GetCapabilities) (void);                             ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)      (ARM_SPI_SignalEvent_t cb_event);   ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface.
+  int32_t              (*Uninitialize)    (void);                             ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface.
+  int32_t              (*PowerControl)    (ARM_POWER_STATE state);            ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power.
+  int32_t              (*Send)            (const void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface.
+  int32_t              (*Receive)         (      void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface.
+  int32_t              (*Transfer)        (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num);                  ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI.
+  uint32_t             (*GetDataCount)    (void);                             ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count.
+  int32_t              (*Control)         (uint32_t control, uint32_t arg);   ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface.
+  ARM_SPI_STATUS       (*GetStatus)       (void);                             ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status.
+} const ARM_DRIVER_SPI;
+
+#endif /* __DRIVER_SPI_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USART.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USART.h
new file mode 100644
index 00000000..731acc94
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USART.h
@@ -0,0 +1,328 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        9. Apr 2014
+ * $Revision:    V2.01
+ *
+ * Project:      USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ *               Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.01
+ *    Removed optional argument parameter from Signal Event
+ *  Version 2.00
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *      renamed driver UART -> USART (Asynchronous & Synchronous)
+ *    Added modes:
+ *      Synchronous
+ *      Single-wire
+ *      IrDA
+ *      Smart Card  
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added events:
+ *      ARM_UART_EVENT_TX_EMPTY,     ARM_UART_EVENT_RX_TIMEOUT
+ *      ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
+ *    Added functions: SetTxThreshold, SetRxThreshold
+ *    Added "rx_timeout_event" to capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_USART_H
+#define __DRIVER_USART_H
+
+#include "Driver_Common.h"
+
+#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01)  /* API version */
+
+
+/****** USART Control Codes *****/
+
+#define ARM_USART_CONTROL_Pos                0
+#define ARM_USART_CONTROL_Msk               (0xFFUL << ARM_USART_CONTROL_Pos)
+
+/*----- USART Control Codes: Mode -----*/
+#define ARM_USART_MODE_ASYNCHRONOUS         (0x01UL << ARM_USART_CONTROL_Pos)   ///< UART (Asynchronous); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_MASTER   (0x02UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Master (generates clock signal); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_SLAVE    (0x03UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Slave (external clock signal)
+#define ARM_USART_MODE_SINGLE_WIRE          (0x04UL << ARM_USART_CONTROL_Pos)   ///< UART Single-wire (half-duplex); arg = Baudrate
+#define ARM_USART_MODE_IRDA                 (0x05UL << ARM_USART_CONTROL_Pos)   ///< UART IrDA; arg = Baudrate
+#define ARM_USART_MODE_SMART_CARD           (0x06UL << ARM_USART_CONTROL_Pos)   ///< UART Smart Card; arg = Baudrate
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_USART_DATA_BITS_Pos              8
+#define ARM_USART_DATA_BITS_Msk             (7UL << ARM_USART_DATA_BITS_Pos)
+#define ARM_USART_DATA_BITS_5               (5UL << ARM_USART_DATA_BITS_Pos)    ///< 5 Data bits
+#define ARM_USART_DATA_BITS_6               (6UL << ARM_USART_DATA_BITS_Pos)    ///< 6 Data bit
+#define ARM_USART_DATA_BITS_7               (7UL << ARM_USART_DATA_BITS_Pos)    ///< 7 Data bits
+#define ARM_USART_DATA_BITS_8               (0UL << ARM_USART_DATA_BITS_Pos)    ///< 8 Data bits (default)
+#define ARM_USART_DATA_BITS_9               (1UL << ARM_USART_DATA_BITS_Pos)    ///< 9 Data bits
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+#define ARM_USART_PARITY_Pos                 12
+#define ARM_USART_PARITY_Msk                (3UL << ARM_USART_PARITY_Pos)
+#define ARM_USART_PARITY_NONE               (0UL << ARM_USART_PARITY_Pos)       ///< No Parity (default)
+#define ARM_USART_PARITY_EVEN               (1UL << ARM_USART_PARITY_Pos)       ///< Even Parity
+#define ARM_USART_PARITY_ODD                (2UL << ARM_USART_PARITY_Pos)       ///< Odd Parity
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+#define ARM_USART_STOP_BITS_Pos              14
+#define ARM_USART_STOP_BITS_Msk             (3UL << ARM_USART_STOP_BITS_Pos)
+#define ARM_USART_STOP_BITS_1               (0UL << ARM_USART_STOP_BITS_Pos)    ///< 1 Stop bit (default)
+#define ARM_USART_STOP_BITS_2               (1UL << ARM_USART_STOP_BITS_Pos)    ///< 2 Stop bits
+#define ARM_USART_STOP_BITS_1_5             (2UL << ARM_USART_STOP_BITS_Pos)    ///< 1.5 Stop bits
+#define ARM_USART_STOP_BITS_0_5             (3UL << ARM_USART_STOP_BITS_Pos)    ///< 0.5 Stop bits
+
+/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
+#define ARM_USART_FLOW_CONTROL_Pos           16
+#define ARM_USART_FLOW_CONTROL_Msk          (3UL << ARM_USART_FLOW_CONTROL_Pos)
+#define ARM_USART_FLOW_CONTROL_NONE         (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
+#define ARM_USART_FLOW_CONTROL_RTS          (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
+#define ARM_USART_FLOW_CONTROL_CTS          (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
+#define ARM_USART_FLOW_CONTROL_RTS_CTS      (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+#define ARM_USART_CPOL_Pos                   17
+#define ARM_USART_CPOL_Msk                  (1UL << ARM_USART_CPOL_Pos)
+#define ARM_USART_CPOL0                     (0UL << ARM_USART_CPOL_Pos)         ///< CPOL = 0 (default)
+#define ARM_USART_CPOL1                     (1UL << ARM_USART_CPOL_Pos)         ///< CPOL = 1
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+#define ARM_USART_CPHA_Pos                   18
+#define ARM_USART_CPHA_Msk                  (1UL << ARM_USART_CPHA_Pos)
+#define ARM_USART_CPHA0                     (0UL << ARM_USART_CPHA_Pos)         ///< CPHA = 0 (default)
+#define ARM_USART_CPHA1                     (1UL << ARM_USART_CPHA_Pos)         ///< CPHA = 1
+
+
+/*----- USART Control Codes: Miscellaneous Controls  -----*/
+#define ARM_USART_SET_DEFAULT_TX_VALUE      (0x10UL << ARM_USART_CONTROL_Pos)   ///< Set default Transmit value (Synchronous Receive only); arg = value
+#define ARM_USART_SET_IRDA_PULSE            (0x11UL << ARM_USART_CONTROL_Pos)   ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period  
+#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Guard Time; arg = number of bit periods
+#define ARM_USART_SET_SMART_CARD_CLOCK      (0x13UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
+#define ARM_USART_CONTROL_SMART_CARD_NACK   (0x14UL << ARM_USART_CONTROL_Pos)   ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_TX                (0x15UL << ARM_USART_CONTROL_Pos)   ///< Transmitter; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_RX                (0x16UL << ARM_USART_CONTROL_Pos)   ///< Receiver; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_BREAK             (0x17UL << ARM_USART_CONTROL_Pos)   ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
+#define ARM_USART_ABORT_SEND                (0x18UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Send
+#define ARM_USART_ABORT_RECEIVE             (0x19UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Receive
+#define ARM_USART_ABORT_TRANSFER            (0x1AUL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Transfer
+
+
+
+/****** USART specific error codes *****/
+#define ARM_USART_ERROR_MODE                (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_USART_ERROR_BAUDRATE            (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified baudrate not supported
+#define ARM_USART_ERROR_DATA_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_USART_ERROR_PARITY              (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Parity not supported
+#define ARM_USART_ERROR_STOP_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified number of Stop bits not supported
+#define ARM_USART_ERROR_FLOW_CONTROL        (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Flow Control not supported
+#define ARM_USART_ERROR_CPOL                (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock Polarity not supported
+#define ARM_USART_ERROR_CPHA                (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Clock Phase not supported
+
+
+/**
+\brief USART Status
+*/
+typedef struct _ARM_USART_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t rx_break         : 1;        ///< Break detected on receive (cleared on start of next receive operation)
+  uint32_t rx_framing_error : 1;        ///< Framing error detected on receive (cleared on start of next receive operation)
+  uint32_t rx_parity_error  : 1;        ///< Parity error detected on receive (cleared on start of next receive operation)
+} ARM_USART_STATUS;
+
+/**
+\brief USART Modem Control
+*/
+typedef enum _ARM_USART_MODEM_CONTROL {
+  ARM_USART_RTS_CLEAR,                  ///< Deactivate RTS
+  ARM_USART_RTS_SET,                    ///< Activate RTS
+  ARM_USART_DTR_CLEAR,                  ///< Deactivate DTR
+  ARM_USART_DTR_SET                     ///< Activate DTR
+} ARM_USART_MODEM_CONTROL;
+
+/**
+\brief USART Modem Status
+*/
+typedef struct _ARM_USART_MODEM_STATUS {
+  uint32_t cts : 1;                     ///< CTS state: 1=Active, 0=Inactive
+  uint32_t dsr : 1;                     ///< DSR state: 1=Active, 0=Inactive
+  uint32_t dcd : 1;                     ///< DCD state: 1=Active, 0=Inactive
+  uint32_t ri  : 1;                     ///< RI  state: 1=Active, 0=Inactive
+} ARM_USART_MODEM_STATUS;
+
+
+/****** USART Event *****/
+#define ARM_USART_EVENT_SEND_COMPLETE       (1UL << 0)  ///< Send completed; however USART may still transmit data
+#define ARM_USART_EVENT_RECEIVE_COMPLETE    (1UL << 1)  ///< Receive completed
+#define ARM_USART_EVENT_TRANSFER_COMPLETE   (1UL << 2)  ///< Transfer completed
+#define ARM_USART_EVENT_TX_COMPLETE         (1UL << 3)  ///< Transmit completed (optional)
+#define ARM_USART_EVENT_TX_UNDERFLOW        (1UL << 4)  ///< Transmit data not available (Synchronous Slave)
+#define ARM_USART_EVENT_RX_OVERFLOW         (1UL << 5)  ///< Receive data overflow
+#define ARM_USART_EVENT_RX_TIMEOUT          (1UL << 6)  ///< Receive character timeout (optional)
+#define ARM_USART_EVENT_RX_BREAK            (1UL << 7)  ///< Break detected on receive
+#define ARM_USART_EVENT_RX_FRAMING_ERROR    (1UL << 8)  ///< Framing error detected on receive
+#define ARM_USART_EVENT_RX_PARITY_ERROR     (1UL << 9)  ///< Parity error detected on receive
+#define ARM_USART_EVENT_CTS                 (1UL << 10) ///< CTS state changed (optional)
+#define ARM_USART_EVENT_DSR                 (1UL << 11) ///< DSR state changed (optional)
+#define ARM_USART_EVENT_DCD                 (1UL << 12) ///< DCD state changed (optional)
+#define ARM_USART_EVENT_RI                  (1UL << 13) ///< RI  state changed (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
+  \brief       Get driver capabilities
+  \return      \ref ARM_USART_CAPABILITIES
+
+  \fn          int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
+  \brief       Initialize USART Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_USART_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Uninitialize (void)
+  \brief       De-initialize USART Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USART Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Send (const void *data, uint32_t num)
+  \brief       Start sending data to USART transmitter.
+  \param[in]   data  Pointer to buffer with data to send to USART transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from USART receiver.
+  \param[out]  data  Pointer to buffer for data to receive from USART receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Transfer (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num)
+  \brief       Start sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_USART_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_USART_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
+  \brief       Control USART Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref usart_execution_status
+
+  \fn          ARM_USART_STATUS ARM_USART_GetStatus (void)
+  \brief       Get USART status.
+  \return      USART status \ref ARM_USART_STATUS
+
+  \fn          int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
+  \brief       Set USART Modem Control line state.
+  \param[in]   control  \ref ARM_USART_MODEM_CONTROL
+  \return      \ref execution_status 
+
+  \fn          ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
+  \brief       Get USART Modem Status lines state.
+  \return      modem status \ref ARM_USART_MODEM_STATUS
+
+  \fn          void ARM_USART_SignalEvent (uint32_t event)
+  \brief       Signal USART Events.
+  \param[in]   event  \ref USART_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_USART_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
+
+
+/**
+\brief USART Device Driver Capabilities.
+*/
+typedef struct _ARM_USART_CAPABILITIES {
+  uint32_t asynchronous       : 1;      ///< supports UART (Asynchronous) mode 
+  uint32_t synchronous_master : 1;      ///< supports Synchronous Master mode
+  uint32_t synchronous_slave  : 1;      ///< supports Synchronous Slave mode
+  uint32_t single_wire        : 1;      ///< supports UART Single-wire mode
+  uint32_t irda               : 1;      ///< supports UART IrDA mode
+  uint32_t smart_card         : 1;      ///< supports UART Smart Card mode
+  uint32_t smart_card_clock   : 1;      ///< Smart Card Clock generator available
+  uint32_t flow_control_rts   : 1;      ///< RTS Flow Control available
+  uint32_t flow_control_cts   : 1;      ///< CTS Flow Control available
+  uint32_t event_tx_complete  : 1;      ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+  uint32_t event_rx_timeout   : 1;      ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+  uint32_t rts                : 1;      ///< RTS Line: 0=not available, 1=available
+  uint32_t cts                : 1;      ///< CTS Line: 0=not available, 1=available
+  uint32_t dtr                : 1;      ///< DTR Line: 0=not available, 1=available
+  uint32_t dsr                : 1;      ///< DSR Line: 0=not available, 1=available
+  uint32_t dcd                : 1;      ///< DCD Line: 0=not available, 1=available
+  uint32_t ri                 : 1;      ///< RI Line: 0=not available, 1=available
+  uint32_t event_cts          : 1;      ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
+  uint32_t event_dsr          : 1;      ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
+  uint32_t event_dcd          : 1;      ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
+  uint32_t event_ri           : 1;      ///< Signal RI change event: \ref ARM_USART_EVENT_RI
+} ARM_USART_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USART Driver.
+*/
+typedef struct _ARM_DRIVER_USART {
+  ARM_DRIVER_VERSION     (*GetVersion)      (void);                              ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
+  ARM_USART_CAPABILITIES (*GetCapabilities) (void);                              ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)      (ARM_USART_SignalEvent_t cb_event);  ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
+  int32_t                (*Uninitialize)    (void);                              ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
+  int32_t                (*PowerControl)    (ARM_POWER_STATE state);             ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
+  int32_t                (*Send)            (const void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
+  int32_t                (*Receive)         (      void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
+  int32_t                (*Transfer)        (const void *data_out,
+                                                   void *data_in,
+                                             uint32_t    num);                   ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
+  uint32_t               (*GetTxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
+  uint32_t               (*GetRxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
+  int32_t                (*Control)         (uint32_t control, uint32_t arg);    ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
+  ARM_USART_STATUS       (*GetStatus)       (void);                              ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
+  int32_t                (*SetModemControl) (ARM_USART_MODEM_CONTROL control);   ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
+  ARM_USART_MODEM_STATUS (*GetModemStatus)  (void);                              ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
+} const ARM_DRIVER_USART;
+
+#endif /* __DRIVER_USART_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USB.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USB.h
new file mode 100644
index 00000000..4f3a1b87
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USB.h
@@ -0,0 +1,95 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        20. May 2014
+ * $Revision:    V2.00
+ *
+ * Project:      USB Driver common definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.00
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added PID Types
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_USB_H
+#define __DRIVER_USB_H
+
+#include "Driver_Common.h"
+
+/* USB Role */
+#define ARM_USB_ROLE_NONE                0
+#define ARM_USB_ROLE_HOST                1
+#define ARM_USB_ROLE_DEVICE              2
+
+/* USB Pins */
+#define ARM_USB_PIN_DP                  (1 << 0) ///< USB D+ pin
+#define ARM_USB_PIN_DM                  (1 << 1) ///< USB D- pin
+#define ARM_USB_PIN_VBUS                (1 << 2) ///< USB VBUS pin
+#define ARM_USB_PIN_OC                  (1 << 3) ///< USB OverCurrent pin
+#define ARM_USB_PIN_ID                  (1 << 4) ///< USB ID pin
+
+/* USB Speed */
+#define ARM_USB_SPEED_LOW                0       ///< Low-speed USB
+#define ARM_USB_SPEED_FULL               1       ///< Full-speed USB
+#define ARM_USB_SPEED_HIGH               2       ///< High-speed USB
+
+/* USB PID Types */
+#define ARM_USB_PID_OUT                  1
+#define ARM_USB_PID_IN                   9
+#define ARM_USB_PID_SOF                  5
+#define ARM_USB_PID_SETUP                13
+#define ARM_USB_PID_DATA0                3
+#define ARM_USB_PID_DATA1                11
+#define ARM_USB_PID_DATA2                7
+#define ARM_USB_PID_MDATA                15
+#define ARM_USB_PID_ACK                  2
+#define ARM_USB_PID_NAK                  10
+#define ARM_USB_PID_STALL                14
+#define ARM_USB_PID_NYET                 6
+#define ARM_USB_PID_PRE                  12
+#define ARM_USB_PID_ERR                  12
+#define ARM_USB_PID_SPLIT                8
+#define ARM_USB_PID_PING                 4
+#define ARM_USB_PID_RESERVED             0
+
+/* USB Endpoint Address (bEndpointAddress) */
+#define ARM_USB_ENDPOINT_NUMBER_MASK     0x0F
+#define ARM_USB_ENDPOINT_DIRECTION_MASK  0x80
+
+/* USB Endpoint Type */
+#define ARM_USB_ENDPOINT_CONTROL         0       ///< Control Endpoint
+#define ARM_USB_ENDPOINT_ISOCHRONOUS     1       ///< Isochronous Endpoint
+#define ARM_USB_ENDPOINT_BULK            2       ///< Bulk Endpoint
+#define ARM_USB_ENDPOINT_INTERRUPT       3       ///< Interrupt Endpoint
+
+/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */
+#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK           0x07FF
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK   0x1800
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1      0x0000
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2      0x0800
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3      0x1000
+
+#endif /* __DRIVER_USB_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USBD.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USBD.h
new file mode 100644
index 00000000..3d363ea5
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USBD.h
@@ -0,0 +1,263 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        3. Jun 2014
+ * $Revision:    V2.01
+ *
+ * Project:      USB Device Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.01
+ *    Added ARM_USBD_ReadSetupPacket function
+ *  Version 2.00
+ *    Removed ARM_USBD_DeviceConfigure function
+ *    Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function
+ *    Removed ARM_USBD_EndpointReadStart function
+ *    Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer
+ *    Added ARM_USBD_EndpointTransferGetResult function
+ *    Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_USBD_H
+#define __DRIVER_USBD_H
+
+#include "Driver_USB.h"
+
+#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01)  /* API version */
+
+
+/**
+\brief USB Device State
+*/
+typedef struct _ARM_USBD_STATE {
+  uint32_t vbus   : 1;                  ///< USB Device VBUS flag
+  uint32_t speed  : 2;                  ///< USB Device speed setting (ARM_USB_SPEED_xxx)
+  uint32_t active : 1;                  ///< USB Device active flag
+} ARM_USBD_STATE;
+
+
+/****** USB Device Event *****/
+#define ARM_USBD_EVENT_VBUS_ON          (1UL << 0)      ///< USB Device VBUS On
+#define ARM_USBD_EVENT_VBUS_OFF         (1UL << 1)      ///< USB Device VBUS Off
+#define ARM_USBD_EVENT_RESET            (1UL << 2)      ///< USB Reset occurred
+#define ARM_USBD_EVENT_HIGH_SPEED       (1UL << 3)      ///< USB switch to High Speed occurred
+#define ARM_USBD_EVENT_SUSPEND          (1UL << 4)      ///< USB Suspend occurred
+#define ARM_USBD_EVENT_RESUME           (1UL << 5)      ///< USB Resume occurred
+
+/****** USB Endpoint Event *****/
+#define ARM_USBD_EVENT_SETUP            (1UL << 0)      ///< SETUP Packet
+#define ARM_USBD_EVENT_OUT              (1UL << 1)      ///< OUT Packet(s)
+#define ARM_USBD_EVENT_IN               (1UL << 2)      ///< IN Packet(s)
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBD_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBD_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                            ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+  \brief       Initialize USB Device Interface.
+  \param[in]   cb_device_event    Pointer to \ref ARM_USBD_SignalDeviceEvent
+  \param[in]   cb_endpoint_event  Pointer to \ref ARM_USBD_SignalEndpointEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_Uninitialize (void)
+  \brief       De-initialize USB Device Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Device Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceConnect (void)
+  \brief       Connect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceDisconnect (void)
+  \brief       Disconnect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBD_STATE ARM_USBD_DeviceGetState (void)
+  \brief       Get current USB Device State.
+  \return      Device State \ref ARM_USBD_STATE
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceRemoteWakeup (void)
+  \brief       Trigger USB Remote Wakeup.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr)
+  \brief       Set USB Device Address.
+  \param[in]   dev_addr  Device Address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup)
+  \brief       Read setup packet received over Control Endpoint.
+  \param[out]  setup  Pointer to buffer for setup packet
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointConfigure (uint8_t  ep_addr,
+                                                   uint8_t  ep_type,
+                                                   uint16_t ep_max_packet_size)
+  \brief       Configure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type  Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr)
+  \brief       Unconfigure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall)
+  \brief       Set/Clear Stall for USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   stall  Operation
+                - \b false Clear
+                - \b true Set
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
+  \brief       Read data from or Write data to USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[out]  data Pointer to buffer for data to read or with data to write
+  \param[in]   num  Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr)
+  \brief       Get result of USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      number of successfully transfered data bytes
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr)
+  \brief       Abort current USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBD_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBD_SignalDeviceEvent (uint32_t event)
+  \brief       Signal USB Device Event.
+  \param[in]   event \ref USBD_dev_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event)
+  \brief       Signal USB Endpoint Event.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   event \ref USBD_ep_events
+  \return      none
+*/
+
+typedef void (*ARM_USBD_SignalDeviceEvent_t)   (uint32_t event);                    ///< Pointer to \ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event.
+typedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event);   ///< Pointer to \ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event.
+
+
+/**
+\brief USB Device Driver Capabilities.
+*/
+typedef struct _ARM_USBD_CAPABILITIES {
+  uint32_t vbus_detection  : 1;         ///< VBUS detection
+  uint32_t event_vbus_on   : 1;         ///< Signal VBUS On event
+  uint32_t event_vbus_off  : 1;         ///< Signal VBUS Off event
+} ARM_USBD_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USB Device Driver.
+*/
+typedef struct _ARM_DRIVER_USBD {
+  ARM_DRIVER_VERSION    (*GetVersion)                (void);                                              ///< Pointer to \ref ARM_USBD_GetVersion : Get driver version.
+  ARM_USBD_CAPABILITIES (*GetCapabilities)           (void);                                              ///< Pointer to \ref ARM_USBD_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)                (ARM_USBD_SignalDeviceEvent_t   cb_device_event,                     
+                                                      ARM_USBD_SignalEndpointEvent_t cb_endpoint_event);  ///< Pointer to \ref ARM_USBD_Initialize : Initialize USB Device Interface. 
+  int32_t               (*Uninitialize)              (void);                                              ///< Pointer to \ref ARM_USBD_Uninitialize : De-initialize USB Device Interface.
+  int32_t               (*PowerControl)              (ARM_POWER_STATE state);                             ///< Pointer to \ref ARM_USBD_PowerControl : Control USB Device Interface Power.
+  int32_t               (*DeviceConnect)             (void);                                              ///< Pointer to \ref ARM_USBD_DeviceConnect : Connect USB Device.
+  int32_t               (*DeviceDisconnect)          (void);                                              ///< Pointer to \ref ARM_USBD_DeviceDisconnect : Disconnect USB Device.
+  ARM_USBD_STATE        (*DeviceGetState)            (void);                                              ///< Pointer to \ref ARM_USBD_DeviceGetState : Get current USB Device State.
+  int32_t               (*DeviceRemoteWakeup)        (void);                                              ///< Pointer to \ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup.
+  int32_t               (*DeviceSetAddress)          (uint8_t dev_addr);                                  ///< Pointer to \ref ARM_USBD_DeviceSetAddress : Set USB Device Address.
+  int32_t               (*ReadSetupPacket)           (uint8_t *setup);                                    ///< Pointer to \ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint.
+  int32_t               (*EndpointConfigure)         (uint8_t ep_addr,
+                                                      uint8_t ep_type,
+                                                      uint16_t ep_max_packet_size);                       ///< Pointer to \ref ARM_USBD_EndpointConfigure : Configure USB Endpoint.
+  int32_t               (*EndpointUnconfigure)       (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.
+  int32_t               (*EndpointStall)             (uint8_t ep_addr, bool stall);                       ///< Pointer to \ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.
+  int32_t               (*EndpointTransfer)          (uint8_t ep_addr, uint8_t *data, uint32_t num);      ///< Pointer to \ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint.
+  uint32_t              (*EndpointTransferGetResult) (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer.
+  int32_t               (*EndpointTransferAbort)     (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer.
+  uint16_t              (*GetFrameNumber)            (void);                                              ///< Pointer to \ref ARM_USBD_GetFrameNumber : Get current USB Frame Number.
+} const ARM_DRIVER_USBD;
+
+#endif /* __DOXYGEN_MW__ */
+
+#endif /* __DRIVER_USBD_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USBH.h b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USBH.h
new file mode 100644
index 00000000..46071f8d
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Driver/Include/Driver_USBH.h
@@ -0,0 +1,406 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        3. September 2014
+ * $Revision:    V2.01
+ *
+ * Project:      USB Host Driver definitions
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.01
+ *    Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE
+ *    Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe...
+ *    Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent
+ *  Version 2.00
+ *    Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff
+ *    Changed function ARM_USBH_EndpointCreate parameters
+ *    Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify
+ *    Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset
+ *    Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer
+ *    Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort
+ *    Added function ARM_USBH_EndpointTransferGetResult
+ *    Added function ARM_USBH_GetFrameNumber
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.20
+ *    Added API for OHCI/EHCI Host Controller Interface (HCI)
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef __DRIVER_USBH_H
+#define __DRIVER_USBH_H
+
+#include "Driver_USB.h"
+
+#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01)  /* API version */
+
+
+/**
+\brief USB Host Port State
+*/
+typedef struct _ARM_USBH_PORT_STATE {
+  uint32_t connected   : 1;             ///< USB Host Port connected flag
+  uint32_t overcurrent : 1;             ///< USB Host Port overcurrent flag
+  uint32_t speed       : 2;             ///< USB Host Port speed setting (ARM_USB_SPEED_xxx)
+} ARM_USBH_PORT_STATE;
+
+/**
+\brief USB Host Pipe Handle
+*/
+typedef uint32_t ARM_USBH_PIPE_HANDLE;
+#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE  /* Legacy name */
+
+
+/****** USB Host Packet Information *****/
+#define ARM_USBH_PACKET_TOKEN_Pos         0
+#define ARM_USBH_PACKET_TOKEN_Msk        (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos)
+#define ARM_USBH_PACKET_SETUP            (0x01UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< SETUP Packet
+#define ARM_USBH_PACKET_OUT              (0x02UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< OUT Packet
+#define ARM_USBH_PACKET_IN               (0x03UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< IN Packet
+#define ARM_USBH_PACKET_PING             (0x04UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< PING Packet
+
+#define ARM_USBH_PACKET_DATA_Pos          4
+#define ARM_USBH_PACKET_DATA_Msk         (0x0FUL << ARM_USBH_PACKET_DATA_Pos)
+#define ARM_USBH_PACKET_DATA0            (0x01UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA0 PID
+#define ARM_USBH_PACKET_DATA1            (0x02UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA1 PID
+
+#define ARM_USBH_PACKET_SPLIT_Pos         8
+#define ARM_USBH_PACKET_SPLIT_Msk        (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos)
+#define ARM_USBH_PACKET_SSPLIT           (0x08UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet
+#define ARM_USBH_PACKET_SSPLIT_S         (0x09UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data Start
+#define ARM_USBH_PACKET_SSPLIT_E         (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data End
+#define ARM_USBH_PACKET_SSPLIT_S_E       (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data All
+#define ARM_USBH_PACKET_CSPLIT           (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< CSPLIT Packet
+
+#define ARM_USBH_PACKET_PRE              (1UL << 12)                            ///< PRE Token
+
+
+/****** USB Host Port Event *****/
+#define ARM_USBH_EVENT_CONNECT           (1UL << 0)     ///< USB Device Connected to Port
+#define ARM_USBH_EVENT_DISCONNECT        (1UL << 1)     ///< USB Device Disconnected from Port
+#define ARM_USBH_EVENT_OVERCURRENT       (1UL << 2)     ///< USB Device caused Overcurrent
+#define ARM_USBH_EVENT_RESET             (1UL << 3)     ///< USB Reset completed
+#define ARM_USBH_EVENT_SUSPEND           (1UL << 4)     ///< USB Suspend occurred
+#define ARM_USBH_EVENT_RESUME            (1UL << 5)     ///< USB Resume occurred
+#define ARM_USBH_EVENT_REMOTE_WAKEUP     (1UL << 6)     ///< USB Device activated Remote Wakeup
+
+/****** USB Host Pipe Event *****/
+#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0)     ///< Transfer completed
+#define ARM_USBH_EVENT_HANDSHAKE_NAK     (1UL << 1)     ///< NAK Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_NYET    (1UL << 2)     ///< NYET Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_MDATA   (1UL << 3)     ///< MDATA Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_STALL   (1UL << 4)     ///< STALL Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_ERR     (1UL << 5)     ///< ERR Handshake received
+#define ARM_USBH_EVENT_BUS_ERROR         (1UL << 6)     ///< Bus Error detected
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event,
+                                            ARM_USBH_SignalPipeEvent_t cb_pipe_event)
+  \brief       Initialize USB Host Interface.
+  \param[in]   cb_port_event  Pointer to \ref ARM_USBH_SignalPortEvent
+  \param[in]   cb_pipe_event  Pointer to \ref ARM_USBH_SignalPipeEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_Uninitialize (void)
+  \brief       De-initialize USB Host Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortReset (uint8_t port)
+  \brief       Do Root HUB Port Reset.
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortSuspend (uint8_t port)
+  \brief       Suspend Root HUB Port (stop generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortResume (uint8_t port)
+  \brief       Resume Root HUB Port (start generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port)
+  \brief       Get current Root HUB Port State.
+  \param[in]   port  Root HUB Port Number
+  \return      Port State \ref ARM_USBH_PORT_STATE
+*/
+/**
+  \fn          ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t  dev_addr,
+                                                         uint8_t  dev_speed,
+                                                         uint8_t  hub_addr,
+                                                         uint8_t  hub_port,
+                                                         uint8_t  ep_addr,
+                                                         uint8_t  ep_type,
+                                                         uint16_t ep_max_packet_size,
+                                                         uint8_t  ep_interval)
+  \brief       Create Pipe in System.
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_addr    Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type    Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \param[in]   ep_interval        Endpoint Polling Interval
+  \return      Pipe Handle \ref ARM_USBH_PIPE_HANDLE
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                            uint8_t              dev_addr,
+                                            uint8_t              dev_speed,
+                                            uint8_t              hub_addr,
+                                            uint8_t              hub_port,
+                                            uint16_t             ep_max_packet_size)
+  \brief       Modify Pipe in System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Delete Pipe from System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Reset Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                              uint32_t             packet,
+                                              uint8_t             *data,
+                                              uint32_t             num)
+  \brief       Transfer packets through USB Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   packet     Packet information
+  \param[in]   data       Pointer to buffer with data to send or for data to receive
+  \param[in]   num        Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Get result of USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      number of successfully transfered data bytes
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Abort current USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBH_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event)
+  \brief       Signal Root HUB Port Event.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   event \ref USBH_port_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)
+  \brief       Signal Pipe Event.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   event  \ref USBH_pipe_events
+  \return      none
+*/
+
+typedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event);                    ///< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event.
+typedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event);  ///< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event.
+#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t  /* Legacy name */
+
+
+/**
+\brief USB Host Driver Capabilities.
+*/
+typedef struct _ARM_USBH_CAPABILITIES {
+  uint32_t port_mask          : 15;     ///< Root HUB available Ports Mask
+  uint32_t auto_split         :  1;     ///< Automatic SPLIT packet handling
+  uint32_t event_connect      :  1;     ///< Signal Connect event
+  uint32_t event_disconnect   :  1;     ///< Signal Disconnect event
+  uint32_t event_overcurrent  :  1;     ///< Signal Overcurrent event
+} ARM_USBH_CAPABILITIES;
+
+
+/**
+\brief Access structure of USB Host Driver.
+*/
+typedef struct _ARM_DRIVER_USBH {
+  ARM_DRIVER_VERSION    (*GetVersion)            (void);                                     ///< Pointer to \ref ARM_USBH_GetVersion : Get driver version.
+  ARM_USBH_CAPABILITIES (*GetCapabilities)       (void);                                     ///< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)            (ARM_USBH_SignalPortEvent_t cb_port_event,            
+                                                  ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface.
+  int32_t               (*Uninitialize)          (void);                                     ///< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface.
+  int32_t               (*PowerControl)          (ARM_POWER_STATE state);                    ///< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power.
+  int32_t               (*PortVbusOnOff)         (uint8_t port, bool vbus);                  ///< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off.
+  int32_t               (*PortReset)             (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset.
+  int32_t               (*PortSuspend)           (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs).
+  int32_t               (*PortResume)            (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs).
+  ARM_USBH_PORT_STATE   (*PortGetState)          (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State.
+  ARM_USBH_PIPE_HANDLE  (*PipeCreate)            (uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint8_t ep_addr,
+                                                  uint8_t ep_type,
+                                                  uint16_t ep_max_packet_size,
+                                                  uint8_t ep_interval);                      ///< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System.
+  int32_t               (*PipeModify)            (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                                  uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint16_t ep_max_packet_size);              ///< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System.
+  int32_t               (*PipeDelete)            (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System.
+  int32_t               (*PipeReset)             (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe.
+  int32_t               (*PipeTransfer)          (ARM_USBH_PIPE_HANDLE pipe_hndl, 
+                                                  uint32_t packet,
+                                                  uint8_t *data,
+                                                  uint32_t num);                             ///< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe.
+  uint32_t              (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer.
+  int32_t               (*PipeTransferAbort)     (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer.
+  uint16_t              (*GetFrameNumber)        (void);                                     ///< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number.                    
+} const ARM_DRIVER_USBH;
+
+
+// HCI (OHCI/EHCI)
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void)
+  \brief       Get USB Host HCI (OHCI/EHCI) driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_HCI_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)
+  \brief       Initialize USB Host HCI (OHCI/EHCI) Interface.
+  \param[in]   cb_interrupt Pointer to Interrupt Handler Routine
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Uninitialize (void)
+  \brief       De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host HCI (OHCI/EHCI) Interface Power.
+  \param[in]   state Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_USBH_HCI_Interrupt (void)
+  \brief       USB Host HCI Interrupt Handler.
+  \return      none
+*/
+
+typedef void (*ARM_USBH_HCI_Interrupt_t) (void);  ///< Pointer to Interrupt Handler Routine.
+
+
+/**
+\brief USB Host HCI (OHCI/EHCI) Driver Capabilities.
+*/
+typedef struct _ARM_USBH_HCI_CAPABILITIES {
+  uint32_t port_mask : 15;              ///< Root HUB available Ports Mask
+} ARM_USBH_HCI_CAPABILITIES;
+
+
+/**
+  \brief Access structure of USB Host HCI (OHCI/EHCI) Driver.
+*/
+typedef struct _ARM_DRIVER_USBH_HCI {
+  ARM_DRIVER_VERSION        (*GetVersion)      (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version.
+  ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities.
+  int32_t                   (*Initialize)      (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*Uninitialize)    (void);                                  ///< Pointer to \ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*PowerControl)    (ARM_POWER_STATE state);                 ///< Pointer to \ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power.
+  int32_t                   (*PortVbusOnOff)   (uint8_t port, bool vbus);               ///< Pointer to \ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+} const ARM_DRIVER_USBH_HCI;
+
+#endif /* __DOXYGEN_MW__ */
+
+#endif /* __DRIVER_USBH_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/arm_common_tables.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 00000000..76aadca4
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/arm_const_structs.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 00000000..217f1d50
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/arm_math.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/arm_math.h
new file mode 100644
index 00000000..49e23ee6
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/arm_math.h
@@ -0,0 +1,7544 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        12. March 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvproj
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm0.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm0.h
new file mode 100644
index 00000000..5186cb48
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm0.h
@@ -0,0 +1,711 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm0plus.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 00000000..17e43984
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,822 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm3.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm3.h
new file mode 100644
index 00000000..e1357c67
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1650 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm4.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm4.h
new file mode 100644
index 00000000..bb6be130
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1802 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm7.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm7.h
new file mode 100644
index 00000000..242540f8
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2221 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     01. September 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x07)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x07)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[1];
+  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
+  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
+  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
+  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+       uint32_t RESERVED3[93];
+  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
+       uint32_t RESERVED4[15];
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
+       uint32_t RESERVED5[1];
+  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
+       uint32_t RESERVED6[1];
+  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
+  __O  uint32_t DCIMVAU;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
+  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
+  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
+  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
+  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
+  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
+  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
+       uint32_t RESERVED7[6];
+  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
+  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
+  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
+  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
+  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
+       uint32_t RESERVED8[1];
+  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL << SCB_CTR_IMINLINE_Pos)                /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL << SCB_CCSIDR_LINESIZE_Pos)               /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos                0                                             /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (1UL << SCB_CSSELR_LEVEL_Pos)                    /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL << SCB_CSSELR_IND_Pos)                    /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL << SCB_STIR_INTID_Pos)                /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1FFUL << SCB_ITCMCR_RETEN_Pos)                /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1FFUL << SCB_ITCMCR_RMW_Pos)                  /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1FFUL << SCB_ITCMCR_EN_Pos)                   /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL << SCB_DTCMCR_EN_Pos)                     /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL << SCB_AHBPCR_EN_Pos)                     /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL << SCB_CACR_SIWT_Pos)                     /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL << SCB_AHBPCR_CTL_Pos)                    /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL << SCB_ABFSR_ITCM_Pos)                    /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+       uint32_t RESERVED3[981];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)]            = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]            >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  Cache functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_CacheFunctions Cache Functions
+    \brief      Functions that configure Instruction and Data cache.
+    @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) >> SCB_CCSIDR_LINESIZE_Pos     )
+
+
+/** \brief Enable I-Cache
+
+    The function turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    SCB->CCR |=  SCB_CCR_IC_Msk;            // enable I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable I-Cache
+
+    The function turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~SCB_CCR_IC_Msk;            // disable I-Cache
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+    The function invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Enable D-Cache
+
+    The function turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+    __DSB();
+
+    SCB->CCR |=  SCB_CCR_DC_Msk;            // enable D-Cache
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable D-Cache
+
+    The function turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    SCB->CCR &= ~SCB_CCR_DC_Msk;            // disable D-Cache
+
+    do {                                    // clean & invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+    The function invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Clean D-Cache
+
+    The function cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCSW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+    The function cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean & invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cmFunc.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 00000000..85e36d48
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,638 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+// : "sp" removed from clobber list to avoid gcc 9 warning.
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack));
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cmInstr.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 00000000..d14110b2
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cmSimd.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 00000000..ee58eee5
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_sc000.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_sc000.h
new file mode 100644
index 00000000..5d0219c8
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_sc000.h
@@ -0,0 +1,842 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/Include/core_sc300.h b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_sc300.h
new file mode 100644
index 00000000..b6f6e8b5
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1630 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/README.txt b/uf2-samdx1/lib/cmsis/CMSIS/README.txt
new file mode 100644
index 00000000..e42a5433
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/README.txt
@@ -0,0 +1,42 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011-2014 ARM Limited. All rights reserved.  
+* 
+* Date:        17 February 2014  
+* Revision:    V4.00 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS_END_USER_LICENCE_AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Libraries.
+
+RTOS                    - CMSIS RTOS API template header file.
+
+Driver                  - CMSIS Peripheral Driver Interface.
+
+Pack                    - CMSIS Software Packs.
+                          Mechanism to install software, device support, APIs, and example projects.
+
+SVD                     - CMSIS SVD Schema files and Conversion Utility.
diff --git a/uf2-samdx1/lib/cmsis/CMSIS/index.html b/uf2-samdx1/lib/cmsis/CMSIS/index.html
new file mode 100644
index 00000000..c6da0802
--- /dev/null
+++ b/uf2-samdx1/lib/cmsis/CMSIS/index.html
@@ -0,0 +1,14 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<title>Redirect to the CMSIS main page after 0 seconds</title>
+<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
+<meta name="keywords" content="automatic redirection">
+</head>
+
+<body>
+
+If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
+
+</body>
+</html>
diff --git a/uf2-samdx1/lib/samd21/Atmel.SAMD21_DFP.pdsc b/uf2-samdx1/lib/samd21/Atmel.SAMD21_DFP.pdsc
new file mode 100644
index 00000000..ff477afb
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/Atmel.SAMD21_DFP.pdsc
@@ -0,0 +1,6324 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
+         xmlns:saxon="http://saxon.sf.net//"
+         schemaVersion="1.3"
+         xs:schemaLocation="http://www.atmel.com/schemas/pack-device-atmel-extension PACK.DEVICE.ATMEL.EXTENSION.xsd"
+         xs:noNamespaceSchemaLocation="PACK.xsd">
+   <vendor>Atmel</vendor>
+   <url>http://packs.download.atmel.com/</url>
+   <name>SAMD21_DFP</name>
+   <description>Atmel SAMD21 Series Device Support</description>
+   <releases>
+      <release version="1.2.276" date="2017-02-07">Added ATSAMD21E15CU and ATSAMD21E16CU. Removed warnings for some component headers.</release>
+      <release version="1.1.271">Fixed GNU/IAR assembler issues. Files now under Apache license.</release>
+      <release version="1.0.231">Updated documentation links.</release>
+      <release version="1.0.229">Added ATSAMD21G15L and ATSAMD21G16L.</release>
+      <release version="1.0.222">Initial release.</release>
+   </releases>
+   <keywords>
+      <keyword>Atmel</keyword>
+      <keyword>Device Support</keyword>
+      <keyword>Device Family Package Atmel</keyword>
+      <keyword>SAMD21</keyword>
+   </keywords>
+   <devices>
+      <family Dfamily="SAMD21" Dvendor="Atmel:3">
+         <device Dname="ATSAMD21E15BU">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21b/include/sam.h" define="__SAMD21E15BU__"/>
+            <debug svd="samd21b/svd/ATSAMD21E15BU.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x400"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <algorithm name="samd21b/keil/Flash/ATSAMD21_32.FLM"
+                       start="0x00000000"
+                       size="0x00008000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21b/atdf/ATSAMD21E15BU.atdf"/>
+                  <at:variant ordercode="SAMD21E15B-UU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E15B-UF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x400"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G17A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21G17A__"/>
+            <debug svd="samd21a/svd/ATSAMD21G17A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x20000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x4000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_128.FLM"
+                       start="0x00000000"
+                       size="0x00020000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21G17A.atdf"/>
+                  <at:variant ordercode="SAMD21G17A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G17A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21G17A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G17A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x20000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x4000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 128KB Flash, 16KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G17.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G15A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21G15A__"/>
+            <debug svd="samd21a/svd/ATSAMD21G15A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_32.FLM"
+                       start="0x00000000"
+                       size="0x00008000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21G15A.atdf"/>
+                  <at:variant ordercode="SAMD21G15A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G15A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21G15A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G15A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G15B">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21G15B__"/>
+            <debug svd="samd21c/svd/ATSAMD21G15B.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x400"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <algorithm name="samd21c/keil/Flash/ATSAMD21_32.FLM"
+                       start="0x00000000"
+                       size="0x00008000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21G15B.atdf"/>
+                  <at:variant ordercode="SAMD21G15B-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G15B-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21G15B-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G15B-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x400"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E16L">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21E16L__"/>
+            <debug svd="samd21c/svd/ATSAMD21E16L.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x800"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21E16L.atdf"/>
+                  <at:variant ordercode="SAMD21E16L-MN"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="105"/>
+                  <at:variant ordercode="SAMD21E16L-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21E16L-AN"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="105"/>
+                  <at:variant ordercode="SAMD21E16L-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x800"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G15L">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21G15L__"/>
+            <debug svd="samd21c/svd/ATSAMD21G15L.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x400"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21G15L.atdf"/>
+                  <at:variant ordercode="SAMD21G15L-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G15L-MN"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="105"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x400"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E16B">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21E16B__"/>
+            <debug svd="samd21c/svd/ATSAMD21E16B.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x800"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <algorithm name="samd21c/keil/Flash/ATSAMD21_64.FLM"
+                       start="0x00000000"
+                       size="0x00010000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21E16B.atdf"/>
+                  <at:variant ordercode="SAMD21E16B-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E16B-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21E16B-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E16B-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x800"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E16A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21E16A__"/>
+            <debug svd="samd21a/svd/ATSAMD21E16A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_64.FLM"
+                       start="0x00000000"
+                       size="0x00010000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21E16A.atdf"/>
+                  <at:variant ordercode="SAMD21E16A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E16A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21E16A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E16A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E16BU">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21b/include/sam.h" define="__SAMD21E16BU__"/>
+            <debug svd="samd21b/svd/ATSAMD21E16BU.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x800"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <algorithm name="samd21b/keil/Flash/ATSAMD21_64.FLM"
+                       start="0x00000000"
+                       size="0x00010000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21b/atdf/ATSAMD21E16BU.atdf"/>
+                  <at:variant ordercode="SAMD21E16B-UU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E16B-UF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x800"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21J15B">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21J15B__"/>
+            <debug svd="samd21c/svd/ATSAMD21J15B.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x400"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <algorithm name="samd21c/keil/Flash/ATSAMD21_32.FLM"
+                       start="0x00000000"
+                       size="0x00008000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21J15B.atdf"/>
+                  <at:variant ordercode="SAMD21J15B-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J15B-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21J15B-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J15B-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x400"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, five 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 20-channel 12-bit ADC, 10-bit DAC, 64 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21J15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21J15A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21J15A__"/>
+            <debug svd="samd21a/svd/ATSAMD21J15A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_32.FLM"
+                       start="0x00000000"
+                       size="0x00008000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21J15A.atdf"/>
+                  <at:variant ordercode="SAMD21J15A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J15A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21J15A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J15A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, five 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 20-channel 12-bit ADC, 10-bit DAC, 64 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21J15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G18A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21G18A__"/>
+            <debug svd="samd21a/svd/ATSAMD21G18A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x40000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x8000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_256.FLM"
+                       start="0x00000000"
+                       size="0x00040000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21G18A.atdf"/>
+                  <at:variant ordercode="SAMD21G18A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G18A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21G18A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G18A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x40000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x8000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 256KB Flash, 32KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G18.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G17AU">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21G17AU__"/>
+            <debug svd="samd21a/svd/ATSAMD21G17AU.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x20000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x4000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_128.FLM"
+                       start="0x00000000"
+                       size="0x00020000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21G17AU.atdf"/>
+                  <at:variant ordercode="SAMD21G17A-UU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x20000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x4000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 128KB Flash, 16KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G17.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21J17A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21J17A__"/>
+            <debug svd="samd21a/svd/ATSAMD21J17A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x20000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x4000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_128.FLM"
+                       start="0x00000000"
+                       size="0x00020000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21J17A.atdf"/>
+                  <at:variant ordercode="SAMD21J17A-CU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J17A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J17A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21J17A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J17A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x20000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x4000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 128KB Flash, 16KB SRAM, 48 MHz, five 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 20-channel 12-bit ADC, 10-bit DAC, 64 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21J17.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E15CU">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21E15CU__"/>
+            <debug svd="samd21c/svd/ATSAMD21E15CU.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x400"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21E15CU.atdf"/>
+                  <at:variant ordercode="SAMD21E15C-UU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E15C-UF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x400"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E15B">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21E15B__"/>
+            <debug svd="samd21c/svd/ATSAMD21E15B.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x400"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <algorithm name="samd21c/keil/Flash/ATSAMD21_32.FLM"
+                       start="0x00000000"
+                       size="0x00008000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21E15B.atdf"/>
+                  <at:variant ordercode="SAMD21E15B-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E15B-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21E15B-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E15B-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x400"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E15A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21E15A__"/>
+            <debug svd="samd21a/svd/ATSAMD21E15A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_32.FLM"
+                       start="0x00000000"
+                       size="0x00008000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21E15A.atdf"/>
+                  <at:variant ordercode="SAMD21E15A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E15A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21E15A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E15A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E17A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21E17A__"/>
+            <debug svd="samd21a/svd/ATSAMD21E17A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x20000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x4000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_128.FLM"
+                       start="0x00000000"
+                       size="0x00020000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21E17A.atdf"/>
+                  <at:variant ordercode="SAMD21E17A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E17A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21E17A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E17A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x20000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x4000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 128KB Flash, 16KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E17.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E15L">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21E15L__"/>
+            <debug svd="samd21c/svd/ATSAMD21E15L.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x8000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x400"/>
+            <memory id="IRAM1" start="0x20000000" size="0x1000" default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21E15L.atdf"/>
+                  <at:variant ordercode="SAMD21E15L-MN"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="105"/>
+                  <at:variant ordercode="SAMD21E15L-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21E15L-AN"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="105"/>
+                  <at:variant ordercode="SAMD21E15L-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x8000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x400"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x1000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 32KB Flash, 4KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E15.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G16L">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21G16L__"/>
+            <debug svd="samd21c/svd/ATSAMD21G16L.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x800"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21G16L.atdf"/>
+                  <at:variant ordercode="SAMD21G16L-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G16L-MN"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="105"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x800"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E16CU">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21E16CU__"/>
+            <debug svd="samd21c/svd/ATSAMD21E16CU.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x800"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21E16CU.atdf"/>
+                  <at:variant ordercode="SAMD21E16C-UU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E16C-UF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x800"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G16A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21G16A__"/>
+            <debug svd="samd21a/svd/ATSAMD21G16A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_64.FLM"
+                       start="0x00000000"
+                       size="0x00010000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21G16A.atdf"/>
+                  <at:variant ordercode="SAMD21G16A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G16A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21G16A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G16A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G16B">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21G16B__"/>
+            <debug svd="samd21c/svd/ATSAMD21G16B.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x800"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <algorithm name="samd21c/keil/Flash/ATSAMD21_64.FLM"
+                       start="0x00000000"
+                       size="0x00010000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21G16B.atdf"/>
+                  <at:variant ordercode="SAMD21G16B-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G16B-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21G16B-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21G16B-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x800"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21J16B">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21c/include/sam.h" define="__SAMD21J16B__"/>
+            <debug svd="samd21c/svd/ATSAMD21J16B.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IROM2" start="0x00400000" size="0x800"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <algorithm name="samd21c/keil/Flash/ATSAMD21_64.FLM"
+                       start="0x00000000"
+                       size="0x00010000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21c/atdf/ATSAMD21J16B.atdf"/>
+                  <at:variant ordercode="SAMD21J16B-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J16B-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21J16B-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J16B-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="AUX3"
+                             start="0x0080A000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="RWW"
+                             start="0x00400000"
+                             size="0x800"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, five 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 20-channel 12-bit ADC, 10-bit DAC, 64 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21J16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21G18AU">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21G18AU__"/>
+            <debug svd="samd21a/svd/ATSAMD21G18AU.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x40000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x8000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_256.FLM"
+                       start="0x00000000"
+                       size="0x00040000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21G18AU.atdf"/>
+                  <at:variant ordercode="SAMD21G18A-UU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x40000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x8000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 256KB Flash, 32KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 14-channel 12-bit ADC, 10-bit DAC, 48 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21G18.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21J16A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21J16A__"/>
+            <debug svd="samd21a/svd/ATSAMD21J16A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x10000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x2000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_64.FLM"
+                       start="0x00000000"
+                       size="0x00010000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21J16A.atdf"/>
+                  <at:variant ordercode="SAMD21J16A-CU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J16A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J16A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21J16A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J16A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x10000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x2000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 64KB Flash, 8KB SRAM, 48 MHz, five 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 20-channel 12-bit ADC, 10-bit DAC, 64 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21J16.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21E18A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21E18A__"/>
+            <debug svd="samd21a/svd/ATSAMD21E18A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x40000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x8000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_256.FLM"
+                       start="0x00000000"
+                       size="0x00040000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21E18A.atdf"/>
+                  <at:variant ordercode="SAMD21E18A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E18A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21E18A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21E18A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x40000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x8000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 256KB Flash, 32KB SRAM, 48 MHz, three 16-bit timer/counters, DMA, 4 SERCOMs, USB Host and Device, 10-channel 12-bit ADC, 10-bit DAC, 32 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21E18.aspx"
+                  title="Device Page"/>
+         </device>
+         <device Dname="ATSAMD21J18A">
+            <processor Dcore="Cortex-M0+"
+                       Dendian="Little-endian"
+                       Dmpu="NO_MPU"
+                       Dfpu="NO_FPU"/>
+            <compile header="samd21a/include/sam.h" define="__SAMD21J18A__"/>
+            <debug svd="samd21a/svd/ATSAMD21J18A.svd"/>
+            <memory id="IROM1"
+                    start="0x00000000"
+                    size="0x40000"
+                    default="1"
+                    startup="1"/>
+            <memory id="IRAM1" start="0x20000000" size="0x8000" default="1"/>
+            <algorithm name="samd21a/keil/Flash/ATSAMD21_256.FLM"
+                       start="0x00000000"
+                       size="0x00040000"
+                       default="1"/>
+            <environment name="atmel">
+               <at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension"
+                             schemaVersion="1.0">
+                  <at:atdf name="samd21a/atdf/ATSAMD21J18A.atdf"/>
+                  <at:variant ordercode="SAMD21J18A-CU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J18A-MU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J18A-MF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:variant ordercode="SAMD21J18A-AU"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="85"/>
+                  <at:variant ordercode="SAMD21J18A-AF"
+                              vccmin="1.62"
+                              vccmax="3.63"
+                              tempmin="-40"
+                              tempmax="125"/>
+                  <at:memory name="FLASH"
+                             start="0x00000000"
+                             size="0x40000"
+                             type="flash"
+                             pagesize="64"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="USER_PAGE"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX0"
+                             start="0x00804000"
+                             size="0x100"
+                             type="user_page"
+                             pagesize="64"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="AUX1"
+                             start="0x00806000"
+                             size="0x100"
+                             type="fuses"
+                             pagesize="64"
+                             rw="R"
+                             address-space="base"/>
+                  <at:memory name="HMCRAMC0"
+                             start="0x20000000"
+                             size="0x8000"
+                             type="ram"
+                             rw="RW"
+                             exec="true"
+                             address-space="base"/>
+                  <at:memory name="HPB0"
+                             start="0x40000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB1"
+                             start="0x41000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="HPB2"
+                             start="0x42000000"
+                             size="0x10000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PPB"
+                             start="0xE0000000"
+                             size="0x100000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="SCS"
+                             start="0xE000E000"
+                             size="0x00001000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:memory name="PERIPHERALS"
+                             start="0x40000000"
+                             size="0x20000000"
+                             type="io"
+                             rw="RW"
+                             address-space="base"/>
+                  <at:interface type="swd" name="SWD"/>
+                  <at:tool id="com.atmel.avrdbg.tool.atmelice"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbgc"/>
+                  <at:tool id="com.atmel.avrdbg.tool.edbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
+                  <at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
+                  <at:tool id="com.atmel.avrdbg.tool.medbg"/>
+                  <at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
+                  <at:tool id="com.atmel.avrdbg.tool.samice"/>
+                  <at:project name="Barebone C Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.c)"/>
+                     </at:component>
+                  </at:project>
+                  <at:project name="Barebone Cpp Project">
+                     <at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
+                     <at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
+                        <at:template select="Main file (.cpp)"/>
+                     </at:component>
+                  </at:project>
+                  <at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
+                  <at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
+                  <at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
+               </at:extension>
+            </environment>
+            <description>ARM Cortex-M0+ based microcontroller with 256KB Flash, 32KB SRAM, 48 MHz, five 16-bit timer/counters, DMA, 6 SERCOMs, USB Host and Device, 20-channel 12-bit ADC, 10-bit DAC, 64 pins</description>
+            <book name="http://www.atmel.com/Images/Atmel-42181-SAM-D21_Summary.pdf"
+                  title="Datasheet (Summary)"/>
+            <book name="http://www.atmel.com/devices/ATSAMD21J18.aspx"
+                  title="Device Page"/>
+         </device>
+      </family>
+   </devices>
+   <conditions>
+      <condition id="ARMCC">
+         <accept Tcompiler="ARMCC"/>
+      </condition>
+      <condition id="ARMCC Exe">
+         <accept Tcompiler="ARMCC" Toutput="exe"/>
+      </condition>
+      <condition id="GCC">
+         <accept Tcompiler="GCC"/>
+      </condition>
+      <condition id="GCC Exe">
+         <accept Tcompiler="GCC" Toutput="exe"/>
+      </condition>
+      <condition id="IAR">
+         <accept Tcompiler="IAR"/>
+      </condition>
+      <condition id="IAR Exe">
+         <accept Tcompiler="IAR" Toutput="exe"/>
+      </condition>
+      <condition id="C">
+         <accept Tcompiler="ARMCC"/>
+         <accept Tcompiler="GCC"/>
+         <accept Tcompiler="IAR"/>
+      </condition>
+      <condition id="C Exe">
+         <accept Tcompiler="ARMCC" Toutput="exe"/>
+         <accept Tcompiler="GCC" Toutput="exe"/>
+         <accept Tcompiler="IAR" Toutput="exe"/>
+      </condition>
+      <condition id="C Lib">
+         <accept Tcompiler="ARMCC" Toutput="lib"/>
+         <accept Tcompiler="GCC" Toutput="lib"/>
+         <accept Tcompiler="IAR" Toutput="lib"/>
+      </condition>
+      <condition id="ATSAMD21E15BU">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E15BU"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G17A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G17A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G15A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G15A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G15B">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G15B"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E16L">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E16L"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G15L">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G15L"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E16B">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E16B"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E16A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E16A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E16BU">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E16BU"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21J15B">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21J15B"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21J15A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21J15A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G18A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G18A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G17AU">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G17AU"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21J17A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21J17A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E15CU">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E15CU"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E15B">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E15B"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E15A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E15A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E17A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E17A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E15L">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E15L"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G16L">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G16L"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E16CU">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E16CU"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G16A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G16A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G16B">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G16B"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21J16B">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21J16B"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21G18AU">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21G18AU"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21J16A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21J16A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21E18A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21E18A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+      <condition id="ATSAMD21J18A">
+         <require Dvendor="Atmel:3" Dname="ATSAMD21J18A"/>
+         <require Cclass="CMSIS" Cgroup="CORE"/>
+      </condition>
+   </conditions>
+   <components>
+      <component Cvendor="Atmel"
+                 Cclass="Device"
+                 Cgroup="Startup"
+                 Cversion="1.2.0"
+                 condition="ATSAMD21E15BU">
+         <description>Headers and startup code for Atmel ATSAMD21E15BU</description>
+         <files>
+            <file condition="C" category="include" name="samd21b/include"/>
+            <file condition="C" category="header" name="samd21b/include/sam.h"/>
+            <file condition="C Exe"
+                  category="source"
+                  name="samd21b/templates/main.c"
+                  attr="template"
+                  select="Main file (.c)"/>
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+                  name="samd21b/templates/main.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
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+                  name="samd21b/templates/library.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
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+                  category="source"
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+                  attr="config"/>
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+                  name="samd21b/gcc/gcc/startup_samd21.c"
+                  attr="config"/>
+            <file condition="GCC Exe"
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+                  name="samd21b/gcc/gcc/samd21e15bu_flash.ld"
+                  attr="config"/>
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+            <file condition="IAR Exe"
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+            <file condition="IAR Exe"
+                  category="other"
+                  name="samd21b/iar/iar/samd21e15bu_sram.icf"
+                  attr="config"/>
+         </files>
+      </component>
+      <component Cvendor="Atmel"
+                 Cclass="Device"
+                 Cgroup="Startup"
+                 Cversion="1.2.0"
+                 condition="ATSAMD21G17A">
+         <description>Headers and startup code for Atmel ATSAMD21G17A</description>
+         <files>
+            <file condition="C" category="include" name="samd21a/include"/>
+            <file condition="C" category="header" name="samd21a/include/sam.h"/>
+            <file condition="C Exe"
+                  category="source"
+                  name="samd21a/templates/main.c"
+                  attr="template"
+                  select="Main file (.c)"/>
+            <file condition="C Exe"
+                  category="source"
+                  name="samd21a/templates/main.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
+            <file condition="C Lib"
+                  category="source"
+                  name="samd21a/templates/library.c"
+                  attr="template"
+                  select="Main file (.c)"/>
+            <file condition="C Lib"
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+                  name="samd21a/templates/library.cpp"
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+                  attr="config"/>
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+                  attr="config"/>
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+                  attr="config"/>
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+                  attr="config"/>
+            <file condition="IAR Exe"
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+            <file condition="IAR Exe"
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+            <file condition="IAR Exe"
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+                  name="samd21a/iar/iar/samd21g17a_sram.icf"
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+         </files>
+      </component>
+      <component Cvendor="Atmel"
+                 Cclass="Device"
+                 Cgroup="Startup"
+                 Cversion="1.2.0"
+                 condition="ATSAMD21G15A">
+         <description>Headers and startup code for Atmel ATSAMD21G15A</description>
+         <files>
+            <file condition="C" category="include" name="samd21a/include"/>
+            <file condition="C" category="header" name="samd21a/include/sam.h"/>
+            <file condition="C Exe"
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+                  name="samd21a/templates/main.c"
+                  attr="template"
+                  select="Main file (.c)"/>
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+                  category="source"
+                  name="samd21a/templates/main.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
+            <file condition="C Lib"
+                  category="source"
+                  name="samd21a/templates/library.c"
+                  attr="template"
+                  select="Main file (.c)"/>
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+                  name="samd21a/templates/library.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
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+                  name="samd21a/gcc/system_samd21.c"
+                  attr="config"/>
+            <file condition="GCC Exe"
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+                  name="samd21a/gcc/gcc/startup_samd21.c"
+                  attr="config"/>
+            <file condition="GCC Exe"
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+                  attr="config"/>
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+            <file condition="ARMCC Exe"
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+                  name="samd21a/armcc/Device/SAMD21/Source/system_samd21.c"
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+                  category="source"
+                  name="samd21a/iar/system_samd21.c"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="source"
+                  name="samd21a/iar/iar/startup_samd21.c"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="linkerScript"
+                  name="samd21a/iar/iar/samd21g15a_flash.icf"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="other"
+                  name="samd21a/iar/iar/samd21g15a_sram.icf"
+                  attr="config"/>
+         </files>
+      </component>
+      <component Cvendor="Atmel"
+                 Cclass="Device"
+                 Cgroup="Startup"
+                 Cversion="1.2.0"
+                 condition="ATSAMD21G15B">
+         <description>Headers and startup code for Atmel ATSAMD21G15B</description>
+         <files>
+            <file condition="C" category="include" name="samd21c/include"/>
+            <file condition="C" category="header" name="samd21c/include/sam.h"/>
+            <file condition="C Exe"
+                  category="source"
+                  name="samd21c/templates/main.c"
+                  attr="template"
+                  select="Main file (.c)"/>
+            <file condition="C Exe"
+                  category="source"
+                  name="samd21c/templates/main.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
+            <file condition="C Lib"
+                  category="source"
+                  name="samd21c/templates/library.c"
+                  attr="template"
+                  select="Main file (.c)"/>
+            <file condition="C Lib"
+                  category="source"
+                  name="samd21c/templates/library.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
+            <file condition="GCC Exe"
+                  category="source"
+                  name="samd21c/gcc/system_samd21.c"
+                  attr="config"/>
+            <file condition="GCC Exe"
+                  category="source"
+                  name="samd21c/gcc/gcc/startup_samd21.c"
+                  attr="config"/>
+            <file condition="GCC Exe"
+                  category="linkerScript"
+                  name="samd21c/gcc/gcc/samd21g15b_flash.ld"
+                  attr="config"/>
+            <file condition="GCC Exe"
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+                  name="samd21c/gcc/gcc/samd21g15b_sram.ld"
+                  attr="config"/>
+            <file condition="ARMCC Exe"
+                  category="source"
+                  name="samd21c/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s"
+                  attr="config"/>
+            <file condition="ARMCC Exe"
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+                  category="source"
+                  name="samd21c/iar/system_samd21.c"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="source"
+                  name="samd21c/iar/iar/startup_samd21.c"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="linkerScript"
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+            <file condition="IAR Exe"
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+                  name="samd21c/iar/iar/samd21g15b_sram.icf"
+                  attr="config"/>
+         </files>
+      </component>
+      <component Cvendor="Atmel"
+                 Cclass="Device"
+                 Cgroup="Startup"
+                 Cversion="1.2.0"
+                 condition="ATSAMD21E16L">
+         <description>Headers and startup code for Atmel ATSAMD21E16L</description>
+         <files>
+            <file condition="C" category="include" name="samd21c/include"/>
+            <file condition="C" category="header" name="samd21c/include/sam.h"/>
+            <file condition="C Exe"
+                  category="source"
+                  name="samd21c/templates/main.c"
+                  attr="template"
+                  select="Main file (.c)"/>
+            <file condition="C Exe"
+                  category="source"
+                  name="samd21c/templates/main.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
+            <file condition="C Lib"
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+                  name="samd21c/templates/library.c"
+                  attr="template"
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+                  select="Main file (.cpp)"/>
+            <file condition="GCC Exe"
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+                  attr="config"/>
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+                  name="samd21c/gcc/gcc/startup_samd21.c"
+                  attr="config"/>
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+                  attr="config"/>
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+      </component>
+      <component Cvendor="Atmel"
+                 Cclass="Device"
+                 Cgroup="Startup"
+                 Cversion="1.2.0"
+                 condition="ATSAMD21G15L">
+         <description>Headers and startup code for Atmel ATSAMD21G15L</description>
+         <files>
+            <file condition="C" category="include" name="samd21c/include"/>
+            <file condition="C" category="header" name="samd21c/include/sam.h"/>
+            <file condition="C Exe"
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+                  name="samd21c/templates/main.c"
+                  attr="template"
+                  select="Main file (.c)"/>
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+                  category="source"
+                  name="samd21c/templates/main.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
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+                  attr="template"
+                  select="Main file (.c)"/>
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+                  name="samd21c/templates/library.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
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+                  attr="config"/>
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+                  attr="config"/>
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+      </component>
+      <component Cvendor="Atmel"
+                 Cclass="Device"
+                 Cgroup="Startup"
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+                 condition="ATSAMD21E16B">
+         <description>Headers and startup code for Atmel ATSAMD21E16B</description>
+         <files>
+            <file condition="C" category="include" name="samd21c/include"/>
+            <file condition="C" category="header" name="samd21c/include/sam.h"/>
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+      <component Cvendor="Atmel"
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+         <description>Headers and startup code for Atmel ATSAMD21E16A</description>
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+      <component Cvendor="Atmel"
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+            <file condition="IAR Exe"
+                  category="source"
+                  name="samd21a/iar/iar/startup_samd21.c"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="linkerScript"
+                  name="samd21a/iar/iar/samd21e18a_flash.icf"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="other"
+                  name="samd21a/iar/iar/samd21e18a_sram.icf"
+                  attr="config"/>
+         </files>
+      </component>
+      <component Cvendor="Atmel"
+                 Cclass="Device"
+                 Cgroup="Startup"
+                 Cversion="1.2.0"
+                 condition="ATSAMD21J18A">
+         <description>Headers and startup code for Atmel ATSAMD21J18A</description>
+         <files>
+            <file condition="C" category="include" name="samd21a/include"/>
+            <file condition="C" category="header" name="samd21a/include/sam.h"/>
+            <file condition="C Exe"
+                  category="source"
+                  name="samd21a/templates/main.c"
+                  attr="template"
+                  select="Main file (.c)"/>
+            <file condition="C Exe"
+                  category="source"
+                  name="samd21a/templates/main.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
+            <file condition="C Lib"
+                  category="source"
+                  name="samd21a/templates/library.c"
+                  attr="template"
+                  select="Main file (.c)"/>
+            <file condition="C Lib"
+                  category="source"
+                  name="samd21a/templates/library.cpp"
+                  attr="template"
+                  select="Main file (.cpp)"/>
+            <file condition="GCC Exe"
+                  category="source"
+                  name="samd21a/gcc/system_samd21.c"
+                  attr="config"/>
+            <file condition="GCC Exe"
+                  category="source"
+                  name="samd21a/gcc/gcc/startup_samd21.c"
+                  attr="config"/>
+            <file condition="GCC Exe"
+                  category="linkerScript"
+                  name="samd21a/gcc/gcc/samd21j18a_flash.ld"
+                  attr="config"/>
+            <file condition="GCC Exe"
+                  category="other"
+                  name="samd21a/gcc/gcc/samd21j18a_sram.ld"
+                  attr="config"/>
+            <file condition="ARMCC Exe"
+                  category="source"
+                  name="samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s"
+                  attr="config"/>
+            <file condition="ARMCC Exe"
+                  category="source"
+                  name="samd21a/armcc/Device/SAMD21/Source/system_samd21.c"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="source"
+                  name="samd21a/iar/system_samd21.c"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="source"
+                  name="samd21a/iar/iar/startup_samd21.c"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="linkerScript"
+                  name="samd21a/iar/iar/samd21j18a_flash.icf"
+                  attr="config"/>
+            <file condition="IAR Exe"
+                  category="other"
+                  name="samd21a/iar/iar/samd21j18a_sram.icf"
+                  attr="config"/>
+         </files>
+      </component>
+   </components>
+</package>
diff --git a/uf2-samdx1/lib/samd21/package.content b/uf2-samdx1/lib/samd21/package.content
new file mode 100644
index 00000000..1ea04215
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/package.content
@@ -0,0 +1,1722 @@
+<?xml version='1.0' encoding='ASCII'?>
+<package schemaVersion="1.0">
+  <content>
+    <fileset id="moduleheaders">
+      <includes pattern="component/*"/>
+      <includes pattern="instance/*"/>
+    </fileset>
+    <resources target="ATSAMD21E15BU">
+      <resource type="atdf" subdir="samd21b/atdf">
+        <includes pattern="ATSAMD21E15BU.atdf"/>
+      </resource>
+      <resource type="svd" subdir="samd21b/svd">
+        <includes pattern="ATSAMD21E15BU.svd"/>
+      </resource>
+      <resource type="c.header" subdir="samd21b/include">
+        <includes pattern="sam.h"/>
+        <includes pattern="samd21.h"/>
+        <includes pattern="samd21e15bu.h"/>
+        <includes pattern="system_samd21.h"/>
+        <includes pattern="pio/*samd21e15bu.h"/>
+        <includes pattern="component-version.h"/>
+        <includes fileset="moduleheaders"/>
+        <meta key="define" value="__SAMD21E15BU__"/>
+      </resource>
+      <resource type="c.source.exe.template" subdir="samd21b/templates">
+        <includes pattern="main.c"/>
+      </resource>
+      <resource type="c.source.lib.template" subdir="samd21b/templates">
+        <includes pattern="library.c"/>
+      </resource>
+      <resource type="cpp.source.exe.template" subdir="samd21b/templates">
+        <includes pattern="main.cpp"/>
+      </resource>
+      <resource type="cpp.source.lib.template" subdir="samd21b/templates">
+        <includes pattern="library.cpp"/>
+      </resource>
+      <resource type="armcc.source.startup" subdir="samd21b/armcc">
+        <includes pattern="Device/SAMD21/Source/ARM/startup_SAMD21.s"/>
+        <includes pattern="Device/SAMD21/Source/system_samd21.c"/>
+      </resource>
+      <resource type="keil.flashloader" subdir="samd21b/keil">
+        <includes pattern="Flash/ATSAMD21_32.FLM"/>
+        <meta key="Flash/ATSAMD21_32.FLM" value="start=0x00000000|size=0x00008000|default=1"/>
+      </resource>
+      <resource type="gcc.source.startup" subdir="samd21b/gcc">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="gcc/startup_samd21.c"/>
+      </resource>
+      <resource type="gcc.linker" subdir="samd21b/gcc">
+        <includes pattern="gcc/samd21e15bu_flash.ld"/>
+        <includes pattern="gcc/samd21e15bu_sram.ld"/>
+      </resource>
+      <resource type="iar.source.startup" subdir="samd21b/iar">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="iar/startup_samd21.c"/>
+      </resource>
+      <resource type="iar.linker" subdir="samd21b/iar">
+        <includes pattern="iar/samd21e15bu_flash.icf"/>
+        <includes pattern="iar/samd21e15bu_sram.icf"/>
+      </resource>
+      <resource type="iar.config" subdir="samd21b/iar">
+        <includes pattern="config/devices/Atmel/**/ATSAMD21E15BU.i79"/>
+        <includes pattern="config/devices/Atmel/**/ATSAMD21E15BU.menu"/>
+        <includes pattern="config/flashloader/Atmel/samd21e15bu/samd21e15bu-flash.board"/>
+        <includes pattern="config/flashloader/Atmel/samd21e15bu/samd21e15bu-flash.flash"/>
+        <includes pattern="config/flashloader/Atmel/samd21e15bu/samd21e15bu-flash.out"/>
+        <includes optional="true" pattern="config/debugger/Atmel/Trace_SAMD21.dmac"/>
+        <includes optional="true" pattern="config/debugger/Atmel/ATSAMD21E15BU.ddf"/>
+      </resource>
+    </resources>
+    <resources target="ATSAMD21G17A">
+      <resource type="atdf" subdir="samd21a/atdf">
+        <includes pattern="ATSAMD21G17A.atdf"/>
+      </resource>
+      <resource type="svd" subdir="samd21a/svd">
+        <includes pattern="ATSAMD21G17A.svd"/>
+      </resource>
+      <resource type="c.header" subdir="samd21a/include">
+        <includes pattern="sam.h"/>
+        <includes pattern="samd21.h"/>
+        <includes pattern="samd21g17a.h"/>
+        <includes pattern="system_samd21.h"/>
+        <includes pattern="pio/*samd21g17a.h"/>
+        <includes pattern="component-version.h"/>
+        <includes fileset="moduleheaders"/>
+        <meta key="define" value="__SAMD21G17A__"/>
+      </resource>
+      <resource type="c.source.exe.template" subdir="samd21a/templates">
+        <includes pattern="main.c"/>
+      </resource>
+      <resource type="c.source.lib.template" subdir="samd21a/templates">
+        <includes pattern="library.c"/>
+      </resource>
+      <resource type="cpp.source.exe.template" subdir="samd21a/templates">
+        <includes pattern="main.cpp"/>
+      </resource>
+      <resource type="cpp.source.lib.template" subdir="samd21a/templates">
+        <includes pattern="library.cpp"/>
+      </resource>
+      <resource type="armcc.source.startup" subdir="samd21a/armcc">
+        <includes pattern="Device/SAMD21/Source/ARM/startup_SAMD21.s"/>
+        <includes pattern="Device/SAMD21/Source/system_samd21.c"/>
+      </resource>
+      <resource type="keil.flashloader" subdir="samd21a/keil">
+        <includes pattern="Flash/ATSAMD21_128.FLM"/>
+        <meta key="Flash/ATSAMD21_128.FLM" value="start=0x00000000|size=0x00020000|default=1"/>
+      </resource>
+      <resource type="gcc.source.startup" subdir="samd21a/gcc">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="gcc/startup_samd21.c"/>
+      </resource>
+      <resource type="gcc.linker" subdir="samd21a/gcc">
+        <includes pattern="gcc/samd21g17a_flash.ld"/>
+        <includes pattern="gcc/samd21g17a_sram.ld"/>
+      </resource>
+      <resource type="iar.source.startup" subdir="samd21a/iar">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="iar/startup_samd21.c"/>
+      </resource>
+      <resource type="iar.linker" subdir="samd21a/iar">
+        <includes pattern="iar/samd21g17a_flash.icf"/>
+        <includes pattern="iar/samd21g17a_sram.icf"/>
+      </resource>
+      <resource type="iar.config" subdir="samd21a/iar">
+        <includes pattern="config/devices/Atmel/**/ATSAMD21G17A.i79"/>
+        <includes pattern="config/devices/Atmel/**/ATSAMD21G17A.menu"/>
+        <includes pattern="config/flashloader/Atmel/samd21g17a/samd21g17a-flash.board"/>
+        <includes pattern="config/flashloader/Atmel/samd21g17a/samd21g17a-flash.flash"/>
+        <includes pattern="config/flashloader/Atmel/samd21g17a/samd21g17a-flash.out"/>
+        <includes optional="true" pattern="config/debugger/Atmel/Trace_SAMD21.dmac"/>
+        <includes optional="true" pattern="config/debugger/Atmel/ATSAMD21G17A.ddf"/>
+      </resource>
+    </resources>
+    <resources target="ATSAMD21G15A">
+      <resource type="atdf" subdir="samd21a/atdf">
+        <includes pattern="ATSAMD21G15A.atdf"/>
+      </resource>
+      <resource type="svd" subdir="samd21a/svd">
+        <includes pattern="ATSAMD21G15A.svd"/>
+      </resource>
+      <resource type="c.header" subdir="samd21a/include">
+        <includes pattern="sam.h"/>
+        <includes pattern="samd21.h"/>
+        <includes pattern="samd21g15a.h"/>
+        <includes pattern="system_samd21.h"/>
+        <includes pattern="pio/*samd21g15a.h"/>
+        <includes pattern="component-version.h"/>
+        <includes fileset="moduleheaders"/>
+        <meta key="define" value="__SAMD21G15A__"/>
+      </resource>
+      <resource type="c.source.exe.template" subdir="samd21a/templates">
+        <includes pattern="main.c"/>
+      </resource>
+      <resource type="c.source.lib.template" subdir="samd21a/templates">
+        <includes pattern="library.c"/>
+      </resource>
+      <resource type="cpp.source.exe.template" subdir="samd21a/templates">
+        <includes pattern="main.cpp"/>
+      </resource>
+      <resource type="cpp.source.lib.template" subdir="samd21a/templates">
+        <includes pattern="library.cpp"/>
+      </resource>
+      <resource type="armcc.source.startup" subdir="samd21a/armcc">
+        <includes pattern="Device/SAMD21/Source/ARM/startup_SAMD21.s"/>
+        <includes pattern="Device/SAMD21/Source/system_samd21.c"/>
+      </resource>
+      <resource type="keil.flashloader" subdir="samd21a/keil">
+        <includes pattern="Flash/ATSAMD21_32.FLM"/>
+        <meta key="Flash/ATSAMD21_32.FLM" value="start=0x00000000|size=0x00008000|default=1"/>
+      </resource>
+      <resource type="gcc.source.startup" subdir="samd21a/gcc">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="gcc/startup_samd21.c"/>
+      </resource>
+      <resource type="gcc.linker" subdir="samd21a/gcc">
+        <includes pattern="gcc/samd21g15a_flash.ld"/>
+        <includes pattern="gcc/samd21g15a_sram.ld"/>
+      </resource>
+      <resource type="iar.source.startup" subdir="samd21a/iar">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="iar/startup_samd21.c"/>
+      </resource>
+      <resource type="iar.linker" subdir="samd21a/iar">
+        <includes pattern="iar/samd21g15a_flash.icf"/>
+        <includes pattern="iar/samd21g15a_sram.icf"/>
+      </resource>
+      <resource type="iar.config" subdir="samd21a/iar">
+        <includes pattern="config/devices/Atmel/**/ATSAMD21G15A.i79"/>
+        <includes pattern="config/devices/Atmel/**/ATSAMD21G15A.menu"/>
+        <includes pattern="config/flashloader/Atmel/samd21g15a/samd21g15a-flash.board"/>
+        <includes pattern="config/flashloader/Atmel/samd21g15a/samd21g15a-flash.flash"/>
+        <includes pattern="config/flashloader/Atmel/samd21g15a/samd21g15a-flash.out"/>
+        <includes optional="true" pattern="config/debugger/Atmel/Trace_SAMD21.dmac"/>
+        <includes optional="true" pattern="config/debugger/Atmel/ATSAMD21G15A.ddf"/>
+      </resource>
+    </resources>
+    <resources target="ATSAMD21G15B">
+      <resource type="atdf" subdir="samd21c/atdf">
+        <includes pattern="ATSAMD21G15B.atdf"/>
+      </resource>
+      <resource type="svd" subdir="samd21c/svd">
+        <includes pattern="ATSAMD21G15B.svd"/>
+      </resource>
+      <resource type="c.header" subdir="samd21c/include">
+        <includes pattern="sam.h"/>
+        <includes pattern="samd21.h"/>
+        <includes pattern="samd21g15b.h"/>
+        <includes pattern="system_samd21.h"/>
+        <includes pattern="pio/*samd21g15b.h"/>
+        <includes pattern="component-version.h"/>
+        <includes fileset="moduleheaders"/>
+        <meta key="define" value="__SAMD21G15B__"/>
+      </resource>
+      <resource type="c.source.exe.template" subdir="samd21c/templates">
+        <includes pattern="main.c"/>
+      </resource>
+      <resource type="c.source.lib.template" subdir="samd21c/templates">
+        <includes pattern="library.c"/>
+      </resource>
+      <resource type="cpp.source.exe.template" subdir="samd21c/templates">
+        <includes pattern="main.cpp"/>
+      </resource>
+      <resource type="cpp.source.lib.template" subdir="samd21c/templates">
+        <includes pattern="library.cpp"/>
+      </resource>
+      <resource type="armcc.source.startup" subdir="samd21c/armcc">
+        <includes pattern="Device/SAMD21/Source/ARM/startup_SAMD21.s"/>
+        <includes pattern="Device/SAMD21/Source/system_samd21.c"/>
+      </resource>
+      <resource type="keil.flashloader" subdir="samd21c/keil">
+        <includes pattern="Flash/ATSAMD21_32.FLM"/>
+        <meta key="Flash/ATSAMD21_32.FLM" value="start=0x00000000|size=0x00008000|default=1"/>
+      </resource>
+      <resource type="gcc.source.startup" subdir="samd21c/gcc">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="gcc/startup_samd21.c"/>
+      </resource>
+      <resource type="gcc.linker" subdir="samd21c/gcc">
+        <includes pattern="gcc/samd21g15b_flash.ld"/>
+        <includes pattern="gcc/samd21g15b_sram.ld"/>
+      </resource>
+      <resource type="iar.source.startup" subdir="samd21c/iar">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="iar/startup_samd21.c"/>
+      </resource>
+      <resource type="iar.linker" subdir="samd21c/iar">
+        <includes pattern="iar/samd21g15b_flash.icf"/>
+        <includes pattern="iar/samd21g15b_sram.icf"/>
+      </resource>
+      <resource type="iar.config" subdir="samd21c/iar">
+        <includes pattern="config/devices/Atmel/**/ATSAMD21G15B.i79"/>
+        <includes pattern="config/devices/Atmel/**/ATSAMD21G15B.menu"/>
+        <includes pattern="config/flashloader/Atmel/samd21g15b/samd21g15b-flash.board"/>
+        <includes pattern="config/flashloader/Atmel/samd21g15b/samd21g15b-flash.flash"/>
+        <includes pattern="config/flashloader/Atmel/samd21g15b/samd21g15b-flash.out"/>
+        <includes optional="true" pattern="config/debugger/Atmel/ATSAMD21G15B.ddf"/>
+      </resource>
+    </resources>
+    <resources target="ATSAMD21E16L">
+      <resource type="atdf" subdir="samd21c/atdf">
+        <includes pattern="ATSAMD21E16L.atdf"/>
+      </resource>
+      <resource type="svd" subdir="samd21c/svd">
+        <includes pattern="ATSAMD21E16L.svd"/>
+      </resource>
+      <resource type="c.header" subdir="samd21c/include">
+        <includes pattern="sam.h"/>
+        <includes pattern="samd21.h"/>
+        <includes pattern="samd21e16l.h"/>
+        <includes pattern="system_samd21.h"/>
+        <includes pattern="pio/*samd21e16l.h"/>
+        <includes pattern="component-version.h"/>
+        <includes fileset="moduleheaders"/>
+        <meta key="define" value="__SAMD21E16L__"/>
+      </resource>
+      <resource type="c.source.exe.template" subdir="samd21c/templates">
+        <includes pattern="main.c"/>
+      </resource>
+      <resource type="c.source.lib.template" subdir="samd21c/templates">
+        <includes pattern="library.c"/>
+      </resource>
+      <resource type="cpp.source.exe.template" subdir="samd21c/templates">
+        <includes pattern="main.cpp"/>
+      </resource>
+      <resource type="cpp.source.lib.template" subdir="samd21c/templates">
+        <includes pattern="library.cpp"/>
+      </resource>
+      <resource type="gcc.source.startup" subdir="samd21c/gcc">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="gcc/startup_samd21.c"/>
+      </resource>
+      <resource type="gcc.linker" subdir="samd21c/gcc">
+        <includes pattern="gcc/samd21e16l_flash.ld"/>
+        <includes pattern="gcc/samd21e16l_sram.ld"/>
+      </resource>
+      <resource type="iar.source.startup" subdir="samd21c/iar">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="iar/startup_samd21.c"/>
+      </resource>
+      <resource type="iar.linker" subdir="samd21c/iar">
+        <includes pattern="iar/samd21e16l_flash.icf"/>
+        <includes pattern="iar/samd21e16l_sram.icf"/>
+      </resource>
+      <resource type="iar.config" subdir="samd21c/iar">
+        <includes pattern="config/devices/Atmel/**/ATSAMD21E16L.i79"/>
+        <includes pattern="config/devices/Atmel/**/ATSAMD21E16L.menu"/>
+        <includes pattern="config/flashloader/Atmel/samd21e16l/samd21e16l-flash.board"/>
+        <includes pattern="config/flashloader/Atmel/samd21e16l/samd21e16l-flash.flash"/>
+        <includes pattern="config/flashloader/Atmel/samd21e16l/samd21e16l-flash.out"/>
+        <includes optional="true" pattern="config/debugger/Atmel/ATSAMD21E16L.ddf"/>
+      </resource>
+    </resources>
+    <resources target="ATSAMD21G15L">
+      <resource type="atdf" subdir="samd21c/atdf">
+        <includes pattern="ATSAMD21G15L.atdf"/>
+      </resource>
+      <resource type="svd" subdir="samd21c/svd">
+        <includes pattern="ATSAMD21G15L.svd"/>
+      </resource>
+      <resource type="c.header" subdir="samd21c/include">
+        <includes pattern="sam.h"/>
+        <includes pattern="samd21.h"/>
+        <includes pattern="samd21g15l.h"/>
+        <includes pattern="system_samd21.h"/>
+        <includes pattern="pio/*samd21g15l.h"/>
+        <includes pattern="component-version.h"/>
+        <includes fileset="moduleheaders"/>
+        <meta key="define" value="__SAMD21G15L__"/>
+      </resource>
+      <resource type="c.source.exe.template" subdir="samd21c/templates">
+        <includes pattern="main.c"/>
+      </resource>
+      <resource type="c.source.lib.template" subdir="samd21c/templates">
+        <includes pattern="library.c"/>
+      </resource>
+      <resource type="cpp.source.exe.template" subdir="samd21c/templates">
+        <includes pattern="main.cpp"/>
+      </resource>
+      <resource type="cpp.source.lib.template" subdir="samd21c/templates">
+        <includes pattern="library.cpp"/>
+      </resource>
+      <resource type="gcc.source.startup" subdir="samd21c/gcc">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="gcc/startup_samd21.c"/>
+      </resource>
+      <resource type="gcc.linker" subdir="samd21c/gcc">
+        <includes pattern="gcc/samd21g15l_flash.ld"/>
+        <includes pattern="gcc/samd21g15l_sram.ld"/>
+      </resource>
+      <resource type="iar.source.startup" subdir="samd21c/iar">
+        <includes pattern="system_samd21.c"/>
+        <includes pattern="iar/startup_samd21.c"/>
+      </resource>
+      <resource type="iar.linker" subdir="samd21c/iar">
+        <includes pattern="iar/samd21g15l_flash.icf"/>
+        <includes pattern="iar/samd21g15l_sram.icf"/>
+      </resource>
+      <resource type="iar.config" subdir="samd21c/iar">
+        <includes pattern="config/devices/Atmel/**/ATSAMD21G15L.i79"/>
+        <includes pattern="config/devices/Atmel/**/ATSAMD21G15L.menu"/>
+        <includes pattern="config/flashloader/Atmel/samd21g15l/samd21g15l-flash.board"/>
+        <includes pattern="config/flashloader/Atmel/samd21g15l/samd21g15l-flash.flash"/>
+        <includes pattern="config/flashloader/Atmel/samd21g15l/samd21g15l-flash.out"/>
+        <includes optional="true" pattern="config/debugger/Atmel/ATSAMD21G15L.ddf"/>
+      </resource>
+    </resources>
+    <resources target="ATSAMD21E16B">
+      <resource type="atdf" subdir="samd21c/atdf">
+        <includes pattern="ATSAMD21E16B.atdf"/>
+      </resource>
+      <resource type="svd" subdir="samd21c/svd">
+        <includes pattern="ATSAMD21E16B.svd"/>
+      </resource>
+      <resource type="c.header" subdir="samd21c/include">
+        <includes pattern="sam.h"/>
+        <includes pattern="samd21.h"/>
+        <includes pattern="samd21e16b.h"/>
+        <includes pattern="system_samd21.h"/>
+        <includes pattern="pio/*samd21e16b.h"/>
+        <includes pattern="component-version.h"/>
+        <includes fileset="moduleheaders"/>
+        <meta key="define" value="__SAMD21E16B__"/>
+      </resource>
+      <resource type="c.source.exe.template" subdir="samd21c/templates">
+        <includes pattern="main.c"/>
+      </resource>
+      <resource type="c.source.lib.template" subdir="samd21c/templates">
+        <includes pattern="library.c"/>
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+        <includes optional="true" pattern="config/debugger/Atmel/Trace_SAMD21.dmac"/>
+        <includes optional="true" pattern="config/debugger/Atmel/ATSAMD21J18A.ddf"/>
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+    </resources>
+  </content>
+  <pdsc xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+		<releases>
+			<release version="1.2.BUILDNUMBER">Added ATSAMD21E15CU and ATSAMD21E16CU. Removed warnings for some component headers.</release>
+			<release version="1.1.271">Fixed GNU/IAR assembler issues. Files now under Apache license.</release>
+			<release version="1.0.231">Updated documentation links.</release>
+			<release version="1.0.229">Added ATSAMD21G15L and ATSAMD21G16L.</release>
+			<release version="1.0.222">Initial release.</release>
+		</releases>
+	</pdsc>
+</package>
diff --git a/uf2-samdx1/lib/samd21/samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s b/uf2-samdx1/lib/samd21/samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s
new file mode 100644
index 00000000..96ef2cdb
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s
@@ -0,0 +1,247 @@
+;/*****************************************************************************
+; * @file     startup_SAMD21.s
+; * @brief    CMSIS Cortex-M0+ Core Device Startup File for
+; *           Atmel SAMD21 Device Series
+; * @version  V1.01
+; * @date     25. March 2015
+; *
+; * @note
+; * Copyright (C) 2014 - 2015 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     PM_Handler                ;  0 Power Manager
+                DCD     SYSCTRL_Handler           ;  1 System Control
+                DCD     WDT_Handler               ;  2 Watchdog Timer
+                DCD     RTC_Handler               ;  3 Real-Time Counter
+                DCD     EIC_Handler               ;  4 External Interrupt Controller
+                DCD     NVMCTRL_Handler           ;  5 Non-Volatile Memory Controller
+                DCD     DMAC_Handler              ;  6 Direct Memory Access Controller
+                DCD     USB_Handler               ;  7 Universal Serial Bus
+                DCD     EVSYS_Handler             ;  8 Event System Interface
+                DCD     SERCOM0_Handler           ;  9 Serial Communication Interface 0
+                DCD     SERCOM1_Handler           ; 10 Serial Communication Interface 1
+                DCD     SERCOM2_Handler           ; 11 Serial Communication Interface 2
+                DCD     SERCOM3_Handler           ; 12 Serial Communication Interface 3
+                DCD     SERCOM4_Handler           ; 13 Serial Communication Interface 4
+                DCD     SERCOM5_Handler           ; 14 Serial Communication Interface 5
+                DCD     TCC0_Handler              ; 15 Timer Counter Control 0
+                DCD     TCC1_Handler              ; 16 Timer Counter Control 1
+                DCD     TCC2_Handler              ; 17 Timer Counter Control 2
+                DCD     TC3_Handler               ; 18 Basic Timer Counter 0
+                DCD     TC4_Handler               ; 19 Basic Timer Counter 1
+                DCD     TC5_Handler               ; 20 Basic Timer Counter 2
+                DCD     TC6_Handler               ; 21 Basic Timer Counter 3
+                DCD     TC7_Handler               ; 22 Basic Timer Counter 4
+                DCD     ADC_Handler               ; 23 Analog Digital Converter
+                DCD     AC_Handler                ; 24 Analog Comparators
+                DCD     DAC_Handler               ; 25 Digital Analog Converter
+                DCD     PTC_Handler               ; 26 Peripheral Touch Controller
+                DCD     I2S_Handler               ; 27 Inter-IC Sound Interface
+                DCD     AC1_Handler               ; 28 Analog Comparators 1
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  PM_Handler                [WEAK]
+                EXPORT  PM_Handler                [WEAK]
+                EXPORT  SYSCTRL_Handler           [WEAK]
+                EXPORT  WDT_Handler               [WEAK]
+                EXPORT  RTC_Handler               [WEAK]
+                EXPORT  EIC_Handler               [WEAK]
+                EXPORT  NVMCTRL_Handler           [WEAK]
+                EXPORT  DMAC_Handler              [WEAK]
+                EXPORT  USB_Handler               [WEAK]
+                EXPORT  EVSYS_Handler             [WEAK]
+                EXPORT  SERCOM0_Handler           [WEAK]
+                EXPORT  SERCOM1_Handler           [WEAK]
+                EXPORT  SERCOM2_Handler           [WEAK]
+                EXPORT  SERCOM3_Handler           [WEAK]
+                EXPORT  SERCOM4_Handler           [WEAK]
+                EXPORT  SERCOM5_Handler           [WEAK]
+                EXPORT  TCC0_Handler              [WEAK]
+                EXPORT  TCC1_Handler              [WEAK]
+                EXPORT  TCC2_Handler              [WEAK]
+                EXPORT  TC3_Handler               [WEAK]
+                EXPORT  TC4_Handler               [WEAK]
+                EXPORT  TC5_Handler               [WEAK]
+                EXPORT  TC6_Handler               [WEAK]
+                EXPORT  TC7_Handler               [WEAK]
+                EXPORT  ADC_Handler               [WEAK]
+                EXPORT  AC_Handler                [WEAK]
+                EXPORT  DAC_Handler               [WEAK]
+                EXPORT  PTC_Handler               [WEAK]
+                EXPORT  I2S_Handler               [WEAK]
+                EXPORT  AC1_Handler               [WEAK]
+
+PM_Handler
+SYSCTRL_Handler
+WDT_Handler
+RTC_Handler
+EIC_Handler
+NVMCTRL_Handler
+DMAC_Handler
+USB_Handler
+EVSYS_Handler
+SERCOM0_Handler
+SERCOM1_Handler
+SERCOM2_Handler
+SERCOM3_Handler
+SERCOM4_Handler
+SERCOM5_Handler
+TCC0_Handler
+TCC1_Handler
+TCC2_Handler
+TC3_Handler
+TC4_Handler
+TC5_Handler
+TC6_Handler
+TC7_Handler
+ADC_Handler
+AC_Handler
+DAC_Handler
+PTC_Handler
+I2S_Handler
+AC1_Handler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/uf2-samdx1/lib/samd21/samd21a/armcc/Device/SAMD21/Source/system_samd21.c b/uf2-samdx1/lib/samd21/samd21a/armcc/Device/SAMD21/Source/system_samd21.c
new file mode 100644
index 00000000..0c62b962
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/armcc/Device/SAMD21/Source/system_samd21.c
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ *  the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK    (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+	// Keep the default device state after reset
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+	// Not implemented
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E15A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E15A.atdf
new file mode 100644
index 00000000..de05e21f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E15A.atdf
@@ -0,0 +1,4997 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21E15A-MU" package="QFN32" pinout="SAMD21EM" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E15A-MF" package="QFN32" pinout="SAMD21EM" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E15A-AU" package="TQFP32" pinout="SAMD21EA" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E15A-AF" package="TQFP32" pinout="SAMD21EA" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21E15A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x8000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x1000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="32768"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="512"/>
+              <param name="PAGES_PR_REGION" value="32"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="1"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x1001030D"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x1001030D" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="1"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21EM" caption="SAMD21EM">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="PA05"/>
+      <pin position="7" pad="PA06"/>
+      <pin position="8" pad="PA07"/>
+      <pin position="9" pad="VDDANA"/>
+      <pin position="10" pad="GNDIO01"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PA10"/>
+      <pin position="14" pad="PA11"/>
+      <pin position="15" pad="PA14"/>
+      <pin position="16" pad="PA15"/>
+      <pin position="17" pad="PA16"/>
+      <pin position="18" pad="PA17"/>
+      <pin position="19" pad="PA18"/>
+      <pin position="20" pad="PA19"/>
+      <pin position="21" pad="PA22"/>
+      <pin position="22" pad="PA23"/>
+      <pin position="23" pad="PA24"/>
+      <pin position="24" pad="PA25"/>
+      <pin position="25" pad="PA27"/>
+      <pin position="26" pad="RESET_N"/>
+      <pin position="27" pad="PA28"/>
+      <pin position="28" pad="GNDIO"/>
+      <pin position="29" pad="VDDCORE"/>
+      <pin position="30" pad="VDDIN"/>
+      <pin position="31" pad="PA30"/>
+      <pin position="32" pad="PA31"/>
+      <pin position="DB" pad="GNDIO"/>
+      <pin position="GND" pad="GNDANA"/>
+    </pinout>
+    <pinout name="SAMD21EA" caption="SAMD21EA">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="PA05"/>
+      <pin position="7" pad="PA06"/>
+      <pin position="8" pad="PA07"/>
+      <pin position="9" pad="VDDANA"/>
+      <pin position="10" pad="GNDIO01"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PA10"/>
+      <pin position="14" pad="PA11"/>
+      <pin position="15" pad="PA14"/>
+      <pin position="16" pad="PA15"/>
+      <pin position="17" pad="PA16"/>
+      <pin position="18" pad="PA17"/>
+      <pin position="19" pad="PA18"/>
+      <pin position="20" pad="PA19"/>
+      <pin position="21" pad="PA22"/>
+      <pin position="22" pad="PA23"/>
+      <pin position="23" pad="PA24"/>
+      <pin position="24" pad="PA25"/>
+      <pin position="25" pad="PA27"/>
+      <pin position="26" pad="RESET_N"/>
+      <pin position="27" pad="PA28"/>
+      <pin position="28" pad="GNDIO"/>
+      <pin position="29" pad="VDDCORE"/>
+      <pin position="30" pad="VDDIN"/>
+      <pin position="31" pad="PA30"/>
+      <pin position="32" pad="PA31"/>
+      <pin position="DB" pad="GNDIO"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E16A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E16A.atdf
new file mode 100644
index 00000000..03a2f42f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E16A.atdf
@@ -0,0 +1,4997 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21E16A-MU" package="QFN32" pinout="SAMD21EM" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E16A-MF" package="QFN32" pinout="SAMD21EM" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E16A-AU" package="TQFP32" pinout="SAMD21EA" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E16A-AF" package="TQFP32" pinout="SAMD21EA" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21E16A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x10000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x2000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="65536"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="1024"/>
+              <param name="PAGES_PR_REGION" value="64"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="1"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x1001030C"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x1001030C" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="1"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21EM" caption="SAMD21EM">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="PA05"/>
+      <pin position="7" pad="PA06"/>
+      <pin position="8" pad="PA07"/>
+      <pin position="9" pad="VDDANA"/>
+      <pin position="10" pad="GNDIO01"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PA10"/>
+      <pin position="14" pad="PA11"/>
+      <pin position="15" pad="PA14"/>
+      <pin position="16" pad="PA15"/>
+      <pin position="17" pad="PA16"/>
+      <pin position="18" pad="PA17"/>
+      <pin position="19" pad="PA18"/>
+      <pin position="20" pad="PA19"/>
+      <pin position="21" pad="PA22"/>
+      <pin position="22" pad="PA23"/>
+      <pin position="23" pad="PA24"/>
+      <pin position="24" pad="PA25"/>
+      <pin position="25" pad="PA27"/>
+      <pin position="26" pad="RESET_N"/>
+      <pin position="27" pad="PA28"/>
+      <pin position="28" pad="GNDIO"/>
+      <pin position="29" pad="VDDCORE"/>
+      <pin position="30" pad="VDDIN"/>
+      <pin position="31" pad="PA30"/>
+      <pin position="32" pad="PA31"/>
+      <pin position="DB" pad="GNDIO"/>
+      <pin position="GND" pad="GNDANA"/>
+    </pinout>
+    <pinout name="SAMD21EA" caption="SAMD21EA">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="PA05"/>
+      <pin position="7" pad="PA06"/>
+      <pin position="8" pad="PA07"/>
+      <pin position="9" pad="VDDANA"/>
+      <pin position="10" pad="GNDIO01"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PA10"/>
+      <pin position="14" pad="PA11"/>
+      <pin position="15" pad="PA14"/>
+      <pin position="16" pad="PA15"/>
+      <pin position="17" pad="PA16"/>
+      <pin position="18" pad="PA17"/>
+      <pin position="19" pad="PA18"/>
+      <pin position="20" pad="PA19"/>
+      <pin position="21" pad="PA22"/>
+      <pin position="22" pad="PA23"/>
+      <pin position="23" pad="PA24"/>
+      <pin position="24" pad="PA25"/>
+      <pin position="25" pad="PA27"/>
+      <pin position="26" pad="RESET_N"/>
+      <pin position="27" pad="PA28"/>
+      <pin position="28" pad="GNDIO"/>
+      <pin position="29" pad="VDDCORE"/>
+      <pin position="30" pad="VDDIN"/>
+      <pin position="31" pad="PA30"/>
+      <pin position="32" pad="PA31"/>
+      <pin position="DB" pad="GNDIO"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E17A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E17A.atdf
new file mode 100644
index 00000000..95c7a0ea
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E17A.atdf
@@ -0,0 +1,4997 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21E17A-MU" package="QFN32" pinout="SAMD21EM" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E17A-MF" package="QFN32" pinout="SAMD21EM" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E17A-AU" package="TQFP32" pinout="SAMD21EA" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E17A-AF" package="TQFP32" pinout="SAMD21EA" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21E17A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x20000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x4000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="131072"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="2048"/>
+              <param name="PAGES_PR_REGION" value="128"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="1"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x1001030B"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x1001030B" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="1"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21EM" caption="SAMD21EM">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="PA05"/>
+      <pin position="7" pad="PA06"/>
+      <pin position="8" pad="PA07"/>
+      <pin position="9" pad="VDDANA"/>
+      <pin position="10" pad="GNDIO01"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PA10"/>
+      <pin position="14" pad="PA11"/>
+      <pin position="15" pad="PA14"/>
+      <pin position="16" pad="PA15"/>
+      <pin position="17" pad="PA16"/>
+      <pin position="18" pad="PA17"/>
+      <pin position="19" pad="PA18"/>
+      <pin position="20" pad="PA19"/>
+      <pin position="21" pad="PA22"/>
+      <pin position="22" pad="PA23"/>
+      <pin position="23" pad="PA24"/>
+      <pin position="24" pad="PA25"/>
+      <pin position="25" pad="PA27"/>
+      <pin position="26" pad="RESET_N"/>
+      <pin position="27" pad="PA28"/>
+      <pin position="28" pad="GNDIO"/>
+      <pin position="29" pad="VDDCORE"/>
+      <pin position="30" pad="VDDIN"/>
+      <pin position="31" pad="PA30"/>
+      <pin position="32" pad="PA31"/>
+      <pin position="DB" pad="GNDIO"/>
+      <pin position="GND" pad="GNDANA"/>
+    </pinout>
+    <pinout name="SAMD21EA" caption="SAMD21EA">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="PA05"/>
+      <pin position="7" pad="PA06"/>
+      <pin position="8" pad="PA07"/>
+      <pin position="9" pad="VDDANA"/>
+      <pin position="10" pad="GNDIO01"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PA10"/>
+      <pin position="14" pad="PA11"/>
+      <pin position="15" pad="PA14"/>
+      <pin position="16" pad="PA15"/>
+      <pin position="17" pad="PA16"/>
+      <pin position="18" pad="PA17"/>
+      <pin position="19" pad="PA18"/>
+      <pin position="20" pad="PA19"/>
+      <pin position="21" pad="PA22"/>
+      <pin position="22" pad="PA23"/>
+      <pin position="23" pad="PA24"/>
+      <pin position="24" pad="PA25"/>
+      <pin position="25" pad="PA27"/>
+      <pin position="26" pad="RESET_N"/>
+      <pin position="27" pad="PA28"/>
+      <pin position="28" pad="GNDIO"/>
+      <pin position="29" pad="VDDCORE"/>
+      <pin position="30" pad="VDDIN"/>
+      <pin position="31" pad="PA30"/>
+      <pin position="32" pad="PA31"/>
+      <pin position="DB" pad="GNDIO"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E18A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E18A.atdf
new file mode 100644
index 00000000..60a52057
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21E18A.atdf
@@ -0,0 +1,4997 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21E18A-MU" package="QFN32" pinout="SAMD21EM" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E18A-MF" package="QFN32" pinout="SAMD21EM" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E18A-AU" package="TQFP32" pinout="SAMD21EA" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21E18A-AF" package="TQFP32" pinout="SAMD21EA" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21E18A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x40000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x8000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="262144"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="4096"/>
+              <param name="PAGES_PR_REGION" value="256"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="1"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x1001030A"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x1001030A" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="1"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21EM" caption="SAMD21EM">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="PA05"/>
+      <pin position="7" pad="PA06"/>
+      <pin position="8" pad="PA07"/>
+      <pin position="9" pad="VDDANA"/>
+      <pin position="10" pad="GNDIO01"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PA10"/>
+      <pin position="14" pad="PA11"/>
+      <pin position="15" pad="PA14"/>
+      <pin position="16" pad="PA15"/>
+      <pin position="17" pad="PA16"/>
+      <pin position="18" pad="PA17"/>
+      <pin position="19" pad="PA18"/>
+      <pin position="20" pad="PA19"/>
+      <pin position="21" pad="PA22"/>
+      <pin position="22" pad="PA23"/>
+      <pin position="23" pad="PA24"/>
+      <pin position="24" pad="PA25"/>
+      <pin position="25" pad="PA27"/>
+      <pin position="26" pad="RESET_N"/>
+      <pin position="27" pad="PA28"/>
+      <pin position="28" pad="GNDIO"/>
+      <pin position="29" pad="VDDCORE"/>
+      <pin position="30" pad="VDDIN"/>
+      <pin position="31" pad="PA30"/>
+      <pin position="32" pad="PA31"/>
+      <pin position="DB" pad="GNDIO"/>
+      <pin position="GND" pad="GNDANA"/>
+    </pinout>
+    <pinout name="SAMD21EA" caption="SAMD21EA">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PA04"/>
+      <pin position="6" pad="PA05"/>
+      <pin position="7" pad="PA06"/>
+      <pin position="8" pad="PA07"/>
+      <pin position="9" pad="VDDANA"/>
+      <pin position="10" pad="GNDIO01"/>
+      <pin position="11" pad="PA08"/>
+      <pin position="12" pad="PA09"/>
+      <pin position="13" pad="PA10"/>
+      <pin position="14" pad="PA11"/>
+      <pin position="15" pad="PA14"/>
+      <pin position="16" pad="PA15"/>
+      <pin position="17" pad="PA16"/>
+      <pin position="18" pad="PA17"/>
+      <pin position="19" pad="PA18"/>
+      <pin position="20" pad="PA19"/>
+      <pin position="21" pad="PA22"/>
+      <pin position="22" pad="PA23"/>
+      <pin position="23" pad="PA24"/>
+      <pin position="24" pad="PA25"/>
+      <pin position="25" pad="PA27"/>
+      <pin position="26" pad="RESET_N"/>
+      <pin position="27" pad="PA28"/>
+      <pin position="28" pad="GNDIO"/>
+      <pin position="29" pad="VDDCORE"/>
+      <pin position="30" pad="VDDIN"/>
+      <pin position="31" pad="PA30"/>
+      <pin position="32" pad="PA31"/>
+      <pin position="DB" pad="GNDIO"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G15A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G15A.atdf
new file mode 100644
index 00000000..e237db55
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G15A.atdf
@@ -0,0 +1,5086 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21G15A-MU" package="QFN48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G15A-MF" package="QFN48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G15A-AU" package="TQFP48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G15A-AF" package="TQFP48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21G15A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x8000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x1000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB11"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PB22"/>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PB23"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="4" function="H" pad="PB10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="5" function="H" pad="PB11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="MCK" index="1" function="G" pad="PB10"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SCK" index="1" function="G" pad="PB11"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="32768"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="512"/>
+              <param name="PAGES_PR_REGION" value="32"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="43" function="default" pad="PB11"/>
+              <signal group="P" index="54" function="default" pad="PB22"/>
+              <signal group="P" index="55" function="default" pad="PB23"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="2" function="D" pad="PB10"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+              <signal group="PAD" index="3" function="D" pad="PB11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="D" pad="PB22"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="D" pad="PB23"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="0" function="E" pad="PB10"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+              <signal group="WO" index="1" function="E" pad="PB11"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="4" function="F" pad="PB10"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="5" function="F" pad="PB11"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x10010308"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x10010308" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21G" caption="SAMD21G">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="GNDANA"/>
+      <pin position="6" pad="VDDANA"/>
+      <pin position="7" pad="PB08"/>
+      <pin position="8" pad="PB09"/>
+      <pin position="9" pad="PA04"/>
+      <pin position="10" pad="PA05"/>
+      <pin position="11" pad="PA06"/>
+      <pin position="12" pad="PA07"/>
+      <pin position="13" pad="PA08"/>
+      <pin position="14" pad="PA09"/>
+      <pin position="15" pad="PA10"/>
+      <pin position="16" pad="PA11"/>
+      <pin position="17" pad="VDDIO02"/>
+      <pin position="18" pad="GNDIO02"/>
+      <pin position="19" pad="PB10"/>
+      <pin position="20" pad="PB11"/>
+      <pin position="21" pad="PA12"/>
+      <pin position="22" pad="PA13"/>
+      <pin position="23" pad="PA14"/>
+      <pin position="24" pad="PA15"/>
+      <pin position="25" pad="PA16"/>
+      <pin position="26" pad="PA17"/>
+      <pin position="27" pad="PA18"/>
+      <pin position="28" pad="PA19"/>
+      <pin position="29" pad="PA20"/>
+      <pin position="30" pad="PA21"/>
+      <pin position="31" pad="PA22"/>
+      <pin position="32" pad="PA23"/>
+      <pin position="33" pad="PA24"/>
+      <pin position="34" pad="PA25"/>
+      <pin position="35" pad="GNDIO04"/>
+      <pin position="36" pad="VDDIO04"/>
+      <pin position="37" pad="PB22"/>
+      <pin position="38" pad="PB23"/>
+      <pin position="39" pad="PA27"/>
+      <pin position="40" pad="RESET_N"/>
+      <pin position="41" pad="PA28"/>
+      <pin position="42" pad="GNDIO"/>
+      <pin position="43" pad="VDDCORE"/>
+      <pin position="44" pad="VDDIN"/>
+      <pin position="45" pad="PA30"/>
+      <pin position="46" pad="PA31"/>
+      <pin position="47" pad="PB02"/>
+      <pin position="48" pad="PB03"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G16A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G16A.atdf
new file mode 100644
index 00000000..8962b248
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G16A.atdf
@@ -0,0 +1,5086 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21G16A-MU" package="QFN48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G16A-MF" package="QFN48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G16A-AU" package="TQFP48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G16A-AF" package="TQFP48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21G16A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x10000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x2000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB11"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PB22"/>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PB23"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="4" function="H" pad="PB10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="5" function="H" pad="PB11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="MCK" index="1" function="G" pad="PB10"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SCK" index="1" function="G" pad="PB11"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="65536"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="1024"/>
+              <param name="PAGES_PR_REGION" value="64"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="43" function="default" pad="PB11"/>
+              <signal group="P" index="54" function="default" pad="PB22"/>
+              <signal group="P" index="55" function="default" pad="PB23"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="2" function="D" pad="PB10"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+              <signal group="PAD" index="3" function="D" pad="PB11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="D" pad="PB22"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="D" pad="PB23"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="0" function="E" pad="PB10"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+              <signal group="WO" index="1" function="E" pad="PB11"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="4" function="F" pad="PB10"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="5" function="F" pad="PB11"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x10010307"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x10010307" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21G" caption="SAMD21G">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="GNDANA"/>
+      <pin position="6" pad="VDDANA"/>
+      <pin position="7" pad="PB08"/>
+      <pin position="8" pad="PB09"/>
+      <pin position="9" pad="PA04"/>
+      <pin position="10" pad="PA05"/>
+      <pin position="11" pad="PA06"/>
+      <pin position="12" pad="PA07"/>
+      <pin position="13" pad="PA08"/>
+      <pin position="14" pad="PA09"/>
+      <pin position="15" pad="PA10"/>
+      <pin position="16" pad="PA11"/>
+      <pin position="17" pad="VDDIO02"/>
+      <pin position="18" pad="GNDIO02"/>
+      <pin position="19" pad="PB10"/>
+      <pin position="20" pad="PB11"/>
+      <pin position="21" pad="PA12"/>
+      <pin position="22" pad="PA13"/>
+      <pin position="23" pad="PA14"/>
+      <pin position="24" pad="PA15"/>
+      <pin position="25" pad="PA16"/>
+      <pin position="26" pad="PA17"/>
+      <pin position="27" pad="PA18"/>
+      <pin position="28" pad="PA19"/>
+      <pin position="29" pad="PA20"/>
+      <pin position="30" pad="PA21"/>
+      <pin position="31" pad="PA22"/>
+      <pin position="32" pad="PA23"/>
+      <pin position="33" pad="PA24"/>
+      <pin position="34" pad="PA25"/>
+      <pin position="35" pad="GNDIO04"/>
+      <pin position="36" pad="VDDIO04"/>
+      <pin position="37" pad="PB22"/>
+      <pin position="38" pad="PB23"/>
+      <pin position="39" pad="PA27"/>
+      <pin position="40" pad="RESET_N"/>
+      <pin position="41" pad="PA28"/>
+      <pin position="42" pad="GNDIO"/>
+      <pin position="43" pad="VDDCORE"/>
+      <pin position="44" pad="VDDIN"/>
+      <pin position="45" pad="PA30"/>
+      <pin position="46" pad="PA31"/>
+      <pin position="47" pad="PB02"/>
+      <pin position="48" pad="PB03"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G17A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G17A.atdf
new file mode 100644
index 00000000..3222e9f7
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G17A.atdf
@@ -0,0 +1,5086 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21G17A-MU" package="QFN48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G17A-MF" package="QFN48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G17A-AU" package="TQFP48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G17A-AF" package="TQFP48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21G17A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x20000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x4000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB11"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PB22"/>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PB23"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="4" function="H" pad="PB10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="5" function="H" pad="PB11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="MCK" index="1" function="G" pad="PB10"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SCK" index="1" function="G" pad="PB11"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="131072"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="2048"/>
+              <param name="PAGES_PR_REGION" value="128"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="43" function="default" pad="PB11"/>
+              <signal group="P" index="54" function="default" pad="PB22"/>
+              <signal group="P" index="55" function="default" pad="PB23"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="2" function="D" pad="PB10"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+              <signal group="PAD" index="3" function="D" pad="PB11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="D" pad="PB22"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="D" pad="PB23"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="0" function="E" pad="PB10"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+              <signal group="WO" index="1" function="E" pad="PB11"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="4" function="F" pad="PB10"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="5" function="F" pad="PB11"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x10010306"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x10010306" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21G" caption="SAMD21G">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="GNDANA"/>
+      <pin position="6" pad="VDDANA"/>
+      <pin position="7" pad="PB08"/>
+      <pin position="8" pad="PB09"/>
+      <pin position="9" pad="PA04"/>
+      <pin position="10" pad="PA05"/>
+      <pin position="11" pad="PA06"/>
+      <pin position="12" pad="PA07"/>
+      <pin position="13" pad="PA08"/>
+      <pin position="14" pad="PA09"/>
+      <pin position="15" pad="PA10"/>
+      <pin position="16" pad="PA11"/>
+      <pin position="17" pad="VDDIO02"/>
+      <pin position="18" pad="GNDIO02"/>
+      <pin position="19" pad="PB10"/>
+      <pin position="20" pad="PB11"/>
+      <pin position="21" pad="PA12"/>
+      <pin position="22" pad="PA13"/>
+      <pin position="23" pad="PA14"/>
+      <pin position="24" pad="PA15"/>
+      <pin position="25" pad="PA16"/>
+      <pin position="26" pad="PA17"/>
+      <pin position="27" pad="PA18"/>
+      <pin position="28" pad="PA19"/>
+      <pin position="29" pad="PA20"/>
+      <pin position="30" pad="PA21"/>
+      <pin position="31" pad="PA22"/>
+      <pin position="32" pad="PA23"/>
+      <pin position="33" pad="PA24"/>
+      <pin position="34" pad="PA25"/>
+      <pin position="35" pad="GNDIO04"/>
+      <pin position="36" pad="VDDIO04"/>
+      <pin position="37" pad="PB22"/>
+      <pin position="38" pad="PB23"/>
+      <pin position="39" pad="PA27"/>
+      <pin position="40" pad="RESET_N"/>
+      <pin position="41" pad="PA28"/>
+      <pin position="42" pad="GNDIO"/>
+      <pin position="43" pad="VDDCORE"/>
+      <pin position="44" pad="VDDIN"/>
+      <pin position="45" pad="PA30"/>
+      <pin position="46" pad="PA31"/>
+      <pin position="47" pad="PB02"/>
+      <pin position="48" pad="PB03"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G17AU.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G17AU.atdf
new file mode 100644
index 00000000..86330091
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G17AU.atdf
@@ -0,0 +1,5106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21G17A-UU" package="WLCSP45" pinout="SAMD21GU" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21G17AU" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x20000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x4000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="12" function="B_ADC" pad="PB04"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="131072"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="2048"/>
+              <param name="PAGES_PR_REGION" value="128"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="36" function="default" pad="PB04"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="10" function="B_PTC" pad="PB04"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+          <instance name="TC6">
+            <register-group name="TC6" name-in-module="TC" address-space="base" offset="0x42003800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PB02"/>
+              <signal group="WO" index="1" function="E" pad="PB03"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="33"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="78"/>
+            </parameters>
+          </instance>
+          <instance name="TC7">
+            <register-group name="TC7" name-in-module="TC" address-space="base" offset="0x42003C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA20"/>
+              <signal group="WO" index="1" function="E" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="36"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="79"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="TC6_IRQn" index="21" module-instance="TC6"/>
+        <interrupt name="TC7_IRQn" index="22" module-instance="TC7"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x10010310"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x10010310" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="TC6_" caption="TC6 APB Clock Enable" mask="0x4000"/>
+          <bitfield name="TC7_" caption="TC7 APB Clock Enable" mask="0x8000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21GU" caption="SAMD21GU">
+      <pin position="A2" pad="PA27"/>
+      <pin position="A4" pad="PA28"/>
+      <pin position="A6" pad="GNDIO"/>
+      <pin position="A8" pad="VDDCORE"/>
+      <pin position="A10" pad="VDDIN"/>
+      <pin position="A12" pad="PB02"/>
+      <pin position="B1" pad="PA25"/>
+      <pin position="B3" pad="VDDIO04"/>
+      <pin position="B5" pad="RESET_N"/>
+      <pin position="B7" pad="PA30"/>
+      <pin position="B9" pad="PA31"/>
+      <pin position="B11" pad="PB03"/>
+      <pin position="B13" pad="PA01"/>
+      <pin position="C2" pad="PA24"/>
+      <pin position="C4" pad="GNDIO04"/>
+      <pin position="C6" pad="PA22"/>
+      <pin position="C8" pad="PA03"/>
+      <pin position="C10" pad="PA02"/>
+      <pin position="C12" pad="PA00"/>
+      <pin position="D1" pad="PA21"/>
+      <pin position="D3" pad="PA23"/>
+      <pin position="D5" pad="PA16"/>
+      <pin position="D7" pad="PA12"/>
+      <pin position="D9" pad="PB08"/>
+      <pin position="D11" pad="PB04"/>
+      <pin position="D13" pad="GNDANA"/>
+      <pin position="E2" pad="PA20"/>
+      <pin position="E4" pad="PA19"/>
+      <pin position="E6" pad="PA09"/>
+      <pin position="E8" pad="PA06"/>
+      <pin position="E10" pad="PB09"/>
+      <pin position="E12" pad="VDDANA"/>
+      <pin position="F1" pad="PA18"/>
+      <pin position="F3" pad="PA17"/>
+      <pin position="F5" pad="PA13"/>
+      <pin position="F7" pad="PA11"/>
+      <pin position="F9" pad="PA08"/>
+      <pin position="F11" pad="PA05"/>
+      <pin position="F13" pad="PA04"/>
+      <pin position="G2" pad="PA15"/>
+      <pin position="G4" pad="PA14"/>
+      <pin position="G6" pad="GNDIO02"/>
+      <pin position="G8" pad="VDDIO02"/>
+      <pin position="G10" pad="PA10"/>
+      <pin position="G12" pad="PA07"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G18A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G18A.atdf
new file mode 100644
index 00000000..1807d0f1
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G18A.atdf
@@ -0,0 +1,5086 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21G18A-MU" package="QFN48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G18A-MF" package="QFN48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G18A-AU" package="TQFP48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21G18A-AF" package="TQFP48" pinout="SAMD21G" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21G18A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x40000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x8000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB11"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PB22"/>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PB23"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="4" function="H" pad="PB10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="5" function="H" pad="PB11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="MCK" index="1" function="G" pad="PB10"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SCK" index="1" function="G" pad="PB11"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="262144"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="4096"/>
+              <param name="PAGES_PR_REGION" value="256"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="43" function="default" pad="PB11"/>
+              <signal group="P" index="54" function="default" pad="PB22"/>
+              <signal group="P" index="55" function="default" pad="PB23"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="2" function="D" pad="PB10"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+              <signal group="PAD" index="3" function="D" pad="PB11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="D" pad="PB22"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="D" pad="PB23"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="0" function="E" pad="PB10"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+              <signal group="WO" index="1" function="E" pad="PB11"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="4" function="F" pad="PB10"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="5" function="F" pad="PB11"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x10010305"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x10010305" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21G" caption="SAMD21G">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="GNDANA"/>
+      <pin position="6" pad="VDDANA"/>
+      <pin position="7" pad="PB08"/>
+      <pin position="8" pad="PB09"/>
+      <pin position="9" pad="PA04"/>
+      <pin position="10" pad="PA05"/>
+      <pin position="11" pad="PA06"/>
+      <pin position="12" pad="PA07"/>
+      <pin position="13" pad="PA08"/>
+      <pin position="14" pad="PA09"/>
+      <pin position="15" pad="PA10"/>
+      <pin position="16" pad="PA11"/>
+      <pin position="17" pad="VDDIO02"/>
+      <pin position="18" pad="GNDIO02"/>
+      <pin position="19" pad="PB10"/>
+      <pin position="20" pad="PB11"/>
+      <pin position="21" pad="PA12"/>
+      <pin position="22" pad="PA13"/>
+      <pin position="23" pad="PA14"/>
+      <pin position="24" pad="PA15"/>
+      <pin position="25" pad="PA16"/>
+      <pin position="26" pad="PA17"/>
+      <pin position="27" pad="PA18"/>
+      <pin position="28" pad="PA19"/>
+      <pin position="29" pad="PA20"/>
+      <pin position="30" pad="PA21"/>
+      <pin position="31" pad="PA22"/>
+      <pin position="32" pad="PA23"/>
+      <pin position="33" pad="PA24"/>
+      <pin position="34" pad="PA25"/>
+      <pin position="35" pad="GNDIO04"/>
+      <pin position="36" pad="VDDIO04"/>
+      <pin position="37" pad="PB22"/>
+      <pin position="38" pad="PB23"/>
+      <pin position="39" pad="PA27"/>
+      <pin position="40" pad="RESET_N"/>
+      <pin position="41" pad="PA28"/>
+      <pin position="42" pad="GNDIO"/>
+      <pin position="43" pad="VDDCORE"/>
+      <pin position="44" pad="VDDIN"/>
+      <pin position="45" pad="PA30"/>
+      <pin position="46" pad="PA31"/>
+      <pin position="47" pad="PB02"/>
+      <pin position="48" pad="PB03"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G18AU.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G18AU.atdf
new file mode 100644
index 00000000..8e2f7efe
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21G18AU.atdf
@@ -0,0 +1,5106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21G18A-UU" package="WLCSP45" pinout="SAMD21GU" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21G18AU" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x40000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x8000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="12" function="B_ADC" pad="PB04"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="262144"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="4096"/>
+              <param name="PAGES_PR_REGION" value="256"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="36" function="default" pad="PB04"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="10" function="B_PTC" pad="PB04"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+          <instance name="TC6">
+            <register-group name="TC6" name-in-module="TC" address-space="base" offset="0x42003800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PB02"/>
+              <signal group="WO" index="1" function="E" pad="PB03"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="33"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="78"/>
+            </parameters>
+          </instance>
+          <instance name="TC7">
+            <register-group name="TC7" name-in-module="TC" address-space="base" offset="0x42003C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA20"/>
+              <signal group="WO" index="1" function="E" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="36"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="79"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="TC6_IRQn" index="21" module-instance="TC6"/>
+        <interrupt name="TC7_IRQn" index="22" module-instance="TC7"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x1001030F"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x1001030F" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="TC6_" caption="TC6 APB Clock Enable" mask="0x4000"/>
+          <bitfield name="TC7_" caption="TC7 APB Clock Enable" mask="0x8000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21GU" caption="SAMD21GU">
+      <pin position="A2" pad="PA27"/>
+      <pin position="A4" pad="PA28"/>
+      <pin position="A6" pad="GNDIO"/>
+      <pin position="A8" pad="VDDCORE"/>
+      <pin position="A10" pad="VDDIN"/>
+      <pin position="A12" pad="PB02"/>
+      <pin position="B1" pad="PA25"/>
+      <pin position="B3" pad="VDDIO04"/>
+      <pin position="B5" pad="RESET_N"/>
+      <pin position="B7" pad="PA30"/>
+      <pin position="B9" pad="PA31"/>
+      <pin position="B11" pad="PB03"/>
+      <pin position="B13" pad="PA01"/>
+      <pin position="C2" pad="PA24"/>
+      <pin position="C4" pad="GNDIO04"/>
+      <pin position="C6" pad="PA22"/>
+      <pin position="C8" pad="PA03"/>
+      <pin position="C10" pad="PA02"/>
+      <pin position="C12" pad="PA00"/>
+      <pin position="D1" pad="PA21"/>
+      <pin position="D3" pad="PA23"/>
+      <pin position="D5" pad="PA16"/>
+      <pin position="D7" pad="PA12"/>
+      <pin position="D9" pad="PB08"/>
+      <pin position="D11" pad="PB04"/>
+      <pin position="D13" pad="GNDANA"/>
+      <pin position="E2" pad="PA20"/>
+      <pin position="E4" pad="PA19"/>
+      <pin position="E6" pad="PA09"/>
+      <pin position="E8" pad="PA06"/>
+      <pin position="E10" pad="PB09"/>
+      <pin position="E12" pad="VDDANA"/>
+      <pin position="F1" pad="PA18"/>
+      <pin position="F3" pad="PA17"/>
+      <pin position="F5" pad="PA13"/>
+      <pin position="F7" pad="PA11"/>
+      <pin position="F9" pad="PA08"/>
+      <pin position="F11" pad="PA05"/>
+      <pin position="F13" pad="PA04"/>
+      <pin position="G2" pad="PA15"/>
+      <pin position="G4" pad="PA14"/>
+      <pin position="G6" pad="GNDIO02"/>
+      <pin position="G8" pad="VDDIO02"/>
+      <pin position="G10" pad="PA10"/>
+      <pin position="G12" pad="PA07"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J15A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J15A.atdf
new file mode 100644
index 00000000..03ea2bd0
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J15A.atdf
@@ -0,0 +1,5227 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21J15A-MU" package="QFN64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J15A-MF" package="QFN64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J15A-AU" package="TQFP64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J15A-AF" package="TQFP64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21J15A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x8000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x1000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="8" function="B_ADC" pad="PB00"/>
+              <signal group="AIN" index="9" function="B_ADC" pad="PB01"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="12" function="B_ADC" pad="PB04"/>
+              <signal group="AIN" index="13" function="B_ADC" pad="PB05"/>
+              <signal group="AIN" index="14" function="B_ADC" pad="PB06"/>
+              <signal group="AIN" index="15" function="B_ADC" pad="PB07"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="5" function="A" pad="PB05"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB11"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="12" function="A" pad="PB12"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="13" function="A" pad="PB13"/>
+              <signal group="EXTINT" index="14" function="A" pad="PB14"/>
+              <signal group="EXTINT" index="14" function="A" pad="PB30"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="EXTINT" index="15" function="A" pad="PB15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PB31"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PB14"/>
+              <signal group="IO" index="0" function="H" pad="PB22"/>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PB15"/>
+              <signal group="IO" index="1" function="H" pad="PB23"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PB16"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="3" function="H" pad="PB17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="4" function="H" pad="PB10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="5" function="H" pad="PB11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="6" function="H" pad="PB12"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+              <signal group="IO" index="7" function="H" pad="PB13"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="FS" index="1" function="G" pad="PB12"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="MCK" index="0" function="G" pad="PB17"/>
+              <signal group="MCK" index="1" function="G" pad="PB10"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SCK" index="1" function="G" pad="PB11"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+              <signal group="SD" index="1" function="G" pad="PB16"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="32768"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="512"/>
+              <param name="PAGES_PR_REGION" value="32"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="32" function="default" pad="PB00"/>
+              <signal group="P" index="33" function="default" pad="PB01"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="36" function="default" pad="PB04"/>
+              <signal group="P" index="37" function="default" pad="PB05"/>
+              <signal group="P" index="38" function="default" pad="PB06"/>
+              <signal group="P" index="39" function="default" pad="PB07"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="43" function="default" pad="PB11"/>
+              <signal group="P" index="44" function="default" pad="PB12"/>
+              <signal group="P" index="45" function="default" pad="PB13"/>
+              <signal group="P" index="46" function="default" pad="PB14"/>
+              <signal group="P" index="47" function="default" pad="PB15"/>
+              <signal group="P" index="48" function="default" pad="PB16"/>
+              <signal group="P" index="49" function="default" pad="PB17"/>
+              <signal group="P" index="54" function="default" pad="PB22"/>
+              <signal group="P" index="55" function="default" pad="PB23"/>
+              <signal group="P" index="62" function="default" pad="PB30"/>
+              <signal group="P" index="63" function="default" pad="PB31"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="X" index="12" function="B_PTC" pad="PB12"/>
+              <signal group="X" index="13" function="B_PTC" pad="PB13"/>
+              <signal group="X" index="14" function="B_PTC" pad="PB14"/>
+              <signal group="X" index="15" function="B_PTC" pad="PB15"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="6" function="B_PTC" pad="PB00"/>
+              <signal group="Y" index="7" function="B_PTC" pad="PB01"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="10" function="B_PTC" pad="PB04"/>
+              <signal group="Y" index="11" function="B_PTC" pad="PB05"/>
+              <signal group="Y" index="12" function="B_PTC" pad="PB06"/>
+              <signal group="Y" index="13" function="B_PTC" pad="PB07"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="0" function="C" pad="PB12"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="1" function="C" pad="PB13"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="2" function="D" pad="PB10"/>
+              <signal group="PAD" index="2" function="C" pad="PB14"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+              <signal group="PAD" index="3" function="D" pad="PB11"/>
+              <signal group="PAD" index="3" function="C" pad="PB15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PB16"/>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="0" function="D" pad="PB30"/>
+              <signal group="PAD" index="1" function="C" pad="PB17"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="1" function="D" pad="PB31"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="D" pad="PB00"/>
+              <signal group="PAD" index="2" function="D" pad="PB22"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="D" pad="PB01"/>
+              <signal group="PAD" index="3" function="D" pad="PB23"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="0" function="E" pad="PB12"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+              <signal group="WO" index="1" function="E" pad="PB13"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="0" function="E" pad="PB10"/>
+              <signal group="WO" index="0" function="E" pad="PB14"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+              <signal group="WO" index="1" function="E" pad="PB11"/>
+              <signal group="WO" index="1" function="E" pad="PB15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+          <instance name="TC6">
+            <register-group name="TC6" name-in-module="TC" address-space="base" offset="0x42003800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PB02"/>
+              <signal group="WO" index="0" function="E" pad="PB16"/>
+              <signal group="WO" index="1" function="E" pad="PB03"/>
+              <signal group="WO" index="1" function="E" pad="PB17"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="33"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="78"/>
+            </parameters>
+          </instance>
+          <instance name="TC7">
+            <register-group name="TC7" name-in-module="TC" address-space="base" offset="0x42003C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA20"/>
+              <signal group="WO" index="0" function="E" pad="PB00"/>
+              <signal group="WO" index="0" function="E" pad="PB22"/>
+              <signal group="WO" index="1" function="E" pad="PA21"/>
+              <signal group="WO" index="1" function="E" pad="PB01"/>
+              <signal group="WO" index="1" function="E" pad="PB23"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="36"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="79"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="0" function="E" pad="PB30"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="1" function="E" pad="PB31"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="4" function="F" pad="PB10"/>
+              <signal group="WO" index="4" function="F" pad="PB16"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="5" function="F" pad="PB11"/>
+              <signal group="WO" index="5" function="F" pad="PB17"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PB12"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PB13"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="2" function="F" pad="PB30"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+              <signal group="WO" index="3" function="F" pad="PB31"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="TC6_IRQn" index="21" module-instance="TC6"/>
+        <interrupt name="TC7_IRQn" index="22" module-instance="TC7"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x10010303"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x10010303" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="TC6_" caption="TC6 APB Clock Enable" mask="0x4000"/>
+          <bitfield name="TC7_" caption="TC7 APB Clock Enable" mask="0x8000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21J" caption="SAMD21J">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PB04"/>
+      <pin position="6" pad="PB05"/>
+      <pin position="7" pad="GNDANA"/>
+      <pin position="8" pad="VDDANA"/>
+      <pin position="9" pad="PB06"/>
+      <pin position="10" pad="PB07"/>
+      <pin position="11" pad="PB08"/>
+      <pin position="12" pad="PB09"/>
+      <pin position="13" pad="PA04"/>
+      <pin position="14" pad="PA05"/>
+      <pin position="15" pad="PA06"/>
+      <pin position="16" pad="PA07"/>
+      <pin position="17" pad="PA08"/>
+      <pin position="18" pad="PA09"/>
+      <pin position="19" pad="PA10"/>
+      <pin position="20" pad="PA11"/>
+      <pin position="21" pad="VDDIO02"/>
+      <pin position="22" pad="GNDIO02"/>
+      <pin position="23" pad="PB10"/>
+      <pin position="24" pad="PB11"/>
+      <pin position="25" pad="PB12"/>
+      <pin position="26" pad="PB13"/>
+      <pin position="27" pad="PB14"/>
+      <pin position="28" pad="PB15"/>
+      <pin position="29" pad="PA12"/>
+      <pin position="30" pad="PA13"/>
+      <pin position="31" pad="PA14"/>
+      <pin position="32" pad="PA15"/>
+      <pin position="33" pad="GNDIO03"/>
+      <pin position="34" pad="VDDIO03"/>
+      <pin position="35" pad="PA16"/>
+      <pin position="36" pad="PA17"/>
+      <pin position="37" pad="PA18"/>
+      <pin position="38" pad="PA19"/>
+      <pin position="39" pad="PB16"/>
+      <pin position="40" pad="PB17"/>
+      <pin position="41" pad="PA20"/>
+      <pin position="42" pad="PA21"/>
+      <pin position="43" pad="PA22"/>
+      <pin position="44" pad="PA23"/>
+      <pin position="45" pad="PA24"/>
+      <pin position="46" pad="PA25"/>
+      <pin position="47" pad="GNDIO04"/>
+      <pin position="48" pad="VDDIO04"/>
+      <pin position="49" pad="PB22"/>
+      <pin position="50" pad="PB23"/>
+      <pin position="51" pad="PA27"/>
+      <pin position="52" pad="RESET_N"/>
+      <pin position="53" pad="PA28"/>
+      <pin position="54" pad="GNDIO"/>
+      <pin position="55" pad="VDDCORE"/>
+      <pin position="56" pad="VDDIN"/>
+      <pin position="57" pad="PA30"/>
+      <pin position="58" pad="PA31"/>
+      <pin position="59" pad="PB30"/>
+      <pin position="60" pad="PB31"/>
+      <pin position="61" pad="PB00"/>
+      <pin position="62" pad="PB01"/>
+      <pin position="63" pad="PB02"/>
+      <pin position="64" pad="PB03"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J16A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J16A.atdf
new file mode 100644
index 00000000..d3ec837a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J16A.atdf
@@ -0,0 +1,5294 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21J16A-CU" package="CTBGA64" pinout="SAMD21JC" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J16A-MU" package="QFN64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J16A-MF" package="QFN64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J16A-AU" package="TQFP64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J16A-AF" package="TQFP64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21J16A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x10000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x2000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="8" function="B_ADC" pad="PB00"/>
+              <signal group="AIN" index="9" function="B_ADC" pad="PB01"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="12" function="B_ADC" pad="PB04"/>
+              <signal group="AIN" index="13" function="B_ADC" pad="PB05"/>
+              <signal group="AIN" index="14" function="B_ADC" pad="PB06"/>
+              <signal group="AIN" index="15" function="B_ADC" pad="PB07"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="5" function="A" pad="PB05"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB11"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="12" function="A" pad="PB12"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="13" function="A" pad="PB13"/>
+              <signal group="EXTINT" index="14" function="A" pad="PB14"/>
+              <signal group="EXTINT" index="14" function="A" pad="PB30"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="EXTINT" index="15" function="A" pad="PB15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PB31"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PB14"/>
+              <signal group="IO" index="0" function="H" pad="PB22"/>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PB15"/>
+              <signal group="IO" index="1" function="H" pad="PB23"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PB16"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="3" function="H" pad="PB17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="4" function="H" pad="PB10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="5" function="H" pad="PB11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="6" function="H" pad="PB12"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+              <signal group="IO" index="7" function="H" pad="PB13"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="FS" index="1" function="G" pad="PB12"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="MCK" index="0" function="G" pad="PB17"/>
+              <signal group="MCK" index="1" function="G" pad="PB10"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SCK" index="1" function="G" pad="PB11"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+              <signal group="SD" index="1" function="G" pad="PB16"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="65536"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="1024"/>
+              <param name="PAGES_PR_REGION" value="64"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="32" function="default" pad="PB00"/>
+              <signal group="P" index="33" function="default" pad="PB01"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="36" function="default" pad="PB04"/>
+              <signal group="P" index="37" function="default" pad="PB05"/>
+              <signal group="P" index="38" function="default" pad="PB06"/>
+              <signal group="P" index="39" function="default" pad="PB07"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="43" function="default" pad="PB11"/>
+              <signal group="P" index="44" function="default" pad="PB12"/>
+              <signal group="P" index="45" function="default" pad="PB13"/>
+              <signal group="P" index="46" function="default" pad="PB14"/>
+              <signal group="P" index="47" function="default" pad="PB15"/>
+              <signal group="P" index="48" function="default" pad="PB16"/>
+              <signal group="P" index="49" function="default" pad="PB17"/>
+              <signal group="P" index="54" function="default" pad="PB22"/>
+              <signal group="P" index="55" function="default" pad="PB23"/>
+              <signal group="P" index="62" function="default" pad="PB30"/>
+              <signal group="P" index="63" function="default" pad="PB31"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="X" index="12" function="B_PTC" pad="PB12"/>
+              <signal group="X" index="13" function="B_PTC" pad="PB13"/>
+              <signal group="X" index="14" function="B_PTC" pad="PB14"/>
+              <signal group="X" index="15" function="B_PTC" pad="PB15"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="6" function="B_PTC" pad="PB00"/>
+              <signal group="Y" index="7" function="B_PTC" pad="PB01"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="10" function="B_PTC" pad="PB04"/>
+              <signal group="Y" index="11" function="B_PTC" pad="PB05"/>
+              <signal group="Y" index="12" function="B_PTC" pad="PB06"/>
+              <signal group="Y" index="13" function="B_PTC" pad="PB07"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="0" function="C" pad="PB12"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="1" function="C" pad="PB13"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="2" function="D" pad="PB10"/>
+              <signal group="PAD" index="2" function="C" pad="PB14"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+              <signal group="PAD" index="3" function="D" pad="PB11"/>
+              <signal group="PAD" index="3" function="C" pad="PB15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PB16"/>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="0" function="D" pad="PB30"/>
+              <signal group="PAD" index="1" function="C" pad="PB17"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="1" function="D" pad="PB31"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="D" pad="PB00"/>
+              <signal group="PAD" index="2" function="D" pad="PB22"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="D" pad="PB01"/>
+              <signal group="PAD" index="3" function="D" pad="PB23"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="0" function="E" pad="PB12"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+              <signal group="WO" index="1" function="E" pad="PB13"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="0" function="E" pad="PB10"/>
+              <signal group="WO" index="0" function="E" pad="PB14"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+              <signal group="WO" index="1" function="E" pad="PB11"/>
+              <signal group="WO" index="1" function="E" pad="PB15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+          <instance name="TC6">
+            <register-group name="TC6" name-in-module="TC" address-space="base" offset="0x42003800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PB02"/>
+              <signal group="WO" index="0" function="E" pad="PB16"/>
+              <signal group="WO" index="1" function="E" pad="PB03"/>
+              <signal group="WO" index="1" function="E" pad="PB17"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="33"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="78"/>
+            </parameters>
+          </instance>
+          <instance name="TC7">
+            <register-group name="TC7" name-in-module="TC" address-space="base" offset="0x42003C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA20"/>
+              <signal group="WO" index="0" function="E" pad="PB00"/>
+              <signal group="WO" index="0" function="E" pad="PB22"/>
+              <signal group="WO" index="1" function="E" pad="PA21"/>
+              <signal group="WO" index="1" function="E" pad="PB01"/>
+              <signal group="WO" index="1" function="E" pad="PB23"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="36"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="79"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="0" function="E" pad="PB30"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="1" function="E" pad="PB31"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="4" function="F" pad="PB10"/>
+              <signal group="WO" index="4" function="F" pad="PB16"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="5" function="F" pad="PB11"/>
+              <signal group="WO" index="5" function="F" pad="PB17"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PB12"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PB13"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="2" function="F" pad="PB30"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+              <signal group="WO" index="3" function="F" pad="PB31"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="TC6_IRQn" index="21" module-instance="TC6"/>
+        <interrupt name="TC7_IRQn" index="22" module-instance="TC7"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x10010302"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x10010302" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="TC6_" caption="TC6 APB Clock Enable" mask="0x4000"/>
+          <bitfield name="TC7_" caption="TC7 APB Clock Enable" mask="0x8000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21JC" caption="SAMD21JC">
+      <pin position="A1" pad="PB02"/>
+      <pin position="A2" pad="PB01"/>
+      <pin position="A3" pad="VDDIN"/>
+      <pin position="A4" pad="VDDCORE"/>
+      <pin position="A5" pad="GNDIO"/>
+      <pin position="A6" pad="PA28"/>
+      <pin position="A7" pad="PB23"/>
+      <pin position="A8" pad="PB22"/>
+      <pin position="B1" pad="PA00"/>
+      <pin position="B2" pad="PB00"/>
+      <pin position="B3" pad="PB31"/>
+      <pin position="B4" pad="PA31"/>
+      <pin position="B5" pad="PA30"/>
+      <pin position="B6" pad="RESET_N"/>
+      <pin position="B7" pad="PA27"/>
+      <pin position="B8" pad="VDDIO04"/>
+      <pin position="C1" pad="PA01"/>
+      <pin position="C2" pad="PB03"/>
+      <pin position="C3" pad="PA02"/>
+      <pin position="C4" pad="PB30"/>
+      <pin position="C5" pad="PA21"/>
+      <pin position="C6" pad="PA22"/>
+      <pin position="C7" pad="PA23"/>
+      <pin position="C8" pad="GNDIO04"/>
+      <pin position="D1" pad="GNDANA"/>
+      <pin position="D2" pad="PB04"/>
+      <pin position="D3" pad="PA03"/>
+      <pin position="D4" pad="PB05"/>
+      <pin position="D5" pad="PB17"/>
+      <pin position="D6" pad="PA20"/>
+      <pin position="D7" pad="PB16"/>
+      <pin position="D8" pad="PA25"/>
+      <pin position="E1" pad="VDDANA"/>
+      <pin position="E2" pad="PB08"/>
+      <pin position="E3" pad="PB07"/>
+      <pin position="E4" pad="PB06"/>
+      <pin position="E5" pad="PB11"/>
+      <pin position="E6" pad="PB15"/>
+      <pin position="E7" pad="PA19"/>
+      <pin position="E8" pad="PA24"/>
+      <pin position="F1" pad="PA04"/>
+      <pin position="F2" pad="PA05"/>
+      <pin position="F3" pad="PA10"/>
+      <pin position="F4" pad="PB09"/>
+      <pin position="F5" pad="PB12"/>
+      <pin position="F6" pad="PA12"/>
+      <pin position="F7" pad="PA18"/>
+      <pin position="F8" pad="PA17"/>
+      <pin position="G1" pad="PA07"/>
+      <pin position="G2" pad="PA06"/>
+      <pin position="G3" pad="PA11"/>
+      <pin position="G4" pad="PB10"/>
+      <pin position="G5" pad="PB13"/>
+      <pin position="G6" pad="PA13"/>
+      <pin position="G7" pad="PA16"/>
+      <pin position="G8" pad="VDDIO03"/>
+      <pin position="H1" pad="PA08"/>
+      <pin position="H2" pad="PA09"/>
+      <pin position="H3" pad="VDDIO02"/>
+      <pin position="H4" pad="GNDIO02"/>
+      <pin position="H5" pad="PB14"/>
+      <pin position="H6" pad="PA14"/>
+      <pin position="H7" pad="PA15"/>
+      <pin position="H8" pad="GNDIO03"/>
+    </pinout>
+    <pinout name="SAMD21J" caption="SAMD21J">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PB04"/>
+      <pin position="6" pad="PB05"/>
+      <pin position="7" pad="GNDANA"/>
+      <pin position="8" pad="VDDANA"/>
+      <pin position="9" pad="PB06"/>
+      <pin position="10" pad="PB07"/>
+      <pin position="11" pad="PB08"/>
+      <pin position="12" pad="PB09"/>
+      <pin position="13" pad="PA04"/>
+      <pin position="14" pad="PA05"/>
+      <pin position="15" pad="PA06"/>
+      <pin position="16" pad="PA07"/>
+      <pin position="17" pad="PA08"/>
+      <pin position="18" pad="PA09"/>
+      <pin position="19" pad="PA10"/>
+      <pin position="20" pad="PA11"/>
+      <pin position="21" pad="VDDIO02"/>
+      <pin position="22" pad="GNDIO02"/>
+      <pin position="23" pad="PB10"/>
+      <pin position="24" pad="PB11"/>
+      <pin position="25" pad="PB12"/>
+      <pin position="26" pad="PB13"/>
+      <pin position="27" pad="PB14"/>
+      <pin position="28" pad="PB15"/>
+      <pin position="29" pad="PA12"/>
+      <pin position="30" pad="PA13"/>
+      <pin position="31" pad="PA14"/>
+      <pin position="32" pad="PA15"/>
+      <pin position="33" pad="GNDIO03"/>
+      <pin position="34" pad="VDDIO03"/>
+      <pin position="35" pad="PA16"/>
+      <pin position="36" pad="PA17"/>
+      <pin position="37" pad="PA18"/>
+      <pin position="38" pad="PA19"/>
+      <pin position="39" pad="PB16"/>
+      <pin position="40" pad="PB17"/>
+      <pin position="41" pad="PA20"/>
+      <pin position="42" pad="PA21"/>
+      <pin position="43" pad="PA22"/>
+      <pin position="44" pad="PA23"/>
+      <pin position="45" pad="PA24"/>
+      <pin position="46" pad="PA25"/>
+      <pin position="47" pad="GNDIO04"/>
+      <pin position="48" pad="VDDIO04"/>
+      <pin position="49" pad="PB22"/>
+      <pin position="50" pad="PB23"/>
+      <pin position="51" pad="PA27"/>
+      <pin position="52" pad="RESET_N"/>
+      <pin position="53" pad="PA28"/>
+      <pin position="54" pad="GNDIO"/>
+      <pin position="55" pad="VDDCORE"/>
+      <pin position="56" pad="VDDIN"/>
+      <pin position="57" pad="PA30"/>
+      <pin position="58" pad="PA31"/>
+      <pin position="59" pad="PB30"/>
+      <pin position="60" pad="PB31"/>
+      <pin position="61" pad="PB00"/>
+      <pin position="62" pad="PB01"/>
+      <pin position="63" pad="PB02"/>
+      <pin position="64" pad="PB03"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J17A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J17A.atdf
new file mode 100644
index 00000000..d1cc30b1
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J17A.atdf
@@ -0,0 +1,5294 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21J17A-CU" package="CTBGA64" pinout="SAMD21JC" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J17A-MU" package="QFN64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J17A-MF" package="QFN64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J17A-AU" package="TQFP64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J17A-AF" package="TQFP64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21J17A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x20000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x4000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="8" function="B_ADC" pad="PB00"/>
+              <signal group="AIN" index="9" function="B_ADC" pad="PB01"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="12" function="B_ADC" pad="PB04"/>
+              <signal group="AIN" index="13" function="B_ADC" pad="PB05"/>
+              <signal group="AIN" index="14" function="B_ADC" pad="PB06"/>
+              <signal group="AIN" index="15" function="B_ADC" pad="PB07"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="5" function="A" pad="PB05"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB11"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="12" function="A" pad="PB12"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="13" function="A" pad="PB13"/>
+              <signal group="EXTINT" index="14" function="A" pad="PB14"/>
+              <signal group="EXTINT" index="14" function="A" pad="PB30"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="EXTINT" index="15" function="A" pad="PB15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PB31"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PB14"/>
+              <signal group="IO" index="0" function="H" pad="PB22"/>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PB15"/>
+              <signal group="IO" index="1" function="H" pad="PB23"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PB16"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="3" function="H" pad="PB17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="4" function="H" pad="PB10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="5" function="H" pad="PB11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="6" function="H" pad="PB12"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+              <signal group="IO" index="7" function="H" pad="PB13"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="FS" index="1" function="G" pad="PB12"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="MCK" index="0" function="G" pad="PB17"/>
+              <signal group="MCK" index="1" function="G" pad="PB10"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SCK" index="1" function="G" pad="PB11"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+              <signal group="SD" index="1" function="G" pad="PB16"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="131072"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="2048"/>
+              <param name="PAGES_PR_REGION" value="128"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="32" function="default" pad="PB00"/>
+              <signal group="P" index="33" function="default" pad="PB01"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="36" function="default" pad="PB04"/>
+              <signal group="P" index="37" function="default" pad="PB05"/>
+              <signal group="P" index="38" function="default" pad="PB06"/>
+              <signal group="P" index="39" function="default" pad="PB07"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="43" function="default" pad="PB11"/>
+              <signal group="P" index="44" function="default" pad="PB12"/>
+              <signal group="P" index="45" function="default" pad="PB13"/>
+              <signal group="P" index="46" function="default" pad="PB14"/>
+              <signal group="P" index="47" function="default" pad="PB15"/>
+              <signal group="P" index="48" function="default" pad="PB16"/>
+              <signal group="P" index="49" function="default" pad="PB17"/>
+              <signal group="P" index="54" function="default" pad="PB22"/>
+              <signal group="P" index="55" function="default" pad="PB23"/>
+              <signal group="P" index="62" function="default" pad="PB30"/>
+              <signal group="P" index="63" function="default" pad="PB31"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="X" index="12" function="B_PTC" pad="PB12"/>
+              <signal group="X" index="13" function="B_PTC" pad="PB13"/>
+              <signal group="X" index="14" function="B_PTC" pad="PB14"/>
+              <signal group="X" index="15" function="B_PTC" pad="PB15"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="6" function="B_PTC" pad="PB00"/>
+              <signal group="Y" index="7" function="B_PTC" pad="PB01"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="10" function="B_PTC" pad="PB04"/>
+              <signal group="Y" index="11" function="B_PTC" pad="PB05"/>
+              <signal group="Y" index="12" function="B_PTC" pad="PB06"/>
+              <signal group="Y" index="13" function="B_PTC" pad="PB07"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="0" function="C" pad="PB12"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="1" function="C" pad="PB13"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="2" function="D" pad="PB10"/>
+              <signal group="PAD" index="2" function="C" pad="PB14"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+              <signal group="PAD" index="3" function="D" pad="PB11"/>
+              <signal group="PAD" index="3" function="C" pad="PB15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PB16"/>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="0" function="D" pad="PB30"/>
+              <signal group="PAD" index="1" function="C" pad="PB17"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="1" function="D" pad="PB31"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="D" pad="PB00"/>
+              <signal group="PAD" index="2" function="D" pad="PB22"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="D" pad="PB01"/>
+              <signal group="PAD" index="3" function="D" pad="PB23"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="0" function="E" pad="PB12"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+              <signal group="WO" index="1" function="E" pad="PB13"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="0" function="E" pad="PB10"/>
+              <signal group="WO" index="0" function="E" pad="PB14"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+              <signal group="WO" index="1" function="E" pad="PB11"/>
+              <signal group="WO" index="1" function="E" pad="PB15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+          <instance name="TC6">
+            <register-group name="TC6" name-in-module="TC" address-space="base" offset="0x42003800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PB02"/>
+              <signal group="WO" index="0" function="E" pad="PB16"/>
+              <signal group="WO" index="1" function="E" pad="PB03"/>
+              <signal group="WO" index="1" function="E" pad="PB17"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="33"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="78"/>
+            </parameters>
+          </instance>
+          <instance name="TC7">
+            <register-group name="TC7" name-in-module="TC" address-space="base" offset="0x42003C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA20"/>
+              <signal group="WO" index="0" function="E" pad="PB00"/>
+              <signal group="WO" index="0" function="E" pad="PB22"/>
+              <signal group="WO" index="1" function="E" pad="PA21"/>
+              <signal group="WO" index="1" function="E" pad="PB01"/>
+              <signal group="WO" index="1" function="E" pad="PB23"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="36"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="79"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="0" function="E" pad="PB30"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="1" function="E" pad="PB31"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="4" function="F" pad="PB10"/>
+              <signal group="WO" index="4" function="F" pad="PB16"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="5" function="F" pad="PB11"/>
+              <signal group="WO" index="5" function="F" pad="PB17"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PB12"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PB13"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="2" function="F" pad="PB30"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+              <signal group="WO" index="3" function="F" pad="PB31"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="TC6_IRQn" index="21" module-instance="TC6"/>
+        <interrupt name="TC7_IRQn" index="22" module-instance="TC7"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x10010301"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x10010301" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="TC6_" caption="TC6 APB Clock Enable" mask="0x4000"/>
+          <bitfield name="TC7_" caption="TC7 APB Clock Enable" mask="0x8000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21JC" caption="SAMD21JC">
+      <pin position="A1" pad="PB02"/>
+      <pin position="A2" pad="PB01"/>
+      <pin position="A3" pad="VDDIN"/>
+      <pin position="A4" pad="VDDCORE"/>
+      <pin position="A5" pad="GNDIO"/>
+      <pin position="A6" pad="PA28"/>
+      <pin position="A7" pad="PB23"/>
+      <pin position="A8" pad="PB22"/>
+      <pin position="B1" pad="PA00"/>
+      <pin position="B2" pad="PB00"/>
+      <pin position="B3" pad="PB31"/>
+      <pin position="B4" pad="PA31"/>
+      <pin position="B5" pad="PA30"/>
+      <pin position="B6" pad="RESET_N"/>
+      <pin position="B7" pad="PA27"/>
+      <pin position="B8" pad="VDDIO04"/>
+      <pin position="C1" pad="PA01"/>
+      <pin position="C2" pad="PB03"/>
+      <pin position="C3" pad="PA02"/>
+      <pin position="C4" pad="PB30"/>
+      <pin position="C5" pad="PA21"/>
+      <pin position="C6" pad="PA22"/>
+      <pin position="C7" pad="PA23"/>
+      <pin position="C8" pad="GNDIO04"/>
+      <pin position="D1" pad="GNDANA"/>
+      <pin position="D2" pad="PB04"/>
+      <pin position="D3" pad="PA03"/>
+      <pin position="D4" pad="PB05"/>
+      <pin position="D5" pad="PB17"/>
+      <pin position="D6" pad="PA20"/>
+      <pin position="D7" pad="PB16"/>
+      <pin position="D8" pad="PA25"/>
+      <pin position="E1" pad="VDDANA"/>
+      <pin position="E2" pad="PB08"/>
+      <pin position="E3" pad="PB07"/>
+      <pin position="E4" pad="PB06"/>
+      <pin position="E5" pad="PB11"/>
+      <pin position="E6" pad="PB15"/>
+      <pin position="E7" pad="PA19"/>
+      <pin position="E8" pad="PA24"/>
+      <pin position="F1" pad="PA04"/>
+      <pin position="F2" pad="PA05"/>
+      <pin position="F3" pad="PA10"/>
+      <pin position="F4" pad="PB09"/>
+      <pin position="F5" pad="PB12"/>
+      <pin position="F6" pad="PA12"/>
+      <pin position="F7" pad="PA18"/>
+      <pin position="F8" pad="PA17"/>
+      <pin position="G1" pad="PA07"/>
+      <pin position="G2" pad="PA06"/>
+      <pin position="G3" pad="PA11"/>
+      <pin position="G4" pad="PB10"/>
+      <pin position="G5" pad="PB13"/>
+      <pin position="G6" pad="PA13"/>
+      <pin position="G7" pad="PA16"/>
+      <pin position="G8" pad="VDDIO03"/>
+      <pin position="H1" pad="PA08"/>
+      <pin position="H2" pad="PA09"/>
+      <pin position="H3" pad="VDDIO02"/>
+      <pin position="H4" pad="GNDIO02"/>
+      <pin position="H5" pad="PB14"/>
+      <pin position="H6" pad="PA14"/>
+      <pin position="H7" pad="PA15"/>
+      <pin position="H8" pad="GNDIO03"/>
+    </pinout>
+    <pinout name="SAMD21J" caption="SAMD21J">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PB04"/>
+      <pin position="6" pad="PB05"/>
+      <pin position="7" pad="GNDANA"/>
+      <pin position="8" pad="VDDANA"/>
+      <pin position="9" pad="PB06"/>
+      <pin position="10" pad="PB07"/>
+      <pin position="11" pad="PB08"/>
+      <pin position="12" pad="PB09"/>
+      <pin position="13" pad="PA04"/>
+      <pin position="14" pad="PA05"/>
+      <pin position="15" pad="PA06"/>
+      <pin position="16" pad="PA07"/>
+      <pin position="17" pad="PA08"/>
+      <pin position="18" pad="PA09"/>
+      <pin position="19" pad="PA10"/>
+      <pin position="20" pad="PA11"/>
+      <pin position="21" pad="VDDIO02"/>
+      <pin position="22" pad="GNDIO02"/>
+      <pin position="23" pad="PB10"/>
+      <pin position="24" pad="PB11"/>
+      <pin position="25" pad="PB12"/>
+      <pin position="26" pad="PB13"/>
+      <pin position="27" pad="PB14"/>
+      <pin position="28" pad="PB15"/>
+      <pin position="29" pad="PA12"/>
+      <pin position="30" pad="PA13"/>
+      <pin position="31" pad="PA14"/>
+      <pin position="32" pad="PA15"/>
+      <pin position="33" pad="GNDIO03"/>
+      <pin position="34" pad="VDDIO03"/>
+      <pin position="35" pad="PA16"/>
+      <pin position="36" pad="PA17"/>
+      <pin position="37" pad="PA18"/>
+      <pin position="38" pad="PA19"/>
+      <pin position="39" pad="PB16"/>
+      <pin position="40" pad="PB17"/>
+      <pin position="41" pad="PA20"/>
+      <pin position="42" pad="PA21"/>
+      <pin position="43" pad="PA22"/>
+      <pin position="44" pad="PA23"/>
+      <pin position="45" pad="PA24"/>
+      <pin position="46" pad="PA25"/>
+      <pin position="47" pad="GNDIO04"/>
+      <pin position="48" pad="VDDIO04"/>
+      <pin position="49" pad="PB22"/>
+      <pin position="50" pad="PB23"/>
+      <pin position="51" pad="PA27"/>
+      <pin position="52" pad="RESET_N"/>
+      <pin position="53" pad="PA28"/>
+      <pin position="54" pad="GNDIO"/>
+      <pin position="55" pad="VDDCORE"/>
+      <pin position="56" pad="VDDIN"/>
+      <pin position="57" pad="PA30"/>
+      <pin position="58" pad="PA31"/>
+      <pin position="59" pad="PB30"/>
+      <pin position="60" pad="PB31"/>
+      <pin position="61" pad="PB00"/>
+      <pin position="62" pad="PB01"/>
+      <pin position="63" pad="PB02"/>
+      <pin position="64" pad="PB03"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J18A.atdf b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J18A.atdf
new file mode 100644
index 00000000..fc34b9b1
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/atdf/ATSAMD21J18A.atdf
@@ -0,0 +1,5294 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- ============================================================================ -->
+<!--                  Atmel Microcontroller Software Support                      -->
+<!-- ============================================================================ -->
+<!-- Copyright (c) 2016 Atmel Corporation,                                        -->
+<!--                    a wholly owned subsidiary of Microchip Technology Inc.    -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");              -->
+<!-- you may not use this file except in compliance with the License.             -->
+<!-- You may obtain a copy of the Licence at                                      -->
+<!--                                                                              -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                               -->
+<!--                                                                              -->
+<!-- Unless required by applicable law or agreed to in writing, software          -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,            -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.     -->
+<!-- See the License for the specific language governing permissions and          -->
+<!-- limitations under the License.                                               -->
+<!-- ============================================================================ -->
+<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
+  <variants>
+    <variant ordercode="SAMD21J18A-CU" package="CTBGA64" pinout="SAMD21JC" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J18A-MU" package="QFN64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J18A-MF" package="QFN64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J18A-AU" package="TQFP64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="85" vccmin="1.62" vccmax="3.63"/>
+    <variant ordercode="SAMD21J18A-AF" package="TQFP64" pinout="SAMD21J" speedmax="48000000" tempmin="-40" tempmax="125" vccmin="1.62" vccmax="3.63"/>
+  </variants>
+  <devices>
+    <device name="ATSAMD21J18A" architecture="CORTEX-M0PLUS" family="SAMD" series="SAMD21">
+      <address-spaces>
+        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
+          <memory-segment name="FLASH" start="0x00000000" size="0x40000" type="flash" pagesize="64" rw="RW" exec="true"/>
+          <memory-segment name="USER_PAGE" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX0" start="0x00804000" size="0x100" type="user_page" pagesize="64" rw="RW"/>
+          <memory-segment name="AUX1" start="0x00806000" size="0x100" type="fuses" pagesize="64" rw="R"/>
+          <memory-segment name="HMCRAMC0" start="0x20000000" size="0x8000" type="ram" rw="RW" exec="true"/>
+          <memory-segment name="HPB0" start="0x40000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB1" start="0x41000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="HPB2" start="0x42000000" size="0x10000" type="io" rw="RW"/>
+          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
+          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
+          <memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io" rw="RW"/>
+        </address-space>
+        <address-space id="fuses" name="fuses" start="0x00800000" size="0x10000" endianness="little"/>
+      </address-spaces>
+      <parameters>
+        <param name="LITTLE_ENDIAN" value="1"/>
+        <param name="__CM0PLUS_REV" value="0x0001"/>
+        <param name="__MPU_PRESENT" value="0"/>
+        <param name="__NVIC_PRIO_BITS" value="2"/>
+        <param name="__VTOR_PRESENT" value="1"/>
+        <param name="__Vendor_SysTickConfig" value="0"/>
+      </parameters>
+      <peripherals>
+        <module name="AC" id="U2205" version="1.1.1">
+          <instance name="AC">
+            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42004400"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
+              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
+              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
+              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
+              <signal group="CMP" index="0" function="H" pad="PA12"/>
+              <signal group="CMP" index="0" function="H" pad="PA18"/>
+              <signal group="CMP" index="1" function="H" pad="PA13"/>
+              <signal group="CMP" index="1" function="H" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="CMP_NUM" value="2"/>
+              <param name="GCLK_ID_ANA" value="32"/>
+              <param name="GCLK_ID_DIG" value="31"/>
+              <param name="NUM_CMP" value="2"/>
+              <param name="PAIRS" value="1"/>
+              <param name="INSTANCE_ID" value="81"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="ADC" id="U2204" version="1.2.0">
+          <instance name="ADC">
+            <register-group name="ADC" name-in-module="ADC" address-space="base" offset="0x42004000"/>
+            <signals>
+              <signal group="AIN" index="0" function="B_ADC" pad="PA02"/>
+              <signal group="AIN" index="1" function="B_ADC" pad="PA03"/>
+              <signal group="AIN" index="2" function="B_ADC" pad="PB08"/>
+              <signal group="AIN" index="3" function="B_ADC" pad="PB09"/>
+              <signal group="AIN" index="4" function="B_ADC" pad="PA04"/>
+              <signal group="AIN" index="5" function="B_ADC" pad="PA05"/>
+              <signal group="AIN" index="6" function="B_ADC" pad="PA06"/>
+              <signal group="AIN" index="7" function="B_ADC" pad="PA07"/>
+              <signal group="AIN" index="8" function="B_ADC" pad="PB00"/>
+              <signal group="AIN" index="9" function="B_ADC" pad="PB01"/>
+              <signal group="AIN" index="10" function="B_ADC" pad="PB02"/>
+              <signal group="AIN" index="11" function="B_ADC" pad="PB03"/>
+              <signal group="AIN" index="12" function="B_ADC" pad="PB04"/>
+              <signal group="AIN" index="13" function="B_ADC" pad="PB05"/>
+              <signal group="AIN" index="14" function="B_ADC" pad="PB06"/>
+              <signal group="AIN" index="15" function="B_ADC" pad="PB07"/>
+              <signal group="AIN" index="16" function="B_ADC" pad="PA08"/>
+              <signal group="AIN" index="17" function="B_ADC" pad="PA09"/>
+              <signal group="AIN" index="18" function="B_ADC" pad="PA10"/>
+              <signal group="AIN" index="19" function="B_ADC" pad="PA11"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA04"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RESRDY" value="39"/>
+              <param name="EXTCHANNEL_MSB" value="19"/>
+              <param name="GCLK_ID" value="30"/>
+              <param name="RESULT_BITS" value="16"/>
+              <param name="RESULT_MSB" value="15"/>
+              <param name="INSTANCE_ID" value="80"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DAC" id="U2214" version="1.1.0">
+          <instance name="DAC">
+            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x42004800"/>
+            <signals>
+              <signal group="VOUT" function="B_DAC" pad="PA02"/>
+              <signal group="VREFP" function="B_ANAREF" pad="PA03"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_EMPTY" value="40"/>
+              <param name="GCLK_ID" value="33"/>
+              <param name="INSTANCE_ID" value="82"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DMAC" id="U2223" version="1.0.0">
+          <instance name="DMAC">
+            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x41004800"/>
+            <parameters>
+              <param name="CH_BITS" value="4"/>
+              <param name="CH_NUM" value="12"/>
+              <param name="EVIN_NUM" value="4"/>
+              <param name="EVOUT_NUM" value="4"/>
+              <param name="LVL_BITS" value="2"/>
+              <param name="LVL_NUM" value="4"/>
+              <param name="TRIG_BITS" value="6"/>
+              <param name="TRIG_NUM" value="45"/>
+              <param name="INSTANCE_ID" value="36"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="DSU" id="U2209" version="2.0.0">
+          <instance name="DSU">
+            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="33"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EIC" id="U2217" version="1.0.1">
+          <instance name="EIC">
+            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40001800"/>
+            <signals>
+              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB00"/>
+              <signal group="EXTINT" index="0" function="A" pad="PB16"/>
+              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB01"/>
+              <signal group="EXTINT" index="1" function="A" pad="PB17"/>
+              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
+              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
+              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
+              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
+              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
+              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
+              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
+              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
+              <signal group="EXTINT" index="5" function="A" pad="PB05"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB06"/>
+              <signal group="EXTINT" index="6" function="A" pad="PB22"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB07"/>
+              <signal group="EXTINT" index="7" function="A" pad="PB23"/>
+              <signal group="EXTINT" index="8" function="A" pad="PA28"/>
+              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
+              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
+              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
+              <signal group="EXTINT" index="10" function="A" pad="PA30"/>
+              <signal group="EXTINT" index="10" function="A" pad="PB10"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
+              <signal group="EXTINT" index="11" function="A" pad="PA31"/>
+              <signal group="EXTINT" index="11" function="A" pad="PB11"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
+              <signal group="EXTINT" index="12" function="A" pad="PA24"/>
+              <signal group="EXTINT" index="12" function="A" pad="PB12"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
+              <signal group="EXTINT" index="13" function="A" pad="PA25"/>
+              <signal group="EXTINT" index="13" function="A" pad="PB13"/>
+              <signal group="EXTINT" index="14" function="A" pad="PB14"/>
+              <signal group="EXTINT" index="14" function="A" pad="PB30"/>
+              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PA27"/>
+              <signal group="EXTINT" index="15" function="A" pad="PB15"/>
+              <signal group="EXTINT" index="15" function="A" pad="PB31"/>
+              <signal group="NMI" function="A" pad="PA08"/>
+            </signals>
+            <parameters>
+              <param name="CONFIG_NUM" value="2"/>
+              <param name="EXTINT_NUM" value="16"/>
+              <param name="GCLK_ID" value="5"/>
+              <param name="INSTANCE_ID" value="6"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="EVSYS" id="U2208" version="1.0.1">
+          <instance name="EVSYS">
+            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x42000400"/>
+            <parameters>
+              <param name="CHANNELS" value="12"/>
+              <param name="CHANNELS_BITS" value="4"/>
+              <param name="CHANNELS_MSB" value="11"/>
+              <param name="EXTEVT_NUM" value="0"/>
+              <param name="GENERATORS" value="73"/>
+              <param name="GENERATORS_BITS" value="7"/>
+              <param name="USERS" value="29"/>
+              <param name="USERS_BITS" value="5"/>
+              <param name="INSTANCE_ID" value="65"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="GCLK" id="U2102" version="2.1.0">
+          <instance name="GCLK">
+            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40000C00"/>
+            <signals>
+              <signal group="IO" index="0" function="H" pad="PB14"/>
+              <signal group="IO" index="0" function="H" pad="PB22"/>
+              <signal group="IO" index="0" function="H" pad="PA14"/>
+              <signal group="IO" index="0" function="H" pad="PA27"/>
+              <signal group="IO" index="0" function="H" pad="PA28"/>
+              <signal group="IO" index="0" function="H" pad="PA30"/>
+              <signal group="IO" index="1" function="H" pad="PB15"/>
+              <signal group="IO" index="1" function="H" pad="PB23"/>
+              <signal group="IO" index="1" function="H" pad="PA15"/>
+              <signal group="IO" index="2" function="H" pad="PB16"/>
+              <signal group="IO" index="2" function="H" pad="PA16"/>
+              <signal group="IO" index="3" function="H" pad="PA17"/>
+              <signal group="IO" index="3" function="H" pad="PB17"/>
+              <signal group="IO" index="4" function="H" pad="PA10"/>
+              <signal group="IO" index="4" function="H" pad="PA20"/>
+              <signal group="IO" index="4" function="H" pad="PB10"/>
+              <signal group="IO" index="5" function="H" pad="PA11"/>
+              <signal group="IO" index="5" function="H" pad="PA21"/>
+              <signal group="IO" index="5" function="H" pad="PB11"/>
+              <signal group="IO" index="6" function="H" pad="PA22"/>
+              <signal group="IO" index="6" function="H" pad="PB12"/>
+              <signal group="IO" index="7" function="H" pad="PA23"/>
+              <signal group="IO" index="7" function="H" pad="PB13"/>
+            </signals>
+            <parameters>
+              <param name="GENDIV_BITS" value="16"/>
+              <param name="GEN_NUM" value="9"/>
+              <param name="GEN_NUM_MSB" value="8"/>
+              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
+              <param name="NUM" value="37"/>
+              <param name="SOURCE_DFLL48M" value="7"/>
+              <param name="SOURCE_FDPLL" value="8"/>
+              <param name="SOURCE_GCLKGEN1" value="2"/>
+              <param name="SOURCE_GCLKIN" value="1"/>
+              <param name="SOURCE_NUM" value="9"/>
+              <param name="SOURCE_OSCULP32K" value="3"/>
+              <param name="SOURCE_OSC8M" value="6"/>
+              <param name="SOURCE_OSC32K" value="4"/>
+              <param name="SOURCE_XOSC" value="0"/>
+              <param name="SOURCE_XOSC32K" value="5"/>
+              <param name="INSTANCE_ID" value="3"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="HMATRIXB" id="I7638" version="2.1.2">
+          <instance name="SBMATRIX">
+            <register-group name="SBMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x41007000"/>
+            <parameters>
+              <param name="MASTER_NUM" value="3"/>
+              <param name="MASTER_CM0PLUS" value="0"/>
+              <param name="MASTER_DSU" value="1"/>
+              <param name="MASTER_DMAC" value="2"/>
+              <param name="SLAVE_NUM" value="7"/>
+              <param name="SLAVE_FLASH" value="0"/>
+              <param name="SLAVE_HPB0" value="1"/>
+              <param name="SLAVE_HPB1" value="2"/>
+              <param name="SLAVE_HPB2" value="3"/>
+              <param name="SLAVE_HMCRAMC0" value="4"/>
+              <param name="SLAVE_HMCRAMC0_ALT0" value="5"/>
+              <param name="SLAVE_HMCRAMC0_ALT1" value="6"/>
+              <param name="INSTANCE_ID" value="39"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="I2S" id="U2224" version="1.0.2">
+          <instance name="I2S">
+            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x42005000"/>
+            <signals>
+              <signal group="FS" index="0" function="G" pad="PA11"/>
+              <signal group="FS" index="0" function="G" pad="PA21"/>
+              <signal group="FS" index="1" function="G" pad="PB12"/>
+              <signal group="MCK" index="0" function="G" pad="PA09"/>
+              <signal group="MCK" index="0" function="G" pad="PB17"/>
+              <signal group="MCK" index="1" function="G" pad="PB10"/>
+              <signal group="SCK" index="0" function="G" pad="PA10"/>
+              <signal group="SCK" index="0" function="G" pad="PA20"/>
+              <signal group="SCK" index="1" function="G" pad="PB11"/>
+              <signal group="SD" index="0" function="G" pad="PA07"/>
+              <signal group="SD" index="0" function="G" pad="PA19"/>
+              <signal group="SD" index="1" function="G" pad="PA08"/>
+              <signal group="SD" index="1" function="G" pad="PB16"/>
+            </signals>
+            <parameters>
+              <param name="CLK_NUM" value="2"/>
+              <param name="MAX_SLOTS" value="8"/>
+              <param name="SER_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="84"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="MTB" id="U2002" version="1.0.0">
+          <instance name="MTB">
+            <register-group name="MTB" name-in-module="MTB" address-space="base" offset="0x41006000"/>
+            <parameters>
+              <param name="INSTANCE_ID" value="38"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="NVMCTRL" id="U2207" version="1.0.6">
+          <instance name="NVMCTRL">
+            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
+            <signals>
+              <signal group="MARGIN" function="default" pad="VMARGIN"/>
+            </signals>
+            <parameters>
+              <param name="FACTORY_WORD_IMPLEMENTED_MASK" value="0xC0000007FFFFFFFF"/>
+              <param name="PMSB" value="3"/>
+              <param name="PSZ_BITS" value="6"/>
+              <param name="ROW_PAGES" value="4"/>
+              <param name="USER_PAGE_OFFSET" value="0x00800000"/>
+              <param name="USER_WORD_IMPLEMENTED_MASK" value="0xC01FFFFFFFFFFFFF"/>
+              <param name="FLASH_SIZE" value="262144"/>
+              <param name="PAGE_SIZE" value="64"/>
+              <param name="PAGES" value="4096"/>
+              <param name="PAGES_PR_REGION" value="256"/>
+                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
+                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
+                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
+                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
+                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
+                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
+                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
+                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
+              <param name="INSTANCE_ID" value="34"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="FUSES" id="U2207" version="1.0.6">
+          <instance name="FUSES">
+            <register-group name="OTP4_FUSES" name-in-module="OTP4_FUSES" address-space="fuses" offset="0x00806020"/>
+            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00806030"/>
+            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
+          </instance>
+        </module>
+        <module name="PAC" id="U2211" version="1.0.1">
+          <instance name="PAC0">
+            <register-group name="PAC0" name-in-module="PAC" address-space="base" offset="0x40000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000000"/>
+              <param name="INSTANCE_ID" value="0"/>
+            </parameters>
+          </instance>
+          <instance name="PAC1">
+            <register-group name="PAC1" name-in-module="PAC" address-space="base" offset="0x41000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00000002"/>
+              <param name="INSTANCE_ID" value="32"/>
+            </parameters>
+          </instance>
+          <instance name="PAC2">
+            <register-group name="PAC2" name-in-module="PAC" address-space="base" offset="0x42000000"/>
+            <parameters>
+              <param name="WPROT_DEFAULT_VAL" value="0x00800000"/>
+              <param name="INSTANCE_ID" value="64"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PM" id="U2206" version="2.0.1">
+          <instance name="PM">
+            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
+            <signals>
+              <signal group="RESET_N" function="default" pad="RESET_N"/>
+            </signals>
+            <parameters>
+              <param name="CTRL_MCSEL_DFLL48M" value="3"/>
+              <param name="CTRL_MCSEL_GCLK" value="0"/>
+              <param name="CTRL_MCSEL_OSC8M" value="1"/>
+              <param name="CTRL_MCSEL_XOSC" value="2"/>
+              <param name="PM_CLK_APB_NUM" value="2"/>
+              <param name="INSTANCE_ID" value="1"/>
+            </parameters>
+            <clock-groups>
+              <clock-group name="AHB" grouporder="0">
+                <clock name="HPB0" bit="0"/>
+                <clock name="HPB1" bit="1"/>
+                <clock name="HPB2" bit="2"/>
+                <clock name="DSU" bit="3"/>
+                <clock name="NVMCTRL" bit="4"/>
+                <clock name="DMAC" bit="5"/>
+                <clock name="USB" bit="6"/>
+              </clock-group>
+            </clock-groups>
+          </instance>
+        </module>
+        <module name="PORT" id="U2210" version="1.0.0">
+          <instance name="PORT">
+            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41004400"/>
+            <register-group name="PORT_IOBUS" name-in-module="PORT" address-space="base" offset="0x60000000"/>
+            <signals>
+              <signal group="P" index="0" function="default" pad="PA00"/>
+              <signal group="P" index="1" function="default" pad="PA01"/>
+              <signal group="P" index="2" function="default" pad="PA02"/>
+              <signal group="P" index="3" function="default" pad="PA03"/>
+              <signal group="P" index="4" function="default" pad="PA04"/>
+              <signal group="P" index="5" function="default" pad="PA05"/>
+              <signal group="P" index="6" function="default" pad="PA06"/>
+              <signal group="P" index="7" function="default" pad="PA07"/>
+              <signal group="P" index="8" function="default" pad="PA08"/>
+              <signal group="P" index="9" function="default" pad="PA09"/>
+              <signal group="P" index="10" function="default" pad="PA10"/>
+              <signal group="P" index="11" function="default" pad="PA11"/>
+              <signal group="P" index="12" function="default" pad="PA12"/>
+              <signal group="P" index="13" function="default" pad="PA13"/>
+              <signal group="P" index="14" function="default" pad="PA14"/>
+              <signal group="P" index="15" function="default" pad="PA15"/>
+              <signal group="P" index="16" function="default" pad="PA16"/>
+              <signal group="P" index="17" function="default" pad="PA17"/>
+              <signal group="P" index="18" function="default" pad="PA18"/>
+              <signal group="P" index="19" function="default" pad="PA19"/>
+              <signal group="P" index="20" function="default" pad="PA20"/>
+              <signal group="P" index="21" function="default" pad="PA21"/>
+              <signal group="P" index="22" function="default" pad="PA22"/>
+              <signal group="P" index="23" function="default" pad="PA23"/>
+              <signal group="P" index="24" function="default" pad="PA24"/>
+              <signal group="P" index="25" function="default" pad="PA25"/>
+              <signal group="P" index="27" function="default" pad="PA27"/>
+              <signal group="P" index="28" function="default" pad="PA28"/>
+              <signal group="P" index="30" function="default" pad="PA30"/>
+              <signal group="P" index="31" function="default" pad="PA31"/>
+              <signal group="P" index="32" function="default" pad="PB00"/>
+              <signal group="P" index="33" function="default" pad="PB01"/>
+              <signal group="P" index="34" function="default" pad="PB02"/>
+              <signal group="P" index="35" function="default" pad="PB03"/>
+              <signal group="P" index="36" function="default" pad="PB04"/>
+              <signal group="P" index="37" function="default" pad="PB05"/>
+              <signal group="P" index="38" function="default" pad="PB06"/>
+              <signal group="P" index="39" function="default" pad="PB07"/>
+              <signal group="P" index="40" function="default" pad="PB08"/>
+              <signal group="P" index="41" function="default" pad="PB09"/>
+              <signal group="P" index="42" function="default" pad="PB10"/>
+              <signal group="P" index="43" function="default" pad="PB11"/>
+              <signal group="P" index="44" function="default" pad="PB12"/>
+              <signal group="P" index="45" function="default" pad="PB13"/>
+              <signal group="P" index="46" function="default" pad="PB14"/>
+              <signal group="P" index="47" function="default" pad="PB15"/>
+              <signal group="P" index="48" function="default" pad="PB16"/>
+              <signal group="P" index="49" function="default" pad="PB17"/>
+              <signal group="P" index="54" function="default" pad="PB22"/>
+              <signal group="P" index="55" function="default" pad="PB23"/>
+              <signal group="P" index="62" function="default" pad="PB30"/>
+              <signal group="P" index="63" function="default" pad="PB31"/>
+            </signals>
+            <parameters>
+              <param name="BITS" value="84"/>
+              <param name="DRVSTR" value="1"/>
+              <param name="GROUPS" value="2"/>
+              <param name="ODRAIN" value="0"/>
+              <param name="SLEWLIM" value="0"/>
+              <param name="INSTANCE_ID" value="35"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="PTC" id="U2215" version="1.0.2">
+          <instance name="PTC">
+            <register-group name="PTC" name-in-module="PTC" address-space="base" offset="0x42004C00"/>
+            <signals>
+              <signal group="X" index="0" function="B_PTC" pad="PA08"/>
+              <signal group="X" index="1" function="B_PTC" pad="PA09"/>
+              <signal group="X" index="2" function="B_PTC" pad="PA10"/>
+              <signal group="X" index="3" function="B_PTC" pad="PA11"/>
+              <signal group="X" index="4" function="B_PTC" pad="PA16"/>
+              <signal group="X" index="5" function="B_PTC" pad="PA17"/>
+              <signal group="X" index="6" function="B_PTC" pad="PA18"/>
+              <signal group="X" index="7" function="B_PTC" pad="PA19"/>
+              <signal group="X" index="8" function="B_PTC" pad="PA20"/>
+              <signal group="X" index="9" function="B_PTC" pad="PA21"/>
+              <signal group="X" index="10" function="B_PTC" pad="PA22"/>
+              <signal group="X" index="11" function="B_PTC" pad="PA23"/>
+              <signal group="X" index="12" function="B_PTC" pad="PB12"/>
+              <signal group="X" index="13" function="B_PTC" pad="PB13"/>
+              <signal group="X" index="14" function="B_PTC" pad="PB14"/>
+              <signal group="X" index="15" function="B_PTC" pad="PB15"/>
+              <signal group="Y" index="0" function="B_PTC" pad="PA02"/>
+              <signal group="Y" index="1" function="B_PTC" pad="PA03"/>
+              <signal group="Y" index="2" function="B_PTC" pad="PA04"/>
+              <signal group="Y" index="3" function="B_PTC" pad="PA05"/>
+              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
+              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
+              <signal group="Y" index="6" function="B_PTC" pad="PB00"/>
+              <signal group="Y" index="7" function="B_PTC" pad="PB01"/>
+              <signal group="Y" index="8" function="B_PTC" pad="PB02"/>
+              <signal group="Y" index="9" function="B_PTC" pad="PB03"/>
+              <signal group="Y" index="10" function="B_PTC" pad="PB04"/>
+              <signal group="Y" index="11" function="B_PTC" pad="PB05"/>
+              <signal group="Y" index="12" function="B_PTC" pad="PB06"/>
+              <signal group="Y" index="13" function="B_PTC" pad="PB07"/>
+              <signal group="Y" index="14" function="B_PTC" pad="PB08"/>
+              <signal group="Y" index="15" function="B_PTC" pad="PB09"/>
+            </signals>
+            <parameters>
+              <param name="GCLK_ID" value="34"/>
+              <param name="INSTANCE_ID" value="83"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="RTC" id="U2202" version="1.0.1">
+          <instance name="RTC">
+            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40001400"/>
+            <parameters>
+              <param name="ALARM_NUM" value="1"/>
+              <param name="COMP16_NUM" value="2"/>
+              <param name="COMP32_NUM" value="1"/>
+              <param name="GCLK_ID" value="4"/>
+              <param name="NUM_OF_ALARMS" value="1"/>
+              <param name="NUM_OF_COMP16" value="2"/>
+              <param name="NUM_OF_COMP32" value="1"/>
+              <param name="INSTANCE_ID" value="5"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SERCOM" id="U2201" version="2.0.0">
+          <instance name="SERCOM0">
+            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x42000800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA04"/>
+              <signal group="PAD" index="0" function="C" pad="PA08"/>
+              <signal group="PAD" index="1" function="D" pad="PA05"/>
+              <signal group="PAD" index="1" function="C" pad="PA09"/>
+              <signal group="PAD" index="2" function="D" pad="PA06"/>
+              <signal group="PAD" index="2" function="C" pad="PA10"/>
+              <signal group="PAD" index="3" function="D" pad="PA07"/>
+              <signal group="PAD" index="3" function="C" pad="PA11"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="1"/>
+              <param name="DMAC_ID_TX" value="2"/>
+              <param name="GCLK_ID_CORE" value="20"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="66"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM1">
+            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x42000C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PA16"/>
+              <signal group="PAD" index="0" function="D" pad="PA00"/>
+              <signal group="PAD" index="1" function="C" pad="PA17"/>
+              <signal group="PAD" index="1" function="D" pad="PA01"/>
+              <signal group="PAD" index="2" function="D" pad="PA30"/>
+              <signal group="PAD" index="2" function="C" pad="PA18"/>
+              <signal group="PAD" index="3" function="D" pad="PA31"/>
+              <signal group="PAD" index="3" function="C" pad="PA19"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="3"/>
+              <param name="DMAC_ID_TX" value="4"/>
+              <param name="GCLK_ID_CORE" value="21"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="67"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM2">
+            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x42001000"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA08"/>
+              <signal group="PAD" index="0" function="C" pad="PA12"/>
+              <signal group="PAD" index="1" function="D" pad="PA09"/>
+              <signal group="PAD" index="1" function="C" pad="PA13"/>
+              <signal group="PAD" index="2" function="D" pad="PA10"/>
+              <signal group="PAD" index="2" function="C" pad="PA14"/>
+              <signal group="PAD" index="3" function="D" pad="PA11"/>
+              <signal group="PAD" index="3" function="C" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="5"/>
+              <param name="DMAC_ID_TX" value="6"/>
+              <param name="GCLK_ID_CORE" value="22"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="68"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM3">
+            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x42001400"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA16"/>
+              <signal group="PAD" index="0" function="C" pad="PA22"/>
+              <signal group="PAD" index="1" function="D" pad="PA17"/>
+              <signal group="PAD" index="1" function="C" pad="PA23"/>
+              <signal group="PAD" index="2" function="D" pad="PA18"/>
+              <signal group="PAD" index="2" function="D" pad="PA20"/>
+              <signal group="PAD" index="2" function="C" pad="PA24"/>
+              <signal group="PAD" index="3" function="D" pad="PA19"/>
+              <signal group="PAD" index="3" function="D" pad="PA21"/>
+              <signal group="PAD" index="3" function="C" pad="PA25"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="7"/>
+              <param name="DMAC_ID_TX" value="8"/>
+              <param name="GCLK_ID_CORE" value="23"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="69"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM4">
+            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x42001800"/>
+            <signals>
+              <signal group="PAD" index="0" function="D" pad="PA12"/>
+              <signal group="PAD" index="0" function="D" pad="PB08"/>
+              <signal group="PAD" index="0" function="C" pad="PB12"/>
+              <signal group="PAD" index="1" function="D" pad="PA13"/>
+              <signal group="PAD" index="1" function="D" pad="PB09"/>
+              <signal group="PAD" index="1" function="C" pad="PB13"/>
+              <signal group="PAD" index="2" function="D" pad="PA14"/>
+              <signal group="PAD" index="2" function="D" pad="PB10"/>
+              <signal group="PAD" index="2" function="C" pad="PB14"/>
+              <signal group="PAD" index="3" function="D" pad="PA15"/>
+              <signal group="PAD" index="3" function="D" pad="PB11"/>
+              <signal group="PAD" index="3" function="C" pad="PB15"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="9"/>
+              <param name="DMAC_ID_TX" value="10"/>
+              <param name="GCLK_ID_CORE" value="24"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="70"/>
+            </parameters>
+          </instance>
+          <instance name="SERCOM5">
+            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x42001C00"/>
+            <signals>
+              <signal group="PAD" index="0" function="C" pad="PB16"/>
+              <signal group="PAD" index="0" function="D" pad="PA22"/>
+              <signal group="PAD" index="0" function="D" pad="PB02"/>
+              <signal group="PAD" index="0" function="D" pad="PB30"/>
+              <signal group="PAD" index="1" function="C" pad="PB17"/>
+              <signal group="PAD" index="1" function="D" pad="PA23"/>
+              <signal group="PAD" index="1" function="D" pad="PB03"/>
+              <signal group="PAD" index="1" function="D" pad="PB31"/>
+              <signal group="PAD" index="2" function="D" pad="PA24"/>
+              <signal group="PAD" index="2" function="D" pad="PB00"/>
+              <signal group="PAD" index="2" function="D" pad="PB22"/>
+              <signal group="PAD" index="2" function="C" pad="PA20"/>
+              <signal group="PAD" index="3" function="D" pad="PA25"/>
+              <signal group="PAD" index="3" function="D" pad="PB01"/>
+              <signal group="PAD" index="3" function="D" pad="PB23"/>
+              <signal group="PAD" index="3" function="C" pad="PA21"/>
+            </signals>
+            <parameters>
+              <param name="DMAC_ID_RX" value="11"/>
+              <param name="DMAC_ID_TX" value="12"/>
+              <param name="GCLK_ID_CORE" value="25"/>
+              <param name="GCLK_ID_SLOW" value="19"/>
+              <param name="INT_MSB" value="6"/>
+              <param name="INSTANCE_ID" value="71"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="SYSCTRL" id="U2100" version="2.0.1">
+          <instance name="SYSCTRL">
+            <register-group name="SYSCTRL" name-in-module="SYSCTRL" address-space="base" offset="0x40000800"/>
+            <signals>
+              <signal group="XIN" function="XIN" pad="PA14"/>
+              <signal group="XIN32" function="XIN32" pad="PA00"/>
+              <signal group="XOUT" function="XOUT" pad="PA15"/>
+              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="BGAP_CALIB_MSB" value="11"/>
+              <param name="BOD33_CALIB_MSB" value="5"/>
+              <param name="DFLL48M_COARSE_MSB" value="5"/>
+              <param name="DFLL48M_FINE_MSB" value="9"/>
+              <param name="GCLK_ID_DFLL48" value="0"/>
+              <param name="GCLK_ID_FDPLL" value="1"/>
+              <param name="GCLK_ID_FDPLL32K" value="2"/>
+              <param name="OSC32K_COARSE_CALIB_MSB" value="6"/>
+              <param name="POR33_ENTEST_MSB" value="1"/>
+              <param name="SYSTEM_CLOCK" value="1000000"/>
+              <param name="ULPVREF_DIVLEV_MSB" value="3"/>
+              <param name="ULPVREG_FORCEGAIN_MSB" value="1"/>
+              <param name="ULPVREG_RAMREFSEL_MSB" value="2"/>
+              <param name="VREF_CONTROL_MSB" value="48"/>
+              <param name="VREF_STATUS_MSB" value="7"/>
+              <param name="VREG_LEVEL_MSB" value="2"/>
+              <param name="BOD12_VERSION" value="0x111"/>
+              <param name="BOD33_VERSION" value="0x111"/>
+              <param name="DFLL48M_VERSION" value="0x301"/>
+              <param name="FDPLL_VERSION" value="0x111"/>
+              <param name="OSCULP32K_VERSION" value="0x111"/>
+              <param name="OSC8M_VERSION" value="0x120"/>
+              <param name="OSC32K_VERSION" value="0x1101"/>
+              <param name="VREF_VERSION" value="0x200"/>
+              <param name="VREG_VERSION" value="0x201"/>
+              <param name="XOSC_VERSION" value="0x1111"/>
+              <param name="XOSC32K_VERSION" value="0x1111"/>
+              <param name="INSTANCE_ID" value="2"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TC" id="U2212" version="1.2.1">
+          <instance name="TC3">
+            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x42002C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA18"/>
+              <signal group="WO" index="0" function="E" pad="PA14"/>
+              <signal group="WO" index="1" function="E" pad="PA19"/>
+              <signal group="WO" index="1" function="E" pad="PA15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="24"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="75"/>
+            </parameters>
+          </instance>
+          <instance name="TC4">
+            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42003000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA22"/>
+              <signal group="WO" index="0" function="E" pad="PB08"/>
+              <signal group="WO" index="0" function="E" pad="PB12"/>
+              <signal group="WO" index="1" function="E" pad="PA23"/>
+              <signal group="WO" index="1" function="E" pad="PB09"/>
+              <signal group="WO" index="1" function="E" pad="PB13"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="27"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="76"/>
+            </parameters>
+          </instance>
+          <instance name="TC5">
+            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42003400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA24"/>
+              <signal group="WO" index="0" function="E" pad="PB10"/>
+              <signal group="WO" index="0" function="E" pad="PB14"/>
+              <signal group="WO" index="1" function="E" pad="PA25"/>
+              <signal group="WO" index="1" function="E" pad="PB11"/>
+              <signal group="WO" index="1" function="E" pad="PB15"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="30"/>
+              <param name="GCLK_ID" value="28"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="77"/>
+            </parameters>
+          </instance>
+          <instance name="TC6">
+            <register-group name="TC6" name-in-module="TC" address-space="base" offset="0x42003800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PB02"/>
+              <signal group="WO" index="0" function="E" pad="PB16"/>
+              <signal group="WO" index="1" function="E" pad="PB03"/>
+              <signal group="WO" index="1" function="E" pad="PB17"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="33"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="1"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="78"/>
+            </parameters>
+          </instance>
+          <instance name="TC7">
+            <register-group name="TC7" name-in-module="TC" address-space="base" offset="0x42003C00"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA20"/>
+              <signal group="WO" index="0" function="E" pad="PB00"/>
+              <signal group="WO" index="0" function="E" pad="PB22"/>
+              <signal group="WO" index="1" function="E" pad="PA21"/>
+              <signal group="WO" index="1" function="E" pad="PB01"/>
+              <signal group="WO" index="1" function="E" pad="PB23"/>
+            </signals>
+            <parameters>
+              <param name="CC8_NUM" value="2"/>
+              <param name="CC16_NUM" value="2"/>
+              <param name="CC32_NUM" value="2"/>
+              <param name="DITHERING_EXT" value="0"/>
+              <param name="DMAC_ID_OVF" value="36"/>
+              <param name="GCLK_ID" value="29"/>
+              <param name="MASTER" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PERIOD_EXT" value="0"/>
+              <param name="SHADOW_EXT" value="0"/>
+              <param name="INSTANCE_ID" value="79"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="TCC" id="U2213" version="1.0.1">
+          <instance name="TCC0">
+            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x42002000"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA04"/>
+              <signal group="WO" index="0" function="E" pad="PA08"/>
+              <signal group="WO" index="0" function="E" pad="PB30"/>
+              <signal group="WO" index="1" function="E" pad="PA05"/>
+              <signal group="WO" index="1" function="E" pad="PA09"/>
+              <signal group="WO" index="1" function="E" pad="PB31"/>
+              <signal group="WO" index="2" function="F" pad="PA10"/>
+              <signal group="WO" index="2" function="F" pad="PA18"/>
+              <signal group="WO" index="3" function="F" pad="PA11"/>
+              <signal group="WO" index="3" function="F" pad="PA19"/>
+              <signal group="WO" index="4" function="F" pad="PA14"/>
+              <signal group="WO" index="4" function="F" pad="PA22"/>
+              <signal group="WO" index="4" function="F" pad="PB10"/>
+              <signal group="WO" index="4" function="F" pad="PB16"/>
+              <signal group="WO" index="5" function="F" pad="PA15"/>
+              <signal group="WO" index="5" function="F" pad="PA23"/>
+              <signal group="WO" index="5" function="F" pad="PB11"/>
+              <signal group="WO" index="5" function="F" pad="PB17"/>
+              <signal group="WO" index="6" function="F" pad="PA12"/>
+              <signal group="WO" index="6" function="F" pad="PA20"/>
+              <signal group="WO" index="6" function="F" pad="PB12"/>
+              <signal group="WO" index="6" function="F" pad="PA16"/>
+              <signal group="WO" index="7" function="F" pad="PA13"/>
+              <signal group="WO" index="7" function="F" pad="PA21"/>
+              <signal group="WO" index="7" function="F" pad="PB13"/>
+              <signal group="WO" index="7" function="F" pad="PA17"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="4"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="13"/>
+              <param name="DTI" value="1"/>
+              <param name="EXT" value="31"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="1"/>
+              <param name="OW_NUM" value="8"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="1"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="72"/>
+            </parameters>
+          </instance>
+          <instance name="TCC1">
+            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x42002400"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA06"/>
+              <signal group="WO" index="0" function="E" pad="PA10"/>
+              <signal group="WO" index="0" function="E" pad="PA30"/>
+              <signal group="WO" index="1" function="E" pad="PA07"/>
+              <signal group="WO" index="1" function="E" pad="PA11"/>
+              <signal group="WO" index="1" function="E" pad="PA31"/>
+              <signal group="WO" index="2" function="F" pad="PA08"/>
+              <signal group="WO" index="2" function="F" pad="PA24"/>
+              <signal group="WO" index="2" function="F" pad="PB30"/>
+              <signal group="WO" index="3" function="F" pad="PA09"/>
+              <signal group="WO" index="3" function="F" pad="PA25"/>
+              <signal group="WO" index="3" function="F" pad="PB31"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="1"/>
+              <param name="DMAC_ID_OVF" value="18"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="24"/>
+              <param name="GCLK_ID" value="26"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="4"/>
+              <param name="PG" value="1"/>
+              <param name="SIZE" value="24"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="73"/>
+            </parameters>
+          </instance>
+          <instance name="TCC2">
+            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42002800"/>
+            <signals>
+              <signal group="WO" index="0" function="E" pad="PA12"/>
+              <signal group="WO" index="0" function="E" pad="PA16"/>
+              <signal group="WO" index="0" function="E" pad="PA00"/>
+              <signal group="WO" index="1" function="E" pad="PA13"/>
+              <signal group="WO" index="1" function="E" pad="PA17"/>
+              <signal group="WO" index="1" function="E" pad="PA01"/>
+            </signals>
+            <parameters>
+              <param name="CC_NUM" value="2"/>
+              <param name="DITHERING" value="0"/>
+              <param name="DMAC_ID_OVF" value="21"/>
+              <param name="DTI" value="0"/>
+              <param name="EXT" value="0"/>
+              <param name="GCLK_ID" value="27"/>
+              <param name="OTMX" value="0"/>
+              <param name="OW_NUM" value="2"/>
+              <param name="PG" value="0"/>
+              <param name="SIZE" value="16"/>
+              <param name="SWAP" value="0"/>
+              <param name="TYPE" value="0"/>
+              <param name="INSTANCE_ID" value="74"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="USB" id="U2222" version="1.0.1">
+          <instance name="USB">
+            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41005000"/>
+            <signals>
+              <signal group="DM" function="G" pad="PA24"/>
+              <signal group="DP" function="G" pad="PA25"/>
+              <signal group="SOF_1KHZ" function="G" pad="PA23"/>
+            </signals>
+            <parameters>
+              <param name="EPT_NBR" value="8"/>
+              <param name="EPT_NUM" value="8"/>
+              <param name="GCLK_ID" value="6"/>
+              <param name="PIPE_NUM" value="8"/>
+              <param name="INSTANCE_ID" value="37"/>
+            </parameters>
+          </instance>
+        </module>
+        <module name="WDT" id="U2203" version="2.0.0">
+          <instance name="WDT">
+            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40001000"/>
+            <parameters>
+              <param name="GCLK_ID" value="3"/>
+              <param name="INSTANCE_ID" value="4"/>
+            </parameters>
+          </instance>
+        </module>
+      <module name="SystemControl">
+          <instance name="SystemControl">
+            <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
+          </instance>
+        </module><module name="SysTick">
+          <instance name="SysTick">
+            <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
+          </instance>
+        </module><module name="NVIC">
+          <instance name="NVIC">
+            <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
+          </instance>
+        </module></peripherals>
+      <interrupts>
+        <interrupt name="NonMaskableInt_IRQn" index="-14" caption="Non Maskable Interrupt"/>
+        <interrupt name="HardFault_IRQn" index="-13" caption="Cortex-M0+ Hard Fault Interrupt"/>
+        <interrupt name="SVCall_IRQn" index="-5" caption="Cortex-M0+ SV Call Interrupt"/>
+        <interrupt name="PendSV_IRQn" index="-2" caption="Cortex-M0+ Pend SV Interrupt"/>
+        <interrupt name="SysTick_IRQn" index="-1" caption="Cortex-M0+ System Tick Interrupt"/>
+        <interrupt name="PM_IRQn" index="0" module-instance="PM"/>
+        <interrupt name="SYSCTRL_IRQn" index="1" module-instance="SYSCTRL"/>
+        <interrupt name="WDT_IRQn" index="2" module-instance="WDT"/>
+        <interrupt name="RTC_IRQn" index="3" module-instance="RTC"/>
+        <interrupt name="EIC_IRQn" index="4" module-instance="EIC"/>
+        <interrupt name="NVMCTRL_IRQn" index="5" module-instance="NVMCTRL"/>
+        <interrupt name="DMAC_IRQn" index="6" module-instance="DMAC"/>
+        <interrupt name="USB_IRQn" index="7" module-instance="USB"/>
+        <interrupt name="EVSYS_IRQn" index="8" module-instance="EVSYS"/>
+        <interrupt name="SERCOM0_IRQn" index="9" module-instance="SERCOM0"/>
+        <interrupt name="SERCOM1_IRQn" index="10" module-instance="SERCOM1"/>
+        <interrupt name="SERCOM2_IRQn" index="11" module-instance="SERCOM2"/>
+        <interrupt name="SERCOM3_IRQn" index="12" module-instance="SERCOM3"/>
+        <interrupt name="SERCOM4_IRQn" index="13" module-instance="SERCOM4"/>
+        <interrupt name="SERCOM5_IRQn" index="14" module-instance="SERCOM5"/>
+        <interrupt name="TCC0_IRQn" index="15" module-instance="TCC0"/>
+        <interrupt name="TCC1_IRQn" index="16" module-instance="TCC1"/>
+        <interrupt name="TCC2_IRQn" index="17" module-instance="TCC2"/>
+        <interrupt name="TC3_IRQn" index="18" module-instance="TC3"/>
+        <interrupt name="TC4_IRQn" index="19" module-instance="TC4"/>
+        <interrupt name="TC5_IRQn" index="20" module-instance="TC5"/>
+        <interrupt name="TC6_IRQn" index="21" module-instance="TC6"/>
+        <interrupt name="TC7_IRQn" index="22" module-instance="TC7"/>
+        <interrupt name="ADC_IRQn" index="23" module-instance="ADC"/>
+        <interrupt name="AC_IRQn" index="24" module-instance="AC"/>
+        <interrupt name="DAC_IRQn" index="25" module-instance="DAC"/>
+        <interrupt name="PTC_IRQn" index="26" module-instance="PTC"/>
+        <interrupt name="I2S_IRQn" index="27" module-instance="I2S"/>
+      </interrupts>
+      <interfaces>
+        <interface name="SWD" type="swd"/>
+      </interfaces>
+      <property-groups>
+        <property-group name="SIGNATURES">
+          <property name="DSU_DID" value="0x10010300"/>
+        </property-group>
+      </property-groups>
+    </device>
+  </devices>
+  <modules>
+    <module name="AC" id="U2205" version="1.1.1" caption="Analog Comparators">
+      <register-group name="AC" caption="Analog Comparators">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+          <bitfield name="LPMUX" caption="Low-Power Mux" mask="0x80"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
+          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
+          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
+          <bitfield name="COMPEI0" caption="Comparator 0 Event Input" mask="0x100"/>
+          <bitfield name="COMPEI1" caption="Comparator 1 Event Input" mask="0x200"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
+          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
+          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x8" rw="R" size="1" initval="0x00" caption="Status A">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
+        </register>
+        <register name="STATUSB" offset="0x9" rw="R" size="1" initval="0x00" caption="Status B">
+          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
+          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="STATUSC" offset="0xA" rw="R" size="1" initval="0x00" caption="Status C">
+          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
+          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
+          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSC__WSTATE0"/>
+        </register>
+        <register name="WINCTRL" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
+          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
+          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
+        </register>
+        <register name="COMPCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
+          <bitfield name="ENABLE" caption="Enable" mask="0x1"/>
+          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x2"/>
+          <bitfield name="SPEED" caption="Speed Selection" mask="0xC" values="AC_COMPCTRL__SPEED"/>
+          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x60" values="AC_COMPCTRL__INTSEL"/>
+          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
+          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x3000" values="AC_COMPCTRL__MUXPOS"/>
+          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
+          <bitfield name="OUT" caption="Output" mask="0x30000" values="AC_COMPCTRL__OUT"/>
+          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x80000"/>
+          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
+        </register>
+        <register name="SCALER" offset="0x20" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
+          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
+        </register>
+      </register-group>
+      <value-group name="AC_STATUSA__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSA__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE0">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_STATUSC__WSTATE1">
+        <value name="ABOVE" caption="Signal is above window" value="0"/>
+        <value name="INSIDE" caption="Signal is inside window" value="1"/>
+        <value name="BELOW" caption="Signal is below window" value="2"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL0">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_WINCTRL__WINTSEL1">
+        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
+        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
+        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
+        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__FLEN">
+        <value name="OFF" caption="No filtering" value="0"/>
+        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
+        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__INTSEL">
+        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
+        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
+        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
+        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXNEG">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+        <value name="GND" caption="Ground" value="4"/>
+        <value name="VSCALE" caption="VDD scaler" value="5"/>
+        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
+        <value name="DAC" caption="DAC output" value="7"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__MUXPOS">
+        <value name="PIN0" caption="I/O pin 0" value="0"/>
+        <value name="PIN1" caption="I/O pin 1" value="1"/>
+        <value name="PIN2" caption="I/O pin 2" value="2"/>
+        <value name="PIN3" caption="I/O pin 3" value="3"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__OUT">
+        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
+        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
+        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
+      </value-group>
+      <value-group name="AC_COMPCTRL__SPEED">
+        <value name="LOW" caption="Low speed" value="0"/>
+        <value name="HIGH" caption="High speed" value="1"/>
+      </value-group>
+    </module>
+    <module name="ADC" id="U2204" version="1.2.0" caption="Analog Digital Converter">
+      <register-group name="ADC" caption="Analog Digital Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="REFCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Reference Control">
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
+          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
+        </register>
+        <register name="AVGCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Average Control">
+          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
+          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
+        </register>
+        <register name="SAMPCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Sampling Time Control">
+          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
+          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x1"/>
+          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x2"/>
+          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x4"/>
+          <bitfield name="CORREN" caption="Digital Correction Logic Enabled" mask="0x8"/>
+          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x30" values="ADC_CTRLB__RESSEL"/>
+          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLB__PRESCALER"/>
+        </register>
+        <register name="WINCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Monitor Control">
+          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x7" values="ADC_WINCTRL__WINMODE"/>
+        </register>
+        <register name="SWTRIG" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
+          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
+          <bitfield name="START" caption="ADC Start Conversion" mask="0x2"/>
+        </register>
+        <register name="INPUTCTRL" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Input Control">
+          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
+          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
+          <bitfield name="INPUTSCAN" caption="Number of Input Channels Included in Scan" mask="0xF0000"/>
+          <bitfield name="INPUTOFFSET" caption="Positive Mux Setting Offset" mask="0xF00000"/>
+          <bitfield name="GAIN" caption="Gain Factor Selection" mask="0xF000000" values="ADC_INPUTCTRL__GAIN"/>
+        </register>
+        <register name="EVCTRL" offset="0x14" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event In" mask="0x1"/>
+          <bitfield name="SYNCEI" caption="Synchronization Event In" mask="0x2"/>
+          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
+          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
+        </register>
+        <register name="INTENCLR" offset="0x16" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTENSET" offset="0x17" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RESRDY" caption="Result Ready" mask="0x1"/>
+          <bitfield name="OVERRUN" caption="Overrun" mask="0x2"/>
+          <bitfield name="WINMON" caption="Window Monitor" mask="0x4"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+        </register>
+        <register name="STATUS" offset="0x19" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="RESULT" offset="0x1A" rw="R" access="RSYNC" size="2" initval="0x0000" caption="Result">
+          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
+        </register>
+        <register name="WINLT" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
+          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="WINUT" offset="0x20" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
+          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
+        </register>
+        <register name="GAINCORR" offset="0x24" rw="RW" size="2" initval="0x0000" caption="Gain Correction">
+          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="OFFSETCORR" offset="0x26" rw="RW" size="2" initval="0x0000" caption="Offset Correction">
+          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
+        </register>
+        <register name="CALIB" offset="0x28" rw="RW" size="2" initval="0x0000" caption="Calibration">
+          <bitfield name="LINEARITY_CAL" caption="Linearity Calibration Value" mask="0xFF"/>
+          <bitfield name="BIAS_CAL" caption="Bias Calibration Value" mask="0x700"/>
+        </register>
+        <register name="DBGCTRL" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="ADC_REFCTRL__REFSEL">
+        <value name="INT1V" caption="1.0V voltage reference" value="0x0"/>
+        <value name="INTVCC0" caption="1/1.48 VDDANA" value="0x1"/>
+        <value name="INTVCC1" caption="1/2 VDDANA (only for VDDANA &gt; 2.0V)" value="0x2"/>
+        <value name="AREFA" caption="External reference" value="0x3"/>
+        <value name="AREFB" caption="External reference" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_AVGCTRL__SAMPLENUM">
+        <value name="1" caption="1 sample" value="0x0"/>
+        <value name="2" caption="2 samples" value="0x1"/>
+        <value name="4" caption="4 samples" value="0x2"/>
+        <value name="8" caption="8 samples" value="0x3"/>
+        <value name="16" caption="16 samples" value="0x4"/>
+        <value name="32" caption="32 samples" value="0x5"/>
+        <value name="64" caption="64 samples" value="0x6"/>
+        <value name="128" caption="128 samples" value="0x7"/>
+        <value name="256" caption="256 samples" value="0x8"/>
+        <value name="512" caption="512 samples" value="0x9"/>
+        <value name="1024" caption="1024 samples" value="0xA"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__PRESCALER">
+        <value name="DIV4" caption="Peripheral clock divided by 4" value="0x0"/>
+        <value name="DIV8" caption="Peripheral clock divided by 8" value="0x1"/>
+        <value name="DIV16" caption="Peripheral clock divided by 16" value="0x2"/>
+        <value name="DIV32" caption="Peripheral clock divided by 32" value="0x3"/>
+        <value name="DIV64" caption="Peripheral clock divided by 64" value="0x4"/>
+        <value name="DIV128" caption="Peripheral clock divided by 128" value="0x5"/>
+        <value name="DIV256" caption="Peripheral clock divided by 256" value="0x6"/>
+        <value name="DIV512" caption="Peripheral clock divided by 512" value="0x7"/>
+      </value-group>
+      <value-group name="ADC_CTRLB__RESSEL">
+        <value name="12BIT" caption="12-bit result" value="0x0"/>
+        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
+        <value name="10BIT" caption="10-bit result" value="0x2"/>
+        <value name="8BIT" caption="8-bit result" value="0x3"/>
+      </value-group>
+      <value-group name="ADC_WINCTRL__WINMODE">
+        <value name="DISABLE" caption="No window mode (default)" value="0x0"/>
+        <value name="MODE1" caption="Mode 1: RESULT &gt; WINLT" value="0x1"/>
+        <value name="MODE2" caption="Mode 2: RESULT &lt; WINUT" value="0x2"/>
+        <value name="MODE3" caption="Mode 3: WINLT &lt; RESULT &lt; WINUT" value="0x3"/>
+        <value name="MODE4" caption="Mode 4: !(WINLT &lt; RESULT &lt; WINUT)" value="0x4"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__GAIN">
+        <value name="1X" caption="1x" value="0x0"/>
+        <value name="2X" caption="2x" value="0x1"/>
+        <value name="4X" caption="4x" value="0x2"/>
+        <value name="8X" caption="8x" value="0x3"/>
+        <value name="16X" caption="16x" value="0x4"/>
+        <value name="DIV2" caption="1/2x" value="0xF"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXNEG">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="GND" caption="Internal Ground" value="0x18"/>
+        <value name="IOGND" caption="I/O Ground" value="0x19"/>
+      </value-group>
+      <value-group name="ADC_INPUTCTRL__MUXPOS">
+        <value name="PIN0" caption="ADC AIN0 Pin" value="0x0"/>
+        <value name="PIN1" caption="ADC AIN1 Pin" value="0x1"/>
+        <value name="PIN2" caption="ADC AIN2 Pin" value="0x2"/>
+        <value name="PIN3" caption="ADC AIN3 Pin" value="0x3"/>
+        <value name="PIN4" caption="ADC AIN4 Pin" value="0x4"/>
+        <value name="PIN5" caption="ADC AIN5 Pin" value="0x5"/>
+        <value name="PIN6" caption="ADC AIN6 Pin" value="0x6"/>
+        <value name="PIN7" caption="ADC AIN7 Pin" value="0x7"/>
+        <value name="PIN8" caption="ADC AIN8 Pin" value="0x8"/>
+        <value name="PIN9" caption="ADC AIN9 Pin" value="0x9"/>
+        <value name="PIN10" caption="ADC AIN10 Pin" value="0xA"/>
+        <value name="PIN11" caption="ADC AIN11 Pin" value="0xB"/>
+        <value name="PIN12" caption="ADC AIN12 Pin" value="0xC"/>
+        <value name="PIN13" caption="ADC AIN13 Pin" value="0xD"/>
+        <value name="PIN14" caption="ADC AIN14 Pin" value="0xE"/>
+        <value name="PIN15" caption="ADC AIN15 Pin" value="0xF"/>
+        <value name="PIN16" caption="ADC AIN16 Pin" value="0x10"/>
+        <value name="PIN17" caption="ADC AIN17 Pin" value="0x11"/>
+        <value name="PIN18" caption="ADC AIN18 Pin" value="0x12"/>
+        <value name="PIN19" caption="ADC AIN19 Pin" value="0x13"/>
+        <value name="TEMP" caption="Temperature Reference" value="0x18"/>
+        <value name="BANDGAP" caption="Bandgap Voltage" value="0x19"/>
+        <value name="SCALEDCOREVCC" caption="1/4  Scaled Core Supply" value="0x1A"/>
+        <value name="SCALEDIOVCC" caption="1/4  Scaled I/O Supply" value="0x1B"/>
+        <value name="DAC" caption="DAC Output" value="0x1C"/>
+      </value-group>
+    </module>
+    <module name="DAC" id="U2214" version="1.1.0" caption="Digital Analog Converter">
+      <register-group name="DAC" caption="Digital Analog Converter">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x4"/>
+        </register>
+        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x00" caption="Control B">
+          <bitfield name="EOEN" caption="External Output Enable" mask="0x1"/>
+          <bitfield name="IOEN" caption="Internal Output Enable" mask="0x2"/>
+          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x4"/>
+          <bitfield name="VPD" caption="Voltage Pump Disable" mask="0x8"/>
+          <bitfield name="BDWP" caption="Bypass DATABUF Write Protection" mask="0x10"/>
+          <bitfield name="REFSEL" caption="Reference Selection" mask="0xC0" values="DAC_CTRLB__REFSEL"/>
+        </register>
+        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
+          <bitfield name="STARTEI" caption="Start Conversion Event Input" mask="0x1"/>
+          <bitfield name="EMPTYEO" caption="Data Buffer Empty Event Output" mask="0x2"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="UNDERRUN" caption="Underrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="UNDERRUN" caption="Underrun" mask="0x1"/>
+          <bitfield name="EMPTY" caption="Data Buffer Empty" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x4"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" access="RSYNC" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="DATA" offset="0x8" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="Data">
+          <bitfield name="DATA" caption="Data value to be converted" mask="0xFFFF"/>
+        </register>
+        <register name="DATABUF" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Data Buffer">
+          <bitfield name="DATABUF" caption="Data Buffer" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DAC_CTRLB__REFSEL">
+        <value name="INT1V" caption="Internal 1.0V reference" value="0"/>
+        <value name="AVCC" caption="AVCC" value="1"/>
+        <value name="VREFP" caption="External reference" value="2"/>
+      </value-group>
+    </module>
+    <module name="DMAC" id="U2223" version="1.0.0" caption="Direct Memory Access Controller">
+      <register-group name="DMAC" caption="Direct Memory Access Controller">
+        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
+          <bitfield name="CRCENABLE" caption="CRC Enable" mask="0x4"/>
+          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
+          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
+          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
+          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
+        </register>
+        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
+          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
+          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
+          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
+        </register>
+        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
+          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
+          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
+          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
+          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
+        </register>
+        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
+        </register>
+        <register name="QOSCTRL" offset="0xE" rw="RW" size="1" initval="0x15" caption="QOS Control">
+          <bitfield name="WRBQOS" caption="Write-Back Quality of Service" mask="0x3" values="DMAC_QOSCTRL__WRBQOS"/>
+          <bitfield name="FQOS" caption="Fetch Quality of Service" mask="0xC" values="DMAC_QOSCTRL__FQOS"/>
+          <bitfield name="DQOS" caption="Data Transfer Quality of Service" mask="0x30" values="DMAC_QOSCTRL__DQOS"/>
+        </register>
+        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
+          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
+          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
+          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
+          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
+          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
+          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
+          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
+          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
+          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
+          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
+          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
+          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
+        </register>
+        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Priority Control 0">
+          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0xF"/>
+          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
+          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0xF00"/>
+          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
+          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0xF0000"/>
+          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
+          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0xF000000"/>
+          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
+        </register>
+        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
+          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
+          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
+          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
+          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
+        </register>
+        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
+          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
+          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
+          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
+          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
+          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
+          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
+          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
+          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
+          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
+          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
+          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
+          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
+        </register>
+        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
+          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
+          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
+          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
+          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
+          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
+          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
+          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
+          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
+          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
+          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
+          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
+          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
+        </register>
+        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
+          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
+          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
+          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
+          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
+          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
+          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
+          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
+          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
+          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
+          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
+          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
+          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
+        </register>
+        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
+          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
+          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
+          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
+          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
+          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
+          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
+          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
+        </register>
+        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
+          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
+          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CHID" offset="0x3F" rw="RW" size="1" initval="0x00" caption="Channel ID">
+          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
+        </register>
+        <register name="CHCTRLA" offset="0x40" rw="RW" size="1" initval="0x00" caption="Channel Control A">
+          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
+        </register>
+        <register name="CHCTRLB" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="Channel Control B">
+          <bitfield name="EVACT" caption="Event Input Action" mask="0x7" values="DMAC_CHCTRLB__EVACT"/>
+          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x8"/>
+          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x10"/>
+          <bitfield name="LVL" caption="Channel Arbitration Level" mask="0x60" values="DMAC_CHCTRLB__LVL"/>
+          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x3F00" values="DMAC_CHCTRLB__TRIGSRC"/>
+          <bitfield name="TRIGACT" caption="Trigger Action" mask="0xC00000" values="DMAC_CHCTRLB__TRIGACT"/>
+          <bitfield name="CMD" caption="Software Command" mask="0x3000000" values="DMAC_CHCTRLB__CMD"/>
+        </register>
+        <register name="CHINTENCLR" offset="0x4C" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel Interrupt Enable Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTENSET" offset="0x4D" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel Interrupt Enable Set">
+          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
+        </register>
+        <register name="CHINTFLAG" offset="0x4E" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel Interrupt Flag Status and Clear">
+          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
+          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
+          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
+        </register>
+        <register name="CHSTATUS" offset="0x4F" rw="R" size="1" initval="0x00" caption="Channel Status">
+          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
+          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
+          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
+        </register>
+      </register-group>
+      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" aligned="8">
+        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
+          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
+          <bitfield name="EVOSEL" caption="Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
+          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
+          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
+          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
+          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
+          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
+          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
+        </register>
+        <register name="BTCNT" offset="0x2" rw="RW" size="2" caption="Block Transfer Count">
+          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
+        </register>
+        <register name="SRCADDR" offset="0x4" rw="RW" size="4" caption="Block Transfer Source Address">
+          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
+          <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
+          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="DMAC_BTCTRL__BEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__BLOCKACT">
+        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
+        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
+        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
+        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__EVOSEL">
+        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
+        <value name="BLOCK" caption="Event strobe when block transfer complete" value="0x1"/>
+        <value name="BEAT" caption="Event strobe when beat transfer complete" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSEL">
+        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
+        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_BTCTRL__STEPSIZE">
+        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
+        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
+        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
+        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
+        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
+        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
+        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
+        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
+        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
+        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
+        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCPOLY">
+        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
+        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
+      </value-group>
+      <value-group name="DMAC_CRCCTRL__CRCSRC">
+        <value name="NOACT" caption="No action" value="0x00"/>
+        <value name="IO" caption="I/O interface" value="0x01"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__FQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_QOSCTRL__WRBQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__CMD">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__EVACT">
+        <value name="NOACT" caption="No action" value="0x0"/>
+        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="0x1"/>
+        <value name="CTRIG" caption="Conditional transfer trigger" value="0x2"/>
+        <value name="CBLOCK" caption="Conditional block transfer" value="0x3"/>
+        <value name="SUSPEND" caption="Channel suspend operation" value="0x4"/>
+        <value name="RESUME" caption="Channel resume operation" value="0x5"/>
+        <value name="SSKIP" caption="Skip next block suspend action" value="0x6"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__LVL">
+        <value name="LVL0" caption="Channel Priority Level 0" value="0x00"/>
+        <value name="LVL1" caption="Channel Priority Level 1" value="0x01"/>
+        <value name="LVL2" caption="Channel Priority Level 2" value="0x02"/>
+        <value name="LVL3" caption="Channel Priority Level 3" value="0x03"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGACT">
+        <value name="BLOCK" caption="One trigger required for each block transfer" value="0x0"/>
+        <value name="BEAT" caption="One trigger required for each beat transfer" value="0x2"/>
+        <value name="TRANSACTION" caption="One trigger required for each transaction" value="0x3"/>
+      </value-group>
+      <value-group name="DMAC_CHCTRLB__TRIGSRC">
+        <value name="DISABLE" caption="Only software/event triggers" value="0x00"/>
+      </value-group>
+    </module>
+    <module name="DSU" id="U2209" version="2.0.0" caption="Device Service Unit">
+      <register-group name="DSU" caption="Device Service Unit">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Check" mask="0x4"/>
+          <bitfield name="MBIST" caption="Memory Built-In Self-Test" mask="0x8"/>
+          <bitfield name="CE" caption="Chip Erase" mask="0x10"/>
+        </register>
+        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
+          <bitfield name="DONE" caption="Done" mask="0x1"/>
+          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
+          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
+          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
+          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
+        </register>
+        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x10" caption="Status B">
+          <bitfield name="PROT" caption="Protected" mask="0x1"/>
+          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
+          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
+          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
+          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
+        </register>
+        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
+          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
+        </register>
+        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
+          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DID" offset="0x18" rw="R" size="4" initval="0x10010300" caption="Device Identification">
+          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
+          <bitfield name="REVISION" caption="Revision" mask="0xF00"/>
+          <bitfield name="DIE" caption="Die Identification" mask="0xF000"/>
+          <bitfield name="SERIES" caption="Product Series" mask="0x3F0000"/>
+          <bitfield name="FAMILY" caption="Product Family" mask="0xF800000"/>
+          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000"/>
+        </register>
+        <register name="ENTRY" offset="0x1000" rw="R" size="4" count="2" initval="0x00000002" caption="Coresight ROM Table Entry n">
+          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
+          <bitfield name="FMT" caption="Format" mask="0x2"/>
+          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
+        </register>
+        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table End">
+          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="Coresight ROM Table Memory Type">
+          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
+        </register>
+        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
+          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
+          <bitfield name="FKBC" caption="4KB Count" mask="0xF0"/>
+        </register>
+        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
+          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
+        </register>
+        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
+          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
+          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
+        </register>
+        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
+          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
+          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
+          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
+          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
+          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
+        </register>
+        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
+          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
+        </register>
+        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
+          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
+          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
+        </register>
+        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
+          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
+        </register>
+        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
+          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="EIC" id="U2217" version="1.0.1" caption="External Interrupt Controller">
+      <register-group name="EIC" caption="External Interrupt Controller">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="NMICTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
+          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
+          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
+        </register>
+        <register name="NMIFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:NMIFLAG" initval="0x00" caption="Non-Maskable Interrupt Flag Status and Clear">
+          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EXTINTEO0" caption="External Interrupt 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="EXTINTEO1" caption="External Interrupt 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="EXTINTEO2" caption="External Interrupt 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="EXTINTEO3" caption="External Interrupt 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="EXTINTEO4" caption="External Interrupt 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="EXTINTEO5" caption="External Interrupt 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="EXTINTEO6" caption="External Interrupt 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="EXTINTEO7" caption="External Interrupt 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="EXTINTEO8" caption="External Interrupt 8 Event Output Enable" mask="0x100"/>
+          <bitfield name="EXTINTEO9" caption="External Interrupt 9 Event Output Enable" mask="0x200"/>
+          <bitfield name="EXTINTEO10" caption="External Interrupt 10 Event Output Enable" mask="0x400"/>
+          <bitfield name="EXTINTEO11" caption="External Interrupt 11 Event Output Enable" mask="0x800"/>
+          <bitfield name="EXTINTEO12" caption="External Interrupt 12 Event Output Enable" mask="0x1000"/>
+          <bitfield name="EXTINTEO13" caption="External Interrupt 13 Event Output Enable" mask="0x2000"/>
+          <bitfield name="EXTINTEO14" caption="External Interrupt 14 Event Output Enable" mask="0x4000"/>
+          <bitfield name="EXTINTEO15" caption="External Interrupt 15 Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x8" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENSET" offset="0xC" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="EXTINT0" caption="External Interrupt 0 Enable" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1 Enable" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2 Enable" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3 Enable" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4 Enable" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5 Enable" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6 Enable" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7 Enable" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8 Enable" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9 Enable" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10 Enable" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11 Enable" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12 Enable" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13 Enable" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14 Enable" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15 Enable" mask="0x8000"/>
+        </register>
+        <register name="INTFLAG" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EXTINT0" caption="External Interrupt 0" mask="0x1"/>
+          <bitfield name="EXTINT1" caption="External Interrupt 1" mask="0x2"/>
+          <bitfield name="EXTINT2" caption="External Interrupt 2" mask="0x4"/>
+          <bitfield name="EXTINT3" caption="External Interrupt 3" mask="0x8"/>
+          <bitfield name="EXTINT4" caption="External Interrupt 4" mask="0x10"/>
+          <bitfield name="EXTINT5" caption="External Interrupt 5" mask="0x20"/>
+          <bitfield name="EXTINT6" caption="External Interrupt 6" mask="0x40"/>
+          <bitfield name="EXTINT7" caption="External Interrupt 7" mask="0x80"/>
+          <bitfield name="EXTINT8" caption="External Interrupt 8" mask="0x100"/>
+          <bitfield name="EXTINT9" caption="External Interrupt 9" mask="0x200"/>
+          <bitfield name="EXTINT10" caption="External Interrupt 10" mask="0x400"/>
+          <bitfield name="EXTINT11" caption="External Interrupt 11" mask="0x800"/>
+          <bitfield name="EXTINT12" caption="External Interrupt 12" mask="0x1000"/>
+          <bitfield name="EXTINT13" caption="External Interrupt 13" mask="0x2000"/>
+          <bitfield name="EXTINT14" caption="External Interrupt 14" mask="0x4000"/>
+          <bitfield name="EXTINT15" caption="External Interrupt 15" mask="0x8000"/>
+        </register>
+        <register name="WAKEUP" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Wake-Up Enable">
+          <bitfield name="WAKEUPEN0" caption="External Interrupt 0 Wake-up Enable" mask="0x1"/>
+          <bitfield name="WAKEUPEN1" caption="External Interrupt 1 Wake-up Enable" mask="0x2"/>
+          <bitfield name="WAKEUPEN2" caption="External Interrupt 2 Wake-up Enable" mask="0x4"/>
+          <bitfield name="WAKEUPEN3" caption="External Interrupt 3 Wake-up Enable" mask="0x8"/>
+          <bitfield name="WAKEUPEN4" caption="External Interrupt 4 Wake-up Enable" mask="0x10"/>
+          <bitfield name="WAKEUPEN5" caption="External Interrupt 5 Wake-up Enable" mask="0x20"/>
+          <bitfield name="WAKEUPEN6" caption="External Interrupt 6 Wake-up Enable" mask="0x40"/>
+          <bitfield name="WAKEUPEN7" caption="External Interrupt 7 Wake-up Enable" mask="0x80"/>
+          <bitfield name="WAKEUPEN8" caption="External Interrupt 8 Wake-up Enable" mask="0x100"/>
+          <bitfield name="WAKEUPEN9" caption="External Interrupt 9 Wake-up Enable" mask="0x200"/>
+          <bitfield name="WAKEUPEN10" caption="External Interrupt 10 Wake-up Enable" mask="0x400"/>
+          <bitfield name="WAKEUPEN11" caption="External Interrupt 11 Wake-up Enable" mask="0x800"/>
+          <bitfield name="WAKEUPEN12" caption="External Interrupt 12 Wake-up Enable" mask="0x1000"/>
+          <bitfield name="WAKEUPEN13" caption="External Interrupt 13 Wake-up Enable" mask="0x2000"/>
+          <bitfield name="WAKEUPEN14" caption="External Interrupt 14 Wake-up Enable" mask="0x4000"/>
+          <bitfield name="WAKEUPEN15" caption="External Interrupt 15 Wake-up Enable" mask="0x8000"/>
+        </register>
+        <register name="CONFIG" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="Configuration n">
+          <bitfield name="SENSE0" caption="Input Sense 0 Configuration" mask="0x7" values="EIC_CONFIG__SENSE0"/>
+          <bitfield name="FILTEN0" caption="Filter 0 Enable" mask="0x8"/>
+          <bitfield name="SENSE1" caption="Input Sense 1 Configuration" mask="0x70" values="EIC_CONFIG__SENSE1"/>
+          <bitfield name="FILTEN1" caption="Filter 1 Enable" mask="0x80"/>
+          <bitfield name="SENSE2" caption="Input Sense 2 Configuration" mask="0x700" values="EIC_CONFIG__SENSE2"/>
+          <bitfield name="FILTEN2" caption="Filter 2 Enable" mask="0x800"/>
+          <bitfield name="SENSE3" caption="Input Sense 3 Configuration" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
+          <bitfield name="FILTEN3" caption="Filter 3 Enable" mask="0x8000"/>
+          <bitfield name="SENSE4" caption="Input Sense 4 Configuration" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
+          <bitfield name="FILTEN4" caption="Filter 4 Enable" mask="0x80000"/>
+          <bitfield name="SENSE5" caption="Input Sense 5 Configuration" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
+          <bitfield name="FILTEN5" caption="Filter 5 Enable" mask="0x800000"/>
+          <bitfield name="SENSE6" caption="Input Sense 6 Configuration" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
+          <bitfield name="FILTEN6" caption="Filter 6 Enable" mask="0x8000000"/>
+          <bitfield name="SENSE7" caption="Input Sense 7 Configuration" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
+          <bitfield name="FILTEN7" caption="Filter 7 Enable" mask="0x80000000"/>
+        </register>
+      </register-group>
+      <value-group name="EIC_NMICTRL__NMISENSE">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE0">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising-edge detection" value="1"/>
+        <value name="FALL" caption="Falling-edge detection" value="2"/>
+        <value name="BOTH" caption="Both-edges detection" value="3"/>
+        <value name="HIGH" caption="High-level detection" value="4"/>
+        <value name="LOW" caption="Low-level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE1">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE2">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE3">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE4">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE5">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE6">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+      <value-group name="EIC_CONFIG__SENSE7">
+        <value name="NONE" caption="No detection" value="0"/>
+        <value name="RISE" caption="Rising edge detection" value="1"/>
+        <value name="FALL" caption="Falling edge detection" value="2"/>
+        <value name="BOTH" caption="Both edges detection" value="3"/>
+        <value name="HIGH" caption="High level detection" value="4"/>
+        <value name="LOW" caption="Low level detection" value="5"/>
+      </value-group>
+    </module>
+    <module name="EVSYS" id="U2208" version="1.0.1" caption="Event System Interface">
+      <register-group name="EVSYS" caption="Event System Interface">
+        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="GCLKREQ" caption="Generic Clock Requests" mask="0x10"/>
+        </register>
+        <register name="CHANNEL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Channel">
+          <bitfield name="CHANNEL" caption="Channel Selection" mask="0xF"/>
+          <bitfield name="SWEVT" caption="Software Event" mask="0x100"/>
+          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F0000"/>
+          <bitfield name="PATH" caption="Path Selection" mask="0x3000000" values="EVSYS_CHANNEL__PATH"/>
+          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC000000" values="EVSYS_CHANNEL__EDGSEL"/>
+        </register>
+        <register name="USER" offset="0x8" rw="RW" size="2" initval="0x0000" caption="User Multiplexer">
+          <bitfield name="USER" caption="User Multiplexer Selection" mask="0x1F"/>
+          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x1F00" values="EVSYS_USER__CHANNEL"/>
+        </register>
+        <register name="CHSTATUS" offset="0xC" rw="R" size="4" initval="0x000F00FF" caption="Channel Status">
+          <bitfield name="USRRDY0" caption="Channel 0 User Ready" mask="0x1"/>
+          <bitfield name="USRRDY1" caption="Channel 1 User Ready" mask="0x2"/>
+          <bitfield name="USRRDY2" caption="Channel 2 User Ready" mask="0x4"/>
+          <bitfield name="USRRDY3" caption="Channel 3 User Ready" mask="0x8"/>
+          <bitfield name="USRRDY4" caption="Channel 4 User Ready" mask="0x10"/>
+          <bitfield name="USRRDY5" caption="Channel 5 User Ready" mask="0x20"/>
+          <bitfield name="USRRDY6" caption="Channel 6 User Ready" mask="0x40"/>
+          <bitfield name="USRRDY7" caption="Channel 7 User Ready" mask="0x80"/>
+          <bitfield name="CHBUSY0" caption="Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CHBUSY1" caption="Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CHBUSY2" caption="Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CHBUSY3" caption="Channel 3 Busy" mask="0x800"/>
+          <bitfield name="CHBUSY4" caption="Channel 4 Busy" mask="0x1000"/>
+          <bitfield name="CHBUSY5" caption="Channel 5 Busy" mask="0x2000"/>
+          <bitfield name="CHBUSY6" caption="Channel 6 Busy" mask="0x4000"/>
+          <bitfield name="CHBUSY7" caption="Channel 7 Busy" mask="0x8000"/>
+          <bitfield name="USRRDY8" caption="Channel 8 User Ready" mask="0x10000"/>
+          <bitfield name="USRRDY9" caption="Channel 9 User Ready" mask="0x20000"/>
+          <bitfield name="USRRDY10" caption="Channel 10 User Ready" mask="0x40000"/>
+          <bitfield name="USRRDY11" caption="Channel 11 User Ready" mask="0x80000"/>
+          <bitfield name="CHBUSY8" caption="Channel 8 Busy" mask="0x1000000"/>
+          <bitfield name="CHBUSY9" caption="Channel 9 Busy" mask="0x2000000"/>
+          <bitfield name="CHBUSY10" caption="Channel 10 Busy" mask="0x4000000"/>
+          <bitfield name="CHBUSY11" caption="Channel 11 Busy" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x10" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENSET" offset="0x14" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVR0" caption="Channel 0 Overrun Interrupt Enable" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun Interrupt Enable" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun Interrupt Enable" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun Interrupt Enable" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun Interrupt Enable" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun Interrupt Enable" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun Interrupt Enable" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection Interrupt Enable" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection Interrupt Enable" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection Interrupt Enable" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection Interrupt Enable" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection Interrupt Enable" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection Interrupt Enable" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection Interrupt Enable" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun Interrupt Enable" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun Interrupt Enable" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun Interrupt Enable" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun Interrupt Enable" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection Interrupt Enable" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection Interrupt Enable" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection Interrupt Enable" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection Interrupt Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVR0" caption="Channel 0 Overrun" mask="0x1"/>
+          <bitfield name="OVR1" caption="Channel 1 Overrun" mask="0x2"/>
+          <bitfield name="OVR2" caption="Channel 2 Overrun" mask="0x4"/>
+          <bitfield name="OVR3" caption="Channel 3 Overrun" mask="0x8"/>
+          <bitfield name="OVR4" caption="Channel 4 Overrun" mask="0x10"/>
+          <bitfield name="OVR5" caption="Channel 5 Overrun" mask="0x20"/>
+          <bitfield name="OVR6" caption="Channel 6 Overrun" mask="0x40"/>
+          <bitfield name="OVR7" caption="Channel 7 Overrun" mask="0x80"/>
+          <bitfield name="EVD0" caption="Channel 0 Event Detection" mask="0x100"/>
+          <bitfield name="EVD1" caption="Channel 1 Event Detection" mask="0x200"/>
+          <bitfield name="EVD2" caption="Channel 2 Event Detection" mask="0x400"/>
+          <bitfield name="EVD3" caption="Channel 3 Event Detection" mask="0x800"/>
+          <bitfield name="EVD4" caption="Channel 4 Event Detection" mask="0x1000"/>
+          <bitfield name="EVD5" caption="Channel 5 Event Detection" mask="0x2000"/>
+          <bitfield name="EVD6" caption="Channel 6 Event Detection" mask="0x4000"/>
+          <bitfield name="EVD7" caption="Channel 7 Event Detection" mask="0x8000"/>
+          <bitfield name="OVR8" caption="Channel 8 Overrun" mask="0x10000"/>
+          <bitfield name="OVR9" caption="Channel 9 Overrun" mask="0x20000"/>
+          <bitfield name="OVR10" caption="Channel 10 Overrun" mask="0x40000"/>
+          <bitfield name="OVR11" caption="Channel 11 Overrun" mask="0x80000"/>
+          <bitfield name="EVD8" caption="Channel 8 Event Detection" mask="0x1000000"/>
+          <bitfield name="EVD9" caption="Channel 9 Event Detection" mask="0x2000000"/>
+          <bitfield name="EVD10" caption="Channel 10 Event Detection" mask="0x4000000"/>
+          <bitfield name="EVD11" caption="Channel 11 Event Detection" mask="0x8000000"/>
+        </register>
+      </register-group>
+      <value-group name="EVSYS_CHANNEL__EDGSEL">
+        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
+        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
+        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
+        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
+      </value-group>
+      <value-group name="EVSYS_CHANNEL__PATH">
+        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
+        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
+        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
+      </value-group>
+      <value-group name="EVSYS_USER__CHANNEL">
+        <value name="0" caption="No Channel Output Selected" value="0"/>
+      </value-group>
+    </module>
+    <module name="GCLK" id="U2102" version="2.1.0" caption="Generic Clock Generator">
+      <register-group name="GCLK" caption="Generic Clock Generator">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x1" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy Status" mask="0x80"/>
+        </register>
+        <register name="CLKCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Generic Clock Control">
+          <bitfield name="ID" caption="Generic Clock Selection ID" mask="0x3F" values="GCLK_CLKCTRL__ID"/>
+          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF00" values="GCLK_CLKCTRL__GEN"/>
+          <bitfield name="CLKEN" caption="Clock Enable" mask="0x4000"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
+        </register>
+        <register name="GENCTRL" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Generic Clock Generator Control">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="SRC" caption="Source Select" mask="0x1F00" values="GCLK_GENCTRL__SRC"/>
+          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x10000"/>
+          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x20000"/>
+          <bitfield name="OOV" caption="Output Off Value" mask="0x40000"/>
+          <bitfield name="OE" caption="Output Enable" mask="0x80000"/>
+          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x100000"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x200000"/>
+        </register>
+        <register name="GENDIV" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Generic Clock Generator Division">
+          <bitfield name="ID" caption="Generic Clock Generator Selection" mask="0xF"/>
+          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF00"/>
+        </register>
+      </register-group>
+      <value-group name="GCLK_CLKCTRL__GEN">
+        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
+        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
+        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
+        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
+        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
+        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
+        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
+        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
+      </value-group>
+      <value-group name="GCLK_CLKCTRL__ID">
+        <value name="DFLL48" caption="DFLL48" value="0x0"/>
+        <value name="FDPLL" caption="FDPLL" value="0x1"/>
+        <value name="FDPLL32K" caption="FDPLL32K" value="0x2"/>
+        <value name="WDT" caption="WDT" value="0x3"/>
+        <value name="RTC" caption="RTC" value="0x4"/>
+        <value name="EIC" caption="EIC" value="0x5"/>
+        <value name="USB" caption="USB" value="0x6"/>
+        <value name="EVSYS_0" caption="EVSYS_0" value="0x7"/>
+        <value name="EVSYS_1" caption="EVSYS_1" value="0x8"/>
+        <value name="EVSYS_2" caption="EVSYS_2" value="0x9"/>
+        <value name="EVSYS_3" caption="EVSYS_3" value="0xA"/>
+        <value name="EVSYS_4" caption="EVSYS_4" value="0xB"/>
+        <value name="EVSYS_5" caption="EVSYS_5" value="0xC"/>
+        <value name="EVSYS_6" caption="EVSYS_6" value="0xD"/>
+        <value name="EVSYS_7" caption="EVSYS_7" value="0xE"/>
+        <value name="EVSYS_8" caption="EVSYS_8" value="0xF"/>
+        <value name="EVSYS_9" caption="EVSYS_9" value="0x10"/>
+        <value name="EVSYS_10" caption="EVSYS_10" value="0x11"/>
+        <value name="EVSYS_11" caption="EVSYS_11" value="0x12"/>
+        <value name="SERCOMX_SLOW" caption="SERCOMX_SLOW" value="0x13"/>
+        <value name="SERCOM0_CORE" caption="SERCOM0_CORE" value="0x14"/>
+        <value name="SERCOM1_CORE" caption="SERCOM1_CORE" value="0x15"/>
+        <value name="SERCOM2_CORE" caption="SERCOM2_CORE" value="0x16"/>
+        <value name="SERCOM3_CORE" caption="SERCOM3_CORE" value="0x17"/>
+        <value name="SERCOM4_CORE" caption="SERCOM4_CORE" value="0x18"/>
+        <value name="SERCOM5_CORE" caption="SERCOM5_CORE" value="0x19"/>
+        <value name="TCC0_TCC1" caption="TCC0_TCC1" value="0x1A"/>
+        <value name="TCC2_TC3" caption="TCC2_TC3" value="0x1B"/>
+        <value name="TC4_TC5" caption="TC4_TC5" value="0x1C"/>
+        <value name="TC6_TC7" caption="TC6_TC7" value="0x1D"/>
+        <value name="ADC" caption="ADC" value="0x1E"/>
+        <value name="AC_DIG" caption="AC_DIG" value="0x1F"/>
+        <value name="AC_ANA" caption="AC_ANA" value="0x20"/>
+        <value name="DAC" caption="DAC" value="0x21"/>
+        <value name="I2S_0" caption="I2S_0" value="0x23"/>
+        <value name="I2S_1" caption="I2S_1" value="0x24"/>
+      </value-group>
+      <value-group name="GCLK_GENCTRL__SRC">
+        <value name="XOSC" caption="XOSC oscillator output" value="0"/>
+        <value name="GCLKIN" caption="Generator input pad" value="1"/>
+        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="2"/>
+        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="3"/>
+        <value name="OSC32K" caption="OSC32K oscillator output" value="4"/>
+        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
+        <value name="OSC8M" caption="OSC8M oscillator output" value="6"/>
+        <value name="DFLL48M" caption="DFLL48M output" value="7"/>
+        <value name="FDPLL" caption="FDPLL output" value="8"/>
+      </value-group>
+    </module>
+    <module name="HMATRIXB" id="I7638" version="2.1.2" caption="HSB Matrix">
+      <register-group name="PRS" size="0x8">
+        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
+        </register>
+        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
+        </register>
+      </register-group>
+      <register-group name="HMATRIXB" caption="HSB Matrix">
+        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
+        <register name="SFR" offset="0x110" rw="RW" size="4" access-size="4" count="16" initval="0x00000000" caption="Special Function">
+          <bitfield name="SFR" caption="Special Function Register" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="I2S" id="U2224" version="1.0.2" caption="Inter-IC Sound Interface">
+      <register-group name="I2S" caption="Inter-IC Sound Interface">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable" mask="0x20"/>
+        </register>
+        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
+          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
+          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
+          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
+          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
+          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
+          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x800"/>
+          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x1000" values="I2S_CLKCTRL__SCKSEL"/>
+          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x10000" values="I2S_CLKCTRL__MCKSEL"/>
+          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x40000"/>
+          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0xF80000"/>
+          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x1F000000"/>
+          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x20000000"/>
+          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x40000000"/>
+          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x80000000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
+          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
+          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
+          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
+          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
+          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
+          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
+          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
+          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
+          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
+          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
+          <bitfield name="SEREN0" caption="Serializer 0 Enable Synchronization Status" mask="0x10"/>
+          <bitfield name="SEREN1" caption="Serializer 1 Enable Synchronization Status" mask="0x20"/>
+          <bitfield name="DATA0" caption="Data 0 Synchronization Status" mask="0x100"/>
+          <bitfield name="DATA1" caption="Data 1 Synchronization Status" mask="0x200"/>
+        </register>
+        <register name="SERCTRL" offset="0x20" rw="RW" size="4" count="2" initval="0x00000000" caption="Serializer n Control">
+          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_SERCTRL__SERMODE"/>
+          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_SERCTRL__TXDEFAULT"/>
+          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_SERCTRL__TXSAME"/>
+          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_SERCTRL__CLKSEL"/>
+          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_SERCTRL__SLOTADJ"/>
+          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_SERCTRL__DATASIZE"/>
+          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_SERCTRL__WORDADJ"/>
+          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_SERCTRL__EXTEND"/>
+          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_SERCTRL__BITREV"/>
+          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
+          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
+          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
+          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
+          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
+          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
+          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
+          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
+          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_SERCTRL__MONO"/>
+          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_SERCTRL__DMA"/>
+          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
+        </register>
+        <register name="DATA" offset="0x30" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Data n">
+          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="I2S_CLKCTRL__BITDELAY">
+        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
+        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSSEL">
+        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
+        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__FSWIDTH">
+        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
+        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
+        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
+        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__MCKSEL">
+        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
+        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SCKSEL">
+        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
+        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_CLKCTRL__SLOTSIZE">
+        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
+        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
+        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
+        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__BITREV">
+        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
+        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__CLKSEL">
+        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
+        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DATASIZE">
+        <value name="32" caption="32 bits" value="0x0"/>
+        <value name="24" caption="24 bits" value="0x1"/>
+        <value name="20" caption="20 bits" value="0x2"/>
+        <value name="18" caption="18 bits" value="0x3"/>
+        <value name="16" caption="16 bits" value="0x4"/>
+        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
+        <value name="8" caption="8 bits" value="0x6"/>
+        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__DMA">
+        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
+        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__EXTEND">
+        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
+        <value name="ONE" caption="Extend with ones" value="0x1"/>
+        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
+        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__MONO">
+        <value name="STEREO" caption="Normal mode" value="0x0"/>
+        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SERMODE">
+        <value name="RX" caption="Receive" value="0x0"/>
+        <value name="TX" caption="Transmit" value="0x1"/>
+        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__SLOTADJ">
+        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXDEFAULT">
+        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
+        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
+        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__TXSAME">
+        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
+        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
+      </value-group>
+      <value-group name="I2S_SERCTRL__WORDADJ">
+        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
+        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
+      </value-group>
+    </module>
+    <module name="MTB" id="U2002" version="1.0.0" caption="Cortex-M0+ Micro-Trace Buffer">
+      <register-group name="MTB" caption="Cortex-M0+ Micro-Trace Buffer">
+        <register name="POSITION" offset="0x0" rw="RW" size="4" access-size="4" caption="MTB Position">
+          <bitfield name="WRAP" caption="Pointer Value Wraps" mask="0x4"/>
+          <bitfield name="POINTER" caption="Trace Packet Location Pointer" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="MASTER" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Master">
+          <bitfield name="MASK" caption="Maximum Value of the Trace Buffer in SRAM" mask="0x1F"/>
+          <bitfield name="TSTARTEN" caption="Trace Start Input Enable" mask="0x20"/>
+          <bitfield name="TSTOPEN" caption="Trace Stop Input Enable" mask="0x40"/>
+          <bitfield name="SFRWPRIV" caption="Special Function Register Write Privilege" mask="0x80"/>
+          <bitfield name="RAMPRIV" caption="SRAM Privilege" mask="0x100"/>
+          <bitfield name="HALTREQ" caption="Halt Request" mask="0x200"/>
+          <bitfield name="EN" caption="Main Trace Enable" mask="0x80000000"/>
+        </register>
+        <register name="FLOW" offset="0x8" rw="RW" size="4" access-size="4" initval="0x00000000" caption="MTB Flow">
+          <bitfield name="AUTOSTOP" caption="Auto Stop Tracing" mask="0x1"/>
+          <bitfield name="AUTOHALT" caption="Auto Halt Request" mask="0x2"/>
+          <bitfield name="WATERMARK" caption="Watermark value" mask="0xFFFFFFF8"/>
+        </register>
+        <register name="BASE" offset="0xC" rw="R" size="4" access-size="4" caption="MTB Base">
+        </register>
+        <register name="ITCTRL" offset="0xF00" rw="RW" size="4" access-size="4" caption="MTB Integration Mode Control">
+        </register>
+        <register name="CLAIMSET" offset="0xFA0" rw="RW" size="4" access-size="4" atomic-op="set:CLAIMSET" caption="MTB Claim Set">
+        </register>
+        <register name="CLAIMCLR" offset="0xFA4" rw="RW" size="4" access-size="4" atomic-op="clear:CLAIMCLR" caption="MTB Claim Clear">
+        </register>
+        <register name="LOCKACCESS" offset="0xFB0" rw="RW" size="4" access-size="4" caption="MTB Lock Access">
+        </register>
+        <register name="LOCKSTATUS" offset="0xFB4" rw="R" size="4" access-size="4" caption="MTB Lock Status">
+        </register>
+        <register name="AUTHSTATUS" offset="0xFB8" rw="R" size="4" access-size="4" caption="MTB Authentication Status">
+        </register>
+        <register name="DEVARCH" offset="0xFBC" rw="R" size="4" access-size="4" caption="MTB Device Architecture">
+        </register>
+        <register name="DEVID" offset="0xFC8" rw="R" size="4" access-size="4" caption="MTB Device Configuration">
+        </register>
+        <register name="DEVTYPE" offset="0xFCC" rw="R" size="4" access-size="4" caption="MTB Device Type">
+        </register>
+        <register name="PID4" offset="0xFD0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID5" offset="0xFD4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID6" offset="0xFD8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID7" offset="0xFDC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID0" offset="0xFE0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID1" offset="0xFE4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID2" offset="0xFE8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="PID3" offset="0xFEC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID0" offset="0xFF0" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID1" offset="0xFF4" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID2" offset="0xFF8" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+        <register name="CID3" offset="0xFFC" rw="R" size="4" access-size="4" caption="CoreSight">
+        </register>
+      </register-group>
+    </module>
+    <module name="NVMCTRL" id="U2207" version="1.0.6" caption="Non-Volatile Memory Controller">
+      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLA__CMD"/>
+          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLA__CMDEX"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
+          <bitfield name="RWS" caption="NVM Read Wait States" mask="0x1E" values="NVMCTRL_CTRLB__RWS"/>
+          <bitfield name="MANW" caption="Manual Write" mask="0x80"/>
+          <bitfield name="SLEEPPRM" caption="Power Reduction Mode during Sleep" mask="0x300" values="NVMCTRL_CTRLB__SLEEPPRM"/>
+          <bitfield name="READMODE" caption="NVMCTRL Read Mode" mask="0x30000" values="NVMCTRL_CTRLB__READMODE"/>
+          <bitfield name="CACHEDIS" caption="Cache Disable" mask="0x40000"/>
+        </register>
+        <register name="PARAM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="NVM Parameter">
+          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
+          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTENSET" offset="0x10" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="READY" caption="NVM Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error Interrupt Enable" mask="0x2"/>
+        </register>
+        <register name="INTFLAG" offset="0x14" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="READY" caption="NVM Ready" mask="0x1"/>
+          <bitfield name="ERROR" caption="Error" mask="0x2"/>
+        </register>
+        <register name="STATUS" offset="0x18" rw="RW" size="2" initval="0x0000" caption="Status">
+          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x1"/>
+          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x2"/>
+          <bitfield name="PROGE" caption="Programming Error Status" mask="0x4"/>
+          <bitfield name="LOCKE" caption="Lock Error Status" mask="0x8"/>
+          <bitfield name="NVME" caption="NVM Error" mask="0x10"/>
+          <bitfield name="SB" caption="Security Bit Status" mask="0x100"/>
+        </register>
+        <register name="ADDR" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="Address">
+          <bitfield name="ADDR" caption="NVM Address" mask="0x3FFFFF"/>
+        </register>
+        <register name="LOCK" offset="0x20" rw="RW" size="2" caption="Lock Section">
+          <bitfield name="LOCK" caption="Region Lock Bits" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="NVMCTRL_CTRLA__CMD">
+        <value name="ER" caption="Erase Row - Erases the row addressed by the ADDR register." value="0x02"/>
+        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register." value="0x04"/>
+        <value name="EAR" caption="Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x05"/>
+        <value name="WAP" caption="Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row." value="0x06"/>
+        <value name="SF" caption="Security Flow Command" value="0x0A"/>
+        <value name="WL" caption="Write lockbits" value="0x0F"/>
+        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x40"/>
+        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x41"/>
+        <value name="SPRM" caption="Sets the power reduction mode." value="0x42"/>
+        <value name="CPRM" caption="Clears the power reduction mode." value="0x43"/>
+        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x44"/>
+        <value name="SSB" caption="Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row." value="0x45"/>
+        <value name="INVALL" caption="Invalidates all cache lines." value="0x46"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLA__CMDEX">
+        <value name="KEY" caption="Execution Key" value="0xA5"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__READMODE">
+        <value name="NO_MISS_PENALTY" caption="The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance." value="0x0"/>
+        <value name="LOW_POWER" caption="Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time." value="0x1"/>
+        <value name="DETERMINISTIC" caption="The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings." value="0x2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__RWS">
+        <value name="SINGLE" caption="Single Auto Wait State" value="0"/>
+        <value name="HALF" caption="Half Auto Wait State" value="1"/>
+        <value name="DUAL" caption="Dual Auto Wait State" value="2"/>
+      </value-group>
+      <value-group name="NVMCTRL_CTRLB__SLEEPPRM">
+        <value name="WAKEONACCESS" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access." value="0"/>
+        <value name="WAKEUPINSTANT" caption="NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep." value="1"/>
+        <value name="DISABLED" caption="Auto power reduction disabled." value="3"/>
+      </value-group>
+      <value-group name="NVMCTRL_PARAM__PSZ">
+        <value name="8" caption="8 bytes" value="0x0"/>
+        <value name="16" caption="16 bytes" value="0x1"/>
+        <value name="32" caption="32 bytes" value="0x2"/>
+        <value name="64" caption="64 bytes" value="0x3"/>
+        <value name="128" caption="128 bytes" value="0x4"/>
+        <value name="256" caption="256 bytes" value="0x5"/>
+        <value name="512" caption="512 bytes" value="0x6"/>
+        <value name="1024" caption="1024 bytes" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="FUSES" id="U2207" version="1.0.6" caption="Non-Volatile Fuses">
+      <register-group name="OTP4_FUSES">
+        <register name="OTP4_WORD_0" offset="0x0" size="4" rw="R" caption="OTP4 Page Word 0">
+          <bitfield name="ADC_LINEARITY_0" caption="ADC Linearity bits 4:0" mask="0xF8000000"/>
+        </register>
+        <register name="OTP4_WORD_1" offset="0x4" size="4" rw="R" caption="OTP4 Page Word 1">
+          <bitfield name="ADC_LINEARITY_1" caption="ADC Linearity bits 7:5" mask="0x7"/>
+          <bitfield name="ADC_BIASCAL" caption="ADC Bias Calibration" mask="0x38"/>
+          <bitfield name="OSC32K_CAL" caption="OSC32K Calibration" mask="0x1FC0"/>
+          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x3E000"/>
+          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x7C0000"/>
+          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x3800000"/>
+          <bitfield name="DFLL48M_COARSE_CAL" caption="DFLL48M Coarse Calibration" mask="0xFC000000"/>
+        </register>
+        <register name="OTP4_WORD_2" offset="0x8" size="4" rw="R" caption="OTP4 Page Word 2">
+          <bitfield name="DFLL48M_FINE_CAL" caption="DFLL48M Fine Calibration" mask="0x3FF"/>
+        </register>
+      </register-group>
+      <register-group name="TEMP_LOG_FUSES">
+        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
+          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
+          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
+          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
+          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
+          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
+        </register>
+        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
+          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
+          <bitfield name="ROOM_ADC_VAL" caption="12-bit ADC conversion at room temperature" mask="0xFFF00"/>
+          <bitfield name="HOT_ADC_VAL" caption="12-bit ADC conversion at hot temperature" mask="0xFFF00000"/>
+        </register>
+      </register-group>
+      <register-group name="USER_FUSES">
+        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
+          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x7"/>
+          <bitfield name="NVMCTRL_EEPROM_SIZE" caption="EEPROM Size" mask="0x70"/>
+          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x3F00"/>
+          <bitfield name="BOD33_EN" caption="BOD33 Enable" mask="0x4000"/>
+          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x18000"/>
+          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x2000000"/>
+          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x4000000"/>
+          <bitfield name="WDT_PER" caption="WDT Period" mask="0x78000000"/>
+          <bitfield name="WDT_WINDOW_0" caption="WDT Window bit 0" mask="0x80000000"/>
+        </register>
+        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
+          <bitfield name="WDT_WINDOW_1" caption="WDT Window bits 3:1" mask="0x7"/>
+          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x78"/>
+          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x80"/>
+          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x100"/>
+          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFF0000"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PAC" id="U2211" version="1.0.1" caption="Peripheral Access Controller">
+      <register-group name="PAC" caption="Peripheral Access Controller">
+        <register name="WPCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:WPCLR" initval="0x00000000" caption="Write Protection Clear">
+          <bitfield name="WP" caption="Write Protection Clear" mask="0xFFFFFFFE"/>
+        </register>
+        <register name="WPSET" offset="0x4" rw="RW" size="4" atomic-op="set:WPSET" initval="0x00000000" caption="Write Protection Set">
+          <bitfield name="WP" caption="Write Protection Set" mask="0xFFFFFFFE"/>
+        </register>
+      </register-group>
+    </module>
+    <module name="PM" id="U2206" version="2.0.1" caption="Power Manager">
+      <register-group name="PM" caption="Power Manager">
+        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
+        </register>
+        <register name="SLEEP" offset="0x1" rw="RW" size="1" initval="0x00" caption="Sleep Mode">
+          <bitfield name="IDLE" caption="Idle Mode Configuration" mask="0x3" values="PM_SLEEP__IDLE"/>
+        </register>
+        <register name="CPUSEL" offset="0x8" rw="RW" size="1" initval="0x00" caption="CPU Clock Select">
+          <bitfield name="CPUDIV" caption="CPU Prescaler Selection" mask="0x7" values="PM_CPUSEL__CPUDIV"/>
+        </register>
+        <register name="APBASEL" offset="0x9" rw="RW" size="1" initval="0x00" caption="APBA Clock Select">
+          <bitfield name="APBADIV" caption="APBA Prescaler Selection" mask="0x7" values="PM_APBASEL__APBADIV"/>
+        </register>
+        <register name="APBBSEL" offset="0xA" rw="RW" size="1" initval="0x00" caption="APBB Clock Select">
+          <bitfield name="APBBDIV" caption="APBB Prescaler Selection" mask="0x7" values="PM_APBBSEL__APBBDIV"/>
+        </register>
+        <register name="APBCSEL" offset="0xB" rw="RW" size="1" initval="0x00" caption="APBC Clock Select">
+          <bitfield name="APBCDIV" caption="APBC Prescaler Selection" mask="0x7" values="PM_APBCSEL__APBCDIV"/>
+        </register>
+        <register name="AHBMASK" offset="0x14" rw="RW" size="4" initval="0x0000007F" caption="AHB Mask">
+          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
+          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
+          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
+          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x8"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x10"/>
+          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x20"/>
+          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x40"/>
+        </register>
+        <register name="APBAMASK" offset="0x18" rw="RW" size="4" initval="0x0000007F" caption="APBA Mask">
+          <bitfield name="PAC0_" caption="PAC0 APB Clock Enable" mask="0x1"/>
+          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
+          <bitfield name="SYSCTRL_" caption="SYSCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x8"/>
+          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x10"/>
+          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x20"/>
+          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBBMASK" offset="0x1C" rw="RW" size="4" initval="0x0000007F" caption="APBB Mask">
+          <bitfield name="PAC1_" caption="PAC1 APB Clock Enable" mask="0x1"/>
+          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
+          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
+          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x8"/>
+          <bitfield name="DMAC_" caption="DMAC APB Clock Enable" mask="0x10"/>
+          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x20"/>
+          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
+        </register>
+        <register name="APBCMASK" offset="0x20" rw="RW" size="4" initval="0x00010000" caption="APBC Mask">
+          <bitfield name="PAC2_" caption="PAC2 APB Clock Enable" mask="0x1"/>
+          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x2"/>
+          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x4"/>
+          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x8"/>
+          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x10"/>
+          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x20"/>
+          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x40"/>
+          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x80"/>
+          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x100"/>
+          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x200"/>
+          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x400"/>
+          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x800"/>
+          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x1000"/>
+          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x2000"/>
+          <bitfield name="TC6_" caption="TC6 APB Clock Enable" mask="0x4000"/>
+          <bitfield name="TC7_" caption="TC7 APB Clock Enable" mask="0x8000"/>
+          <bitfield name="ADC_" caption="ADC APB Clock Enable" mask="0x10000"/>
+          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x20000"/>
+          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x40000"/>
+          <bitfield name="PTC_" caption="PTC APB Clock Enable" mask="0x80000"/>
+          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x100000"/>
+        </register>
+        <register name="INTENCLR" offset="0x34" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x35" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x36" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
+        </register>
+        <register name="RCAUSE" offset="0x38" rw="R" size="1" initval="0x01" caption="Reset Cause">
+          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
+          <bitfield name="BOD12" caption="Brown Out 12 Detector Reset" mask="0x2"/>
+          <bitfield name="BOD33" caption="Brown Out 33 Detector Reset" mask="0x4"/>
+          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
+          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
+          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
+        </register>
+      </register-group>
+      <value-group name="PM_SLEEP__IDLE">
+        <value name="CPU" caption="The CPU clock domain is stopped" value="0"/>
+        <value name="AHB" caption="The CPU and AHB clock domains are stopped" value="1"/>
+        <value name="APB" caption="The CPU, AHB and APB clock domains are stopped" value="2"/>
+      </value-group>
+      <value-group name="PM_CPUSEL__CPUDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBASEL__APBADIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBBSEL__APBBDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+      <value-group name="PM_APBCSEL__APBCDIV">
+        <value name="DIV1" caption="Divide by 1" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV32" caption="Divide by 32" value="5"/>
+        <value name="DIV64" caption="Divide by 64" value="6"/>
+        <value name="DIV128" caption="Divide by 128" value="7"/>
+      </value-group>
+    </module>
+    <module name="PORT" id="U2210" version="1.0.0" caption="Port Module">
+      <register-group name="GROUP" size="0x80">
+        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
+          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
+          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
+          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
+          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
+          <bitfield name="OUT" caption="Port Data Output Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
+          <bitfield name="OUTCLR" caption="Port Data Output Value Clear" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
+          <bitfield name="OUTSET" caption="Port Data Output Value Set" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
+          <bitfield name="OUTTGL" caption="Port Data Output Value Toggle" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
+          <bitfield name="IN" caption="Port Data Input Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
+          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
+          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
+          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
+          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
+          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
+          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
+        </register>
+        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing n">
+          <bitfield name="PMUXE" caption="Peripheral Multiplexing Even" mask="0xF" values="PORT_PMUX__PMUXE"/>
+          <bitfield name="PMUXO" caption="Peripheral Multiplexing Odd" mask="0xF0" values="PORT_PMUX__PMUXO"/>
+        </register>
+        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration n">
+          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
+          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
+          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
+          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="PORT" caption="Port Module">
+        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="2"/>
+      </register-group>
+      <value-group name="PORT_PMUX__PMUXE">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+      <value-group name="PORT_PMUX__PMUXO">
+        <value name="A" caption="Peripheral function A selected" value="0x0"/>
+        <value name="B" caption="Peripheral function B selected" value="0x1"/>
+        <value name="C" caption="Peripheral function C selected" value="0x2"/>
+        <value name="D" caption="Peripheral function D selected" value="0x3"/>
+        <value name="E" caption="Peripheral function E selected" value="0x4"/>
+        <value name="F" caption="Peripheral function F selected" value="0x5"/>
+        <value name="G" caption="Peripheral function G selected" value="0x6"/>
+        <value name="H" caption="Peripheral function H selected" value="0x7"/>
+      </value-group>
+    </module>
+    <module name="PTC" id="U2215" version="1.0.2" caption="Peripheral Touch Controller">
+      <register-group name="PTC" caption="Peripheral Touch Controller"/>
+    </module>
+    <module name="RTC" id="U2202" version="1.0.1" caption="Real-Time Counter">
+      <register-group name="MODE2_ALARM" size="0x8">
+        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
+          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="RTC.MODE0.CTRL.MODE" name="RTC" caption="Real-Time Counter">
+        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
+        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
+        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRL__MODE"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE0 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE0 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE0 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE0 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="4" count="1" initval="0x00000000" caption="MODE0 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRL__MODE"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE1 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE1 Interrupt Enable Clear">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE1 Interrupt Enable Set">
+          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE1 Interrupt Flag Status and Clear">
+          <bitfield name="CMP0" caption="Compare 0" mask="0x1"/>
+          <bitfield name="CMP1" caption="Compare 1" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
+          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
+        </register>
+        <register name="COMP" offset="0x18" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="MODE1 Compare n Value">
+          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRL__MODE"/>
+          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
+          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRL__PRESCALER"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0010" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x3F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="MODE2 Event Control">
+          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
+          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
+          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
+          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
+          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
+          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
+          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
+          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
+          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
+          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x6" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="MODE2 Interrupt Enable Clear">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x7" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="MODE2 Interrupt Enable Set">
+          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="MODE2 Interrupt Flag Status and Clear">
+          <bitfield name="ALARM0" caption="Alarm 0" mask="0x1"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x40"/>
+          <bitfield name="OVF" caption="Overflow" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xA" rw="RW" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="DBGCTRL" offset="0xB" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
+        </register>
+        <register name="FREQCORR" offset="0xC" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
+          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
+          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
+        </register>
+        <register name="CLOCK" offset="0x10" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
+          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
+          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
+          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
+          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
+          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
+          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
+        </register>
+        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x18" count="1"/>
+      </register-group>
+      <value-group name="RTC_MODE0_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE0_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE1_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__MODE">
+        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
+        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
+        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CTRL__PRESCALER">
+        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
+        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x1"/>
+        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x2"/>
+        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x3"/>
+        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x4"/>
+        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x5"/>
+        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x6"/>
+        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x7"/>
+        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x8"/>
+        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0x9"/>
+        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xA"/>
+      </value-group>
+      <value-group name="RTC_MODE2_CLOCK__HOUR">
+        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
+        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
+        <value name="AM" caption="Morning hour" value="0x00"/>
+        <value name="PM" caption="Afternoon hour" value="0x10"/>
+      </value-group>
+      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
+        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
+        <value name="SS" caption="Match seconds only" value="0x1"/>
+        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
+        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
+        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
+        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
+        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
+      </value-group>
+    </module>
+    <module name="SERCOM" id="U2201" version="2.0.0" caption="Serial Communication Interface">
+      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
+        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
+        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
+        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
+        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
+      </register-group>
+      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CM_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
+          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
+          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
+          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
+          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
+          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
+          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
+          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CM Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_I2CS_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
+          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
+          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
+          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
+          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
+          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
+          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
+          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
+          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="CMD" caption="Command" mask="0x30000"/>
+          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
+          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
+          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
+          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
+          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
+          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
+          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
+          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
+          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
+          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
+          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
+          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
+          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
+          <bitfield name="HS" caption="High Speed" mask="0x400"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
+          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
+          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
+          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="1" initval="0x00" caption="I2CS Data">
+          <bitfield name="DATA" caption="Data Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_SPI_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
+          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
+          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
+          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
+          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
+          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
+          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
+          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x1C" values="SERCOM_USART_CTRLA__MODE"/>
+          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
+          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
+          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
+          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
+          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
+          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
+          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
+          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
+          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
+          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
+        </register>
+        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
+          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
+          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
+          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
+          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
+          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
+          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
+          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
+          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
+        </register>
+        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
+          <mode name="DEFAULT_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+          <mode name="FRAC_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="FRACFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
+            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
+          </mode>
+          <mode name="USARTFP_MODE">
+            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
+          </mode>
+        </register>
+        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
+          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
+        </register>
+        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
+        </register>
+        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
+          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
+          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
+          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
+          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
+          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
+          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
+          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
+          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
+          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
+          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
+          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
+          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
+          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Syncbusy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
+        </register>
+        <register name="DATA" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USART Data">
+          <bitfield name="DATA" caption="Data Value" mask="0x1FF"/>
+        </register>
+        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
+          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
+        </register>
+      </register-group>
+      <value-group name="SERCOM_I2CM_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_I2CS_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_SPI_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+      <value-group name="SERCOM_USART_CTRLA__MODE">
+        <value name="USART_EXT_CLK" caption="USART mode with external clock" value="0"/>
+        <value name="USART_INT_CLK" caption="USART mode with internal clock" value="1"/>
+        <value name="SPI_SLAVE" caption="SPI mode with external clock" value="2"/>
+        <value name="SPI_MASTER" caption="SPI mode with internal clock" value="3"/>
+        <value name="I2C_SLAVE" caption="I2C mode with external clock" value="4"/>
+        <value name="I2C_MASTER" caption="I2C mode with internal clock" value="5"/>
+      </value-group>
+    </module>
+    <module name="SYSCTRL" id="U2100" version="2.0.1" caption="System Control">
+      <register-group name="SYSCTRL" caption="System Control">
+        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="XOSCRDY" caption="XOSC Ready Interrupt Enable" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready Interrupt Enable" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready Interrupt Enable" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection Interrupt Enable" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready Interrupt Enable" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise Interrupt Enable" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall Interrupt Enable" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout Interrupt Enable" mask="0x20000"/>
+        </register>
+        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="PCLKSR" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
+          <bitfield name="XOSCRDY" caption="XOSC Ready" mask="0x1"/>
+          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x2"/>
+          <bitfield name="OSC32KRDY" caption="OSC32K Ready" mask="0x4"/>
+          <bitfield name="OSC8MRDY" caption="OSC8M Ready" mask="0x8"/>
+          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x10"/>
+          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x20"/>
+          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x40"/>
+          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x80"/>
+          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x100"/>
+          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x200"/>
+          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x400"/>
+          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x800"/>
+          <bitfield name="DPLLLCKR" caption="DPLL Lock Rise" mask="0x8000"/>
+          <bitfield name="DPLLLCKF" caption="DPLL Lock Fall" mask="0x10000"/>
+          <bitfield name="DPLLLTO" caption="DPLL Lock Timeout" mask="0x20000"/>
+        </register>
+        <register name="XOSC" offset="0x10" rw="RW" size="2" initval="0x0080" caption="External Multipurpose Crystal Oscillator (XOSC) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="GAIN" caption="Oscillator Gain" mask="0x700" values="SYSCTRL_XOSC__GAIN"/>
+          <bitfield name="AMPGC" caption="Automatic Amplitude Gain Control" mask="0x800"/>
+          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF000"/>
+        </register>
+        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x0080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
+          <bitfield name="AAMPEN" caption="Automatic Amplitude Control Enable" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+        </register>
+        <register name="OSC32K" offset="0x18" rw="RW" size="4" initval="0x003F0080" caption="32kHz Internal Oscillator (OSC32K) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x4"/>
+          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x8"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x7F0000"/>
+        </register>
+        <register name="OSCULP32K" offset="0x1C" rw="RW" size="1" initval="0x1F" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x1F"/>
+          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
+        </register>
+        <register name="OSC8M" offset="0x20" rw="RW" size="4" initval="0x87070382" caption="8MHz Internal Oscillator (OSC8M) Control">
+          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="PRESC" caption="Oscillator Prescaler" mask="0x300" values="SYSCTRL_OSC8M__PRESC"/>
+          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0xFFF0000"/>
+          <bitfield name="FRANGE" caption="Oscillator Frequency Range" mask="0xC0000000" values="SYSCTRL_OSC8M__FRANGE"/>
+        </register>
+        <register name="DFLLCTRL" offset="0x24" rw="RW" access="WSYNC" size="2" initval="0x0080" caption="DFLL48M Control">
+          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x4"/>
+          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x8"/>
+          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x10"/>
+          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x20"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
+          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x100"/>
+          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x200"/>
+          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x400"/>
+          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x800"/>
+        </register>
+        <register name="DFLLVAL" offset="0x28" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
+          <bitfield name="FINE" caption="Fine Value" mask="0x3FF"/>
+          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
+          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
+        </register>
+        <register name="DFLLMUL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
+          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
+          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0x3FF0000"/>
+          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
+        </register>
+        <register name="DFLLSYNC" offset="0x30" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
+          <bitfield name="READREQ" caption="Read Request" mask="0x80"/>
+        </register>
+        <register name="BOD33" offset="0x34" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="3.3V Brown-Out Detector (BOD33) Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="HYST" caption="Hysteresis" mask="0x4"/>
+          <bitfield name="ACTION" caption="BOD33 Action" mask="0x18" values="SYSCTRL_BOD33__ACTION"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="MODE" caption="Operation Mode" mask="0x100"/>
+          <bitfield name="CEN" caption="Clock Enable" mask="0x200"/>
+          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SYSCTRL_BOD33__PSEL"/>
+          <bitfield name="LEVEL" caption="BOD33 Threshold Level" mask="0x3F0000"/>
+        </register>
+        <register name="VREG" offset="0x3C" rw="RW" size="2" initval="0x0000" caption="Voltage Regulator System (VREG) Control">
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="FORCELDO" caption="Force LDO Voltage Regulator" mask="0x2000"/>
+        </register>
+        <register name="VREF" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Voltage References System (VREF) Control">
+          <bitfield name="TSEN" caption="Temperature Sensor Enable" mask="0x2"/>
+          <bitfield name="BGOUTEN" caption="Bandgap Output Enable" mask="0x4"/>
+          <bitfield name="CALIB" caption="Bandgap Voltage Generator Calibration" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLCTRLA" offset="0x44" rw="RW" size="1" initval="0x80" caption="DPLL Control A">
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
+          <bitfield name="ONDEMAND" caption="On Demand Clock Activation" mask="0x80"/>
+        </register>
+        <register name="DPLLRATIO" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="DPLL Ratio Control">
+          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0xFFF"/>
+          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0xF0000"/>
+        </register>
+        <register name="DPLLCTRLB" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="DPLL Control B">
+          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0x3" values="SYSCTRL_DPLLCTRLB__FILTER"/>
+          <bitfield name="LPEN" caption="Low-Power Enable" mask="0x4"/>
+          <bitfield name="WUF" caption="Wake Up Fast" mask="0x8"/>
+          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0x30" values="SYSCTRL_DPLLCTRLB__REFCLK"/>
+          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="SYSCTRL_DPLLCTRLB__LTIME"/>
+          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x1000"/>
+          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
+        </register>
+        <register name="DPLLSTATUS" offset="0x50" rw="R" size="1" initval="0x00" caption="DPLL Status">
+          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
+          <bitfield name="CLKRDY" caption="Output Clock Ready" mask="0x2"/>
+          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x4"/>
+          <bitfield name="DIV" caption="Divider Enable" mask="0x8"/>
+        </register>
+      </register-group>
+      <value-group name="SYSCTRL_XOSC__GAIN">
+        <value name="0" caption="2MHz" value="0x0"/>
+        <value name="1" caption="4MHz" value="0x1"/>
+        <value name="2" caption="8MHz" value="0x2"/>
+        <value name="3" caption="16MHz" value="0x3"/>
+        <value name="4" caption="30MHz" value="0x4"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__FRANGE">
+        <value name="0" caption="4 to 6MHz" value="0x0"/>
+        <value name="1" caption="6 to 8MHz" value="0x1"/>
+        <value name="2" caption="8 to 11MHz" value="0x2"/>
+        <value name="3" caption="11 to 15MHz" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_OSC8M__PRESC">
+        <value name="0" caption="1" value="0x0"/>
+        <value name="1" caption="2" value="0x1"/>
+        <value name="2" caption="4" value="0x2"/>
+        <value name="3" caption="8" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__ACTION">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
+        <value name="INTERRUPT" caption="The BOD33 generates an interrupt" value="0x2"/>
+      </value-group>
+      <value-group name="SYSCTRL_BOD33__PSEL">
+        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
+        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
+        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
+        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
+        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
+        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
+        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
+        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
+        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
+        <value name="DIV1K" caption="Divide clock by 1024" value="0x9"/>
+        <value name="DIV2K" caption="Divide clock by 2048" value="0xA"/>
+        <value name="DIV4K" caption="Divide clock by 4096" value="0xB"/>
+        <value name="DIV8K" caption="Divide clock by 8192" value="0xC"/>
+        <value name="DIV16K" caption="Divide clock by 16384" value="0xD"/>
+        <value name="DIV32K" caption="Divide clock by 32768" value="0xE"/>
+        <value name="DIV64K" caption="Divide clock by 65536" value="0xF"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__FILTER">
+        <value name="DEFAULT" caption="Default filter mode" value="0x0"/>
+        <value name="LBFILT" caption="Low bandwidth filter" value="0x1"/>
+        <value name="HBFILT" caption="High bandwidth filter" value="0x2"/>
+        <value name="HDFILT" caption="High damping filter" value="0x3"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__LTIME">
+        <value name="DEFAULT" caption="No time-out" value="0x0"/>
+        <value name="8MS" caption="Time-out if no lock within 8 ms" value="0x4"/>
+        <value name="9MS" caption="Time-out if no lock within 9 ms" value="0x5"/>
+        <value name="10MS" caption="Time-out if no lock within 10 ms" value="0x6"/>
+        <value name="11MS" caption="Time-out if no lock within 11 ms" value="0x7"/>
+      </value-group>
+      <value-group name="SYSCTRL_DPLLCTRLB__REFCLK">
+        <value name="REF0" caption="CLK_DPLL_REF0 clock reference" value="0x0"/>
+        <value name="REF1" caption="CLK_DPLL_REF1 clock reference" value="0x1"/>
+        <value name="GCLK" caption="GCLK_DPLL clock reference" value="0x2"/>
+      </value-group>
+    </module>
+    <module name="TC" id="U2212" version="1.2.1" caption="Basic Timer Counter">
+      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
+        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
+        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
+        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
+      </register-group>
+      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="1" initval="0x00" caption="COUNT8 Counter Value">
+          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
+        </register>
+        <register name="PER" offset="0x14" rw="RW" size="1" initval="0xFF" caption="COUNT8 Period Value">
+          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="1" count="2" initval="0x00" caption="COUNT8 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="2" initval="0x0000" caption="COUNT16 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="2" count="2" initval="0x0000" caption="COUNT16 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFF"/>
+        </register>
+      </register-group>
+      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
+        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="MODE" caption="TC Mode" mask="0xC" values="TC_CTRLA__MODE"/>
+          <bitfield name="WAVEGEN" caption="Waveform Generation Operation" mask="0x60" values="TC_CTRLA__WAVEGEN"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x3000" values="TC_CTRLA__PRESCSYNC"/>
+        </register>
+        <register name="READREQ" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Read Request">
+          <bitfield name="ADDR" caption="Address" mask="0x1F"/>
+          <bitfield name="RCONT" caption="Read Continuously" mask="0x4000"/>
+          <bitfield name="RREQ" caption="Read Request" mask="0x8000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CTRLBCLR" initval="0x02" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="CMD" caption="Command" mask="0xC0" values="TC_CTRLBSET__CMD"/>
+        </register>
+        <register name="CTRLC" offset="0x6" rw="RW" size="1" initval="0x00" caption="Control C">
+          <bitfield name="INVEN0" caption="Output Waveform 0 Invert Enable" mask="0x1"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Invert Enable" mask="0x2"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x10"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x20"/>
+        </register>
+        <register name="DBGCTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
+        </register>
+        <register name="EVCTRL" offset="0xA" rw="RW" size="2" initval="0x0000" caption="Event Control">
+          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
+          <bitfield name="TCINV" caption="TC Inverted Event Input" mask="0x10"/>
+          <bitfield name="TCEI" caption="TC Event Input" mask="0x20"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Event Output Enable" mask="0x100"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000"/>
+        </register>
+        <register name="INTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready Interrupt Enable" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20"/>
+        </register>
+        <register name="INTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="ERR" caption="Error" mask="0x2"/>
+          <bitfield name="SYNCRDY" caption="Synchronization Ready" mask="0x8"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0" mask="0x10"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1" mask="0x20"/>
+        </register>
+        <register name="STATUS" offset="0xF" rw="R" size="1" initval="0x08" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="COUNT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="COUNT32 Counter Value">
+          <bitfield name="COUNT" caption="Count Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="CC" offset="0x18" rw="RW" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare/Capture">
+          <bitfield name="CC" caption="Compare/Capture Value" mask="0xFFFFFFFF"/>
+        </register>
+      </register-group>
+      <value-group name="TC_CTRLA__MODE">
+        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
+        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
+        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0x0"/>
+        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="0x1"/>
+        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="0x2"/>
+        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="0x3"/>
+        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="0x4"/>
+        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="0x5"/>
+        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="0x6"/>
+        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="0x7"/>
+      </value-group>
+      <value-group name="TC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
+        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset the counter on next generic clock. Reset the prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLA__WAVEGEN">
+        <value name="NFRQ" value="0"/>
+        <value name="MFRQ" value="1"/>
+        <value name="NPWM" value="2"/>
+        <value name="MPWM" value="3"/>
+      </value-group>
+      <value-group name="TC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force a stop" value="2"/>
+      </value-group>
+      <value-group name="TC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0x0"/>
+        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="0x1"/>
+        <value name="STOP" caption="Force a stop" value="0x2"/>
+      </value-group>
+      <value-group name="TC_EVCTRL__EVACT">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
+        <value name="COUNT" caption="Count on event" value="2"/>
+        <value name="START" caption="Start TC on event" value="3"/>
+        <value name="PPW" caption="Period captured in CC0, pulse width in CC1" value="5"/>
+        <value name="PWP" caption="Period captured in CC1, pulse width in CC0" value="6"/>
+      </value-group>
+    </module>
+    <module name="TCC" id="U2213" version="1.0.1" caption="Timer Counter Control">
+      <register-group name="TCC" caption="Timer Counter Control">
+        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
+          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
+          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
+          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
+          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
+          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
+          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
+          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
+        </register>
+        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
+        </register>
+        <register name="CTRLBSET" offset="0x5" rw="RW" access="WSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
+          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
+          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
+          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
+          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
+          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
+          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
+          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
+          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
+          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
+          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
+          <bitfield name="PER" caption="Period busy" mask="0x80"/>
+          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
+          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
+          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
+          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
+          <bitfield name="PATTB" caption="Pattern Buffer Busy" mask="0x10000"/>
+          <bitfield name="WAVEB" caption="Wave Buffer Busy" mask="0x20000"/>
+          <bitfield name="PERB" caption="Period Buffer Busy" mask="0x40000"/>
+          <bitfield name="CCB0" caption="Compare Channel Buffer 0 Busy" mask="0x80000"/>
+          <bitfield name="CCB1" caption="Compare Channel Buffer 1 Busy" mask="0x100000"/>
+          <bitfield name="CCB2" caption="Compare Channel Buffer 2 Busy" mask="0x200000"/>
+          <bitfield name="CCB3" caption="Compare Channel Buffer 3 Busy" mask="0x400000"/>
+        </register>
+        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
+          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
+          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
+          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
+          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
+          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
+          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
+          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
+          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
+          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
+          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
+          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
+          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
+          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
+          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
+        </register>
+        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
+          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
+          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
+          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
+          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
+          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
+          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
+          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
+        </register>
+        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
+          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
+          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
+          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
+          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
+          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
+          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
+          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
+          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
+          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
+          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
+          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
+          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
+          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
+          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
+          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
+          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
+          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
+          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
+          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
+          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
+          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
+          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
+          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
+          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
+          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
+          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
+        </register>
+        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
+          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
+          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
+        </register>
+        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
+          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
+          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
+          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
+          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
+          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
+          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
+          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
+          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
+          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
+          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
+          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
+          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
+          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
+          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
+          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
+          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
+          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
+          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
+        </register>
+        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
+          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
+          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
+        </register>
+        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
+          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
+          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
+          <bitfield name="CNT" caption="Counter" mask="0x4"/>
+          <bitfield name="ERR" caption="Error" mask="0x8"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
+          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
+          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
+          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
+          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
+        </register>
+        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
+          <bitfield name="STOP" caption="Stop" mask="0x1"/>
+          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
+          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
+          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
+          <bitfield name="PATTBV" caption="Pattern Buffer Valid" mask="0x20"/>
+          <bitfield name="WAVEBV" caption="Wave Buffer Valid" mask="0x40"/>
+          <bitfield name="PERBV" caption="Period Buffer Valid" mask="0x80"/>
+          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
+          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
+          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
+          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
+          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
+          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
+          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
+          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
+          <bitfield name="CCBV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
+          <bitfield name="CCBV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
+          <bitfield name="CCBV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
+          <bitfield name="CCBV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
+          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
+          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
+          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
+          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
+        </register>
+        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
+          <mode name="DITH4">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
+          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
+          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
+          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
+          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
+          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
+          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
+          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
+          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
+          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
+          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
+          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
+          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
+          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
+          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
+          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
+          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
+        </register>
+        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
+          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
+          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
+          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
+          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
+          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
+          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
+          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
+          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
+          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
+          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
+          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
+          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
+          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
+          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
+          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
+        </register>
+        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CC" offset="0x44" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture">
+          <mode name="DITH4">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0xF"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x1F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCY" caption="Dithering Cycle Number" mask="0x3F"/>
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="PATTB" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
+          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
+          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
+          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
+          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
+          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
+          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
+          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
+          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
+          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
+          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
+          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
+          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
+          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
+          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
+          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
+          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
+        </register>
+        <register name="WAVEB" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Waveform Control Buffer">
+          <bitfield name="WAVEGENB" caption="Waveform Generation Buffer" mask="0x7" values="TCC_WAVEB__WAVEGENB"/>
+          <bitfield name="RAMPB" caption="Ramp Mode Buffer" mask="0x30" values="TCC_WAVEB__RAMPB"/>
+          <bitfield name="CIPERENB" caption="Circular Period Enable Buffer" mask="0x80"/>
+          <bitfield name="CICCENB0" caption="Circular Channel 0 Enable Buffer" mask="0x100"/>
+          <bitfield name="CICCENB1" caption="Circular Channel 1 Enable Buffer" mask="0x200"/>
+          <bitfield name="CICCENB2" caption="Circular Channel 2 Enable Buffer" mask="0x400"/>
+          <bitfield name="CICCENB3" caption="Circular Channel 3 Enable Buffer" mask="0x800"/>
+          <bitfield name="POLB0" caption="Channel 0 Polarity Buffer" mask="0x10000"/>
+          <bitfield name="POLB1" caption="Channel 1 Polarity Buffer" mask="0x20000"/>
+          <bitfield name="POLB2" caption="Channel 2 Polarity Buffer" mask="0x40000"/>
+          <bitfield name="POLB3" caption="Channel 3 Polarity Buffer" mask="0x80000"/>
+          <bitfield name="SWAPB0" caption="Swap DTI Output Pair 0 Buffer" mask="0x1000000"/>
+          <bitfield name="SWAPB1" caption="Swap DTI Output Pair 1 Buffer" mask="0x2000000"/>
+          <bitfield name="SWAPB2" caption="Swap DTI Output Pair 2 Buffer" mask="0x4000000"/>
+          <bitfield name="SWAPB3" caption="Swap DTI Output Pair 3 Buffer" mask="0x8000000"/>
+        </register>
+        <register name="PERB" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="PERB" caption="Period Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+        <register name="CCB" offset="0x70" rw="RW" size="4" count="4" initval="0x00000000" caption="Compare and Capture Buffer">
+          <mode name="DITH4">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0xF"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFF0"/>
+          </mode>
+          <mode name="DITH5">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
+          </mode>
+          <mode name="DITH6">
+            <bitfield name="DITHERCYB" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
+          </mode>
+          <mode name="DEFAULT_MODE">
+            <bitfield name="CCB" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
+          </mode>
+        </register>
+      </register-group>
+      <value-group name="TCC_CTRLA__PRESCALER">
+        <value name="DIV1" caption="No division" value="0"/>
+        <value name="DIV2" caption="Divide by 2" value="1"/>
+        <value name="DIV4" caption="Divide by 4" value="2"/>
+        <value name="DIV8" caption="Divide by 8" value="3"/>
+        <value name="DIV16" caption="Divide by 16" value="4"/>
+        <value name="DIV64" caption="Divide by 64" value="5"/>
+        <value name="DIV256" caption="Divide by 256" value="6"/>
+        <value name="DIV1024" caption="Divide by 1024" value="7"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__PRESCSYNC">
+        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
+        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
+        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
+      </value-group>
+      <value-group name="TCC_CTRLA__RESOLUTION">
+        <value name="NONE" caption="Dithering is disabled" value="0"/>
+        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
+        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
+        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBCLR__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__CMD">
+        <value name="NONE" caption="No action" value="0"/>
+        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
+        <value name="STOP" caption="Force stop" value="2"/>
+        <value name="UPDATE" caption="Force update of double buffered registers" value="3"/>
+        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
+      </value-group>
+      <value-group name="TCC_CTRLBSET__IDXCMD">
+        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
+        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
+        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
+        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLA__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__BLANK">
+        <value name="NONE" caption="No blanking applied" value="0"/>
+        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
+        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
+        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CAPTURE">
+        <value name="DISABLE" caption="No capture" value="0"/>
+        <value name="CAPT" caption="Capture on fault" value="1"/>
+        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
+        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
+        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
+        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
+        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__CHSEL">
+        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
+        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
+        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
+        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__HALT">
+        <value name="DISABLE" caption="Halt action disabled" value="0"/>
+        <value name="HW" caption="Hardware halt action" value="1"/>
+        <value name="SW" caption="Software halt action" value="2"/>
+        <value name="NR" caption="Non-recoverable fault" value="3"/>
+      </value-group>
+      <value-group name="TCC_FCTRLB__SRC">
+        <value name="DISABLE" caption="Fault input disabled" value="0"/>
+        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
+        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
+        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__CNTSEL">
+        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
+        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
+        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
+        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT0">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
+        <value name="COUNTEV" caption="Count on event" value="2"/>
+        <value name="START" caption="Start counter on event" value="3"/>
+        <value name="INC" caption="Increment counter on event" value="4"/>
+        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_EVCTRL__EVACT1">
+        <value name="OFF" caption="Event action disabled" value="0"/>
+        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
+        <value name="DIR" caption="Direction control" value="2"/>
+        <value name="STOP" caption="Stop counter on event" value="3"/>
+        <value name="DEC" caption="Decrement counter on event" value="4"/>
+        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
+        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
+        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVE__RAMP">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVE__WAVEGEN">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__RAMPB">
+        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
+        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
+        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
+      </value-group>
+      <value-group name="TCC_WAVEB__WAVEGENB">
+        <value name="NFRQ" caption="Normal frequency" value="0"/>
+        <value name="MFRQ" caption="Match frequency" value="1"/>
+        <value name="NPWM" caption="Normal PWM" value="2"/>
+        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
+        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
+        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
+        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
+      </value-group>
+    </module>
+    <module name="USB" id="U2222" version="1.0.1" caption="Universal Serial Bus">
+      <register-group name="DEVICE_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_DESC_BANK" size="0x10">
+        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
+          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
+          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
+          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
+          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
+          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
+        </register>
+        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
+          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
+          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
+        </register>
+        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
+          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
+          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
+        </register>
+        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
+          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
+          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
+          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
+        </register>
+        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
+          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
+          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
+          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
+          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
+          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
+          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
+        </register>
+      </register-group>
+      <register-group name="DEVICE_ENDPOINT" size="0x20">
+        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
+          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
+          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
+          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
+          <bitfield name="CURBK" caption="Curren Bank Clear" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
+          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
+          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
+          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
+          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
+        </register>
+        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
+        </register>
+        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
+          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
+          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
+          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
+        </register>
+      </register-group>
+      <register-group name="HOST_PIPE" size="0x20">
+        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
+          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
+          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
+          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
+        </register>
+        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
+          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
+        </register>
+        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
+          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
+          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
+        </register>
+        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
+          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
+        </register>
+        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
+          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
+          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
+          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
+          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
+          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
+        </register>
+        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
+        </register>
+        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Disable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
+        </register>
+        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
+          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
+          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
+          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
+          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
+          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
+          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
+        </register>
+      </register-group>
+      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
+        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
+        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
+      </register-group>
+      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
+          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
+          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
+          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
+          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
+          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
+        </register>
+        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
+          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
+          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
+          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
+          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
+          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
+          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
+          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
+          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
+        </register>
+        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
+          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
+        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
+        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
+          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
+          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
+        </register>
+        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
+          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
+          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
+        </register>
+        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x05" caption="USB Quality Of Service">
+          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3" values="USB_QOSCTRL__CQOS"/>
+          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC" values="USB_QOSCTRL__DQOS"/>
+        </register>
+        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
+          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
+          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
+          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
+          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
+          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
+          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
+          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
+          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
+        </register>
+        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
+          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
+          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
+        </register>
+        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
+          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
+          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
+        </register>
+        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
+          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
+        </register>
+        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
+          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
+          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
+        </register>
+        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
+          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
+        </register>
+        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
+          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
+        </register>
+        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
+          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
+          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
+          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
+        </register>
+        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
+          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
+          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
+          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
+          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
+          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
+          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
+          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
+          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
+        </register>
+        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
+          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
+          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
+          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
+          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
+          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
+          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
+          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
+          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
+        </register>
+        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
+          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
+        </register>
+        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
+          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
+          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
+          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
+        </register>
+        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
+      </register-group>
+      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
+        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
+      </register-group>
+      <value-group name="USB_CTRLA__MODE">
+        <value name="DEVICE" caption="Device Mode" value="0"/>
+        <value name="HOST" caption="Host Mode" value="1"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__CQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_QOSCTRL__DQOS">
+        <value name="DISABLE" caption="Background (no sensitive operation)" value="0x0"/>
+        <value name="LOW" caption="Sensitive Bandwidth" value="0x1"/>
+        <value name="MEDIUM" caption="Sensitive Latency" value="0x2"/>
+        <value name="HIGH" caption="Critical Latency" value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
+        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
+        <value name="ACK" caption="ACK" value="1"/>
+        <value name="NYET" caption="NYET" value="2"/>
+        <value name="STALL" caption="STALL" value="3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
+        <value name="FS" caption="FS : Full Speed" value="0x0"/>
+        <value name="LS" caption="LS : Low Speed" value="0x1"/>
+        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
+        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
+      </value-group>
+      <value-group name="USB_HOST_CTRLB__SPDCONF">
+        <value name="NORMAL" caption="Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
+        <value name="FS" caption="Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__LINESTATE">
+        <value name="0" caption="SE0/RESET" value="0x0"/>
+        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
+        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
+      </value-group>
+      <value-group name="USB_DEVICE_STATUS__SPEED">
+        <value name="FS" caption="Full-speed mode" value="0x0"/>
+        <value name="HS" caption="High-speed mode" value="0x1"/>
+        <value name="LS" caption="Low-speed mode" value="0x2"/>
+      </value-group>
+      <value-group name="USB_FSMSTATUS__FSMSTATE">
+        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
+        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
+        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
+        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
+        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
+        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
+        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
+      </value-group>
+    </module>
+    <module name="WDT" id="U2203" version="2.0.0" caption="Watchdog Timer">
+      <register-group name="WDT" caption="Watchdog Timer">
+        <register name="CTRL" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
+          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
+          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
+          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
+        </register>
+        <register name="CONFIG" offset="0x1" rw="RW" access="WSYNC" size="1" initval="0xBB" caption="Configuration">
+          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
+          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
+        </register>
+        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
+          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
+        </register>
+        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
+          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
+        </register>
+        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
+          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
+        </register>
+        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
+          <bitfield name="SYNCBUSY" caption="Synchronization Busy" mask="0x80"/>
+        </register>
+        <register name="CLEAR" offset="0x8" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
+          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
+        </register>
+      </register-group>
+      <value-group name="WDT_CONFIG__PER">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CONFIG__WINDOW">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_EWCTRL__EWOFFSET">
+        <value name="8" caption="8 clock cycles" value="0x0"/>
+        <value name="16" caption="16 clock cycles" value="0x1"/>
+        <value name="32" caption="32 clock cycles" value="0x2"/>
+        <value name="64" caption="64 clock cycles" value="0x3"/>
+        <value name="128" caption="128 clock cycles" value="0x4"/>
+        <value name="256" caption="256 clock cycles" value="0x5"/>
+        <value name="512" caption="512 clock cycles" value="0x6"/>
+        <value name="1K" caption="1024 clock cycles" value="0x7"/>
+        <value name="2K" caption="2048 clock cycles" value="0x8"/>
+        <value name="4K" caption="4096 clock cycles" value="0x9"/>
+        <value name="8K" caption="8192 clock cycles" value="0xA"/>
+        <value name="16K" caption="16384 clock cycles" value="0xB"/>
+      </value-group>
+      <value-group name="WDT_CLEAR__CLEAR">
+        <value name="KEY" caption="Clear Key" value="0xA5"/>
+      </value-group>
+    </module>
+  <module name="SystemControl" caption="System Control Registers">
+      <register-group name="SystemControl" caption="System Control Registers">
+        <register offset="0x00000d00" size="4" name="CPUID" initval="0x410CC601" caption="CPUID Base Register">
+          <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
+          <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
+          <bitfield mask="0x000f0000" name="ARCHITECTURE" caption="Constant that defines the architecture of the processor"/>
+          <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
+          <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
+        </register>
+        <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
+          <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
+          <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
+          <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
+          <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
+          <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
+        </register>
+        <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
+          <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
+        </register>
+        <register offset="0x00000d0c" size="4" name="AIRCR" initval="0xFA050000" caption="Application Interrupt and Reset Control Register">
+          <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
+          <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
+          <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
+        </register>
+        <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
+          <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
+          <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
+        </register>
+        <register offset="0x00000d14" size="4" name="CCR" initval="0x00000204" caption="Configuration and Control Register">
+          <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
+          <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
+        </register>
+        <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
+          <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
+        </register>
+        <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
+          <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
+          <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
+        </register>
+      </register-group>
+      <value-group name="PENDSTCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
+      </value-group>
+      <value-group name="PENDSTSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
+      </value-group>
+      <value-group name="PENDSVCLR">
+        <value value="0" name="VALUE_0" caption="no effect"/>
+        <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
+      </value-group>
+      <value-group name="PENDSVSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
+      </value-group>
+      <value-group name="NMIPENDSET">
+        <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
+        <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
+      </value-group>
+      <value-group name="SYSRESETREQ">
+        <value value="0" name="VALUE_0" caption="no system reset request"/>
+        <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
+      </value-group>
+      <value-group name="ENDIANNESS">
+        <value value="0" name="VALUE_0" caption="Little-endian"/>
+        <value value="1" name="VALUE_1" caption="Big-endian"/>
+      </value-group>
+      <value-group name="SLEEPONEXIT">
+        <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
+        <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
+      </value-group>
+      <value-group name="SLEEPDEEP">
+        <value value="0" name="VALUE_0" caption="sleep"/>
+        <value value="1" name="VALUE_1" caption="deep sleep"/>
+      </value-group>
+      <value-group name="SEVONPEND">
+        <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
+        <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
+      </value-group>
+      <value-group name="UNALIGN_TRP">
+        <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
+        <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
+      </value-group>
+      <value-group name="STKALIGN">
+        <value value="0" name="VALUE_0" caption="4-byte aligned"/>
+        <value value="1" name="VALUE_1" caption="8-byte aligned"/>
+      </value-group>
+    </module><module name="SysTick" caption="System timer">
+      <register-group name="SysTick" caption="System timer">
+        <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
+          <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
+          <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
+          <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
+          <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
+        </register>
+        <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
+          <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
+        </register>
+        <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
+          <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
+        </register>
+        <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
+          <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
+          <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
+          <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
+        </register>
+      </register-group>
+      <value-group name="ENABLE">
+        <value value="0" name="VALUE_0" caption="counter disabled"/>
+        <value value="1" name="VALUE_1" caption="counter enabled"/>
+      </value-group>
+      <value-group name="TICKINT">
+        <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
+        <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
+      </value-group>
+      <value-group name="CLKSOURCE">
+        <value value="0" name="VALUE_0" caption="external clock"/>
+        <value value="1" name="VALUE_1" caption="processor clock"/>
+      </value-group>
+      <value-group name="SKEW">
+        <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
+        <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
+      </value-group>
+      <value-group name="NOREF">
+        <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
+        <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
+      </value-group>
+    </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
+      <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
+        <register offset="0x00000000" size="4" name="NVICISER" initval="0" caption="Interrupt Set Enable Register">
+          <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
+        </register>
+        <register offset="0x00000080" size="4" name="NVICICER" initval="0" caption="Interrupt Clear Enable Register">
+          <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
+        </register>
+        <register offset="0x00000100" size="4" name="NVICISPR" initval="0" caption="Interrupt Set Pending Register">
+          <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
+        </register>
+        <register offset="0x00000180" size="4" name="NVICICPR" initval="0" caption="Interrupt Clear Pending Register">
+          <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
+        </register>
+        <register offset="0x00000300" size="4" name="NVICIPR0" initval="0" caption="Interrupt Priority Register 0">
+          <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
+          <bitfield mask="0x0000ff00" name="PRI1" caption="Priority of interrupt 1"/>
+          <bitfield mask="0x00ff0000" name="PRI2" caption="Priority of interrupt 2"/>
+          <bitfield mask="0xff000000" name="PRI3" caption="Priority of interrupt 3"/>
+        </register>
+        <register offset="0x00000304" size="4" name="NVICIPR1" initval="0" caption="Interrupt Priority Register 1">
+          <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
+          <bitfield mask="0x0000ff00" name="PRI5" caption="Priority of interrupt 5"/>
+          <bitfield mask="0x00ff0000" name="PRI6" caption="Priority of interrupt 6"/>
+          <bitfield mask="0xff000000" name="PRI7" caption="Priority of interrupt 7"/>
+        </register>
+        <register offset="0x00000308" size="4" name="NVICIPR2" initval="0" caption="Interrupt Priority Register 2">
+          <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
+          <bitfield mask="0x0000ff00" name="PRI9" caption="Priority of interrupt 9"/>
+          <bitfield mask="0x00ff0000" name="PRI10" caption="Priority of interrupt 10"/>
+          <bitfield mask="0xff000000" name="PRI11" caption="Priority of interrupt 11"/>
+        </register>
+        <register offset="0x0000030C" size="4" name="NVICIPR3" initval="0" caption="Interrupt Priority Register 3">
+          <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
+          <bitfield mask="0x0000ff00" name="PRI13" caption="Priority of interrupt 13"/>
+          <bitfield mask="0x00ff0000" name="PRI14" caption="Priority of interrupt 14"/>
+          <bitfield mask="0xff000000" name="PRI15" caption="Priority of interrupt 15"/>
+        </register>
+        <register offset="0x00000310" size="4" name="NVICIPR4" initval="0" caption="Interrupt Priority Register 4">
+          <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
+          <bitfield mask="0x0000ff00" name="PRI17" caption="Priority of interrupt 17"/>
+          <bitfield mask="0x00ff0000" name="PRI18" caption="Priority of interrupt 18"/>
+          <bitfield mask="0xff000000" name="PRI19" caption="Priority of interrupt 19"/>
+        </register>
+        <register offset="0x00000314" size="4" name="NVICIPR5" initval="0" caption="Interrupt Priority Register 5">
+          <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
+          <bitfield mask="0x0000ff00" name="PRI21" caption="Priority of interrupt 21"/>
+          <bitfield mask="0x00ff0000" name="PRI22" caption="Priority of interrupt 22"/>
+          <bitfield mask="0xff000000" name="PRI23" caption="Priority of interrupt 23"/>
+        </register>
+        <register offset="0x00000318" size="4" name="NVICIPR6" initval="0" caption="Interrupt Priority Register 6">
+          <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
+          <bitfield mask="0x0000ff00" name="PRI25" caption="Priority of interrupt 25"/>
+          <bitfield mask="0x00ff0000" name="PRI26" caption="Priority of interrupt 26"/>
+          <bitfield mask="0xff000000" name="PRI27" caption="Priority of interrupt 27"/>
+        </register>
+        <register offset="0x0000031C" size="4" name="NVICIPR7" initval="0" caption="Interrupt Priority Register 7">
+          <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
+          <bitfield mask="0x0000ff00" name="PRI29" caption="Priority of interrupt 29"/>
+          <bitfield mask="0x00ff0000" name="PRI30" caption="Priority of interrupt 30"/>
+          <bitfield mask="0xff000000" name="PRI31" caption="Priority of interrupt 31"/>
+        </register>
+      </register-group>
+    </module></modules>
+  <pinouts>
+    <pinout name="SAMD21JC" caption="SAMD21JC">
+      <pin position="A1" pad="PB02"/>
+      <pin position="A2" pad="PB01"/>
+      <pin position="A3" pad="VDDIN"/>
+      <pin position="A4" pad="VDDCORE"/>
+      <pin position="A5" pad="GNDIO"/>
+      <pin position="A6" pad="PA28"/>
+      <pin position="A7" pad="PB23"/>
+      <pin position="A8" pad="PB22"/>
+      <pin position="B1" pad="PA00"/>
+      <pin position="B2" pad="PB00"/>
+      <pin position="B3" pad="PB31"/>
+      <pin position="B4" pad="PA31"/>
+      <pin position="B5" pad="PA30"/>
+      <pin position="B6" pad="RESET_N"/>
+      <pin position="B7" pad="PA27"/>
+      <pin position="B8" pad="VDDIO04"/>
+      <pin position="C1" pad="PA01"/>
+      <pin position="C2" pad="PB03"/>
+      <pin position="C3" pad="PA02"/>
+      <pin position="C4" pad="PB30"/>
+      <pin position="C5" pad="PA21"/>
+      <pin position="C6" pad="PA22"/>
+      <pin position="C7" pad="PA23"/>
+      <pin position="C8" pad="GNDIO04"/>
+      <pin position="D1" pad="GNDANA"/>
+      <pin position="D2" pad="PB04"/>
+      <pin position="D3" pad="PA03"/>
+      <pin position="D4" pad="PB05"/>
+      <pin position="D5" pad="PB17"/>
+      <pin position="D6" pad="PA20"/>
+      <pin position="D7" pad="PB16"/>
+      <pin position="D8" pad="PA25"/>
+      <pin position="E1" pad="VDDANA"/>
+      <pin position="E2" pad="PB08"/>
+      <pin position="E3" pad="PB07"/>
+      <pin position="E4" pad="PB06"/>
+      <pin position="E5" pad="PB11"/>
+      <pin position="E6" pad="PB15"/>
+      <pin position="E7" pad="PA19"/>
+      <pin position="E8" pad="PA24"/>
+      <pin position="F1" pad="PA04"/>
+      <pin position="F2" pad="PA05"/>
+      <pin position="F3" pad="PA10"/>
+      <pin position="F4" pad="PB09"/>
+      <pin position="F5" pad="PB12"/>
+      <pin position="F6" pad="PA12"/>
+      <pin position="F7" pad="PA18"/>
+      <pin position="F8" pad="PA17"/>
+      <pin position="G1" pad="PA07"/>
+      <pin position="G2" pad="PA06"/>
+      <pin position="G3" pad="PA11"/>
+      <pin position="G4" pad="PB10"/>
+      <pin position="G5" pad="PB13"/>
+      <pin position="G6" pad="PA13"/>
+      <pin position="G7" pad="PA16"/>
+      <pin position="G8" pad="VDDIO03"/>
+      <pin position="H1" pad="PA08"/>
+      <pin position="H2" pad="PA09"/>
+      <pin position="H3" pad="VDDIO02"/>
+      <pin position="H4" pad="GNDIO02"/>
+      <pin position="H5" pad="PB14"/>
+      <pin position="H6" pad="PA14"/>
+      <pin position="H7" pad="PA15"/>
+      <pin position="H8" pad="GNDIO03"/>
+    </pinout>
+    <pinout name="SAMD21J" caption="SAMD21J">
+      <pin position="1" pad="PA00"/>
+      <pin position="2" pad="PA01"/>
+      <pin position="3" pad="PA02"/>
+      <pin position="4" pad="PA03"/>
+      <pin position="5" pad="PB04"/>
+      <pin position="6" pad="PB05"/>
+      <pin position="7" pad="GNDANA"/>
+      <pin position="8" pad="VDDANA"/>
+      <pin position="9" pad="PB06"/>
+      <pin position="10" pad="PB07"/>
+      <pin position="11" pad="PB08"/>
+      <pin position="12" pad="PB09"/>
+      <pin position="13" pad="PA04"/>
+      <pin position="14" pad="PA05"/>
+      <pin position="15" pad="PA06"/>
+      <pin position="16" pad="PA07"/>
+      <pin position="17" pad="PA08"/>
+      <pin position="18" pad="PA09"/>
+      <pin position="19" pad="PA10"/>
+      <pin position="20" pad="PA11"/>
+      <pin position="21" pad="VDDIO02"/>
+      <pin position="22" pad="GNDIO02"/>
+      <pin position="23" pad="PB10"/>
+      <pin position="24" pad="PB11"/>
+      <pin position="25" pad="PB12"/>
+      <pin position="26" pad="PB13"/>
+      <pin position="27" pad="PB14"/>
+      <pin position="28" pad="PB15"/>
+      <pin position="29" pad="PA12"/>
+      <pin position="30" pad="PA13"/>
+      <pin position="31" pad="PA14"/>
+      <pin position="32" pad="PA15"/>
+      <pin position="33" pad="GNDIO03"/>
+      <pin position="34" pad="VDDIO03"/>
+      <pin position="35" pad="PA16"/>
+      <pin position="36" pad="PA17"/>
+      <pin position="37" pad="PA18"/>
+      <pin position="38" pad="PA19"/>
+      <pin position="39" pad="PB16"/>
+      <pin position="40" pad="PB17"/>
+      <pin position="41" pad="PA20"/>
+      <pin position="42" pad="PA21"/>
+      <pin position="43" pad="PA22"/>
+      <pin position="44" pad="PA23"/>
+      <pin position="45" pad="PA24"/>
+      <pin position="46" pad="PA25"/>
+      <pin position="47" pad="GNDIO04"/>
+      <pin position="48" pad="VDDIO04"/>
+      <pin position="49" pad="PB22"/>
+      <pin position="50" pad="PB23"/>
+      <pin position="51" pad="PA27"/>
+      <pin position="52" pad="RESET_N"/>
+      <pin position="53" pad="PA28"/>
+      <pin position="54" pad="GNDIO"/>
+      <pin position="55" pad="VDDCORE"/>
+      <pin position="56" pad="VDDIN"/>
+      <pin position="57" pad="PA30"/>
+      <pin position="58" pad="PA31"/>
+      <pin position="59" pad="PB30"/>
+      <pin position="60" pad="PB31"/>
+      <pin position="61" pad="PB00"/>
+      <pin position="62" pad="PB01"/>
+      <pin position="63" pad="PB02"/>
+      <pin position="64" pad="PB03"/>
+    </pinout>
+  </pinouts>
+</avr-tools-device-file>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E15A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E15A.ddf
new file mode 100644
index 00000000..f3842ad6
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E15A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21E15A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E16A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E16A.ddf
new file mode 100644
index 00000000..8b63a4c5
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E16A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21E16A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E17A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E17A.ddf
new file mode 100644
index 00000000..b4864a6b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E17A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21E17A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E18A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E18A.ddf
new file mode 100644
index 00000000..c7c63257
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21E18A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21E18A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G15A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G15A.ddf
new file mode 100644
index 00000000..a263068a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G15A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21G15A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G16A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G16A.ddf
new file mode 100644
index 00000000..9815e291
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G16A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21G16A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G17A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G17A.ddf
new file mode 100644
index 00000000..387dcad9
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G17A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21G17A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G17AU.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G17AU.ddf
new file mode 100644
index 00000000..257516b5
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G17AU.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21G17AU.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G18A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G18A.ddf
new file mode 100644
index 00000000..15c4b00e
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G18A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21G18A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G18AU.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G18AU.ddf
new file mode 100644
index 00000000..ef0cf28f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21G18AU.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21G18AU.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J15A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J15A.ddf
new file mode 100644
index 00000000..a4aed8e9
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J15A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21J15A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J16A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J16A.ddf
new file mode 100644
index 00000000..82f1a957
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J16A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21J16A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J17A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J17A.ddf
new file mode 100644
index 00000000..61f26883
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J17A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21J17A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J18A.ddf b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J18A.ddf
new file mode 100644
index 00000000..1ac8d46f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/ATSAMD21J18A.ddf
@@ -0,0 +1,25 @@
+
+;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Used to define address zones within the ARM address space (Memory).
+;;
+;;   Name      may be almost anything
+;;   AdrSpace  must be Memory
+;;   StartAdr  start of memory block
+;;   EndAdr    end of memory block
+;;   AccType   type of access, read-only (R), read-write (RW) or SFR (W)
+
+[Memory]
+;;          Name      AdrSpace  StartAdr    EndAdr      AccType
+Memory0  =  FLASH       Memory  0x00000000  0x0003FFFF  R
+Memory1  =  HMCRAMC0    Memory  0x20000000  0x20007FFF  RW
+Memory2  =  HPB0        Memory  0x40000000  0x4000FFFF  W
+Memory3  =  HPB1        Memory  0x41000000  0x4100FFFF  W
+Memory4  =  HPB2        Memory  0x42000000  0x4200FFFF  W
+Memory5  =  PPB         Memory  0xE0000000  0xE00FFFFF  W
+
+TrustedRanges = true
+UseSfrFilter = true
+
+[SfrInclude]
+File = ATSAMD21J18A.svd
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/Trace_SAMD21.dmac b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/Trace_SAMD21.dmac
new file mode 100644
index 00000000..8ce00e51
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/debugger/Atmel/Trace_SAMD21.dmac
@@ -0,0 +1,78 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  NANTES  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any  kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: Trace_SAMD21.dmac
+//  User setup file for CSPY debugger.
+// ---------------------------------------------------------
+
+/*********************************************************************
+*
+*       execUserReset()
+*  Called once after the target application is downloaded.
+*  Implement this macro to set up the memory map, breakpoints,
+*  interrupts, register macro files, etc.
+*
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+    __message "-------------------------------Set PC Reset ----------------------------------";
+    __writeMemory32(0x05FA0004,0xE000ED0C,"Memory");
+    //__hwReset(0);
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+* Called after communication with the target system is established
+* but before downloading the target application.
+* Implement this macro to initialize memory locations and/or
+* registers which are vital for loading data properly.
+*
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+}
+
+/*********************************************************************
+*
+*       execUserFlashInit()
+*
+* Called once before the flash loader is downloaded to RAM.
+* Implement this macro typically for setting up the memory map
+* required by the flash loader. This macro is only called when you
+* are programming flash, and it should only be used for flash loader
+* functionality.
+*
+*/
+
+execUserFlashInit()
+{
+
+    __message "------------------------------ execUserFlashInit ---------------------------------";
+
+}
+
+
+/*********************************************************************
+*
+*       execUserFlashExit()
+* Called once when the debug session ends.
+* Implement this macro to save status data etc. This macro is useful
+* for flash loader functionality
+*
+*/
+execUserFlashExit()
+{
+    __message "------------------------------ execUserFlashExit ---------------------------------";
+    //__hwReset(0);
+}
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E15A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E15A.i79
new file mode 100644
index 00000000..07468dde
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E15A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21E15A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21E15A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21e15a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e15a\samd21e15a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E15A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E15A.menu
new file mode 100644
index 00000000..51430c5b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E15A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21E15A</tag>
+  <display>Atmel ATSAMD21E15A</display>
+  <data>$CUR_DIR$\ATSAMD21E15A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E16A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E16A.i79
new file mode 100644
index 00000000..3aa8965c
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E16A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21E16A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21E16A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21e16a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e16a\samd21e16a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E16A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E16A.menu
new file mode 100644
index 00000000..0653daed
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E16A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21E16A</tag>
+  <display>Atmel ATSAMD21E16A</display>
+  <data>$CUR_DIR$\ATSAMD21E16A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E17A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E17A.i79
new file mode 100644
index 00000000..36a7da7f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E17A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21E17A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21E17A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21e17a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e17a\samd21e17a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E17A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E17A.menu
new file mode 100644
index 00000000..89b31446
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E17A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21E17A</tag>
+  <display>Atmel ATSAMD21E17A</display>
+  <data>$CUR_DIR$\ATSAMD21E17A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E18A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E18A.i79
new file mode 100644
index 00000000..31d0a83d
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E18A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21E18A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21E18A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21e18a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e18a\samd21e18a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E18A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E18A.menu
new file mode 100644
index 00000000..3a4a8b76
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21E18A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21E18A</tag>
+  <display>Atmel ATSAMD21E18A</display>
+  <data>$CUR_DIR$\ATSAMD21E18A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G15A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G15A.i79
new file mode 100644
index 00000000..f6713698
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G15A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21G15A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21G15A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21g15a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g15a\samd21g15a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G15A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G15A.menu
new file mode 100644
index 00000000..f2189301
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G15A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21G15A</tag>
+  <display>Atmel ATSAMD21G15A</display>
+  <data>$CUR_DIR$\ATSAMD21G15A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G16A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G16A.i79
new file mode 100644
index 00000000..d2f053ed
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G16A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21G16A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21G16A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21g16a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g16a\samd21g16a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G16A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G16A.menu
new file mode 100644
index 00000000..cb3fe40f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G16A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21G16A</tag>
+  <display>Atmel ATSAMD21G16A</display>
+  <data>$CUR_DIR$\ATSAMD21G16A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17A.i79
new file mode 100644
index 00000000..a59ff071
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21G17A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21G17A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21g17a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g17a\samd21g17a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17A.menu
new file mode 100644
index 00000000..00b1cc56
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21G17A</tag>
+  <display>Atmel ATSAMD21G17A</display>
+  <data>$CUR_DIR$\ATSAMD21G17A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17AU.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17AU.i79
new file mode 100644
index 00000000..5fd7bb40
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17AU.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21G17AU
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21G17AU.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21g17au\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g17au\samd21g17au-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17AU.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17AU.menu
new file mode 100644
index 00000000..ce64be9a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G17AU.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21G17AU</tag>
+  <display>Atmel ATSAMD21G17AU</display>
+  <data>$CUR_DIR$\ATSAMD21G17AU.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18A.i79
new file mode 100644
index 00000000..3e5a7ab4
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21G18A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21G18A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21g18a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g18a\samd21g18a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18A.menu
new file mode 100644
index 00000000..e440f9c8
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21G18A</tag>
+  <display>Atmel ATSAMD21G18A</display>
+  <data>$CUR_DIR$\ATSAMD21G18A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18AU.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18AU.i79
new file mode 100644
index 00000000..22c4e796
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18AU.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21G18AU
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21G18AU.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21g18au\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g18au\samd21g18au-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18AU.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18AU.menu
new file mode 100644
index 00000000..d3ba2352
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21G18AU.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21G18AU</tag>
+  <display>Atmel ATSAMD21G18AU</display>
+  <data>$CUR_DIR$\ATSAMD21G18AU.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J15A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J15A.i79
new file mode 100644
index 00000000..6d2f1c79
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J15A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21J15A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21J15A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21j15a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j15a\samd21j15a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J15A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J15A.menu
new file mode 100644
index 00000000..525c8aea
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J15A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21J15A</tag>
+  <display>Atmel ATSAMD21J15A</display>
+  <data>$CUR_DIR$\ATSAMD21J15A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J16A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J16A.i79
new file mode 100644
index 00000000..2862f551
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J16A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21J16A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21J16A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21j16a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j16a\samd21j16a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J16A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J16A.menu
new file mode 100644
index 00000000..b05f83ae
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J16A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21J16A</tag>
+  <display>Atmel ATSAMD21J16A</display>
+  <data>$CUR_DIR$\ATSAMD21J16A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J17A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J17A.i79
new file mode 100644
index 00000000..64552937
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J17A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21J17A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21J17A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21j17a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j17a\samd21j17a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J17A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J17A.menu
new file mode 100644
index 00000000..209d0a13
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J17A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21J17A</tag>
+  <display>Atmel ATSAMD21J17A</display>
+  <data>$CUR_DIR$\ATSAMD21J17A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J18A.i79 b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J18A.i79
new file mode 100644
index 00000000..20b82fe1
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J18A.i79
@@ -0,0 +1,41 @@
+[FILEFORMAT]
+rev=1.6
+
+[CHIP]
+// Chip name
+name=ATSAMD21J18A
+
+// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
+endiansupport=le
+
+// Does the chip support the thumb instruction set? (true(default), false)
+thumbsupport=true
+
+// Does the chip support the arm instruction set? (true(default), false)
+armsupport=false
+
+// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFP9-S, MaverickCrunch, None(default))
+fpu=None
+
+// Chip specific macros
+//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac
+
+//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
+JTAG=false
+RTCK=false
+SWD=true
+SWO_TraceD0=false
+
+[CORE]
+// Name of ARM processor core
+name=Cortex-M0+
+
+[DDF FILE]
+name=Atmel\ATSAMD21J18A.ddf
+
+[LINKER FILE]
+//Name of the linker config file
+name=$TOOLKIT_DIR$\config\linker\Atmel\samd21j18a\flash.icf
+
+[FLASH LOADER]
+little=$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j18a\samd21j18a-flash.board
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J18A.menu b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J18A.menu
new file mode 100644
index 00000000..420fdf62
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/devices/Atmel/ATSAMD21/ATSAMD21J18A.menu
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<optionMenuItem>
+  <tag>ATSAMD21J18A</tag>
+  <display>Atmel ATSAMD21J18A</display>
+  <data>$CUR_DIR$\ATSAMD21J18A.i79</data>
+</optionMenuItem>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e15a/samd21e15a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e15a/samd21e15a-flash.board
new file mode 100644
index 00000000..e9243385
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e15a/samd21e15a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e15a\samd21e15a-flash.flash</loader>
+    <range>CODE 0x00000000 0x7FFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e15a/samd21e15a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e15a/samd21e15a-flash.flash
new file mode 100644
index 00000000..06ca78ae
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e15a/samd21e15a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e15a\samd21e15a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>128 0x100</block--> <!-- 128 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x8000</block> <!-- Full erase of 32k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e15a/samd21e15a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e15a/samd21e15a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..e237c4862a95b65ea74f93ab0d9c6fd5f5fcb528
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e16a/samd21e16a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e16a/samd21e16a-flash.board
new file mode 100644
index 00000000..60f77cc0
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e16a/samd21e16a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e16a\samd21e16a-flash.flash</loader>
+    <range>CODE 0x00000000 0xFFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e16a/samd21e16a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e16a/samd21e16a-flash.flash
new file mode 100644
index 00000000..7a014333
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e16a/samd21e16a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e16a\samd21e16a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>256 0x100</block--> <!-- 256 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x10000</block> <!-- Full erase of 64k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e16a/samd21e16a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e16a/samd21e16a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..26e8d3bb6467ce59b59c6125a5d1aac6713fb735
GIT binary patch
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dbg!&q%vcDdEf632PXRl>cOtS4*~mot{{!gMwH*Ke

literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e17a/samd21e17a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e17a/samd21e17a-flash.board
new file mode 100644
index 00000000..111cf220
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e17a/samd21e17a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e17a\samd21e17a-flash.flash</loader>
+    <range>CODE 0x00000000 0x1FFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e17a/samd21e17a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e17a/samd21e17a-flash.flash
new file mode 100644
index 00000000..9561bfad
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e17a/samd21e17a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e17a\samd21e17a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>512 0x100</block--> <!-- 512 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x20000</block> <!-- Full erase of 128k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e17a/samd21e17a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e17a/samd21e17a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..f8918c4bf5796a86dcbb37edcad9db7896752564
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e18a/samd21e18a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e18a/samd21e18a-flash.board
new file mode 100644
index 00000000..30c88c68
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e18a/samd21e18a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e18a\samd21e18a-flash.flash</loader>
+    <range>CODE 0x00000000 0x3FFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e18a/samd21e18a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e18a/samd21e18a-flash.flash
new file mode 100644
index 00000000..9dc96dac
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e18a/samd21e18a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21e18a\samd21e18a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>1024 0x100</block--> <!-- 1024 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x40000</block> <!-- Full erase of 256k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e18a/samd21e18a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21e18a/samd21e18a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..d36fb2dba6ba03ed9b83f2d6da1052483201e9e2
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g15a/samd21g15a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g15a/samd21g15a-flash.board
new file mode 100644
index 00000000..803468dc
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g15a/samd21g15a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g15a\samd21g15a-flash.flash</loader>
+    <range>CODE 0x00000000 0x7FFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g15a/samd21g15a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g15a/samd21g15a-flash.flash
new file mode 100644
index 00000000..5ef43ad2
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g15a/samd21g15a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g15a\samd21g15a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>128 0x100</block--> <!-- 128 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x8000</block> <!-- Full erase of 32k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g15a/samd21g15a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g15a/samd21g15a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..e237c4862a95b65ea74f93ab0d9c6fd5f5fcb528
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g16a/samd21g16a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g16a/samd21g16a-flash.board
new file mode 100644
index 00000000..14d1438c
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g16a/samd21g16a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g16a\samd21g16a-flash.flash</loader>
+    <range>CODE 0x00000000 0xFFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g16a/samd21g16a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g16a/samd21g16a-flash.flash
new file mode 100644
index 00000000..8e9ab5b3
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g16a/samd21g16a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g16a\samd21g16a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>256 0x100</block--> <!-- 256 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x10000</block> <!-- Full erase of 64k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g16a/samd21g16a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g16a/samd21g16a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..26e8d3bb6467ce59b59c6125a5d1aac6713fb735
GIT binary patch
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dbg!&q%vcDdEf632PXRl>cOtS4*~mot{{!gMwH*Ke

literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17a/samd21g17a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17a/samd21g17a-flash.board
new file mode 100644
index 00000000..2d3c6ca3
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17a/samd21g17a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g17a\samd21g17a-flash.flash</loader>
+    <range>CODE 0x00000000 0x1FFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17a/samd21g17a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17a/samd21g17a-flash.flash
new file mode 100644
index 00000000..201ffe2b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17a/samd21g17a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g17a\samd21g17a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>512 0x100</block--> <!-- 512 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x20000</block> <!-- Full erase of 128k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17a/samd21g17a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17a/samd21g17a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..f8918c4bf5796a86dcbb37edcad9db7896752564
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17au/samd21g17au-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17au/samd21g17au-flash.board
new file mode 100644
index 00000000..e063ab72
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17au/samd21g17au-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g17au\samd21g17au-flash.flash</loader>
+    <range>CODE 0x00000000 0x1FFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17au/samd21g17au-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17au/samd21g17au-flash.flash
new file mode 100644
index 00000000..8e1b0097
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17au/samd21g17au-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g17au\samd21g17au-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>512 0x100</block--> <!-- 512 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x20000</block> <!-- Full erase of 128k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17au/samd21g17au-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g17au/samd21g17au-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..f8918c4bf5796a86dcbb37edcad9db7896752564
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18a/samd21g18a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18a/samd21g18a-flash.board
new file mode 100644
index 00000000..e743907d
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18a/samd21g18a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g18a\samd21g18a-flash.flash</loader>
+    <range>CODE 0x00000000 0x3FFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18a/samd21g18a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18a/samd21g18a-flash.flash
new file mode 100644
index 00000000..b6af5270
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18a/samd21g18a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g18a\samd21g18a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>1024 0x100</block--> <!-- 1024 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x40000</block> <!-- Full erase of 256k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18a/samd21g18a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18a/samd21g18a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..d36fb2dba6ba03ed9b83f2d6da1052483201e9e2
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18au/samd21g18au-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18au/samd21g18au-flash.board
new file mode 100644
index 00000000..8da8d0e1
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18au/samd21g18au-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g18au\samd21g18au-flash.flash</loader>
+    <range>CODE 0x00000000 0x3FFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18au/samd21g18au-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18au/samd21g18au-flash.flash
new file mode 100644
index 00000000..6fd41759
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18au/samd21g18au-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21g18au\samd21g18au-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>1024 0x100</block--> <!-- 1024 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x40000</block> <!-- Full erase of 256k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18au/samd21g18au-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21g18au/samd21g18au-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..d36fb2dba6ba03ed9b83f2d6da1052483201e9e2
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j15a/samd21j15a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j15a/samd21j15a-flash.board
new file mode 100644
index 00000000..9d9d402f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j15a/samd21j15a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j15a\samd21j15a-flash.flash</loader>
+    <range>CODE 0x00000000 0x7FFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j15a/samd21j15a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j15a/samd21j15a-flash.flash
new file mode 100644
index 00000000..efe00bfc
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j15a/samd21j15a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j15a\samd21j15a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>128 0x100</block--> <!-- 128 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x8000</block> <!-- Full erase of 32k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j15a/samd21j15a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j15a/samd21j15a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..e237c4862a95b65ea74f93ab0d9c6fd5f5fcb528
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j16a/samd21j16a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j16a/samd21j16a-flash.board
new file mode 100644
index 00000000..41ff5051
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j16a/samd21j16a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j16a\samd21j16a-flash.flash</loader>
+    <range>CODE 0x00000000 0xFFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j16a/samd21j16a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j16a/samd21j16a-flash.flash
new file mode 100644
index 00000000..138125f0
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j16a/samd21j16a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j16a\samd21j16a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>256 0x100</block--> <!-- 256 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x10000</block> <!-- Full erase of 64k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j16a/samd21j16a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j16a/samd21j16a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..26e8d3bb6467ce59b59c6125a5d1aac6713fb735
GIT binary patch
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dbg!&q%vcDdEf632PXRl>cOtS4*~mot{{!gMwH*Ke

literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j17a/samd21j17a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j17a/samd21j17a-flash.board
new file mode 100644
index 00000000..f1dc5c08
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j17a/samd21j17a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j17a\samd21j17a-flash.flash</loader>
+    <range>CODE 0x00000000 0x1FFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j17a/samd21j17a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j17a/samd21j17a-flash.flash
new file mode 100644
index 00000000..53091680
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j17a/samd21j17a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j17a\samd21j17a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>512 0x100</block--> <!-- 512 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x20000</block> <!-- Full erase of 128k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j17a/samd21j17a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j17a/samd21j17a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..f8918c4bf5796a86dcbb37edcad9db7896752564
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j18a/samd21j18a-flash.board b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j18a/samd21j18a-flash.board
new file mode 100644
index 00000000..bfcf6a5b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j18a/samd21j18a-flash.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j18a\samd21j18a-flash.flash</loader>
+    <range>CODE 0x00000000 0x3FFFF</range>
+    <rel_offset>0x0</rel_offset>
+  </pass>
+</flash_board>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j18a/samd21j18a-flash.flash b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j18a/samd21j18a-flash.flash
new file mode 100644
index 00000000..afa8d477
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j18a/samd21j18a-flash.flash
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$TOOLKIT_DIR$\config\flashloader\Atmel\samd21j18a\samd21j18a-flash.out</exe>
+  <flash_base>0x00000000</flash_base>
+  <page>64</page>
+  <!--block>1024 0x100</block--> <!-- 1024 erase rows of 256 bytes, with 4 pages per erase row -->
+  <block>1 0x40000</block> <!-- Full erase of 256k bytes -->
+  <macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAMD21.mac</macro>
+  <args>--flash</args>
+  <args_doc>--flash : mandatory param</args_doc>
+  <aggregate>1</aggregate>
+</flash_device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j18a/samd21j18a-flash.out b/uf2-samdx1/lib/samd21/samd21a/iar/config/flashloader/Atmel/samd21j18a/samd21j18a-flash.out
new file mode 100644
index 0000000000000000000000000000000000000000..d36fb2dba6ba03ed9b83f2d6da1052483201e9e2
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e15a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e15a_flash.icf
new file mode 100644
index 00000000..869af5fd
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e15a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e15a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e15a_sram.icf
new file mode 100644
index 00000000..44d12e46
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e15a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e16a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e16a_flash.icf
new file mode 100644
index 00000000..98535fbb
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e16a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e16a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e16a_sram.icf
new file mode 100644
index 00000000..4402bc7f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e16a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e17a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e17a_flash.icf
new file mode 100644
index 00000000..5986daf8
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e17a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e17a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e17a_sram.icf
new file mode 100644
index 00000000..8f0c04f3
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e17a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e18a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e18a_flash.icf
new file mode 100644
index 00000000..bd017b48
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e18a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e18a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e18a_sram.icf
new file mode 100644
index 00000000..7b079569
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21e18a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g15a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g15a_flash.icf
new file mode 100644
index 00000000..8e848340
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g15a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g15a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g15a_sram.icf
new file mode 100644
index 00000000..360f02b2
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g15a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g16a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g16a_flash.icf
new file mode 100644
index 00000000..f0e65d1c
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g16a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g16a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g16a_sram.icf
new file mode 100644
index 00000000..8c89ee7f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g16a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17a_flash.icf
new file mode 100644
index 00000000..cb329223
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17a_sram.icf
new file mode 100644
index 00000000..c23ecdbf
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17au_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17au_flash.icf
new file mode 100644
index 00000000..d3e10f64
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17au_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17AU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17au_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17au_sram.icf
new file mode 100644
index 00000000..89551bde
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g17au_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G17AU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18a_flash.icf
new file mode 100644
index 00000000..167ff69a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18a_sram.icf
new file mode 100644
index 00000000..b6414f67
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18au_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18au_flash.icf
new file mode 100644
index 00000000..550f6503
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18au_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18AU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18au_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18au_sram.icf
new file mode 100644
index 00000000..8cc8d830
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21g18au_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G18AU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j15a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j15a_flash.icf
new file mode 100644
index 00000000..ebaf7a00
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j15a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x00007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j15a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j15a_sram.icf
new file mode 100644
index 00000000..d59f5325
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j15a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20000FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x400;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j16a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j16a_flash.icf
new file mode 100644
index 00000000..62363352
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j16a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0000FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j16a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j16a_sram.icf
new file mode 100644
index 00000000..f6fdc902
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j16a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20001FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x800;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j17a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j17a_flash.icf
new file mode 100644
index 00000000..5b6f7e9a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j17a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0001FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j17a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j17a_sram.icf
new file mode 100644
index 00000000..0e65b22a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j17a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x1000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j18a_flash.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j18a_flash.icf
new file mode 100644
index 00000000..68a663b3
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j18a_flash.icf
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region    = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j18a_sram.icf b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j18a_sram.icf
new file mode 100644
index 00000000..b98f8909
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/samd21j18a_sram.icf
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__        = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/*-Sizes-*/
+if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
+  define symbol __ICFEDIT_size_cstack__    = 0x2000;
+}
+if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
+  define symbol __ICFEDIT_size_heap__      = 0x0;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region RAM_region    = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP   with alignment = 8, size = __ICFEDIT_size_heap__   { };
+
+initialize by copy with packing=none  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region                           { readonly };
+place in RAM_region                           { readwrite };
+place at end of RAM_region                    { block CSTACK, block HEAP };
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/iar/startup_samd21.c b/uf2-samdx1/lib/samd21/samd21a/iar/iar/startup_samd21.c
new file mode 100644
index 00000000..89176d4c
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/iar/startup_samd21.c
@@ -0,0 +1,231 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+typedef void (*intfunc) (void);
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+#pragma weak NMI_Handler              = Dummy_Handler
+#pragma weak HardFault_Handler        = Dummy_Handler
+#pragma weak SVC_Handler              = Dummy_Handler
+#pragma weak PendSV_Handler           = Dummy_Handler
+#pragma weak SysTick_Handler          = Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak PM_Handler               = Dummy_Handler
+#pragma weak SYSCTRL_Handler          = Dummy_Handler
+#pragma weak WDT_Handler              = Dummy_Handler
+#pragma weak RTC_Handler              = Dummy_Handler
+#pragma weak EIC_Handler              = Dummy_Handler
+#pragma weak NVMCTRL_Handler          = Dummy_Handler
+#pragma weak DMAC_Handler             = Dummy_Handler
+#ifdef       ID_USB
+#pragma weak USB_Handler              = Dummy_Handler
+#endif
+#pragma weak EVSYS_Handler            = Dummy_Handler
+#pragma weak SERCOM0_Handler          = Dummy_Handler
+#pragma weak SERCOM1_Handler          = Dummy_Handler
+#pragma weak SERCOM2_Handler          = Dummy_Handler
+#pragma weak SERCOM3_Handler          = Dummy_Handler
+#ifdef       ID_SERCOM4
+#pragma weak SERCOM4_Handler          = Dummy_Handler
+#endif
+#ifdef       ID_SERCOM5
+#pragma weak SERCOM5_Handler          = Dummy_Handler
+#endif
+#pragma weak TCC0_Handler             = Dummy_Handler
+#pragma weak TCC1_Handler             = Dummy_Handler
+#pragma weak TCC2_Handler             = Dummy_Handler
+#pragma weak TC3_Handler              = Dummy_Handler
+#pragma weak TC4_Handler              = Dummy_Handler
+#pragma weak TC5_Handler              = Dummy_Handler
+#ifdef       ID_TC6
+#pragma weak TC6_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_TC7
+#pragma weak TC7_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_ADC
+#pragma weak ADC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_AC
+#pragma weak AC_Handler               = Dummy_Handler
+#endif
+#ifdef       ID_DAC
+#pragma weak DAC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_PTC
+#pragma weak PTC_Handler              = Dummy_Handler
+#endif
+#pragma weak I2S_Handler              = Dummy_Handler
+
+/* Exception Table */
+#pragma language = extended
+#pragma segment  = "CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section  = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+        (void*) __sfe("CSTACK"),
+        (void*) Reset_Handler,
+        (void*) NMI_Handler,
+        (void*) HardFault_Handler,
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) SVC_Handler,
+        (void*) (0UL), /* Reserved */
+        (void*) (0UL), /* Reserved */
+        (void*) PendSV_Handler,
+        (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        (void*) PM_Handler,             /*  0 Power Manager */
+        (void*) SYSCTRL_Handler,        /*  1 System Control */
+        (void*) WDT_Handler,            /*  2 Watchdog Timer */
+        (void*) RTC_Handler,            /*  3 Real-Time Counter */
+        (void*) EIC_Handler,            /*  4 External Interrupt Controller */
+        (void*) NVMCTRL_Handler,        /*  5 Non-Volatile Memory Controller */
+        (void*) DMAC_Handler,           /*  6 Direct Memory Access Controller */
+#ifdef ID_USB
+        (void*) USB_Handler,            /*  7 Universal Serial Bus */
+#else
+        (void*) (0UL),                  /*  7 Reserved */
+#endif
+        (void*) EVSYS_Handler,          /*  8 Event System Interface */
+        (void*) SERCOM0_Handler,        /*  9 Serial Communication Interface 0 */
+        (void*) SERCOM1_Handler,        /* 10 Serial Communication Interface 1 */
+        (void*) SERCOM2_Handler,        /* 11 Serial Communication Interface 2 */
+        (void*) SERCOM3_Handler,        /* 12 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+        (void*) SERCOM4_Handler,        /* 13 Serial Communication Interface 4 */
+#else
+        (void*) (0UL),                  /* 13 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        (void*) SERCOM5_Handler,        /* 14 Serial Communication Interface 5 */
+#else
+        (void*) (0UL),                  /* 14 Reserved */
+#endif
+        (void*) TCC0_Handler,           /* 15 Timer Counter Control 0 */
+        (void*) TCC1_Handler,           /* 16 Timer Counter Control 1 */
+        (void*) TCC2_Handler,           /* 17 Timer Counter Control 2 */
+        (void*) TC3_Handler,            /* 18 Basic Timer Counter 0 */
+        (void*) TC4_Handler,            /* 19 Basic Timer Counter 1 */
+        (void*) TC5_Handler,            /* 20 Basic Timer Counter 2 */
+#ifdef ID_TC6
+        (void*) TC6_Handler,            /* 21 Basic Timer Counter 3 */
+#else
+        (void*) (0UL),                  /* 21 Reserved */
+#endif
+#ifdef ID_TC7
+        (void*) TC7_Handler,            /* 22 Basic Timer Counter 4 */
+#else
+        (void*) (0UL),                  /* 22 Reserved */
+#endif
+#ifdef ID_ADC
+        (void*) ADC_Handler,            /* 23 Analog Digital Converter */
+#else
+        (void*) (0UL),                  /* 23 Reserved */
+#endif
+#ifdef ID_AC
+        (void*) AC_Handler,             /* 24 Analog Comparators */
+#else
+        (void*) (0UL),                  /* 24 Reserved */
+#endif
+#ifdef ID_DAC
+        (void*) DAC_Handler,            /* 25 Digital Analog Converter */
+#else
+        (void*) (0UL),                  /* 25 Reserved */
+#endif
+#ifdef ID_PTC
+        (void*) PTC_Handler,            /* 26 Peripheral Touch Controller */
+#else
+        (void*) (0UL),                  /* 26 Reserved */
+#endif
+        (void*) I2S_Handler,            /* 27 Inter-IC Sound Interface */
+        (void*) (0UL)                   /* 28 Reserved */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+        uint32_t *pSrc = __section_begin(".intvec");
+
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+        return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+        /* Change default QOS values to have the best performance and correct USB behaviour */
+        SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+#if defined(ID_USB)
+        USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+        USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+#endif
+        DMAC->QOSCTRL.bit.DQOS = 2;
+        DMAC->QOSCTRL.bit.FQOS = 2;
+        DMAC->QOSCTRL.bit.WRBQOS = 2;
+
+        /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+        NVMCTRL->CTRLB.bit.MANW = 1;
+
+        __iar_program_start();
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/uf2-samdx1/lib/samd21/samd21a/iar/system_samd21.c b/uf2-samdx1/lib/samd21/samd21a/iar/system_samd21.c
new file mode 100644
index 00000000..e52b5691
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/iar/system_samd21.c
@@ -0,0 +1,63 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ *  the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK    (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+	// Keep the default device state after reset
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+	// Not implemented
+	SystemCoreClock = __SYSTEM_CLOCK;
+	return;
+}
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component-version.h b/uf2-samdx1/lib/samd21/samd21a/include/component-version.h
new file mode 100644
index 00000000..dcf909ba
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component-version.h
@@ -0,0 +1,65 @@
+/**
+ * \file
+ *
+ * \brief Component version header file
+ *
+ * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \license_stop
+ *
+ */
+
+#ifndef _COMPONENT_VERSION_H_INCLUDED
+#define _COMPONENT_VERSION_H_INCLUDED
+
+#define COMPONENT_VERSION_MAJOR 1
+#define COMPONENT_VERSION_MINOR 2
+
+//
+// The COMPONENT_VERSION define is composed of the major and the minor version number.
+//
+// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
+// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION
+// is at least 8 digits long.
+//
+#define COMPONENT_VERSION 00010002
+
+//
+// The build number does not refer to the component, but to the build number
+// of the device pack that provides the component.
+//
+#define BUILD_NUMBER 276
+
+//
+// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
+//
+#define COMPONENT_VERSION_STRING "1.2"
+
+//
+// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
+//
+// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
+//
+//     "%Y-%m-%d %H:%M:%S"
+//
+//
+#define COMPONENT_DATE_STRING "2017-02-07 19:08:26"
+
+#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
+
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/ac.h b/uf2-samdx1/lib/samd21/samd21a/include/component/ac.h
new file mode 100644
index 00000000..80ea1abe
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/ac.h
@@ -0,0 +1,544 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_COMPONENT_
+#define _SAMD21_AC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2205
+#define REV_AC                      0x111
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  LPMUX:1;          /*!< bit:      7  Low-Power Mux                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET             0x00         /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE         _U(0x00)     /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos          0            /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST              (_U(0x1) << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos         1            /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE             (_U(0x1) << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_RUNSTDBY_Pos       2            /**< \brief (AC_CTRLA) Run in Standby */
+#define AC_CTRLA_RUNSTDBY_Msk       (_U(0x1) << AC_CTRLA_RUNSTDBY_Pos)
+#define AC_CTRLA_RUNSTDBY(value)    (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
+#define AC_CTRLA_LPMUX_Pos          7            /**< \brief (AC_CTRLA) Low-Power Mux */
+#define AC_CTRLA_LPMUX              (_U(0x1) << AC_CTRLA_LPMUX_Pos)
+#define AC_CTRLA_MASK               _U(0x87)     /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  START0:1;         /*!< bit:      0  Comparator 0 Start Comparison      */
+    uint8_t  START1:1;         /*!< bit:      1  Comparator 1 Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  START:2;          /*!< bit:  0.. 1  Comparator x Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET             0x01         /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE         _U(0x00)     /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos         0            /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0             (1 << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos         1            /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1             (1 << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos          0            /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk          (_U(0x3) << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value)       (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
+#define AC_CTRLB_MASK               _U(0x03)     /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMPEO0:1;        /*!< bit:      0  Comparator 0 Event Output Enable   */
+    uint16_t COMPEO1:1;        /*!< bit:      1  Comparator 1 Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO0:1;         /*!< bit:      4  Window 0 Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI0:1;        /*!< bit:      8  Comparator 0 Event Input           */
+    uint16_t COMPEI1:1;        /*!< bit:      9  Comparator 1 Event Input           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t COMPEO:2;         /*!< bit:  0.. 1  Comparator x Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO:1;          /*!< bit:      4  Window x Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI:2;         /*!< bit:  8.. 9  Comparator x Event Input           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET            0x02         /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE        _U(0x0000)   /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos       0            /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0           (1 << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos       1            /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1           (1 << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos        0            /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk        (_U(0x3) << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value)     (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
+#define AC_EVCTRL_WINEO0_Pos        4            /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0            (1 << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos         4            /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk         (_U(0x1) << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value)      (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
+#define AC_EVCTRL_COMPEI0_Pos       8            /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
+#define AC_EVCTRL_COMPEI0           (1 << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos       9            /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
+#define AC_EVCTRL_COMPEI1           (1 << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos        8            /**< \brief (AC_EVCTRL) Comparator x Event Input */
+#define AC_EVCTRL_COMPEI_Msk        (_U(0x3) << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value)     (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
+#define AC_EVCTRL_MASK              _U(0x0313)   /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET          0x04         /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE      _U(0x00)     /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos       0            /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0           (1 << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos       1            /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1           (1 << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos        0            /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk        (_U(0x3) << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value)     (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
+#define AC_INTENCLR_WIN0_Pos        4            /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0            (1 << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos         4            /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk         (_U(0x1) << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value)      (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
+#define AC_INTENCLR_MASK            _U(0x13)     /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET          0x05         /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE      _U(0x00)     /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos       0            /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0           (1 << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos       1            /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1           (1 << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos        0            /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk        (_U(0x3) << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value)     (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
+#define AC_INTENSET_WIN0_Pos        4            /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0            (1 << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos         4            /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk         (_U(0x1) << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value)      (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
+#define AC_INTENSET_MASK            _U(0x13)     /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0                       */
+    __I uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN0:1;           /*!< bit:      4  Window 0                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN:1;            /*!< bit:      4  Window x                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET           0x06         /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE       _U(0x00)     /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos        0            /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0            (1 << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos        1            /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1            (1 << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos         0            /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk         (_U(0x3) << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value)      (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
+#define AC_INTFLAG_WIN0_Pos         4            /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0             (1 << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos          4            /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk          (_U(0x1) << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value)       (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
+#define AC_INTFLAG_MASK             _U(0x13)     /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x08) (R/   8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET           0x08         /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE       _U(0x00)     /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos       0            /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0           (1 << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos       1            /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1           (1 << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos        0            /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk        (_U(0x3) << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value)     (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
+#define AC_STATUSA_WSTATE0_Pos      4            /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk      (_U(0x3) << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value)   (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
+#define   AC_STATUSA_WSTATE0_ABOVE_Val    _U(0x0)   /**< \brief (AC_STATUSA) Signal is above window */
+#define   AC_STATUSA_WSTATE0_INSIDE_Val   _U(0x1)   /**< \brief (AC_STATUSA) Signal is inside window */
+#define   AC_STATUSA_WSTATE0_BELOW_Val    _U(0x2)   /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE    (AC_STATUSA_WSTATE0_ABOVE_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE   (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW    (AC_STATUSA_WSTATE0_BELOW_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK             _U(0x33)     /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x09) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY0:1;         /*!< bit:      0  Comparator 0 Ready                 */
+    uint8_t  READY1:1;         /*!< bit:      1  Comparator 1 Ready                 */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  READY:2;          /*!< bit:  0.. 1  Comparator x Ready                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET           0x09         /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE       _U(0x00)     /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos       0            /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0           (1 << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos       1            /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1           (1 << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos        0            /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk        (_U(0x3) << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value)     (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
+#define AC_STATUSB_SYNCBUSY_Pos     7            /**< \brief (AC_STATUSB) Synchronization Busy */
+#define AC_STATUSB_SYNCBUSY         (_U(0x1) << AC_STATUSB_SYNCBUSY_Pos)
+#define AC_STATUSB_MASK             _U(0x83)     /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/   8) Status C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSC_OFFSET           0x0A         /**< \brief (AC_STATUSC offset) Status C */
+#define AC_STATUSC_RESETVALUE       _U(0x00)     /**< \brief (AC_STATUSC reset_value) Status C */
+
+#define AC_STATUSC_STATE0_Pos       0            /**< \brief (AC_STATUSC) Comparator 0 Current State */
+#define AC_STATUSC_STATE0           (1 << AC_STATUSC_STATE0_Pos)
+#define AC_STATUSC_STATE1_Pos       1            /**< \brief (AC_STATUSC) Comparator 1 Current State */
+#define AC_STATUSC_STATE1           (1 << AC_STATUSC_STATE1_Pos)
+#define AC_STATUSC_STATE_Pos        0            /**< \brief (AC_STATUSC) Comparator x Current State */
+#define AC_STATUSC_STATE_Msk        (_U(0x3) << AC_STATUSC_STATE_Pos)
+#define AC_STATUSC_STATE(value)     (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
+#define AC_STATUSC_WSTATE0_Pos      4            /**< \brief (AC_STATUSC) Window 0 Current State */
+#define AC_STATUSC_WSTATE0_Msk      (_U(0x3) << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0(value)   (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
+#define   AC_STATUSC_WSTATE0_ABOVE_Val    _U(0x0)   /**< \brief (AC_STATUSC) Signal is above window */
+#define   AC_STATUSC_WSTATE0_INSIDE_Val   _U(0x1)   /**< \brief (AC_STATUSC) Signal is inside window */
+#define   AC_STATUSC_WSTATE0_BELOW_Val    _U(0x2)   /**< \brief (AC_STATUSC) Signal is below window */
+#define AC_STATUSC_WSTATE0_ABOVE    (AC_STATUSC_WSTATE0_ABOVE_Val  << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_INSIDE   (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_BELOW    (AC_STATUSC_WSTATE0_BELOW_Val  << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_MASK             _U(0x33)     /**< \brief (AC_STATUSC) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W  8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WEN0:1;           /*!< bit:      0  Window 0 Mode Enable               */
+    uint8_t  WINTSEL0:2;       /*!< bit:  1.. 2  Window 0 Interrupt Selection       */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET           0x0C         /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE       _U(0x00)     /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos         0            /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0             (_U(0x1) << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos     1            /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk     (_U(0x3) << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value)  (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
+#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   _U(0x0)   /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  _U(0x1)   /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define   AC_WINCTRL_WINTSEL0_BELOW_Val   _U(0x2)   /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U(0x3)   /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE   (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE  (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW   (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK             _U(0x07)     /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ENABLE:1;         /*!< bit:      0  Enable                             */
+    uint32_t SINGLE:1;         /*!< bit:      1  Single-Shot Mode                   */
+    uint32_t SPEED:2;          /*!< bit:  2.. 3  Speed Selection                    */
+    uint32_t :1;               /*!< bit:      4  Reserved                           */
+    uint32_t INTSEL:2;         /*!< bit:  5.. 6  Interrupt Selection                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MUXNEG:3;         /*!< bit:  8..10  Negative Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t MUXPOS:2;         /*!< bit: 12..13  Positive Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     14  Reserved                           */
+    uint32_t SWAP:1;           /*!< bit:     15  Swap Inputs and Invert             */
+    uint32_t OUT:2;            /*!< bit: 16..17  Output                             */
+    uint32_t :1;               /*!< bit:     18  Reserved                           */
+    uint32_t HYST:1;           /*!< bit:     19  Hysteresis Enable                  */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t FLEN:3;           /*!< bit: 24..26  Filter Length                      */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET          0x10         /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE      _U(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos      0            /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE          (_U(0x1) << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos      1            /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE          (_U(0x1) << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_SPEED_Pos       2            /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk       (_U(0x3) << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value)    (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
+#define   AC_COMPCTRL_SPEED_LOW_Val       _U(0x0)   /**< \brief (AC_COMPCTRL) Low speed */
+#define   AC_COMPCTRL_SPEED_HIGH_Val      _U(0x1)   /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_LOW       (AC_COMPCTRL_SPEED_LOW_Val     << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_HIGH      (AC_COMPCTRL_SPEED_HIGH_Val    << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_INTSEL_Pos      5            /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk      (_U(0x3) << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value)   (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
+#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   _U(0x0)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define   AC_COMPCTRL_INTSEL_RISING_Val   _U(0x1)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define   AC_COMPCTRL_INTSEL_FALLING_Val  _U(0x2)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define   AC_COMPCTRL_INTSEL_EOC_Val      _U(0x3)   /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE   (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING   (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING  (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC      (AC_COMPCTRL_INTSEL_EOC_Val    << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos      8            /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk      (_U(0x7) << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value)   (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
+#define   AC_COMPCTRL_MUXNEG_PIN0_Val     _U(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXNEG_PIN1_Val     _U(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXNEG_PIN2_Val     _U(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXNEG_PIN3_Val     _U(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXNEG_GND_Val      _U(0x4)   /**< \brief (AC_COMPCTRL) Ground */
+#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   _U(0x5)   /**< \brief (AC_COMPCTRL) VDD scaler */
+#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  _U(0x6)   /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define   AC_COMPCTRL_MUXNEG_DAC_Val      _U(0x7)   /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0     (AC_COMPCTRL_MUXNEG_PIN0_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1     (AC_COMPCTRL_MUXNEG_PIN1_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2     (AC_COMPCTRL_MUXNEG_PIN2_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3     (AC_COMPCTRL_MUXNEG_PIN3_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND      (AC_COMPCTRL_MUXNEG_GND_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE   (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP  (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC      (AC_COMPCTRL_MUXNEG_DAC_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos      12           /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk      (_U(0x3) << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value)   (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
+#define   AC_COMPCTRL_MUXPOS_PIN0_Val     _U(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXPOS_PIN1_Val     _U(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXPOS_PIN2_Val     _U(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXPOS_PIN3_Val     _U(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_PIN0     (AC_COMPCTRL_MUXPOS_PIN0_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1     (AC_COMPCTRL_MUXPOS_PIN1_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2     (AC_COMPCTRL_MUXPOS_PIN2_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3     (AC_COMPCTRL_MUXPOS_PIN3_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos        15           /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP            (_U(0x1) << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_OUT_Pos         16           /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk         (_U(0x3) << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value)      (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
+#define   AC_COMPCTRL_OUT_OFF_Val         _U(0x0)   /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_ASYNC_Val       _U(0x1)   /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_SYNC_Val        _U(0x2)   /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF         (AC_COMPCTRL_OUT_OFF_Val       << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC       (AC_COMPCTRL_OUT_ASYNC_Val     << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC        (AC_COMPCTRL_OUT_SYNC_Val      << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_HYST_Pos        19           /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYST            (_U(0x1) << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos        24           /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk        (_U(0x7) << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value)     (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
+#define   AC_COMPCTRL_FLEN_OFF_Val        _U(0x0)   /**< \brief (AC_COMPCTRL) No filtering */
+#define   AC_COMPCTRL_FLEN_MAJ3_Val       _U(0x1)   /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define   AC_COMPCTRL_FLEN_MAJ5_Val       _U(0x2)   /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF        (AC_COMPCTRL_FLEN_OFF_Val      << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3       (AC_COMPCTRL_FLEN_MAJ3_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5       (AC_COMPCTRL_FLEN_MAJ5_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_MASK            _U(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x20) (R/W  8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:6;          /*!< bit:  0.. 5  Scaler Value                       */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET            0x20         /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE        _U(0x00)     /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos         0            /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk         (_U(0x3F) << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value)      (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
+#define AC_SCALER_MASK              _U(0x3F)     /**< \brief (AC_SCALER) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO AC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __O  AC_CTRLB_Type             CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B */
+  __IO AC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x02 (R/W 16) Event Control */
+  __IO AC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO AC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO AC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __I  AC_STATUSA_Type           STATUSA;     /**< \brief Offset: 0x08 (R/   8) Status A */
+  __I  AC_STATUSB_Type           STATUSB;     /**< \brief Offset: 0x09 (R/   8) Status B */
+  __I  AC_STATUSC_Type           STATUSC;     /**< \brief Offset: 0x0A (R/   8) Status C */
+       RoReg8                    Reserved2[0x1];
+  __IO AC_WINCTRL_Type           WINCTRL;     /**< \brief Offset: 0x0C (R/W  8) Window Control */
+       RoReg8                    Reserved3[0x3];
+  __IO AC_COMPCTRL_Type          COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+       RoReg8                    Reserved4[0x8];
+  __IO AC_SCALER_Type            SCALER[2];   /**< \brief Offset: 0x20 (R/W  8) Scaler n */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_AC_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/adc.h b/uf2-samdx1/lib/samd21/samd21a/include/component/adc.h
new file mode 100644
index 00000000..fe415212
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/adc.h
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_COMPONENT_
+#define _SAMD21_ADC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2204
+#define REV_ADC                     0x120
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET            0x00         /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE        _U(0x00)     /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos         0            /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST             (_U(0x1) << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos        1            /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE            (_U(0x1) << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY          (_U(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_MASK              _U(0x07)     /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W  8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  REFSEL:4;         /*!< bit:  0.. 3  Reference Selection                */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  REFCOMP:1;        /*!< bit:      7  Reference Buffer Offset Compensation Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET          0x01         /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE      _U(0x00)     /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos      0            /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk      (_U(0xF) << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value)   (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
+#define   ADC_REFCTRL_REFSEL_INT1V_Val    _U(0x0)   /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
+#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  _U(0x1)   /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
+#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  _U(0x2)   /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
+#define   ADC_REFCTRL_REFSEL_AREFA_Val    _U(0x3)   /**< \brief (ADC_REFCTRL) External reference */
+#define   ADC_REFCTRL_REFSEL_AREFB_Val    _U(0x4)   /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_INT1V    (ADC_REFCTRL_REFSEL_INT1V_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos     7            /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP         (_U(0x1) << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK            _U(0x8F)     /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W  8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLENUM:4;      /*!< bit:  0.. 3  Number of Samples to be Collected  */
+    uint8_t  ADJRES:3;         /*!< bit:  4.. 6  Adjusting Result / Division Coefficient */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET          0x02         /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE      _U(0x00)     /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos   0            /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk   (_U(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
+#define   ADC_AVGCTRL_SAMPLENUM_1_Val     _U(0x0)   /**< \brief (ADC_AVGCTRL) 1 sample */
+#define   ADC_AVGCTRL_SAMPLENUM_2_Val     _U(0x1)   /**< \brief (ADC_AVGCTRL) 2 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_4_Val     _U(0x2)   /**< \brief (ADC_AVGCTRL) 4 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_8_Val     _U(0x3)   /**< \brief (ADC_AVGCTRL) 8 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_16_Val    _U(0x4)   /**< \brief (ADC_AVGCTRL) 16 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_32_Val    _U(0x5)   /**< \brief (ADC_AVGCTRL) 32 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_64_Val    _U(0x6)   /**< \brief (ADC_AVGCTRL) 64 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_128_Val   _U(0x7)   /**< \brief (ADC_AVGCTRL) 128 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_256_Val   _U(0x8)   /**< \brief (ADC_AVGCTRL) 256 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_512_Val   _U(0x9)   /**< \brief (ADC_AVGCTRL) 512 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  _U(0xA)   /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8     (ADC_AVGCTRL_SAMPLENUM_8_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16    (ADC_AVGCTRL_SAMPLENUM_16_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32    (ADC_AVGCTRL_SAMPLENUM_32_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64    (ADC_AVGCTRL_SAMPLENUM_64_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128   (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256   (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos      4            /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk      (_U(0x7) << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value)   (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
+#define ADC_AVGCTRL_MASK            _U(0x7F)     /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W  8) Sampling Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLEN:6;        /*!< bit:  0.. 5  Sampling Time Length               */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET         0x03         /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
+#define ADC_SAMPCTRL_RESETVALUE     _U(0x00)     /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos    0            /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk    (_U(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
+#define ADC_SAMPCTRL_MASK           _U(0x3F)     /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DIFFMODE:1;       /*!< bit:      0  Differential Mode                  */
+    uint16_t LEFTADJ:1;        /*!< bit:      1  Left-Adjusted Result               */
+    uint16_t FREERUN:1;        /*!< bit:      2  Free Running Mode                  */
+    uint16_t CORREN:1;         /*!< bit:      3  Digital Correction Logic Enabled   */
+    uint16_t RESSEL:2;         /*!< bit:  4.. 5  Conversion Result Resolution       */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler Configuration            */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET            0x04         /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE        _U(0x0000)   /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_DIFFMODE_Pos      0            /**< \brief (ADC_CTRLB) Differential Mode */
+#define ADC_CTRLB_DIFFMODE          (_U(0x1) << ADC_CTRLB_DIFFMODE_Pos)
+#define ADC_CTRLB_LEFTADJ_Pos       1            /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ           (_U(0x1) << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos       2            /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN           (_U(0x1) << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos        3            /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
+#define ADC_CTRLB_CORREN            (_U(0x1) << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos        4            /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk        (_U(0x3) << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value)     (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
+#define   ADC_CTRLB_RESSEL_12BIT_Val      _U(0x0)   /**< \brief (ADC_CTRLB) 12-bit result */
+#define   ADC_CTRLB_RESSEL_16BIT_Val      _U(0x1)   /**< \brief (ADC_CTRLB) For averaging mode output */
+#define   ADC_CTRLB_RESSEL_10BIT_Val      _U(0x2)   /**< \brief (ADC_CTRLB) 10-bit result */
+#define   ADC_CTRLB_RESSEL_8BIT_Val       _U(0x3)   /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT      (ADC_CTRLB_RESSEL_12BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT      (ADC_CTRLB_RESSEL_16BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT      (ADC_CTRLB_RESSEL_10BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT       (ADC_CTRLB_RESSEL_8BIT_Val     << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_PRESCALER_Pos     8            /**< \brief (ADC_CTRLB) Prescaler Configuration */
+#define ADC_CTRLB_PRESCALER_Msk     (_U(0x7) << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER(value)  (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
+#define   ADC_CTRLB_PRESCALER_DIV4_Val    _U(0x0)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define   ADC_CTRLB_PRESCALER_DIV8_Val    _U(0x1)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define   ADC_CTRLB_PRESCALER_DIV16_Val   _U(0x2)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define   ADC_CTRLB_PRESCALER_DIV32_Val   _U(0x3)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define   ADC_CTRLB_PRESCALER_DIV64_Val   _U(0x4)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define   ADC_CTRLB_PRESCALER_DIV128_Val  _U(0x5)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define   ADC_CTRLB_PRESCALER_DIV256_Val  _U(0x6)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define   ADC_CTRLB_PRESCALER_DIV512_Val  _U(0x7)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
+#define ADC_CTRLB_PRESCALER_DIV4    (ADC_CTRLB_PRESCALER_DIV4_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV8    (ADC_CTRLB_PRESCALER_DIV8_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV16   (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV32   (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV64   (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV128  (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV256  (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV512  (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_MASK              _U(0x073F)   /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W  8) Window Monitor Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WINMODE:3;        /*!< bit:  0.. 2  Window Monitor Mode                */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINCTRL_OFFSET          0x08         /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
+#define ADC_WINCTRL_RESETVALUE      _U(0x00)     /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
+
+#define ADC_WINCTRL_WINMODE_Pos     0            /**< \brief (ADC_WINCTRL) Window Monitor Mode */
+#define ADC_WINCTRL_WINMODE_Msk     (_U(0x7) << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE(value)  (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
+#define   ADC_WINCTRL_WINMODE_DISABLE_Val _U(0x0)   /**< \brief (ADC_WINCTRL) No window mode (default) */
+#define   ADC_WINCTRL_WINMODE_MODE1_Val   _U(0x1)   /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
+#define   ADC_WINCTRL_WINMODE_MODE2_Val   _U(0x2)   /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE3_Val   _U(0x3)   /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE4_Val   _U(0x4)   /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
+#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE1   (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE2   (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE3   (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE4   (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_MASK            _U(0x07)     /**< \brief (ADC_WINCTRL) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W  8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLUSH:1;          /*!< bit:      0  ADC Conversion Flush               */
+    uint8_t  START:1;          /*!< bit:      1  ADC Start Conversion               */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET           0x0C         /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE       _U(0x00)     /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH            (_U(0x1) << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) ADC Start Conversion */
+#define ADC_SWTRIG_START            (_U(0x1) << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK             _U(0x03)     /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUXPOS:5;         /*!< bit:  0.. 4  Positive Mux Input Selection       */
+    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint32_t MUXNEG:5;         /*!< bit:  8..12  Negative Mux Input Selection       */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t INPUTSCAN:4;      /*!< bit: 16..19  Number of Input Channels Included in Scan */
+    uint32_t INPUTOFFSET:4;    /*!< bit: 20..23  Positive Mux Setting Offset        */
+    uint32_t GAIN:4;           /*!< bit: 24..27  Gain Factor Selection              */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET        0x10         /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE    _U(0x00000000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos    0            /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk    (_U(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
+#define   ADC_INPUTCTRL_MUXPOS_PIN0_Val   _U(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN1_Val   _U(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN2_Val   _U(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN3_Val   _U(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN4_Val   _U(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN5_Val   _U(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN6_Val   _U(0x6)   /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN7_Val   _U(0x7)   /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN8_Val   _U(0x8)   /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN9_Val   _U(0x9)   /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN10_Val  _U(0xA)   /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN11_Val  _U(0xB)   /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN12_Val  _U(0xC)   /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN13_Val  _U(0xD)   /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN14_Val  _U(0xE)   /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN15_Val  _U(0xF)   /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN16_Val  _U(0x10)   /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN17_Val  _U(0x11)   /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN18_Val  _U(0x12)   /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN19_Val  _U(0x13)   /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_TEMP_Val   _U(0x18)   /**< \brief (ADC_INPUTCTRL) Temperature Reference */
+#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U(0x19)   /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U(0x1A)   /**< \brief (ADC_INPUTCTRL) 1/4  Scaled Core Supply */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U(0x1B)   /**< \brief (ADC_INPUTCTRL) 1/4  Scaled I/O Supply */
+#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    _U(0x1C)   /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PIN0   (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN1   (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN2   (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN3   (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN4   (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN5   (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN6   (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN7   (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN8   (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN9   (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN10  (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN11  (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN12  (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN13  (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN14  (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN15  (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN16  (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN17  (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN18  (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN19  (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_TEMP   (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC    (ADC_INPUTCTRL_MUXPOS_DAC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos    8            /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk    (_U(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
+#define   ADC_INPUTCTRL_MUXNEG_PIN0_Val   _U(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN1_Val   _U(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN2_Val   _U(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN3_Val   _U(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN4_Val   _U(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN5_Val   _U(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN6_Val   _U(0x6)   /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN7_Val   _U(0x7)   /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_GND_Val    _U(0x18)   /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define   ADC_INPUTCTRL_MUXNEG_IOGND_Val  _U(0x19)   /**< \brief (ADC_INPUTCTRL) I/O Ground */
+#define ADC_INPUTCTRL_MUXNEG_PIN0   (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN1   (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN2   (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN3   (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN4   (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN5   (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN6   (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN7   (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_IOGND  (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN_Pos 16           /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
+#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20           /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos)
+#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
+#define ADC_INPUTCTRL_GAIN_Pos      24           /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
+#define ADC_INPUTCTRL_GAIN_Msk      (_U(0xF) << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN(value)   (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
+#define   ADC_INPUTCTRL_GAIN_1X_Val       _U(0x0)   /**< \brief (ADC_INPUTCTRL) 1x */
+#define   ADC_INPUTCTRL_GAIN_2X_Val       _U(0x1)   /**< \brief (ADC_INPUTCTRL) 2x */
+#define   ADC_INPUTCTRL_GAIN_4X_Val       _U(0x2)   /**< \brief (ADC_INPUTCTRL) 4x */
+#define   ADC_INPUTCTRL_GAIN_8X_Val       _U(0x3)   /**< \brief (ADC_INPUTCTRL) 8x */
+#define   ADC_INPUTCTRL_GAIN_16X_Val      _U(0x4)   /**< \brief (ADC_INPUTCTRL) 16x */
+#define   ADC_INPUTCTRL_GAIN_DIV2_Val     _U(0xF)   /**< \brief (ADC_INPUTCTRL) 1/2x */
+#define ADC_INPUTCTRL_GAIN_1X       (ADC_INPUTCTRL_GAIN_1X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_2X       (ADC_INPUTCTRL_GAIN_2X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_4X       (ADC_INPUTCTRL_GAIN_4X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_8X       (ADC_INPUTCTRL_GAIN_8X_Val     << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_16X      (ADC_INPUTCTRL_GAIN_16X_Val    << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_DIV2     (ADC_INPUTCTRL_GAIN_DIV2_Val   << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_MASK          _U(0x0FFF1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event In          */
+    uint8_t  SYNCEI:1;         /*!< bit:      1  Synchronization Event In           */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  RESRDYEO:1;       /*!< bit:      4  Result Ready Event Out             */
+    uint8_t  WINMONEO:1;       /*!< bit:      5  Window Monitor Event Out           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET           0x14         /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE       _U(0x00)     /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_STARTEI_Pos      0            /**< \brief (ADC_EVCTRL) Start Conversion Event In */
+#define ADC_EVCTRL_STARTEI          (_U(0x1) << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_SYNCEI_Pos       1            /**< \brief (ADC_EVCTRL) Synchronization Event In */
+#define ADC_EVCTRL_SYNCEI           (_U(0x1) << ADC_EVCTRL_SYNCEI_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos     4            /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO         (_U(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos     5            /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO         (_U(0x1) << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK             _U(0x33)     /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET         0x16         /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE     _U(0x00)     /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos     0            /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
+#define ADC_INTENCLR_RESRDY         (_U(0x1) << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos    1            /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
+#define ADC_INTENCLR_OVERRUN        (_U(0x1) << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos     2            /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
+#define ADC_INTENCLR_WINMON         (_U(0x1) << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_SYNCRDY_Pos    3            /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define ADC_INTENCLR_SYNCRDY        (_U(0x1) << ADC_INTENCLR_SYNCRDY_Pos)
+#define ADC_INTENCLR_MASK           _U(0x0F)     /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET         0x17         /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE     _U(0x00)     /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos     0            /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY         (_U(0x1) << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos    1            /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN        (_U(0x1) << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos     2            /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON         (_U(0x1) << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_SYNCRDY_Pos    3            /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
+#define ADC_INTENSET_SYNCRDY        (_U(0x1) << ADC_INTENSET_SYNCRDY_Pos)
+#define ADC_INTENSET_MASK           _U(0x0F)     /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready                       */
+    __I uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun                            */
+    __I uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor                     */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
+    __I uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET          0x18         /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE      _U(0x00)     /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos      0            /**< \brief (ADC_INTFLAG) Result Ready */
+#define ADC_INTFLAG_RESRDY          (_U(0x1) << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos     1            /**< \brief (ADC_INTFLAG) Overrun */
+#define ADC_INTFLAG_OVERRUN         (_U(0x1) << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos      2            /**< \brief (ADC_INTFLAG) Window Monitor */
+#define ADC_INTFLAG_WINMON          (_U(0x1) << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_SYNCRDY_Pos     3            /**< \brief (ADC_INTFLAG) Synchronization Ready */
+#define ADC_INTFLAG_SYNCRDY         (_U(0x1) << ADC_INTFLAG_SYNCRDY_Pos)
+#define ADC_INTFLAG_MASK            _U(0x0F)     /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET           0x19         /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE       _U(0x00)     /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_SYNCBUSY_Pos     7            /**< \brief (ADC_STATUS) Synchronization Busy */
+#define ADC_STATUS_SYNCBUSY         (_U(0x1) << ADC_STATUS_SYNCBUSY_Pos)
+#define ADC_STATUS_MASK             _U(0x80)     /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/  16) Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RESULT:16;        /*!< bit:  0..15  Result Conversion Value            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET           0x1A         /**< \brief (ADC_RESULT offset) Result */
+#define ADC_RESULT_RESETVALUE       _U(0x0000)   /**< \brief (ADC_RESULT reset_value) Result */
+
+#define ADC_RESULT_RESULT_Pos       0            /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk       (_U(0xFFFF) << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value)    (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
+#define ADC_RESULT_MASK             _U(0xFFFF)   /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINLT:16;         /*!< bit:  0..15  Window Lower Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET            0x1C         /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE        _U(0x0000)   /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos         0            /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk         (_U(0xFFFF) << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value)      (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
+#define ADC_WINLT_MASK              _U(0xFFFF)   /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINUT:16;         /*!< bit:  0..15  Window Upper Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET            0x20         /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE        _U(0x0000)   /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos         0            /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk         (_U(0xFFFF) << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value)      (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
+#define ADC_WINUT_MASK              _U(0xFFFF)   /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t GAINCORR:12;      /*!< bit:  0..11  Gain Correction Value              */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET         0x24         /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE     _U(0x0000)   /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos   0            /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk   (_U(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
+#define ADC_GAINCORR_MASK           _U(0x0FFF)   /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t OFFSETCORR:12;    /*!< bit:  0..11  Offset Correction Value            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET       0x26         /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE   _U(0x0000)   /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0            /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
+#define ADC_OFFSETCORR_MASK         _U(0x0FFF)   /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LINEARITY_CAL:8;  /*!< bit:  0.. 7  Linearity Calibration Value        */
+    uint16_t BIAS_CAL:3;       /*!< bit:  8..10  Bias Calibration Value             */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET            0x28         /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE        _U(0x0000)   /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_LINEARITY_CAL_Pos 0            /**< \brief (ADC_CALIB) Linearity Calibration Value */
+#define ADC_CALIB_LINEARITY_CAL_Msk (_U(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos)
+#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
+#define ADC_CALIB_BIAS_CAL_Pos      8            /**< \brief (ADC_CALIB) Bias Calibration Value */
+#define ADC_CALIB_BIAS_CAL_Msk      (_U(0x7) << ADC_CALIB_BIAS_CAL_Pos)
+#define ADC_CALIB_BIAS_CAL(value)   (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
+#define ADC_CALIB_MASK              _U(0x07FF)   /**< \brief (ADC_CALIB) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET          0x2A         /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE      _U(0x00)     /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN          (_U(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK            _U(0x01)     /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO ADC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO ADC_REFCTRL_Type          REFCTRL;     /**< \brief Offset: 0x01 (R/W  8) Reference Control */
+  __IO ADC_AVGCTRL_Type          AVGCTRL;     /**< \brief Offset: 0x02 (R/W  8) Average Control */
+  __IO ADC_SAMPCTRL_Type         SAMPCTRL;    /**< \brief Offset: 0x03 (R/W  8) Sampling Time Control */
+  __IO ADC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x04 (R/W 16) Control B */
+       RoReg8                    Reserved1[0x2];
+  __IO ADC_WINCTRL_Type          WINCTRL;     /**< \brief Offset: 0x08 (R/W  8) Window Monitor Control */
+       RoReg8                    Reserved2[0x3];
+  __IO ADC_SWTRIG_Type           SWTRIG;      /**< \brief Offset: 0x0C (R/W  8) Software Trigger */
+       RoReg8                    Reserved3[0x3];
+  __IO ADC_INPUTCTRL_Type        INPUTCTRL;   /**< \brief Offset: 0x10 (R/W 32) Input Control */
+  __IO ADC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x14 (R/W  8) Event Control */
+       RoReg8                    Reserved4[0x1];
+  __IO ADC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x16 (R/W  8) Interrupt Enable Clear */
+  __IO ADC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x17 (R/W  8) Interrupt Enable Set */
+  __IO ADC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) Interrupt Flag Status and Clear */
+  __I  ADC_STATUS_Type           STATUS;      /**< \brief Offset: 0x19 (R/   8) Status */
+  __I  ADC_RESULT_Type           RESULT;      /**< \brief Offset: 0x1A (R/  16) Result */
+  __IO ADC_WINLT_Type            WINLT;       /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+       RoReg8                    Reserved5[0x2];
+  __IO ADC_WINUT_Type            WINUT;       /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+       RoReg8                    Reserved6[0x2];
+  __IO ADC_GAINCORR_Type         GAINCORR;    /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+  __IO ADC_OFFSETCORR_Type       OFFSETCORR;  /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+  __IO ADC_CALIB_Type            CALIB;       /**< \brief Offset: 0x28 (R/W 16) Calibration */
+  __IO ADC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x2A (R/W  8) Debug Control */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_ADC_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/dac.h b/uf2-samdx1/lib/samd21/samd21a/include/component/dac.h
new file mode 100644
index 00000000..ba84975e
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/dac.h
@@ -0,0 +1,271 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_COMPONENT_
+#define _SAMD21_DAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DAC Digital Analog Converter */
+/*@{*/
+
+#define DAC_U2214
+#define REV_DAC                     0x110
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby                     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET            0x0          /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE        _U(0x00)     /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos         0            /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST             (_U(0x1) << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos        1            /**< \brief (DAC_CTRLA) Enable */
+#define DAC_CTRLA_ENABLE            (_U(0x1) << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (DAC_CTRLA) Run in Standby */
+#define DAC_CTRLA_RUNSTDBY          (_U(0x1) << DAC_CTRLA_RUNSTDBY_Pos)
+#define DAC_CTRLA_MASK              _U(0x07)     /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EOEN:1;           /*!< bit:      0  External Output Enable             */
+    uint8_t  IOEN:1;           /*!< bit:      1  Internal Output Enable             */
+    uint8_t  LEFTADJ:1;        /*!< bit:      2  Left Adjusted Data                 */
+    uint8_t  VPD:1;            /*!< bit:      3  Voltage Pump Disable               */
+    uint8_t  BDWP:1;           /*!< bit:      4  Bypass DATABUF Write Protection    */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  REFSEL:2;         /*!< bit:  6.. 7  Reference Selection                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET            0x1          /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE        _U(0x00)     /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_EOEN_Pos          0            /**< \brief (DAC_CTRLB) External Output Enable */
+#define DAC_CTRLB_EOEN              (_U(0x1) << DAC_CTRLB_EOEN_Pos)
+#define DAC_CTRLB_IOEN_Pos          1            /**< \brief (DAC_CTRLB) Internal Output Enable */
+#define DAC_CTRLB_IOEN              (_U(0x1) << DAC_CTRLB_IOEN_Pos)
+#define DAC_CTRLB_LEFTADJ_Pos       2            /**< \brief (DAC_CTRLB) Left Adjusted Data */
+#define DAC_CTRLB_LEFTADJ           (_U(0x1) << DAC_CTRLB_LEFTADJ_Pos)
+#define DAC_CTRLB_VPD_Pos           3            /**< \brief (DAC_CTRLB) Voltage Pump Disable */
+#define DAC_CTRLB_VPD               (_U(0x1) << DAC_CTRLB_VPD_Pos)
+#define DAC_CTRLB_BDWP_Pos          4            /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
+#define DAC_CTRLB_BDWP              (_U(0x1) << DAC_CTRLB_BDWP_Pos)
+#define DAC_CTRLB_REFSEL_Pos        6            /**< \brief (DAC_CTRLB) Reference Selection */
+#define DAC_CTRLB_REFSEL_Msk        (_U(0x3) << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value)     (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
+#define   DAC_CTRLB_REFSEL_INT1V_Val      _U(0x0)   /**< \brief (DAC_CTRLB) Internal 1.0V reference */
+#define   DAC_CTRLB_REFSEL_AVCC_Val       _U(0x1)   /**< \brief (DAC_CTRLB) AVCC */
+#define   DAC_CTRLB_REFSEL_VREFP_Val      _U(0x2)   /**< \brief (DAC_CTRLB) External reference */
+#define DAC_CTRLB_REFSEL_INT1V      (DAC_CTRLB_REFSEL_INT1V_Val    << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_AVCC       (DAC_CTRLB_REFSEL_AVCC_Val     << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFP      (DAC_CTRLB_REFSEL_VREFP_Val    << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK              _U(0xDF)     /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI:1;        /*!< bit:      0  Start Conversion Event Input       */
+    uint8_t  EMPTYEO:1;        /*!< bit:      1  Data Buffer Empty Event Output     */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET           0x2          /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE       _U(0x00)     /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI_Pos      0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
+#define DAC_EVCTRL_STARTEI          (_U(0x1) << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos      1            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
+#define DAC_EVCTRL_EMPTYEO          (_U(0x1) << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_MASK             _U(0x03)     /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
+    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
+    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET         0x4          /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE     _U(0x00)     /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN_Pos   0            /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN       (_U(0x1) << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_EMPTY_Pos      1            /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY          (_U(0x1) << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_SYNCRDY_Pos    2            /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define DAC_INTENCLR_SYNCRDY        (_U(0x1) << DAC_INTENCLR_SYNCRDY_Pos)
+#define DAC_INTENCLR_MASK           _U(0x07)     /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun Interrupt Enable          */
+    uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty Interrupt Enable */
+    uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready Interrupt Enable */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET         0x5          /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE     _U(0x00)     /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN_Pos   0            /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN       (_U(0x1) << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_EMPTY_Pos      1            /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY          (_U(0x1) << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_SYNCRDY_Pos    2            /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
+#define DAC_INTENSET_SYNCRDY        (_U(0x1) << DAC_INTENSET_SYNCRDY_Pos)
+#define DAC_INTENSET_MASK           _U(0x07)     /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun                           */
+    __I uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty                  */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      2  Synchronization Ready              */
+    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET          0x6          /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE      _U(0x00)     /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN_Pos    0            /**< \brief (DAC_INTFLAG) Underrun */
+#define DAC_INTFLAG_UNDERRUN        (_U(0x1) << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_EMPTY_Pos       1            /**< \brief (DAC_INTFLAG) Data Buffer Empty */
+#define DAC_INTFLAG_EMPTY           (_U(0x1) << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_SYNCRDY_Pos     2            /**< \brief (DAC_INTFLAG) Synchronization Ready */
+#define DAC_INTFLAG_SYNCRDY         (_U(0x1) << DAC_INTFLAG_SYNCRDY_Pos)
+#define DAC_INTFLAG_MASK            _U(0x07)     /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET           0x7          /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE       _U(0x00)     /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_SYNCBUSY_Pos     7            /**< \brief (DAC_STATUS) Synchronization Busy Status */
+#define DAC_STATUS_SYNCBUSY         (_U(0x1) << DAC_STATUS_SYNCBUSY_Pos)
+#define DAC_STATUS_MASK             _U(0x80)     /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:16;          /*!< bit:  0..15  Data value to be converted         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET             0x8          /**< \brief (DAC_DATA offset) Data */
+#define DAC_DATA_RESETVALUE         _U(0x0000)   /**< \brief (DAC_DATA reset_value) Data */
+
+#define DAC_DATA_DATA_Pos           0            /**< \brief (DAC_DATA) Data value to be converted */
+#define DAC_DATA_DATA_Msk           (_U(0xFFFF) << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value)        (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
+#define DAC_DATA_MASK               _U(0xFFFF)   /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATABUF:16;       /*!< bit:  0..15  Data Buffer                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET          0xC          /**< \brief (DAC_DATABUF offset) Data Buffer */
+#define DAC_DATABUF_RESETVALUE      _U(0x0000)   /**< \brief (DAC_DATABUF reset_value) Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos     0            /**< \brief (DAC_DATABUF) Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk     (_U(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value)  (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
+#define DAC_DATABUF_MASK            _U(0xFFFF)   /**< \brief (DAC_DATABUF) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DAC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x0 (R/W  8) Control A */
+  __IO DAC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x1 (R/W  8) Control B */
+  __IO DAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x2 (R/W  8) Event Control */
+       RoReg8                    Reserved1[0x1];
+  __IO DAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
+  __IO DAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
+  __IO DAC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
+  __I  DAC_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
+  __IO DAC_DATA_Type             DATA;        /**< \brief Offset: 0x8 (R/W 16) Data */
+       RoReg8                    Reserved2[0x2];
+  __IO DAC_DATABUF_Type          DATABUF;     /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DAC_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/dmac.h b/uf2-samdx1/lib/samd21/samd21a/include/component/dmac.h
new file mode 100644
index 00000000..1d7c8c0e
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/dmac.h
@@ -0,0 +1,1072 @@
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_COMPONENT_
+#define _SAMD21_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2223
+#define REV_DMAC                    0x100
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t DMAENABLE:1;      /*!< bit:      1  DMA Enable                         */
+    uint16_t CRCENABLE:1;      /*!< bit:      2  CRC Enable                         */
+    uint16_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint16_t LVLEN0:1;         /*!< bit:      8  Priority Level 0 Enable            */
+    uint16_t LVLEN1:1;         /*!< bit:      9  Priority Level 1 Enable            */
+    uint16_t LVLEN2:1;         /*!< bit:     10  Priority Level 2 Enable            */
+    uint16_t LVLEN3:1;         /*!< bit:     11  Priority Level 3 Enable            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint16_t LVLEN:4;          /*!< bit:  8..11  Priority Level x Enable            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET            0x00         /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE        _U(0x0000)   /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos         0            /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST             (_U(0x1) << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos     1            /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE         (_U(0x1) << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_CRCENABLE_Pos     2            /**< \brief (DMAC_CTRL) CRC Enable */
+#define DMAC_CTRL_CRCENABLE         (_U(0x1) << DMAC_CTRL_CRCENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos        8            /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0            (1 << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos        9            /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1            (1 << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos        10           /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2            (1 << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos        11           /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3            (1 << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos         8            /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk         (_U(0xF) << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value)      (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
+#define DMAC_CTRL_MASK              _U(0x0F07)   /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CRCBEATSIZE:2;    /*!< bit:  0.. 1  CRC Beat Size                      */
+    uint16_t CRCPOLY:2;        /*!< bit:  2.. 3  CRC Polynomial Type                */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t CRCSRC:6;         /*!< bit:  8..13  CRC Input Source                   */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET         0x02         /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE     _U(0x0000)   /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0            /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
+#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U(0x0)   /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U(0x1)   /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U(0x2)   /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos    2            /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk    (_U(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
+#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val  _U(0x0)   /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val  _U(0x1)   /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16  (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32  (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos     8            /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk     (_U(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value)  (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
+#define   DMAC_CRCCTRL_CRCSRC_NOACT_Val   _U(0x0)   /**< \brief (DMAC_CRCCTRL) No action */
+#define   DMAC_CRCCTRL_CRCSRC_IO_Val      _U(0x1)   /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_NOACT   (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO      (DMAC_CRCCTRL_CRCSRC_IO_Val    << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_MASK           _U(0x3F0F)   /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CRCDATAIN:32;     /*!< bit:  0..31  CRC Data Input                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET       0x04         /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE   _U(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0            /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
+#define DMAC_CRCDATAIN_MASK         _U(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CRCCHKSUM:32;     /*!< bit:  0..31  CRC Checksum                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET       0x08         /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE   _U(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0            /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
+#define DMAC_CRCCHKSUM_MASK         _U(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W  8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCBUSY:1;        /*!< bit:      0  CRC Module Busy                    */
+    uint8_t  CRCZERO:1;        /*!< bit:      1  CRC Zero                           */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET       0x0C         /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE   _U(0x00)     /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos  0            /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY      (_U(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos  1            /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO      (_U(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_MASK         _U(0x03)     /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET         0x0D         /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE     _U(0x00)     /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN         (_U(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK           _U(0x01)     /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W  8) QOS Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WRBQOS:2;         /*!< bit:  0.. 1  Write-Back Quality of Service      */
+    uint8_t  FQOS:2;           /*!< bit:  2.. 3  Fetch Quality of Service           */
+    uint8_t  DQOS:2;           /*!< bit:  4.. 5  Data Transfer Quality of Service   */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_QOSCTRL_OFFSET         0x0E         /**< \brief (DMAC_QOSCTRL offset) QOS Control */
+#define DMAC_QOSCTRL_RESETVALUE     _U(0x15)     /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
+
+#define DMAC_QOSCTRL_WRBQOS_Pos     0            /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
+#define DMAC_QOSCTRL_WRBQOS_Msk     (_U(0x3) << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS(value)  (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
+#define   DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U(0x0)   /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_WRBQOS_LOW_Val     _U(0x1)   /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_WRBQOS_MEDIUM_Val  _U(0x2)   /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_WRBQOS_HIGH_Val    _U(0x3)   /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_LOW     (DMAC_QOSCTRL_WRBQOS_LOW_Val   << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM  (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_HIGH    (DMAC_QOSCTRL_WRBQOS_HIGH_Val  << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_Pos       2            /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
+#define DMAC_QOSCTRL_FQOS_Msk       (_U(0x3) << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS(value)    (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
+#define   DMAC_QOSCTRL_FQOS_DISABLE_Val   _U(0x0)   /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_FQOS_LOW_Val       _U(0x1)   /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_FQOS_MEDIUM_Val    _U(0x2)   /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_FQOS_HIGH_Val      _U(0x3)   /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_FQOS_DISABLE   (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_LOW       (DMAC_QOSCTRL_FQOS_LOW_Val     << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_MEDIUM    (DMAC_QOSCTRL_FQOS_MEDIUM_Val  << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_HIGH      (DMAC_QOSCTRL_FQOS_HIGH_Val    << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_Pos       4            /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
+#define DMAC_QOSCTRL_DQOS_Msk       (_U(0x3) << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS(value)    (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
+#define   DMAC_QOSCTRL_DQOS_DISABLE_Val   _U(0x0)   /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_DQOS_LOW_Val       _U(0x1)   /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_DQOS_MEDIUM_Val    _U(0x2)   /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_DQOS_HIGH_Val      _U(0x3)   /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_DQOS_DISABLE   (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_LOW       (DMAC_QOSCTRL_DQOS_LOW_Val     << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_MEDIUM    (DMAC_QOSCTRL_DQOS_MEDIUM_Val  << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_HIGH      (DMAC_QOSCTRL_DQOS_HIGH_Val    << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_MASK           _U(0x3F)     /**< \brief (DMAC_QOSCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWTRIG0:1;        /*!< bit:      0  Channel 0 Software Trigger         */
+    uint32_t SWTRIG1:1;        /*!< bit:      1  Channel 1 Software Trigger         */
+    uint32_t SWTRIG2:1;        /*!< bit:      2  Channel 2 Software Trigger         */
+    uint32_t SWTRIG3:1;        /*!< bit:      3  Channel 3 Software Trigger         */
+    uint32_t SWTRIG4:1;        /*!< bit:      4  Channel 4 Software Trigger         */
+    uint32_t SWTRIG5:1;        /*!< bit:      5  Channel 5 Software Trigger         */
+    uint32_t SWTRIG6:1;        /*!< bit:      6  Channel 6 Software Trigger         */
+    uint32_t SWTRIG7:1;        /*!< bit:      7  Channel 7 Software Trigger         */
+    uint32_t SWTRIG8:1;        /*!< bit:      8  Channel 8 Software Trigger         */
+    uint32_t SWTRIG9:1;        /*!< bit:      9  Channel 9 Software Trigger         */
+    uint32_t SWTRIG10:1;       /*!< bit:     10  Channel 10 Software Trigger        */
+    uint32_t SWTRIG11:1;       /*!< bit:     11  Channel 11 Software Trigger        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t SWTRIG:12;        /*!< bit:  0..11  Channel x Software Trigger         */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET      0x10         /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE  _U(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0            /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0     (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1            /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1     (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2            /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2     (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3            /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3     (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4            /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4     (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5            /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5     (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6            /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6     (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7            /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7     (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8            /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8     (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9            /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9     (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10           /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10    (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11           /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11    (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos  0            /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk  (_U(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
+#define DMAC_SWTRIGCTRL_MASK        _U(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LVLPRI0:4;        /*!< bit:  0.. 3  Level 0 Channel Priority Number    */
+    uint32_t :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint32_t RRLVLEN0:1;       /*!< bit:      7  Level 0 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI1:4;        /*!< bit:  8..11  Level 1 Channel Priority Number    */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t RRLVLEN1:1;       /*!< bit:     15  Level 1 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI2:4;        /*!< bit: 16..19  Level 2 Channel Priority Number    */
+    uint32_t :3;               /*!< bit: 20..22  Reserved                           */
+    uint32_t RRLVLEN2:1;       /*!< bit:     23  Level 2 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI3:4;        /*!< bit: 24..27  Level 3 Channel Priority Number    */
+    uint32_t :3;               /*!< bit: 28..30  Reserved                           */
+    uint32_t RRLVLEN3:1;       /*!< bit:     31  Level 3 Round-Robin Scheduling Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET        0x14         /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE    _U(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos   0            /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk   (_U(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
+#define DMAC_PRICTRL0_RRLVLEN0_Pos  7            /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0      (_U(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos   8            /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk   (_U(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
+#define DMAC_PRICTRL0_RRLVLEN1_Pos  15           /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1      (_U(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos   16           /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk   (_U(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
+#define DMAC_PRICTRL0_RRLVLEN2_Pos  23           /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2      (_U(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos   24           /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk   (_U(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
+#define DMAC_PRICTRL0_RRLVLEN3_Pos  31           /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3      (_U(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK          _U(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ID:4;             /*!< bit:  0.. 3  Channel ID                         */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t TERR:1;           /*!< bit:      8  Transfer Error                     */
+    uint16_t TCMPL:1;          /*!< bit:      9  Transfer Complete                  */
+    uint16_t SUSP:1;           /*!< bit:     10  Channel Suspend                    */
+    uint16_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint16_t FERR:1;           /*!< bit:     13  Fetch Error                        */
+    uint16_t BUSY:1;           /*!< bit:     14  Busy                               */
+    uint16_t PEND:1;           /*!< bit:     15  Pending                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET         0x20         /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE     _U(0x0000)   /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos         0            /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk         (_U(0xF) << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value)      (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
+#define DMAC_INTPEND_TERR_Pos       8            /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR           (_U(0x1) << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos      9            /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL          (_U(0x1) << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos       10           /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP           (_U(0x1) << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_FERR_Pos       13           /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR           (_U(0x1) << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos       14           /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY           (_U(0x1) << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos       15           /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND           (_U(0x1) << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK           _U(0xE70F)   /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/  32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHINT0:1;         /*!< bit:      0  Channel 0 Pending Interrupt        */
+    uint32_t CHINT1:1;         /*!< bit:      1  Channel 1 Pending Interrupt        */
+    uint32_t CHINT2:1;         /*!< bit:      2  Channel 2 Pending Interrupt        */
+    uint32_t CHINT3:1;         /*!< bit:      3  Channel 3 Pending Interrupt        */
+    uint32_t CHINT4:1;         /*!< bit:      4  Channel 4 Pending Interrupt        */
+    uint32_t CHINT5:1;         /*!< bit:      5  Channel 5 Pending Interrupt        */
+    uint32_t CHINT6:1;         /*!< bit:      6  Channel 6 Pending Interrupt        */
+    uint32_t CHINT7:1;         /*!< bit:      7  Channel 7 Pending Interrupt        */
+    uint32_t CHINT8:1;         /*!< bit:      8  Channel 8 Pending Interrupt        */
+    uint32_t CHINT9:1;         /*!< bit:      9  Channel 9 Pending Interrupt        */
+    uint32_t CHINT10:1;        /*!< bit:     10  Channel 10 Pending Interrupt       */
+    uint32_t CHINT11:1;        /*!< bit:     11  Channel 11 Pending Interrupt       */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t CHINT:12;         /*!< bit:  0..11  Channel x Pending Interrupt        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET       0x24         /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE   _U(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos   0            /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0       (1 << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos   1            /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1       (1 << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos   2            /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2       (1 << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos   3            /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3       (1 << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos   4            /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4       (1 << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos   5            /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5       (1 << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos   6            /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6       (1 << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos   7            /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7       (1 << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos   8            /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8       (1 << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos   9            /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9       (1 << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos  10           /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10      (1 << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos  11           /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11      (1 << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos    0            /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk    (_U(0xFFF) << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
+#define DMAC_INTSTATUS_MASK         _U(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/  32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BUSYCH0:1;        /*!< bit:      0  Busy Channel 0                     */
+    uint32_t BUSYCH1:1;        /*!< bit:      1  Busy Channel 1                     */
+    uint32_t BUSYCH2:1;        /*!< bit:      2  Busy Channel 2                     */
+    uint32_t BUSYCH3:1;        /*!< bit:      3  Busy Channel 3                     */
+    uint32_t BUSYCH4:1;        /*!< bit:      4  Busy Channel 4                     */
+    uint32_t BUSYCH5:1;        /*!< bit:      5  Busy Channel 5                     */
+    uint32_t BUSYCH6:1;        /*!< bit:      6  Busy Channel 6                     */
+    uint32_t BUSYCH7:1;        /*!< bit:      7  Busy Channel 7                     */
+    uint32_t BUSYCH8:1;        /*!< bit:      8  Busy Channel 8                     */
+    uint32_t BUSYCH9:1;        /*!< bit:      9  Busy Channel 9                     */
+    uint32_t BUSYCH10:1;       /*!< bit:     10  Busy Channel 10                    */
+    uint32_t BUSYCH11:1;       /*!< bit:     11  Busy Channel 11                    */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t BUSYCH:12;        /*!< bit:  0..11  Busy Channel x                     */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET          0x28         /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE      _U(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos     0            /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0         (1 << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos     1            /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1         (1 << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos     2            /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2         (1 << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos     3            /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3         (1 << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos     4            /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4         (1 << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos     5            /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5         (1 << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos     6            /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6         (1 << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos     7            /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7         (1 << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos     8            /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8         (1 << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos     9            /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9         (1 << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos    10           /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10        (1 << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos    11           /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11        (1 << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos      0            /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk      (_U(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value)   (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
+#define DMAC_BUSYCH_MASK            _U(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/  32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PENDCH0:1;        /*!< bit:      0  Pending Channel 0                  */
+    uint32_t PENDCH1:1;        /*!< bit:      1  Pending Channel 1                  */
+    uint32_t PENDCH2:1;        /*!< bit:      2  Pending Channel 2                  */
+    uint32_t PENDCH3:1;        /*!< bit:      3  Pending Channel 3                  */
+    uint32_t PENDCH4:1;        /*!< bit:      4  Pending Channel 4                  */
+    uint32_t PENDCH5:1;        /*!< bit:      5  Pending Channel 5                  */
+    uint32_t PENDCH6:1;        /*!< bit:      6  Pending Channel 6                  */
+    uint32_t PENDCH7:1;        /*!< bit:      7  Pending Channel 7                  */
+    uint32_t PENDCH8:1;        /*!< bit:      8  Pending Channel 8                  */
+    uint32_t PENDCH9:1;        /*!< bit:      9  Pending Channel 9                  */
+    uint32_t PENDCH10:1;       /*!< bit:     10  Pending Channel 10                 */
+    uint32_t PENDCH11:1;       /*!< bit:     11  Pending Channel 11                 */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t PENDCH:12;        /*!< bit:  0..11  Pending Channel x                  */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET          0x2C         /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE      _U(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos     0            /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0         (1 << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos     1            /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1         (1 << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos     2            /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2         (1 << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos     3            /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3         (1 << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos     4            /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4         (1 << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos     5            /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5         (1 << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos     6            /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6         (1 << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos     7            /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7         (1 << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos     8            /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8         (1 << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos     9            /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9         (1 << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos    10           /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10        (1 << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos    11           /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11        (1 << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH_Pos      0            /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk      (_U(0xFFF) << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value)   (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
+#define DMAC_PENDCH_MASK            _U(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/  32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LVLEX0:1;         /*!< bit:      0  Level 0 Channel Trigger Request Executing */
+    uint32_t LVLEX1:1;         /*!< bit:      1  Level 1 Channel Trigger Request Executing */
+    uint32_t LVLEX2:1;         /*!< bit:      2  Level 2 Channel Trigger Request Executing */
+    uint32_t LVLEX3:1;         /*!< bit:      3  Level 3 Channel Trigger Request Executing */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t ID:5;             /*!< bit:  8..12  Active Channel ID                  */
+    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
+    uint32_t ABUSY:1;          /*!< bit:     15  Active Channel Busy                */
+    uint32_t BTCNT:16;         /*!< bit: 16..31  Active Channel Block Transfer Count */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t LVLEX:4;          /*!< bit:  0.. 3  Level x Channel Trigger Request Executing */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET          0x30         /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE      _U(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos      0            /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0          (1 << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos      1            /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1          (1 << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos      2            /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2          (1 << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos      3            /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3          (1 << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos       0            /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk       (_U(0xF) << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value)    (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
+#define DMAC_ACTIVE_ID_Pos          8            /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk          (_U(0x1F) << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value)       (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
+#define DMAC_ACTIVE_ABUSY_Pos       15           /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY           (_U(0x1) << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos       16           /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk       (_U(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value)    (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
+#define DMAC_ACTIVE_MASK            _U(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BASEADDR:32;      /*!< bit:  0..31  Descriptor Memory Base Address     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET        0x34         /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE    _U(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos  0            /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk  (_U(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
+#define DMAC_BASEADDR_MASK          _U(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WRBADDR:32;       /*!< bit:  0..31  Write-Back Memory Base Address     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET         0x38         /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE     _U(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos    0            /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk    (_U(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
+#define DMAC_WRBADDR_MASK           _U(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W  8) Channel ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ID:4;             /*!< bit:  0.. 3  Channel ID                         */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHID_OFFSET            0x3F         /**< \brief (DMAC_CHID offset) Channel ID */
+#define DMAC_CHID_RESETVALUE        _U(0x00)     /**< \brief (DMAC_CHID reset_value) Channel ID */
+
+#define DMAC_CHID_ID_Pos            0            /**< \brief (DMAC_CHID) Channel ID */
+#define DMAC_CHID_ID_Msk            (_U(0xF) << DMAC_CHID_ID_Pos)
+#define DMAC_CHID_ID(value)         (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
+#define DMAC_CHID_MASK              _U(0x0F)     /**< \brief (DMAC_CHID) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W  8) Channel Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Channel Software Reset             */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Channel Enable                     */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET         0x40         /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
+#define DMAC_CHCTRLA_RESETVALUE     _U(0x00)     /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos      0            /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST          (_U(0x1) << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos     1            /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE         (_U(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_MASK           _U(0x03)     /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT:3;          /*!< bit:  0.. 2  Event Input Action                 */
+    uint32_t EVIE:1;           /*!< bit:      3  Channel Event Input Enable         */
+    uint32_t EVOE:1;           /*!< bit:      4  Channel Event Output Enable        */
+    uint32_t LVL:2;            /*!< bit:  5.. 6  Channel Arbitration Level          */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t TRIGSRC:6;        /*!< bit:  8..13  Trigger Source                     */
+    uint32_t :8;               /*!< bit: 14..21  Reserved                           */
+    uint32_t TRIGACT:2;        /*!< bit: 22..23  Trigger Action                     */
+    uint32_t CMD:2;            /*!< bit: 24..25  Software Command                   */
+    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET         0x44         /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
+#define DMAC_CHCTRLB_RESETVALUE     _U(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
+
+#define DMAC_CHCTRLB_EVACT_Pos      0            /**< \brief (DMAC_CHCTRLB) Event Input Action */
+#define DMAC_CHCTRLB_EVACT_Msk      (_U(0x7) << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT(value)   (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
+#define   DMAC_CHCTRLB_EVACT_NOACT_Val    _U(0x0)   /**< \brief (DMAC_CHCTRLB) No action */
+#define   DMAC_CHCTRLB_EVACT_TRIG_Val     _U(0x1)   /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
+#define   DMAC_CHCTRLB_EVACT_CTRIG_Val    _U(0x2)   /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
+#define   DMAC_CHCTRLB_EVACT_CBLOCK_Val   _U(0x3)   /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
+#define   DMAC_CHCTRLB_EVACT_SUSPEND_Val  _U(0x4)   /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define   DMAC_CHCTRLB_EVACT_RESUME_Val   _U(0x5)   /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define   DMAC_CHCTRLB_EVACT_SSKIP_Val    _U(0x6)   /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
+#define DMAC_CHCTRLB_EVACT_NOACT    (DMAC_CHCTRLB_EVACT_NOACT_Val  << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_TRIG     (DMAC_CHCTRLB_EVACT_TRIG_Val   << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CTRIG    (DMAC_CHCTRLB_EVACT_CTRIG_Val  << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CBLOCK   (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SUSPEND  (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_RESUME   (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SSKIP    (DMAC_CHCTRLB_EVACT_SSKIP_Val  << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVIE_Pos       3            /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
+#define DMAC_CHCTRLB_EVIE           (_U(0x1) << DMAC_CHCTRLB_EVIE_Pos)
+#define DMAC_CHCTRLB_EVOE_Pos       4            /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
+#define DMAC_CHCTRLB_EVOE           (_U(0x1) << DMAC_CHCTRLB_EVOE_Pos)
+#define DMAC_CHCTRLB_LVL_Pos        5            /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
+#define DMAC_CHCTRLB_LVL_Msk        (_U(0x3) << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL(value)     (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
+#define   DMAC_CHCTRLB_LVL_LVL0_Val       _U(0x0)   /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
+#define   DMAC_CHCTRLB_LVL_LVL1_Val       _U(0x1)   /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
+#define   DMAC_CHCTRLB_LVL_LVL2_Val       _U(0x2)   /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
+#define   DMAC_CHCTRLB_LVL_LVL3_Val       _U(0x3)   /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
+#define DMAC_CHCTRLB_LVL_LVL0       (DMAC_CHCTRLB_LVL_LVL0_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL1       (DMAC_CHCTRLB_LVL_LVL1_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL2       (DMAC_CHCTRLB_LVL_LVL2_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL3       (DMAC_CHCTRLB_LVL_LVL3_Val     << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_TRIGSRC_Pos    8            /**< \brief (DMAC_CHCTRLB) Trigger Source */
+#define DMAC_CHCTRLB_TRIGSRC_Msk    (_U(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
+#define   DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U(0x0)   /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGACT_Pos    22           /**< \brief (DMAC_CHCTRLB) Trigger Action */
+#define DMAC_CHCTRLB_TRIGACT_Msk    (_U(0x3) << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
+#define   DMAC_CHCTRLB_TRIGACT_BLOCK_Val  _U(0x0)   /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
+#define   DMAC_CHCTRLB_TRIGACT_BEAT_Val   _U(0x2)   /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
+#define   DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U(0x3)   /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
+#define DMAC_CHCTRLB_TRIGACT_BLOCK  (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_BEAT   (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_CMD_Pos        24           /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk        (_U(0x3) << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value)     (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
+#define   DMAC_CHCTRLB_CMD_NOACT_Val      _U(0x0)   /**< \brief (DMAC_CHCTRLB) No action */
+#define   DMAC_CHCTRLB_CMD_SUSPEND_Val    _U(0x1)   /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define   DMAC_CHCTRLB_CMD_RESUME_Val     _U(0x2)   /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT      (DMAC_CHCTRLB_CMD_NOACT_Val    << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND    (DMAC_CHCTRLB_CMD_SUSPEND_Val  << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME     (DMAC_CHCTRLB_CMD_RESUME_Val   << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK           _U(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W  8) Channel Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TERR:1;           /*!< bit:      0  Channel Transfer Error Interrupt Enable */
+    uint8_t  TCMPL:1;          /*!< bit:      1  Channel Transfer Complete Interrupt Enable */
+    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET      0x4C         /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE  _U(0x00)     /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos    0            /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR        (_U(0x1) << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL       (_U(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos    2            /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP        (_U(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK        _U(0x07)     /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W  8) Channel Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TERR:1;           /*!< bit:      0  Channel Transfer Error Interrupt Enable */
+    uint8_t  TCMPL:1;          /*!< bit:      1  Channel Transfer Complete Interrupt Enable */
+    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET      0x4D         /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE  _U(0x00)     /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos    0            /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR        (_U(0x1) << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL       (_U(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos    2            /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP        (_U(0x1) << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK        _U(0x07)     /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W  8) Channel Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TERR:1;           /*!< bit:      0  Channel Transfer Error             */
+    __I uint8_t  TCMPL:1;          /*!< bit:      1  Channel Transfer Complete          */
+    __I uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend                    */
+    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET       0x4E         /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE   _U(0x00)     /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos     0            /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
+#define DMAC_CHINTFLAG_TERR         (_U(0x1) << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos    1            /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL        (_U(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos     2            /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP         (_U(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK         _U(0x07)     /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/   8) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PEND:1;           /*!< bit:      0  Channel Pending                    */
+    uint8_t  BUSY:1;           /*!< bit:      1  Channel Busy                       */
+    uint8_t  FERR:1;           /*!< bit:      2  Channel Fetch Error                */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET        0x4F         /**< \brief (DMAC_CHSTATUS offset) Channel Status */
+#define DMAC_CHSTATUS_RESETVALUE    _U(0x00)     /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
+
+#define DMAC_CHSTATUS_PEND_Pos      0            /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND          (_U(0x1) << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos      1            /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY          (_U(0x1) << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos      2            /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
+#define DMAC_CHSTATUS_FERR          (_U(0x1) << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_MASK          _U(0x07)     /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t VALID:1;          /*!< bit:      0  Descriptor Valid                   */
+    uint16_t EVOSEL:2;         /*!< bit:  1.. 2  Event Output Selection             */
+    uint16_t BLOCKACT:2;       /*!< bit:  3.. 4  Block Action                       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t BEATSIZE:2;       /*!< bit:  8.. 9  Beat Size                          */
+    uint16_t SRCINC:1;         /*!< bit:     10  Source Address Increment Enable    */
+    uint16_t DSTINC:1;         /*!< bit:     11  Destination Address Increment Enable */
+    uint16_t STEPSEL:1;        /*!< bit:     12  Step Selection                     */
+    uint16_t STEPSIZE:3;       /*!< bit: 13..15  Address Increment Step Size        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET          0x00         /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE      _U(0x0000)   /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos       0            /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID           (_U(0x1) << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos      1            /**< \brief (DMAC_BTCTRL) Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk      (_U(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value)   (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
+#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val  _U(0x0)   /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val    _U(0x1)   /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
+#define   DMAC_BTCTRL_EVOSEL_BEAT_Val     _U(0x3)   /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
+#define DMAC_BTCTRL_EVOSEL_DISABLE  (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK    (DMAC_BTCTRL_EVOSEL_BLOCK_Val  << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BEAT     (DMAC_BTCTRL_EVOSEL_BEAT_Val   << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos    3            /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk    (_U(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
+#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val  _U(0x0)   /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
+#define   DMAC_BTCTRL_BLOCKACT_INT_Val    _U(0x1)   /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
+#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U(0x2)   /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val   _U(0x3)   /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT  (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT    (DMAC_BTCTRL_BLOCKACT_INT_Val  << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH   (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos    8            /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk    (_U(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
+#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val   _U(0x0)   /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
+#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val  _U(0x1)   /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
+#define   DMAC_BTCTRL_BEATSIZE_WORD_Val   _U(0x2)   /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_BYTE   (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD  (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD   (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos      10           /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC          (_U(0x1) << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos      11           /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC          (_U(0x1) << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos     12           /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL         (_U(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
+#define   DMAC_BTCTRL_STEPSEL_DST_Val     _U(0x0)   /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define   DMAC_BTCTRL_STEPSEL_SRC_Val     _U(0x1)   /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST     (DMAC_BTCTRL_STEPSEL_DST_Val   << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC     (DMAC_BTCTRL_STEPSEL_SRC_Val   << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos    13           /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk    (_U(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
+#define   DMAC_BTCTRL_STEPSIZE_X1_Val     _U(0x0)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1 */
+#define   DMAC_BTCTRL_STEPSIZE_X2_Val     _U(0x1)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2 */
+#define   DMAC_BTCTRL_STEPSIZE_X4_Val     _U(0x2)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4 */
+#define   DMAC_BTCTRL_STEPSIZE_X8_Val     _U(0x3)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8 */
+#define   DMAC_BTCTRL_STEPSIZE_X16_Val    _U(0x4)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16 */
+#define   DMAC_BTCTRL_STEPSIZE_X32_Val    _U(0x5)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32 */
+#define   DMAC_BTCTRL_STEPSIZE_X64_Val    _U(0x6)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64 */
+#define   DMAC_BTCTRL_STEPSIZE_X128_Val   _U(0x7)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128 */
+#define DMAC_BTCTRL_STEPSIZE_X1     (DMAC_BTCTRL_STEPSIZE_X1_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X2     (DMAC_BTCTRL_STEPSIZE_X2_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X4     (DMAC_BTCTRL_STEPSIZE_X4_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X8     (DMAC_BTCTRL_STEPSIZE_X8_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X16    (DMAC_BTCTRL_STEPSIZE_X16_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X32    (DMAC_BTCTRL_STEPSIZE_X32_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X64    (DMAC_BTCTRL_STEPSIZE_X64_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X128   (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_MASK            _U(0xFF1F)   /**< \brief (DMAC_BTCTRL) MASK Register */
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BTCNT:16;         /*!< bit:  0..15  Block Transfer Count               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_BTCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCNT_OFFSET           0x02         /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
+
+#define DMAC_BTCNT_BTCNT_Pos        0            /**< \brief (DMAC_BTCNT) Block Transfer Count */
+#define DMAC_BTCNT_BTCNT_Msk        (_U(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT(value)     (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
+#define DMAC_BTCNT_MASK             _U(0xFFFF)   /**< \brief (DMAC_BTCNT) MASK Register */
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRCADDR:32;       /*!< bit:  0..31  Transfer Source Address            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_SRCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SRCADDR_OFFSET         0x04         /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
+
+#define DMAC_SRCADDR_SRCADDR_Pos    0            /**< \brief (DMAC_SRCADDR) Transfer Source Address */
+#define DMAC_SRCADDR_SRCADDR_Msk    (_U(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
+#define DMAC_SRCADDR_MASK           _U(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DSTADDR:32;       /*!< bit:  0..31  Transfer Destination Address       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_DSTADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DSTADDR_OFFSET         0x08         /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
+
+#define DMAC_DSTADDR_DSTADDR_Pos    0            /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
+#define DMAC_DSTADDR_DSTADDR_Msk    (_U(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
+#define DMAC_DSTADDR_MASK           _U(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DESCADDR:32;      /*!< bit:  0..31  Next Descriptor Address            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_DESCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DESCADDR_OFFSET        0x0C         /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
+
+#define DMAC_DESCADDR_DESCADDR_Pos  0            /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
+#define DMAC_DESCADDR_DESCADDR_Msk  (_U(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
+#define DMAC_DESCADDR_MASK          _U(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */
+
+/** \brief DMAC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DMAC_CTRL_Type            CTRL;        /**< \brief Offset: 0x00 (R/W 16) Control */
+  __IO DMAC_CRCCTRL_Type         CRCCTRL;     /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+  __IO DMAC_CRCDATAIN_Type       CRCDATAIN;   /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+  __IO DMAC_CRCCHKSUM_Type       CRCCHKSUM;   /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+  __IO DMAC_CRCSTATUS_Type       CRCSTATUS;   /**< \brief Offset: 0x0C (R/W  8) CRC Status */
+  __IO DMAC_DBGCTRL_Type         DBGCTRL;     /**< \brief Offset: 0x0D (R/W  8) Debug Control */
+  __IO DMAC_QOSCTRL_Type         QOSCTRL;     /**< \brief Offset: 0x0E (R/W  8) QOS Control */
+       RoReg8                    Reserved1[0x1];
+  __IO DMAC_SWTRIGCTRL_Type      SWTRIGCTRL;  /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+  __IO DMAC_PRICTRL0_Type        PRICTRL0;    /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+       RoReg8                    Reserved2[0x8];
+  __IO DMAC_INTPEND_Type         INTPEND;     /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+       RoReg8                    Reserved3[0x2];
+  __I  DMAC_INTSTATUS_Type       INTSTATUS;   /**< \brief Offset: 0x24 (R/  32) Interrupt Status */
+  __I  DMAC_BUSYCH_Type          BUSYCH;      /**< \brief Offset: 0x28 (R/  32) Busy Channels */
+  __I  DMAC_PENDCH_Type          PENDCH;      /**< \brief Offset: 0x2C (R/  32) Pending Channels */
+  __I  DMAC_ACTIVE_Type          ACTIVE;      /**< \brief Offset: 0x30 (R/  32) Active Channel and Levels */
+  __IO DMAC_BASEADDR_Type        BASEADDR;    /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+  __IO DMAC_WRBADDR_Type         WRBADDR;     /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+       RoReg8                    Reserved4[0x3];
+  __IO DMAC_CHID_Type            CHID;        /**< \brief Offset: 0x3F (R/W  8) Channel ID */
+  __IO DMAC_CHCTRLA_Type         CHCTRLA;     /**< \brief Offset: 0x40 (R/W  8) Channel Control A */
+       RoReg8                    Reserved5[0x3];
+  __IO DMAC_CHCTRLB_Type         CHCTRLB;     /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+       RoReg8                    Reserved6[0x4];
+  __IO DMAC_CHINTENCLR_Type      CHINTENCLR;  /**< \brief Offset: 0x4C (R/W  8) Channel Interrupt Enable Clear */
+  __IO DMAC_CHINTENSET_Type      CHINTENSET;  /**< \brief Offset: 0x4D (R/W  8) Channel Interrupt Enable Set */
+  __IO DMAC_CHINTFLAG_Type       CHINTFLAG;   /**< \brief Offset: 0x4E (R/W  8) Channel Interrupt Flag Status and Clear */
+  __I  DMAC_CHSTATUS_Type        CHSTATUS;    /**< \brief Offset: 0x4F (R/   8) Channel Status */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DMAC_BTCTRL_Type          BTCTRL;      /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+  __IO DMAC_BTCNT_Type           BTCNT;       /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+  __IO DMAC_SRCADDR_Type         SRCADDR;     /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
+  __IO DMAC_DSTADDR_Type         DSTADDR;     /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
+  __IO DMAC_DESCADDR_Type        DESCADDR;    /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+} DmacDescriptor
+#ifdef __GNUC__
+  __attribute__ ((aligned (8)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_DMAC_DESCRIPTOR
+
+/*@}*/
+
+#endif /* _SAMD21_DMAC_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/dsu.h b/uf2-samdx1/lib/samd21/samd21a/include/component/dsu.h
new file mode 100644
index 00000000..75c14804
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/dsu.h
@@ -0,0 +1,536 @@
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_COMPONENT_
+#define _SAMD21_DSU_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2209
+#define REV_DSU                     0x200
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CRC:1;            /*!< bit:      2  32-bit Cyclic Redundancy Check     */
+    uint8_t  MBIST:1;          /*!< bit:      3  Memory Built-In Self-Test          */
+    uint8_t  CE:1;             /*!< bit:      4  Chip Erase                         */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET             0x0000       /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE         _U(0x00)     /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos          0            /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST              (_U(0x1) << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos            2            /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
+#define DSU_CTRL_CRC                (_U(0x1) << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos          3            /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
+#define DSU_CTRL_MBIST              (_U(0x1) << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos             4            /**< \brief (DSU_CTRL) Chip Erase */
+#define DSU_CTRL_CE                 (_U(0x1) << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_MASK               _U(0x1D)     /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W  8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DONE:1;           /*!< bit:      0  Done                               */
+    uint8_t  CRSTEXT:1;        /*!< bit:      1  CPU Reset Phase Extension          */
+    uint8_t  BERR:1;           /*!< bit:      2  Bus Error                          */
+    uint8_t  FAIL:1;           /*!< bit:      3  Failure                            */
+    uint8_t  PERR:1;           /*!< bit:      4  Protection Error                   */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET          0x0001       /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE      _U(0x00)     /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos        0            /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE            (_U(0x1) << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos     1            /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT         (_U(0x1) << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos        2            /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR            (_U(0x1) << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos        3            /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL            (_U(0x1) << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos        4            /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR            (_U(0x1) << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK            _U(0x1F)     /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PROT:1;           /*!< bit:      0  Protected                          */
+    uint8_t  DBGPRES:1;        /*!< bit:      1  Debugger Present                   */
+    uint8_t  DCCD0:1;          /*!< bit:      2  Debug Communication Channel 0 Dirty */
+    uint8_t  DCCD1:1;          /*!< bit:      3  Debug Communication Channel 1 Dirty */
+    uint8_t  HPE:1;            /*!< bit:      4  Hot-Plugging Enable                */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  DCCD:2;           /*!< bit:  2.. 3  Debug Communication Channel x Dirty */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET          0x0002       /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE      _U(0x10)     /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos        0            /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT            (_U(0x1) << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos     1            /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES         (_U(0x1) << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos       2            /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0           (1 << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos       3            /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1           (1 << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos        2            /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk        (_U(0x3) << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value)     (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
+#define DSU_STATUSB_HPE_Pos         4            /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE             (_U(0x1) << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_MASK            _U(0x1F)     /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t ADDR:30;          /*!< bit:  2..31  Address                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET             0x0004       /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE         _U(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_ADDR_Pos           2            /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk           (_U(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value)        (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
+#define DSU_ADDR_MASK               _U(0xFFFFFFFC) /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t LENGTH:30;        /*!< bit:  2..31  Length                             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET           0x0008       /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE       _U(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos       2            /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk       (_U(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value)    (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
+#define DSU_LENGTH_MASK             _U(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET             0x000C       /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE         _U(0x00000000) /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos           0            /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk           (_U(0xFFFFFFFF) << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value)        (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
+#define DSU_DATA_MASK               _U(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET              0x0010       /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE          _U(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos            0            /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk            (_U(0xFFFFFFFF) << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value)         (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
+#define DSU_DCC_MASK                _U(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/  32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DEVSEL:8;         /*!< bit:  0.. 7  Device Select                      */
+    uint32_t REVISION:4;       /*!< bit:  8..11  Revision                           */
+    uint32_t DIE:4;            /*!< bit: 12..15  Die Identification                 */
+    uint32_t SERIES:6;         /*!< bit: 16..21  Product Series                     */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t FAMILY:5;         /*!< bit: 23..27  Product Family                     */
+    uint32_t PROCESSOR:4;      /*!< bit: 28..31  Processor                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET              0x0018       /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos          0            /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk          (_U(0xFF) << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value)       (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
+#define DSU_DID_REVISION_Pos        8            /**< \brief (DSU_DID) Revision */
+#define DSU_DID_REVISION_Msk        (_U(0xF) << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value)     (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
+#define DSU_DID_DIE_Pos             12           /**< \brief (DSU_DID) Die Identification */
+#define DSU_DID_DIE_Msk             (_U(0xF) << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value)          (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
+#define DSU_DID_SERIES_Pos          16           /**< \brief (DSU_DID) Product Series */
+#define DSU_DID_SERIES_Msk          (_U(0x3F) << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value)       (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
+#define DSU_DID_FAMILY_Pos          23           /**< \brief (DSU_DID) Product Family */
+#define DSU_DID_FAMILY_Msk          (_U(0x1F) << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value)       (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
+#define DSU_DID_PROCESSOR_Pos       28           /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk       (_U(0xF) << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value)    (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
+#define DSU_DID_MASK                _U(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/  32) Coresight ROM Table Entry n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EPRES:1;          /*!< bit:      0  Entry Present                      */
+    uint32_t FMT:1;            /*!< bit:      1  Format                             */
+    uint32_t :10;              /*!< bit:  2..11  Reserved                           */
+    uint32_t ADDOFF:20;        /*!< bit: 12..31  Address Offset                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ENTRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY_OFFSET            0x1000       /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
+#define DSU_ENTRY_RESETVALUE        _U(0x00000002) /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
+
+#define DSU_ENTRY_EPRES_Pos         0            /**< \brief (DSU_ENTRY) Entry Present */
+#define DSU_ENTRY_EPRES             (_U(0x1) << DSU_ENTRY_EPRES_Pos)
+#define DSU_ENTRY_FMT_Pos           1            /**< \brief (DSU_ENTRY) Format */
+#define DSU_ENTRY_FMT               (_U(0x1) << DSU_ENTRY_FMT_Pos)
+#define DSU_ENTRY_ADDOFF_Pos        12           /**< \brief (DSU_ENTRY) Address Offset */
+#define DSU_ENTRY_ADDOFF_Msk        (_U(0xFFFFF) << DSU_ENTRY_ADDOFF_Pos)
+#define DSU_ENTRY_ADDOFF(value)     (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
+#define DSU_ENTRY_MASK              _U(0xFFFFF003) /**< \brief (DSU_ENTRY) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/  32) Coresight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t END:32;           /*!< bit:  0..31  End Marker                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET              0x1008       /**< \brief (DSU_END offset) Coresight ROM Table End */
+#define DSU_END_RESETVALUE          _U(0x00000000) /**< \brief (DSU_END reset_value) Coresight ROM Table End */
+
+#define DSU_END_END_Pos             0            /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk             (_U(0xFFFFFFFF) << DSU_END_END_Pos)
+#define DSU_END_END(value)          (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
+#define DSU_END_MASK                _U(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/  32) Coresight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SMEMP:1;          /*!< bit:      0  System Memory Present              */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET          0x1FCC       /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE      _U(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos       0            /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP           (_U(0x1) << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK            _U(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/  32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPCC:4;          /*!< bit:  0.. 3  JEP-106 Continuation Code          */
+    uint32_t FKBC:4;           /*!< bit:  4.. 7  4KB Count                          */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET             0x1FD0       /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE         _U(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos          0            /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk          (_U(0xF) << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value)       (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
+#define DSU_PID4_FKBC_Pos           4            /**< \brief (DSU_PID4) 4KB Count */
+#define DSU_PID4_FKBC_Msk           (_U(0xF) << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value)        (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
+#define DSU_PID4_MASK               _U(0x000000FF) /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/  32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBL:8;        /*!< bit:  0.. 7  Part Number Low                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET             0x1FE0       /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE         _U(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos        0            /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk        (_U(0xFF) << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value)     (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
+#define DSU_PID0_MASK               _U(0x000000FF) /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/  32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBH:4;        /*!< bit:  0.. 3  Part Number High                   */
+    uint32_t JEPIDCL:4;        /*!< bit:  4.. 7  Low part of the JEP-106 Identity Code */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET             0x1FE4       /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE         _U(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos        0            /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk        (_U(0xF) << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value)     (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
+#define DSU_PID1_JEPIDCL_Pos        4            /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk        (_U(0xF) << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value)     (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
+#define DSU_PID1_MASK               _U(0x000000FF) /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/  32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPIDCH:3;        /*!< bit:  0.. 2  JEP-106 Identity Code High         */
+    uint32_t JEPU:1;           /*!< bit:      3  JEP-106 Identity Code is used      */
+    uint32_t REVISION:4;       /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET             0x1FE8       /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE         _U(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos        0            /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk        (_U(0x7) << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value)     (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
+#define DSU_PID2_JEPU_Pos           3            /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU               (_U(0x1) << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos       4            /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk       (_U(0xF) << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value)    (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
+#define DSU_PID2_MASK               _U(0x000000FF) /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/  32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CUSMOD:4;         /*!< bit:  0.. 3  ARM CUSMOD                         */
+    uint32_t REVAND:4;         /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET             0x1FEC       /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE         _U(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos         0            /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk         (_U(0xF) << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value)      (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
+#define DSU_PID3_REVAND_Pos         4            /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk         (_U(0xF) << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value)      (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
+#define DSU_PID3_MASK               _U(0x000000FF) /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/  32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB0:8;     /*!< bit:  0.. 7  Preamble Byte 0                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET             0x1FF0       /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE         _U(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos     0            /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk     (_U(0xFF) << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value)  (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
+#define DSU_CID0_MASK               _U(0x000000FF) /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/  32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLE:4;       /*!< bit:  0.. 3  Preamble                           */
+    uint32_t CCLASS:4;         /*!< bit:  4.. 7  Component Class                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET             0x1FF4       /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE         _U(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos       0            /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk       (_U(0xF) << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value)    (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
+#define DSU_CID1_CCLASS_Pos         4            /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk         (_U(0xF) << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value)      (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
+#define DSU_CID1_MASK               _U(0x000000FF) /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/  32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB2:8;     /*!< bit:  0.. 7  Preamble Byte 2                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET             0x1FF8       /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE         _U(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos     0            /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk     (_U(0xFF) << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value)  (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
+#define DSU_CID2_MASK               _U(0x000000FF) /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/  32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB3:8;     /*!< bit:  0.. 7  Preamble Byte 3                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET             0x1FFC       /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE         _U(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos     0            /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk     (_U(0xFF) << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value)  (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
+#define DSU_CID3_MASK               _U(0x000000FF) /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  DSU_CTRL_Type             CTRL;        /**< \brief Offset: 0x0000 ( /W  8) Control */
+  __IO DSU_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x0001 (R/W  8) Status A */
+  __I  DSU_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x0002 (R/   8) Status B */
+       RoReg8                    Reserved1[0x1];
+  __IO DSU_ADDR_Type             ADDR;        /**< \brief Offset: 0x0004 (R/W 32) Address */
+  __IO DSU_LENGTH_Type           LENGTH;      /**< \brief Offset: 0x0008 (R/W 32) Length */
+  __IO DSU_DATA_Type             DATA;        /**< \brief Offset: 0x000C (R/W 32) Data */
+  __IO DSU_DCC_Type              DCC[2];      /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+  __I  DSU_DID_Type              DID;         /**< \brief Offset: 0x0018 (R/  32) Device Identification */
+       RoReg8                    Reserved2[0xFE4];
+  __I  DSU_ENTRY_Type            ENTRY[2];    /**< \brief Offset: 0x1000 (R/  32) Coresight ROM Table Entry n */
+  __I  DSU_END_Type              END;         /**< \brief Offset: 0x1008 (R/  32) Coresight ROM Table End */
+       RoReg8                    Reserved3[0xFC0];
+  __I  DSU_MEMTYPE_Type          MEMTYPE;     /**< \brief Offset: 0x1FCC (R/  32) Coresight ROM Table Memory Type */
+  __I  DSU_PID4_Type             PID4;        /**< \brief Offset: 0x1FD0 (R/  32) Peripheral Identification 4 */
+       RoReg8                    Reserved4[0xC];
+  __I  DSU_PID0_Type             PID0;        /**< \brief Offset: 0x1FE0 (R/  32) Peripheral Identification 0 */
+  __I  DSU_PID1_Type             PID1;        /**< \brief Offset: 0x1FE4 (R/  32) Peripheral Identification 1 */
+  __I  DSU_PID2_Type             PID2;        /**< \brief Offset: 0x1FE8 (R/  32) Peripheral Identification 2 */
+  __I  DSU_PID3_Type             PID3;        /**< \brief Offset: 0x1FEC (R/  32) Peripheral Identification 3 */
+  __I  DSU_CID0_Type             CID0;        /**< \brief Offset: 0x1FF0 (R/  32) Component Identification 0 */
+  __I  DSU_CID1_Type             CID1;        /**< \brief Offset: 0x1FF4 (R/  32) Component Identification 1 */
+  __I  DSU_CID2_Type             CID2;        /**< \brief Offset: 0x1FF8 (R/  32) Component Identification 2 */
+  __I  DSU_CID3_Type             CID3;        /**< \brief Offset: 0x1FFC (R/  32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DSU_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/eic.h b/uf2-samdx1/lib/samd21/samd21a/include/component/eic.h
new file mode 100644
index 00000000..5adb7d76
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/eic.h
@@ -0,0 +1,666 @@
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_COMPONENT_
+#define _SAMD21_EIC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2217
+#define REV_EIC                     0x101
+
+/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRL_OFFSET             0x00         /**< \brief (EIC_CTRL offset) Control */
+#define EIC_CTRL_RESETVALUE         _U(0x00)     /**< \brief (EIC_CTRL reset_value) Control */
+
+#define EIC_CTRL_SWRST_Pos          0            /**< \brief (EIC_CTRL) Software Reset */
+#define EIC_CTRL_SWRST              (_U(0x1) << EIC_CTRL_SWRST_Pos)
+#define EIC_CTRL_ENABLE_Pos         1            /**< \brief (EIC_CTRL) Enable */
+#define EIC_CTRL_ENABLE             (_U(0x1) << EIC_CTRL_ENABLE_Pos)
+#define EIC_CTRL_MASK               _U(0x03)     /**< \brief (EIC_CTRL) MASK Register */
+
+/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_STATUS_OFFSET           0x01         /**< \brief (EIC_STATUS offset) Status */
+#define EIC_STATUS_RESETVALUE       _U(0x00)     /**< \brief (EIC_STATUS reset_value) Status */
+
+#define EIC_STATUS_SYNCBUSY_Pos     7            /**< \brief (EIC_STATUS) Synchronization Busy */
+#define EIC_STATUS_SYNCBUSY         (_U(0x1) << EIC_STATUS_SYNCBUSY_Pos)
+#define EIC_STATUS_MASK             _U(0x80)     /**< \brief (EIC_STATUS) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W  8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMISENSE:3;       /*!< bit:  0.. 2  Non-Maskable Interrupt Sense       */
+    uint8_t  NMIFILTEN:1;      /*!< bit:      3  Non-Maskable Interrupt Filter Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET          0x02         /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE      _U(0x00)     /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos    0            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
+#define EIC_NMICTRL_NMISENSE_Msk    (_U(0x7) << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
+#define   EIC_NMICTRL_NMISENSE_NONE_Val   _U(0x0)   /**< \brief (EIC_NMICTRL) No detection */
+#define   EIC_NMICTRL_NMISENSE_RISE_Val   _U(0x1)   /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define   EIC_NMICTRL_NMISENSE_FALL_Val   _U(0x2)   /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define   EIC_NMICTRL_NMISENSE_BOTH_Val   _U(0x3)   /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define   EIC_NMICTRL_NMISENSE_HIGH_Val   _U(0x4)   /**< \brief (EIC_NMICTRL) High-level detection */
+#define   EIC_NMICTRL_NMISENSE_LOW_Val    _U(0x5)   /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE   (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE   (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL   (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH   (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH   (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW    (EIC_NMICTRL_NMISENSE_LOW_Val  << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos   3            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN       (_U(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_MASK            _U(0x0F)     /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W  8) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMI:1;            /*!< bit:      0  Non-Maskable Interrupt             */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET          0x03         /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE      _U(0x00)     /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos         0            /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI             (_U(0x1) << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK            _U(0x01)     /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINTEO0:1;      /*!< bit:      0  External Interrupt 0 Event Output Enable */
+    uint32_t EXTINTEO1:1;      /*!< bit:      1  External Interrupt 1 Event Output Enable */
+    uint32_t EXTINTEO2:1;      /*!< bit:      2  External Interrupt 2 Event Output Enable */
+    uint32_t EXTINTEO3:1;      /*!< bit:      3  External Interrupt 3 Event Output Enable */
+    uint32_t EXTINTEO4:1;      /*!< bit:      4  External Interrupt 4 Event Output Enable */
+    uint32_t EXTINTEO5:1;      /*!< bit:      5  External Interrupt 5 Event Output Enable */
+    uint32_t EXTINTEO6:1;      /*!< bit:      6  External Interrupt 6 Event Output Enable */
+    uint32_t EXTINTEO7:1;      /*!< bit:      7  External Interrupt 7 Event Output Enable */
+    uint32_t EXTINTEO8:1;      /*!< bit:      8  External Interrupt 8 Event Output Enable */
+    uint32_t EXTINTEO9:1;      /*!< bit:      9  External Interrupt 9 Event Output Enable */
+    uint32_t EXTINTEO10:1;     /*!< bit:     10  External Interrupt 10 Event Output Enable */
+    uint32_t EXTINTEO11:1;     /*!< bit:     11  External Interrupt 11 Event Output Enable */
+    uint32_t EXTINTEO12:1;     /*!< bit:     12  External Interrupt 12 Event Output Enable */
+    uint32_t EXTINTEO13:1;     /*!< bit:     13  External Interrupt 13 Event Output Enable */
+    uint32_t EXTINTEO14:1;     /*!< bit:     14  External Interrupt 14 Event Output Enable */
+    uint32_t EXTINTEO15:1;     /*!< bit:     15  External Interrupt 15 Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINTEO:16;      /*!< bit:  0..15  External Interrupt x Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET           0x04         /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE       _U(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO0_Pos    0            /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO0        (1 << EIC_EVCTRL_EXTINTEO0_Pos)
+#define EIC_EVCTRL_EXTINTEO1_Pos    1            /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO1        (1 << EIC_EVCTRL_EXTINTEO1_Pos)
+#define EIC_EVCTRL_EXTINTEO2_Pos    2            /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO2        (1 << EIC_EVCTRL_EXTINTEO2_Pos)
+#define EIC_EVCTRL_EXTINTEO3_Pos    3            /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO3        (1 << EIC_EVCTRL_EXTINTEO3_Pos)
+#define EIC_EVCTRL_EXTINTEO4_Pos    4            /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO4        (1 << EIC_EVCTRL_EXTINTEO4_Pos)
+#define EIC_EVCTRL_EXTINTEO5_Pos    5            /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO5        (1 << EIC_EVCTRL_EXTINTEO5_Pos)
+#define EIC_EVCTRL_EXTINTEO6_Pos    6            /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO6        (1 << EIC_EVCTRL_EXTINTEO6_Pos)
+#define EIC_EVCTRL_EXTINTEO7_Pos    7            /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO7        (1 << EIC_EVCTRL_EXTINTEO7_Pos)
+#define EIC_EVCTRL_EXTINTEO8_Pos    8            /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO8        (1 << EIC_EVCTRL_EXTINTEO8_Pos)
+#define EIC_EVCTRL_EXTINTEO9_Pos    9            /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO9        (1 << EIC_EVCTRL_EXTINTEO9_Pos)
+#define EIC_EVCTRL_EXTINTEO10_Pos   10           /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO10       (1 << EIC_EVCTRL_EXTINTEO10_Pos)
+#define EIC_EVCTRL_EXTINTEO11_Pos   11           /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO11       (1 << EIC_EVCTRL_EXTINTEO11_Pos)
+#define EIC_EVCTRL_EXTINTEO12_Pos   12           /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO12       (1 << EIC_EVCTRL_EXTINTEO12_Pos)
+#define EIC_EVCTRL_EXTINTEO13_Pos   13           /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO13       (1 << EIC_EVCTRL_EXTINTEO13_Pos)
+#define EIC_EVCTRL_EXTINTEO14_Pos   14           /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO14       (1 << EIC_EVCTRL_EXTINTEO14_Pos)
+#define EIC_EVCTRL_EXTINTEO15_Pos   15           /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO15       (1 << EIC_EVCTRL_EXTINTEO15_Pos)
+#define EIC_EVCTRL_EXTINTEO_Pos     0            /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk     (_U(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value)  (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
+#define EIC_EVCTRL_MASK             _U(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
+    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
+    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
+    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
+    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
+    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
+    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
+    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
+    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
+    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
+    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
+    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
+    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
+    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
+    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
+    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET         0x08         /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE     _U(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT0_Pos    0            /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
+#define EIC_INTENCLR_EXTINT0        (1 << EIC_INTENCLR_EXTINT0_Pos)
+#define EIC_INTENCLR_EXTINT1_Pos    1            /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
+#define EIC_INTENCLR_EXTINT1        (1 << EIC_INTENCLR_EXTINT1_Pos)
+#define EIC_INTENCLR_EXTINT2_Pos    2            /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
+#define EIC_INTENCLR_EXTINT2        (1 << EIC_INTENCLR_EXTINT2_Pos)
+#define EIC_INTENCLR_EXTINT3_Pos    3            /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
+#define EIC_INTENCLR_EXTINT3        (1 << EIC_INTENCLR_EXTINT3_Pos)
+#define EIC_INTENCLR_EXTINT4_Pos    4            /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
+#define EIC_INTENCLR_EXTINT4        (1 << EIC_INTENCLR_EXTINT4_Pos)
+#define EIC_INTENCLR_EXTINT5_Pos    5            /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
+#define EIC_INTENCLR_EXTINT5        (1 << EIC_INTENCLR_EXTINT5_Pos)
+#define EIC_INTENCLR_EXTINT6_Pos    6            /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
+#define EIC_INTENCLR_EXTINT6        (1 << EIC_INTENCLR_EXTINT6_Pos)
+#define EIC_INTENCLR_EXTINT7_Pos    7            /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
+#define EIC_INTENCLR_EXTINT7        (1 << EIC_INTENCLR_EXTINT7_Pos)
+#define EIC_INTENCLR_EXTINT8_Pos    8            /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
+#define EIC_INTENCLR_EXTINT8        (1 << EIC_INTENCLR_EXTINT8_Pos)
+#define EIC_INTENCLR_EXTINT9_Pos    9            /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
+#define EIC_INTENCLR_EXTINT9        (1 << EIC_INTENCLR_EXTINT9_Pos)
+#define EIC_INTENCLR_EXTINT10_Pos   10           /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
+#define EIC_INTENCLR_EXTINT10       (1 << EIC_INTENCLR_EXTINT10_Pos)
+#define EIC_INTENCLR_EXTINT11_Pos   11           /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
+#define EIC_INTENCLR_EXTINT11       (1 << EIC_INTENCLR_EXTINT11_Pos)
+#define EIC_INTENCLR_EXTINT12_Pos   12           /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
+#define EIC_INTENCLR_EXTINT12       (1 << EIC_INTENCLR_EXTINT12_Pos)
+#define EIC_INTENCLR_EXTINT13_Pos   13           /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
+#define EIC_INTENCLR_EXTINT13       (1 << EIC_INTENCLR_EXTINT13_Pos)
+#define EIC_INTENCLR_EXTINT14_Pos   14           /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
+#define EIC_INTENCLR_EXTINT14       (1 << EIC_INTENCLR_EXTINT14_Pos)
+#define EIC_INTENCLR_EXTINT15_Pos   15           /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
+#define EIC_INTENCLR_EXTINT15       (1 << EIC_INTENCLR_EXTINT15_Pos)
+#define EIC_INTENCLR_EXTINT_Pos     0            /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
+#define EIC_INTENCLR_EXTINT_Msk     (_U(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value)  (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
+#define EIC_INTENCLR_MASK           _U(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 Enable        */
+    uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1 Enable        */
+    uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2 Enable        */
+    uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3 Enable        */
+    uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4 Enable        */
+    uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5 Enable        */
+    uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6 Enable        */
+    uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7 Enable        */
+    uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8 Enable        */
+    uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9 Enable        */
+    uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10 Enable       */
+    uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11 Enable       */
+    uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12 Enable       */
+    uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13 Enable       */
+    uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14 Enable       */
+    uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15 Enable       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x Enable        */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET         0x0C         /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE     _U(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT0_Pos    0            /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
+#define EIC_INTENSET_EXTINT0        (1 << EIC_INTENSET_EXTINT0_Pos)
+#define EIC_INTENSET_EXTINT1_Pos    1            /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
+#define EIC_INTENSET_EXTINT1        (1 << EIC_INTENSET_EXTINT1_Pos)
+#define EIC_INTENSET_EXTINT2_Pos    2            /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
+#define EIC_INTENSET_EXTINT2        (1 << EIC_INTENSET_EXTINT2_Pos)
+#define EIC_INTENSET_EXTINT3_Pos    3            /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
+#define EIC_INTENSET_EXTINT3        (1 << EIC_INTENSET_EXTINT3_Pos)
+#define EIC_INTENSET_EXTINT4_Pos    4            /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
+#define EIC_INTENSET_EXTINT4        (1 << EIC_INTENSET_EXTINT4_Pos)
+#define EIC_INTENSET_EXTINT5_Pos    5            /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
+#define EIC_INTENSET_EXTINT5        (1 << EIC_INTENSET_EXTINT5_Pos)
+#define EIC_INTENSET_EXTINT6_Pos    6            /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
+#define EIC_INTENSET_EXTINT6        (1 << EIC_INTENSET_EXTINT6_Pos)
+#define EIC_INTENSET_EXTINT7_Pos    7            /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
+#define EIC_INTENSET_EXTINT7        (1 << EIC_INTENSET_EXTINT7_Pos)
+#define EIC_INTENSET_EXTINT8_Pos    8            /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
+#define EIC_INTENSET_EXTINT8        (1 << EIC_INTENSET_EXTINT8_Pos)
+#define EIC_INTENSET_EXTINT9_Pos    9            /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
+#define EIC_INTENSET_EXTINT9        (1 << EIC_INTENSET_EXTINT9_Pos)
+#define EIC_INTENSET_EXTINT10_Pos   10           /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
+#define EIC_INTENSET_EXTINT10       (1 << EIC_INTENSET_EXTINT10_Pos)
+#define EIC_INTENSET_EXTINT11_Pos   11           /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
+#define EIC_INTENSET_EXTINT11       (1 << EIC_INTENSET_EXTINT11_Pos)
+#define EIC_INTENSET_EXTINT12_Pos   12           /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
+#define EIC_INTENSET_EXTINT12       (1 << EIC_INTENSET_EXTINT12_Pos)
+#define EIC_INTENSET_EXTINT13_Pos   13           /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
+#define EIC_INTENSET_EXTINT13       (1 << EIC_INTENSET_EXTINT13_Pos)
+#define EIC_INTENSET_EXTINT14_Pos   14           /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
+#define EIC_INTENSET_EXTINT14       (1 << EIC_INTENSET_EXTINT14_Pos)
+#define EIC_INTENSET_EXTINT15_Pos   15           /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
+#define EIC_INTENSET_EXTINT15       (1 << EIC_INTENSET_EXTINT15_Pos)
+#define EIC_INTENSET_EXTINT_Pos     0            /**< \brief (EIC_INTENSET) External Interrupt x Enable */
+#define EIC_INTENSET_EXTINT_Msk     (_U(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value)  (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
+#define EIC_INTENSET_MASK           _U(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0               */
+    __I uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1               */
+    __I uint32_t EXTINT2:1;        /*!< bit:      2  External Interrupt 2               */
+    __I uint32_t EXTINT3:1;        /*!< bit:      3  External Interrupt 3               */
+    __I uint32_t EXTINT4:1;        /*!< bit:      4  External Interrupt 4               */
+    __I uint32_t EXTINT5:1;        /*!< bit:      5  External Interrupt 5               */
+    __I uint32_t EXTINT6:1;        /*!< bit:      6  External Interrupt 6               */
+    __I uint32_t EXTINT7:1;        /*!< bit:      7  External Interrupt 7               */
+    __I uint32_t EXTINT8:1;        /*!< bit:      8  External Interrupt 8               */
+    __I uint32_t EXTINT9:1;        /*!< bit:      9  External Interrupt 9               */
+    __I uint32_t EXTINT10:1;       /*!< bit:     10  External Interrupt 10              */
+    __I uint32_t EXTINT11:1;       /*!< bit:     11  External Interrupt 11              */
+    __I uint32_t EXTINT12:1;       /*!< bit:     12  External Interrupt 12              */
+    __I uint32_t EXTINT13:1;       /*!< bit:     13  External Interrupt 13              */
+    __I uint32_t EXTINT14:1;       /*!< bit:     14  External Interrupt 14              */
+    __I uint32_t EXTINT15:1;       /*!< bit:     15  External Interrupt 15              */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt x               */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET          0x10         /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE      _U(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT0_Pos     0            /**< \brief (EIC_INTFLAG) External Interrupt 0 */
+#define EIC_INTFLAG_EXTINT0         (1 << EIC_INTFLAG_EXTINT0_Pos)
+#define EIC_INTFLAG_EXTINT1_Pos     1            /**< \brief (EIC_INTFLAG) External Interrupt 1 */
+#define EIC_INTFLAG_EXTINT1         (1 << EIC_INTFLAG_EXTINT1_Pos)
+#define EIC_INTFLAG_EXTINT2_Pos     2            /**< \brief (EIC_INTFLAG) External Interrupt 2 */
+#define EIC_INTFLAG_EXTINT2         (1 << EIC_INTFLAG_EXTINT2_Pos)
+#define EIC_INTFLAG_EXTINT3_Pos     3            /**< \brief (EIC_INTFLAG) External Interrupt 3 */
+#define EIC_INTFLAG_EXTINT3         (1 << EIC_INTFLAG_EXTINT3_Pos)
+#define EIC_INTFLAG_EXTINT4_Pos     4            /**< \brief (EIC_INTFLAG) External Interrupt 4 */
+#define EIC_INTFLAG_EXTINT4         (1 << EIC_INTFLAG_EXTINT4_Pos)
+#define EIC_INTFLAG_EXTINT5_Pos     5            /**< \brief (EIC_INTFLAG) External Interrupt 5 */
+#define EIC_INTFLAG_EXTINT5         (1 << EIC_INTFLAG_EXTINT5_Pos)
+#define EIC_INTFLAG_EXTINT6_Pos     6            /**< \brief (EIC_INTFLAG) External Interrupt 6 */
+#define EIC_INTFLAG_EXTINT6         (1 << EIC_INTFLAG_EXTINT6_Pos)
+#define EIC_INTFLAG_EXTINT7_Pos     7            /**< \brief (EIC_INTFLAG) External Interrupt 7 */
+#define EIC_INTFLAG_EXTINT7         (1 << EIC_INTFLAG_EXTINT7_Pos)
+#define EIC_INTFLAG_EXTINT8_Pos     8            /**< \brief (EIC_INTFLAG) External Interrupt 8 */
+#define EIC_INTFLAG_EXTINT8         (1 << EIC_INTFLAG_EXTINT8_Pos)
+#define EIC_INTFLAG_EXTINT9_Pos     9            /**< \brief (EIC_INTFLAG) External Interrupt 9 */
+#define EIC_INTFLAG_EXTINT9         (1 << EIC_INTFLAG_EXTINT9_Pos)
+#define EIC_INTFLAG_EXTINT10_Pos    10           /**< \brief (EIC_INTFLAG) External Interrupt 10 */
+#define EIC_INTFLAG_EXTINT10        (1 << EIC_INTFLAG_EXTINT10_Pos)
+#define EIC_INTFLAG_EXTINT11_Pos    11           /**< \brief (EIC_INTFLAG) External Interrupt 11 */
+#define EIC_INTFLAG_EXTINT11        (1 << EIC_INTFLAG_EXTINT11_Pos)
+#define EIC_INTFLAG_EXTINT12_Pos    12           /**< \brief (EIC_INTFLAG) External Interrupt 12 */
+#define EIC_INTFLAG_EXTINT12        (1 << EIC_INTFLAG_EXTINT12_Pos)
+#define EIC_INTFLAG_EXTINT13_Pos    13           /**< \brief (EIC_INTFLAG) External Interrupt 13 */
+#define EIC_INTFLAG_EXTINT13        (1 << EIC_INTFLAG_EXTINT13_Pos)
+#define EIC_INTFLAG_EXTINT14_Pos    14           /**< \brief (EIC_INTFLAG) External Interrupt 14 */
+#define EIC_INTFLAG_EXTINT14        (1 << EIC_INTFLAG_EXTINT14_Pos)
+#define EIC_INTFLAG_EXTINT15_Pos    15           /**< \brief (EIC_INTFLAG) External Interrupt 15 */
+#define EIC_INTFLAG_EXTINT15        (1 << EIC_INTFLAG_EXTINT15_Pos)
+#define EIC_INTFLAG_EXTINT_Pos      0            /**< \brief (EIC_INTFLAG) External Interrupt x */
+#define EIC_INTFLAG_EXTINT_Msk      (_U(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value)   (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
+#define EIC_INTFLAG_MASK            _U(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAKEUPEN0:1;      /*!< bit:      0  External Interrupt 0 Wake-up Enable */
+    uint32_t WAKEUPEN1:1;      /*!< bit:      1  External Interrupt 1 Wake-up Enable */
+    uint32_t WAKEUPEN2:1;      /*!< bit:      2  External Interrupt 2 Wake-up Enable */
+    uint32_t WAKEUPEN3:1;      /*!< bit:      3  External Interrupt 3 Wake-up Enable */
+    uint32_t WAKEUPEN4:1;      /*!< bit:      4  External Interrupt 4 Wake-up Enable */
+    uint32_t WAKEUPEN5:1;      /*!< bit:      5  External Interrupt 5 Wake-up Enable */
+    uint32_t WAKEUPEN6:1;      /*!< bit:      6  External Interrupt 6 Wake-up Enable */
+    uint32_t WAKEUPEN7:1;      /*!< bit:      7  External Interrupt 7 Wake-up Enable */
+    uint32_t WAKEUPEN8:1;      /*!< bit:      8  External Interrupt 8 Wake-up Enable */
+    uint32_t WAKEUPEN9:1;      /*!< bit:      9  External Interrupt 9 Wake-up Enable */
+    uint32_t WAKEUPEN10:1;     /*!< bit:     10  External Interrupt 10 Wake-up Enable */
+    uint32_t WAKEUPEN11:1;     /*!< bit:     11  External Interrupt 11 Wake-up Enable */
+    uint32_t WAKEUPEN12:1;     /*!< bit:     12  External Interrupt 12 Wake-up Enable */
+    uint32_t WAKEUPEN13:1;     /*!< bit:     13  External Interrupt 13 Wake-up Enable */
+    uint32_t WAKEUPEN14:1;     /*!< bit:     14  External Interrupt 14 Wake-up Enable */
+    uint32_t WAKEUPEN15:1;     /*!< bit:     15  External Interrupt 15 Wake-up Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t WAKEUPEN:16;      /*!< bit:  0..15  External Interrupt x Wake-up Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_WAKEUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_WAKEUP_OFFSET           0x14         /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
+#define EIC_WAKEUP_RESETVALUE       _U(0x00000000) /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
+
+#define EIC_WAKEUP_WAKEUPEN0_Pos    0            /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN0        (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
+#define EIC_WAKEUP_WAKEUPEN1_Pos    1            /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN1        (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
+#define EIC_WAKEUP_WAKEUPEN2_Pos    2            /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN2        (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
+#define EIC_WAKEUP_WAKEUPEN3_Pos    3            /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN3        (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
+#define EIC_WAKEUP_WAKEUPEN4_Pos    4            /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN4        (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
+#define EIC_WAKEUP_WAKEUPEN5_Pos    5            /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN5        (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
+#define EIC_WAKEUP_WAKEUPEN6_Pos    6            /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN6        (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
+#define EIC_WAKEUP_WAKEUPEN7_Pos    7            /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN7        (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
+#define EIC_WAKEUP_WAKEUPEN8_Pos    8            /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN8        (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
+#define EIC_WAKEUP_WAKEUPEN9_Pos    9            /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN9        (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
+#define EIC_WAKEUP_WAKEUPEN10_Pos   10           /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN10       (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
+#define EIC_WAKEUP_WAKEUPEN11_Pos   11           /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN11       (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
+#define EIC_WAKEUP_WAKEUPEN12_Pos   12           /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN12       (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
+#define EIC_WAKEUP_WAKEUPEN13_Pos   13           /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN13       (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
+#define EIC_WAKEUP_WAKEUPEN14_Pos   14           /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN14       (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
+#define EIC_WAKEUP_WAKEUPEN15_Pos   15           /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN15       (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
+#define EIC_WAKEUP_WAKEUPEN_Pos     0            /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN_Msk     (_U(0xFFFF) << EIC_WAKEUP_WAKEUPEN_Pos)
+#define EIC_WAKEUP_WAKEUPEN(value)  (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
+#define EIC_WAKEUP_MASK             _U(0x0000FFFF) /**< \brief (EIC_WAKEUP) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SENSE0:3;         /*!< bit:  0.. 2  Input Sense 0 Configuration        */
+    uint32_t FILTEN0:1;        /*!< bit:      3  Filter 0 Enable                    */
+    uint32_t SENSE1:3;         /*!< bit:  4.. 6  Input Sense 1 Configuration        */
+    uint32_t FILTEN1:1;        /*!< bit:      7  Filter 1 Enable                    */
+    uint32_t SENSE2:3;         /*!< bit:  8..10  Input Sense 2 Configuration        */
+    uint32_t FILTEN2:1;        /*!< bit:     11  Filter 2 Enable                    */
+    uint32_t SENSE3:3;         /*!< bit: 12..14  Input Sense 3 Configuration        */
+    uint32_t FILTEN3:1;        /*!< bit:     15  Filter 3 Enable                    */
+    uint32_t SENSE4:3;         /*!< bit: 16..18  Input Sense 4 Configuration        */
+    uint32_t FILTEN4:1;        /*!< bit:     19  Filter 4 Enable                    */
+    uint32_t SENSE5:3;         /*!< bit: 20..22  Input Sense 5 Configuration        */
+    uint32_t FILTEN5:1;        /*!< bit:     23  Filter 5 Enable                    */
+    uint32_t SENSE6:3;         /*!< bit: 24..26  Input Sense 6 Configuration        */
+    uint32_t FILTEN6:1;        /*!< bit:     27  Filter 6 Enable                    */
+    uint32_t SENSE7:3;         /*!< bit: 28..30  Input Sense 7 Configuration        */
+    uint32_t FILTEN7:1;        /*!< bit:     31  Filter 7 Enable                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET           0x18         /**< \brief (EIC_CONFIG offset) Configuration n */
+#define EIC_CONFIG_RESETVALUE       _U(0x00000000) /**< \brief (EIC_CONFIG reset_value) Configuration n */
+
+#define EIC_CONFIG_SENSE0_Pos       0            /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
+#define EIC_CONFIG_SENSE0_Msk       (_U(0x7) << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value)    (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
+#define   EIC_CONFIG_SENSE0_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE0_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising-edge detection */
+#define   EIC_CONFIG_SENSE0_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling-edge detection */
+#define   EIC_CONFIG_SENSE0_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both-edges detection */
+#define   EIC_CONFIG_SENSE0_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High-level detection */
+#define   EIC_CONFIG_SENSE0_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low-level detection */
+#define EIC_CONFIG_SENSE0_NONE      (EIC_CONFIG_SENSE0_NONE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE      (EIC_CONFIG_SENSE0_RISE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL      (EIC_CONFIG_SENSE0_FALL_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH      (EIC_CONFIG_SENSE0_BOTH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH      (EIC_CONFIG_SENSE0_HIGH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW       (EIC_CONFIG_SENSE0_LOW_Val     << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos      3            /**< \brief (EIC_CONFIG) Filter 0 Enable */
+#define EIC_CONFIG_FILTEN0          (_U(0x1) << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos       4            /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
+#define EIC_CONFIG_SENSE1_Msk       (_U(0x7) << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value)    (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
+#define   EIC_CONFIG_SENSE1_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE1_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE1_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE1_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE1_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE1_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE      (EIC_CONFIG_SENSE1_NONE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE      (EIC_CONFIG_SENSE1_RISE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL      (EIC_CONFIG_SENSE1_FALL_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH      (EIC_CONFIG_SENSE1_BOTH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH      (EIC_CONFIG_SENSE1_HIGH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW       (EIC_CONFIG_SENSE1_LOW_Val     << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos      7            /**< \brief (EIC_CONFIG) Filter 1 Enable */
+#define EIC_CONFIG_FILTEN1          (_U(0x1) << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos       8            /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
+#define EIC_CONFIG_SENSE2_Msk       (_U(0x7) << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value)    (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
+#define   EIC_CONFIG_SENSE2_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE2_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE2_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE2_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE2_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE2_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE      (EIC_CONFIG_SENSE2_NONE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE      (EIC_CONFIG_SENSE2_RISE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL      (EIC_CONFIG_SENSE2_FALL_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH      (EIC_CONFIG_SENSE2_BOTH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH      (EIC_CONFIG_SENSE2_HIGH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW       (EIC_CONFIG_SENSE2_LOW_Val     << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos      11           /**< \brief (EIC_CONFIG) Filter 2 Enable */
+#define EIC_CONFIG_FILTEN2          (_U(0x1) << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos       12           /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
+#define EIC_CONFIG_SENSE3_Msk       (_U(0x7) << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value)    (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
+#define   EIC_CONFIG_SENSE3_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE3_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE3_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE3_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE3_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE3_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE      (EIC_CONFIG_SENSE3_NONE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE      (EIC_CONFIG_SENSE3_RISE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL      (EIC_CONFIG_SENSE3_FALL_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH      (EIC_CONFIG_SENSE3_BOTH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH      (EIC_CONFIG_SENSE3_HIGH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW       (EIC_CONFIG_SENSE3_LOW_Val     << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos      15           /**< \brief (EIC_CONFIG) Filter 3 Enable */
+#define EIC_CONFIG_FILTEN3          (_U(0x1) << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos       16           /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
+#define EIC_CONFIG_SENSE4_Msk       (_U(0x7) << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value)    (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
+#define   EIC_CONFIG_SENSE4_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE4_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE4_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE4_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE4_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE4_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE      (EIC_CONFIG_SENSE4_NONE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE      (EIC_CONFIG_SENSE4_RISE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL      (EIC_CONFIG_SENSE4_FALL_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH      (EIC_CONFIG_SENSE4_BOTH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH      (EIC_CONFIG_SENSE4_HIGH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW       (EIC_CONFIG_SENSE4_LOW_Val     << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos      19           /**< \brief (EIC_CONFIG) Filter 4 Enable */
+#define EIC_CONFIG_FILTEN4          (_U(0x1) << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos       20           /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
+#define EIC_CONFIG_SENSE5_Msk       (_U(0x7) << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value)    (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
+#define   EIC_CONFIG_SENSE5_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE5_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE5_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE5_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE5_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE5_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE      (EIC_CONFIG_SENSE5_NONE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE      (EIC_CONFIG_SENSE5_RISE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL      (EIC_CONFIG_SENSE5_FALL_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH      (EIC_CONFIG_SENSE5_BOTH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH      (EIC_CONFIG_SENSE5_HIGH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW       (EIC_CONFIG_SENSE5_LOW_Val     << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos      23           /**< \brief (EIC_CONFIG) Filter 5 Enable */
+#define EIC_CONFIG_FILTEN5          (_U(0x1) << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos       24           /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
+#define EIC_CONFIG_SENSE6_Msk       (_U(0x7) << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value)    (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
+#define   EIC_CONFIG_SENSE6_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE6_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE6_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE6_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE6_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE6_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE      (EIC_CONFIG_SENSE6_NONE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE      (EIC_CONFIG_SENSE6_RISE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL      (EIC_CONFIG_SENSE6_FALL_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH      (EIC_CONFIG_SENSE6_BOTH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH      (EIC_CONFIG_SENSE6_HIGH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW       (EIC_CONFIG_SENSE6_LOW_Val     << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos      27           /**< \brief (EIC_CONFIG) Filter 6 Enable */
+#define EIC_CONFIG_FILTEN6          (_U(0x1) << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos       28           /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
+#define EIC_CONFIG_SENSE7_Msk       (_U(0x7) << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value)    (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
+#define   EIC_CONFIG_SENSE7_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE7_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE7_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE7_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE7_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE7_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE      (EIC_CONFIG_SENSE7_NONE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE      (EIC_CONFIG_SENSE7_RISE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL      (EIC_CONFIG_SENSE7_FALL_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH      (EIC_CONFIG_SENSE7_BOTH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH      (EIC_CONFIG_SENSE7_HIGH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW       (EIC_CONFIG_SENSE7_LOW_Val     << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos      31           /**< \brief (EIC_CONFIG) Filter 7 Enable */
+#define EIC_CONFIG_FILTEN7          (_U(0x1) << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK             _U(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO EIC_CTRL_Type             CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
+  __I  EIC_STATUS_Type           STATUS;      /**< \brief Offset: 0x01 (R/   8) Status */
+  __IO EIC_NMICTRL_Type          NMICTRL;     /**< \brief Offset: 0x02 (R/W  8) Non-Maskable Interrupt Control */
+  __IO EIC_NMIFLAG_Type          NMIFLAG;     /**< \brief Offset: 0x03 (R/W  8) Non-Maskable Interrupt Flag Status and Clear */
+  __IO EIC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) Event Control */
+  __IO EIC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+  __IO EIC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+  __IO EIC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+  __IO EIC_WAKEUP_Type           WAKEUP;      /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+  __IO EIC_CONFIG_Type           CONFIG[2];   /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EIC_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/evsys.h b/uf2-samdx1/lib/samd21/samd21a/include/component/evsys.h
new file mode 100644
index 00000000..7fff962f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/evsys.h
@@ -0,0 +1,589 @@
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_COMPONENT_
+#define _SAMD21_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2208
+#define REV_EVSYS                   0x101
+
+/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :3;               /*!< bit:  1.. 3  Reserved                           */
+    uint8_t  GCLKREQ:1;        /*!< bit:      4  Generic Clock Requests             */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRL_OFFSET           0x00         /**< \brief (EVSYS_CTRL offset) Control */
+#define EVSYS_CTRL_RESETVALUE       _U(0x00)     /**< \brief (EVSYS_CTRL reset_value) Control */
+
+#define EVSYS_CTRL_SWRST_Pos        0            /**< \brief (EVSYS_CTRL) Software Reset */
+#define EVSYS_CTRL_SWRST            (_U(0x1) << EVSYS_CTRL_SWRST_Pos)
+#define EVSYS_CTRL_GCLKREQ_Pos      4            /**< \brief (EVSYS_CTRL) Generic Clock Requests */
+#define EVSYS_CTRL_GCLKREQ          (_U(0x1) << EVSYS_CTRL_GCLKREQ_Pos)
+#define EVSYS_CTRL_MASK             _U(0x11)     /**< \brief (EVSYS_CTRL) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHANNEL:4;        /*!< bit:  0.. 3  Channel Selection                  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t SWEVT:1;          /*!< bit:      8  Software Event                     */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t EVGEN:7;          /*!< bit: 16..22  Event Generator Selection          */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PATH:2;           /*!< bit: 24..25  Path Selection                     */
+    uint32_t EDGSEL:2;         /*!< bit: 26..27  Edge Detection Selection           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET        0x04         /**< \brief (EVSYS_CHANNEL offset) Channel */
+#define EVSYS_CHANNEL_RESETVALUE    _U(0x00000000) /**< \brief (EVSYS_CHANNEL reset_value) Channel */
+
+#define EVSYS_CHANNEL_CHANNEL_Pos   0            /**< \brief (EVSYS_CHANNEL) Channel Selection */
+#define EVSYS_CHANNEL_CHANNEL_Msk   (_U(0xF) << EVSYS_CHANNEL_CHANNEL_Pos)
+#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
+#define EVSYS_CHANNEL_SWEVT_Pos     8            /**< \brief (EVSYS_CHANNEL) Software Event */
+#define EVSYS_CHANNEL_SWEVT         (_U(0x1) << EVSYS_CHANNEL_SWEVT_Pos)
+#define EVSYS_CHANNEL_EVGEN_Pos     16           /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk     (_U(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
+#define EVSYS_CHANNEL_PATH_Pos      24           /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk      (_U(0x3) << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
+#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U(0x0)   /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U(0x1)   /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U(0x2)   /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos    26           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk    (_U(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
+#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U(0x0)   /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U(0x1)   /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U(0x2)   /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U(0x3)   /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_MASK          _U(0x0F7F010F) /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t USER:5;           /*!< bit:  0.. 4  User Multiplexer Selection         */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t CHANNEL:5;        /*!< bit:  8..12  Channel Event Selection            */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET           0x08         /**< \brief (EVSYS_USER offset) User Multiplexer */
+#define EVSYS_USER_RESETVALUE       _U(0x0000)   /**< \brief (EVSYS_USER reset_value) User Multiplexer */
+
+#define EVSYS_USER_USER_Pos         0            /**< \brief (EVSYS_USER) User Multiplexer Selection */
+#define EVSYS_USER_USER_Msk         (_U(0x1F) << EVSYS_USER_USER_Pos)
+#define EVSYS_USER_USER(value)      (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
+#define EVSYS_USER_CHANNEL_Pos      8            /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk      (_U(0x1F) << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
+#define   EVSYS_USER_CHANNEL_0_Val        _U(0x0)   /**< \brief (EVSYS_USER) No Channel Output Selected */
+#define EVSYS_USER_CHANNEL_0        (EVSYS_USER_CHANNEL_0_Val      << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_MASK             _U(0x1F1F)   /**< \brief (EVSYS_USER) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USRRDY0:1;        /*!< bit:      0  Channel 0 User Ready               */
+    uint32_t USRRDY1:1;        /*!< bit:      1  Channel 1 User Ready               */
+    uint32_t USRRDY2:1;        /*!< bit:      2  Channel 2 User Ready               */
+    uint32_t USRRDY3:1;        /*!< bit:      3  Channel 3 User Ready               */
+    uint32_t USRRDY4:1;        /*!< bit:      4  Channel 4 User Ready               */
+    uint32_t USRRDY5:1;        /*!< bit:      5  Channel 5 User Ready               */
+    uint32_t USRRDY6:1;        /*!< bit:      6  Channel 6 User Ready               */
+    uint32_t USRRDY7:1;        /*!< bit:      7  Channel 7 User Ready               */
+    uint32_t CHBUSY0:1;        /*!< bit:      8  Channel 0 Busy                     */
+    uint32_t CHBUSY1:1;        /*!< bit:      9  Channel 1 Busy                     */
+    uint32_t CHBUSY2:1;        /*!< bit:     10  Channel 2 Busy                     */
+    uint32_t CHBUSY3:1;        /*!< bit:     11  Channel 3 Busy                     */
+    uint32_t CHBUSY4:1;        /*!< bit:     12  Channel 4 Busy                     */
+    uint32_t CHBUSY5:1;        /*!< bit:     13  Channel 5 Busy                     */
+    uint32_t CHBUSY6:1;        /*!< bit:     14  Channel 6 Busy                     */
+    uint32_t CHBUSY7:1;        /*!< bit:     15  Channel 7 Busy                     */
+    uint32_t USRRDY8:1;        /*!< bit:     16  Channel 8 User Ready               */
+    uint32_t USRRDY9:1;        /*!< bit:     17  Channel 9 User Ready               */
+    uint32_t USRRDY10:1;       /*!< bit:     18  Channel 10 User Ready              */
+    uint32_t USRRDY11:1;       /*!< bit:     19  Channel 11 User Ready              */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CHBUSY8:1;        /*!< bit:     24  Channel 8 Busy                     */
+    uint32_t CHBUSY9:1;        /*!< bit:     25  Channel 9 Busy                     */
+    uint32_t CHBUSY10:1;       /*!< bit:     26  Channel 10 Busy                    */
+    uint32_t CHBUSY11:1;       /*!< bit:     27  Channel 11 Busy                    */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t USRRDY:8;         /*!< bit:  0.. 7  Channel x User Ready               */
+    uint32_t CHBUSY:8;         /*!< bit:  8..15  Channel x Busy                     */
+    uint32_t USRRDYp8:4;       /*!< bit: 16..19  Channel x+8 User Ready             */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CHBUSYp8:4;       /*!< bit: 24..27  Channel x+8 Busy                   */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE   _U(0x000F00FF) /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+
+#define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
+#define EVSYS_CHSTATUS_USRRDY0      (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
+#define EVSYS_CHSTATUS_USRRDY1_Pos  1            /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
+#define EVSYS_CHSTATUS_USRRDY1      (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
+#define EVSYS_CHSTATUS_USRRDY2_Pos  2            /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
+#define EVSYS_CHSTATUS_USRRDY2      (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
+#define EVSYS_CHSTATUS_USRRDY3_Pos  3            /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
+#define EVSYS_CHSTATUS_USRRDY3      (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
+#define EVSYS_CHSTATUS_USRRDY4_Pos  4            /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
+#define EVSYS_CHSTATUS_USRRDY4      (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
+#define EVSYS_CHSTATUS_USRRDY5_Pos  5            /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
+#define EVSYS_CHSTATUS_USRRDY5      (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
+#define EVSYS_CHSTATUS_USRRDY6_Pos  6            /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
+#define EVSYS_CHSTATUS_USRRDY6      (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
+#define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
+#define EVSYS_CHSTATUS_USRRDY7      (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
+#define EVSYS_CHSTATUS_USRRDY_Msk   (_U(0xFF) << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
+#define EVSYS_CHSTATUS_CHBUSY0_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
+#define EVSYS_CHSTATUS_CHBUSY0      (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
+#define EVSYS_CHSTATUS_CHBUSY1_Pos  9            /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
+#define EVSYS_CHSTATUS_CHBUSY1      (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
+#define EVSYS_CHSTATUS_CHBUSY2_Pos  10           /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
+#define EVSYS_CHSTATUS_CHBUSY2      (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
+#define EVSYS_CHSTATUS_CHBUSY3_Pos  11           /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
+#define EVSYS_CHSTATUS_CHBUSY3      (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
+#define EVSYS_CHSTATUS_CHBUSY4_Pos  12           /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
+#define EVSYS_CHSTATUS_CHBUSY4      (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
+#define EVSYS_CHSTATUS_CHBUSY5_Pos  13           /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
+#define EVSYS_CHSTATUS_CHBUSY5      (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
+#define EVSYS_CHSTATUS_CHBUSY6_Pos  14           /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
+#define EVSYS_CHSTATUS_CHBUSY6      (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
+#define EVSYS_CHSTATUS_CHBUSY7_Pos  15           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
+#define EVSYS_CHSTATUS_CHBUSY7      (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Pos   8            /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
+#define EVSYS_CHSTATUS_CHBUSY_Msk   (_U(0xFF) << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
+#define EVSYS_CHSTATUS_USRRDY8_Pos  16           /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
+#define EVSYS_CHSTATUS_USRRDY8      (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
+#define EVSYS_CHSTATUS_USRRDY9_Pos  17           /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
+#define EVSYS_CHSTATUS_USRRDY9      (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
+#define EVSYS_CHSTATUS_USRRDY10_Pos 18           /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
+#define EVSYS_CHSTATUS_USRRDY10     (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
+#define EVSYS_CHSTATUS_USRRDY11_Pos 19           /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
+#define EVSYS_CHSTATUS_USRRDY11     (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8_Pos 16           /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
+#define EVSYS_CHSTATUS_USRRDYp8_Msk (_U(0xF) << EVSYS_CHSTATUS_USRRDYp8_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
+#define EVSYS_CHSTATUS_CHBUSY8_Pos  24           /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
+#define EVSYS_CHSTATUS_CHBUSY8      (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
+#define EVSYS_CHSTATUS_CHBUSY9_Pos  25           /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
+#define EVSYS_CHSTATUS_CHBUSY9      (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
+#define EVSYS_CHSTATUS_CHBUSY10_Pos 26           /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
+#define EVSYS_CHSTATUS_CHBUSY10     (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
+#define EVSYS_CHSTATUS_CHBUSY11_Pos 27           /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
+#define EVSYS_CHSTATUS_CHBUSY11     (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24           /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
+#define EVSYS_CHSTATUS_CHBUSYp8_Msk (_U(0xF) << EVSYS_CHSTATUS_CHBUSYp8_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
+#define EVSYS_CHSTATUS_MASK         _U(0x0F0FFFFF) /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE   _U(0x00000000) /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR0         (1 << EVSYS_INTENCLR_OVR0_Pos)
+#define EVSYS_INTENCLR_OVR1_Pos     1            /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR1         (1 << EVSYS_INTENCLR_OVR1_Pos)
+#define EVSYS_INTENCLR_OVR2_Pos     2            /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR2         (1 << EVSYS_INTENCLR_OVR2_Pos)
+#define EVSYS_INTENCLR_OVR3_Pos     3            /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR3         (1 << EVSYS_INTENCLR_OVR3_Pos)
+#define EVSYS_INTENCLR_OVR4_Pos     4            /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR4         (1 << EVSYS_INTENCLR_OVR4_Pos)
+#define EVSYS_INTENCLR_OVR5_Pos     5            /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR5         (1 << EVSYS_INTENCLR_OVR5_Pos)
+#define EVSYS_INTENCLR_OVR6_Pos     6            /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR6         (1 << EVSYS_INTENCLR_OVR6_Pos)
+#define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR7         (1 << EVSYS_INTENCLR_OVR7_Pos)
+#define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR_Msk      (_U(0xFF) << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR(value)   (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
+#define EVSYS_INTENCLR_EVD0_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD0         (1 << EVSYS_INTENCLR_EVD0_Pos)
+#define EVSYS_INTENCLR_EVD1_Pos     9            /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD1         (1 << EVSYS_INTENCLR_EVD1_Pos)
+#define EVSYS_INTENCLR_EVD2_Pos     10           /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD2         (1 << EVSYS_INTENCLR_EVD2_Pos)
+#define EVSYS_INTENCLR_EVD3_Pos     11           /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD3         (1 << EVSYS_INTENCLR_EVD3_Pos)
+#define EVSYS_INTENCLR_EVD4_Pos     12           /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD4         (1 << EVSYS_INTENCLR_EVD4_Pos)
+#define EVSYS_INTENCLR_EVD5_Pos     13           /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD5         (1 << EVSYS_INTENCLR_EVD5_Pos)
+#define EVSYS_INTENCLR_EVD6_Pos     14           /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD6         (1 << EVSYS_INTENCLR_EVD6_Pos)
+#define EVSYS_INTENCLR_EVD7_Pos     15           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD7         (1 << EVSYS_INTENCLR_EVD7_Pos)
+#define EVSYS_INTENCLR_EVD_Pos      8            /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD_Msk      (_U(0xFF) << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD(value)   (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
+#define EVSYS_INTENCLR_OVR8_Pos     16           /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR8         (1 << EVSYS_INTENCLR_OVR8_Pos)
+#define EVSYS_INTENCLR_OVR9_Pos     17           /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR9         (1 << EVSYS_INTENCLR_OVR9_Pos)
+#define EVSYS_INTENCLR_OVR10_Pos    18           /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR10        (1 << EVSYS_INTENCLR_OVR10_Pos)
+#define EVSYS_INTENCLR_OVR11_Pos    19           /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR11        (1 << EVSYS_INTENCLR_OVR11_Pos)
+#define EVSYS_INTENCLR_OVRp8_Pos    16           /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVRp8_Msk    (_U(0xF) << EVSYS_INTENCLR_OVRp8_Pos)
+#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
+#define EVSYS_INTENCLR_EVD8_Pos     24           /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD8         (1 << EVSYS_INTENCLR_EVD8_Pos)
+#define EVSYS_INTENCLR_EVD9_Pos     25           /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD9         (1 << EVSYS_INTENCLR_EVD9_Pos)
+#define EVSYS_INTENCLR_EVD10_Pos    26           /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD10        (1 << EVSYS_INTENCLR_EVD10_Pos)
+#define EVSYS_INTENCLR_EVD11_Pos    27           /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD11        (1 << EVSYS_INTENCLR_EVD11_Pos)
+#define EVSYS_INTENCLR_EVDp8_Pos    24           /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVDp8_Msk    (_U(0xF) << EVSYS_INTENCLR_EVDp8_Pos)
+#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
+#define EVSYS_INTENCLR_MASK         _U(0x0F0FFFFF) /**< \brief (EVSYS_INTENCLR) MASK Register */
+
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun Interrupt Enable */
+    uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection Interrupt Enable */
+    uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE   _U(0x00000000) /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+
+#define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR0         (1 << EVSYS_INTENSET_OVR0_Pos)
+#define EVSYS_INTENSET_OVR1_Pos     1            /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR1         (1 << EVSYS_INTENSET_OVR1_Pos)
+#define EVSYS_INTENSET_OVR2_Pos     2            /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR2         (1 << EVSYS_INTENSET_OVR2_Pos)
+#define EVSYS_INTENSET_OVR3_Pos     3            /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR3         (1 << EVSYS_INTENSET_OVR3_Pos)
+#define EVSYS_INTENSET_OVR4_Pos     4            /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR4         (1 << EVSYS_INTENSET_OVR4_Pos)
+#define EVSYS_INTENSET_OVR5_Pos     5            /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR5         (1 << EVSYS_INTENSET_OVR5_Pos)
+#define EVSYS_INTENSET_OVR6_Pos     6            /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR6         (1 << EVSYS_INTENSET_OVR6_Pos)
+#define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR7         (1 << EVSYS_INTENSET_OVR7_Pos)
+#define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR_Msk      (_U(0xFF) << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR(value)   (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
+#define EVSYS_INTENSET_EVD0_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD0         (1 << EVSYS_INTENSET_EVD0_Pos)
+#define EVSYS_INTENSET_EVD1_Pos     9            /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD1         (1 << EVSYS_INTENSET_EVD1_Pos)
+#define EVSYS_INTENSET_EVD2_Pos     10           /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD2         (1 << EVSYS_INTENSET_EVD2_Pos)
+#define EVSYS_INTENSET_EVD3_Pos     11           /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD3         (1 << EVSYS_INTENSET_EVD3_Pos)
+#define EVSYS_INTENSET_EVD4_Pos     12           /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD4         (1 << EVSYS_INTENSET_EVD4_Pos)
+#define EVSYS_INTENSET_EVD5_Pos     13           /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD5         (1 << EVSYS_INTENSET_EVD5_Pos)
+#define EVSYS_INTENSET_EVD6_Pos     14           /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD6         (1 << EVSYS_INTENSET_EVD6_Pos)
+#define EVSYS_INTENSET_EVD7_Pos     15           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD7         (1 << EVSYS_INTENSET_EVD7_Pos)
+#define EVSYS_INTENSET_EVD_Pos      8            /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD_Msk      (_U(0xFF) << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD(value)   (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
+#define EVSYS_INTENSET_OVR8_Pos     16           /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR8         (1 << EVSYS_INTENSET_OVR8_Pos)
+#define EVSYS_INTENSET_OVR9_Pos     17           /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR9         (1 << EVSYS_INTENSET_OVR9_Pos)
+#define EVSYS_INTENSET_OVR10_Pos    18           /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR10        (1 << EVSYS_INTENSET_OVR10_Pos)
+#define EVSYS_INTENSET_OVR11_Pos    19           /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR11        (1 << EVSYS_INTENSET_OVR11_Pos)
+#define EVSYS_INTENSET_OVRp8_Pos    16           /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVRp8_Msk    (_U(0xF) << EVSYS_INTENSET_OVRp8_Pos)
+#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
+#define EVSYS_INTENSET_EVD8_Pos     24           /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD8         (1 << EVSYS_INTENSET_EVD8_Pos)
+#define EVSYS_INTENSET_EVD9_Pos     25           /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD9         (1 << EVSYS_INTENSET_EVD9_Pos)
+#define EVSYS_INTENSET_EVD10_Pos    26           /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD10        (1 << EVSYS_INTENSET_EVD10_Pos)
+#define EVSYS_INTENSET_EVD11_Pos    27           /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD11        (1 << EVSYS_INTENSET_EVD11_Pos)
+#define EVSYS_INTENSET_EVDp8_Pos    24           /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVDp8_Msk    (_U(0xF) << EVSYS_INTENSET_EVDp8_Pos)
+#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
+#define EVSYS_INTENSET_MASK         _U(0x0F0FFFFF) /**< \brief (EVSYS_INTENSET) MASK Register */
+
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
+    __I uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
+    __I uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun                  */
+    __I uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun                  */
+    __I uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun                  */
+    __I uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun                  */
+    __I uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun                  */
+    __I uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun                  */
+    __I uint32_t EVD0:1;           /*!< bit:      8  Channel 0 Event Detection          */
+    __I uint32_t EVD1:1;           /*!< bit:      9  Channel 1 Event Detection          */
+    __I uint32_t EVD2:1;           /*!< bit:     10  Channel 2 Event Detection          */
+    __I uint32_t EVD3:1;           /*!< bit:     11  Channel 3 Event Detection          */
+    __I uint32_t EVD4:1;           /*!< bit:     12  Channel 4 Event Detection          */
+    __I uint32_t EVD5:1;           /*!< bit:     13  Channel 5 Event Detection          */
+    __I uint32_t EVD6:1;           /*!< bit:     14  Channel 6 Event Detection          */
+    __I uint32_t EVD7:1;           /*!< bit:     15  Channel 7 Event Detection          */
+    __I uint32_t OVR8:1;           /*!< bit:     16  Channel 8 Overrun                  */
+    __I uint32_t OVR9:1;           /*!< bit:     17  Channel 9 Overrun                  */
+    __I uint32_t OVR10:1;          /*!< bit:     18  Channel 10 Overrun                 */
+    __I uint32_t OVR11:1;          /*!< bit:     19  Channel 11 Overrun                 */
+    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    __I uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection          */
+    __I uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection          */
+    __I uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection         */
+    __I uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection         */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t OVR:8;            /*!< bit:  0.. 7  Channel x Overrun                  */
+    __I uint32_t EVD:8;            /*!< bit:  8..15  Channel x Event Detection          */
+    __I uint32_t OVRp8:4;          /*!< bit: 16..19  Channel x+8 Overrun                */
+    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    __I uint32_t EVDp8:4;          /*!< bit: 24..27  Channel x+8 Event Detection        */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE    _U(0x00000000) /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
+#define EVSYS_INTFLAG_OVR0          (1 << EVSYS_INTFLAG_OVR0_Pos)
+#define EVSYS_INTFLAG_OVR1_Pos      1            /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
+#define EVSYS_INTFLAG_OVR1          (1 << EVSYS_INTFLAG_OVR1_Pos)
+#define EVSYS_INTFLAG_OVR2_Pos      2            /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
+#define EVSYS_INTFLAG_OVR2          (1 << EVSYS_INTFLAG_OVR2_Pos)
+#define EVSYS_INTFLAG_OVR3_Pos      3            /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
+#define EVSYS_INTFLAG_OVR3          (1 << EVSYS_INTFLAG_OVR3_Pos)
+#define EVSYS_INTFLAG_OVR4_Pos      4            /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
+#define EVSYS_INTFLAG_OVR4          (1 << EVSYS_INTFLAG_OVR4_Pos)
+#define EVSYS_INTFLAG_OVR5_Pos      5            /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
+#define EVSYS_INTFLAG_OVR5          (1 << EVSYS_INTFLAG_OVR5_Pos)
+#define EVSYS_INTFLAG_OVR6_Pos      6            /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
+#define EVSYS_INTFLAG_OVR6          (1 << EVSYS_INTFLAG_OVR6_Pos)
+#define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
+#define EVSYS_INTFLAG_OVR7          (1 << EVSYS_INTFLAG_OVR7_Pos)
+#define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
+#define EVSYS_INTFLAG_OVR_Msk       (_U(0xFF) << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR(value)    (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
+#define EVSYS_INTFLAG_EVD0_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
+#define EVSYS_INTFLAG_EVD0          (1 << EVSYS_INTFLAG_EVD0_Pos)
+#define EVSYS_INTFLAG_EVD1_Pos      9            /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
+#define EVSYS_INTFLAG_EVD1          (1 << EVSYS_INTFLAG_EVD1_Pos)
+#define EVSYS_INTFLAG_EVD2_Pos      10           /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
+#define EVSYS_INTFLAG_EVD2          (1 << EVSYS_INTFLAG_EVD2_Pos)
+#define EVSYS_INTFLAG_EVD3_Pos      11           /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
+#define EVSYS_INTFLAG_EVD3          (1 << EVSYS_INTFLAG_EVD3_Pos)
+#define EVSYS_INTFLAG_EVD4_Pos      12           /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
+#define EVSYS_INTFLAG_EVD4          (1 << EVSYS_INTFLAG_EVD4_Pos)
+#define EVSYS_INTFLAG_EVD5_Pos      13           /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
+#define EVSYS_INTFLAG_EVD5          (1 << EVSYS_INTFLAG_EVD5_Pos)
+#define EVSYS_INTFLAG_EVD6_Pos      14           /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
+#define EVSYS_INTFLAG_EVD6          (1 << EVSYS_INTFLAG_EVD6_Pos)
+#define EVSYS_INTFLAG_EVD7_Pos      15           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
+#define EVSYS_INTFLAG_EVD7          (1 << EVSYS_INTFLAG_EVD7_Pos)
+#define EVSYS_INTFLAG_EVD_Pos       8            /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
+#define EVSYS_INTFLAG_EVD_Msk       (_U(0xFF) << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD(value)    (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
+#define EVSYS_INTFLAG_OVR8_Pos      16           /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
+#define EVSYS_INTFLAG_OVR8          (1 << EVSYS_INTFLAG_OVR8_Pos)
+#define EVSYS_INTFLAG_OVR9_Pos      17           /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
+#define EVSYS_INTFLAG_OVR9          (1 << EVSYS_INTFLAG_OVR9_Pos)
+#define EVSYS_INTFLAG_OVR10_Pos     18           /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
+#define EVSYS_INTFLAG_OVR10         (1 << EVSYS_INTFLAG_OVR10_Pos)
+#define EVSYS_INTFLAG_OVR11_Pos     19           /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
+#define EVSYS_INTFLAG_OVR11         (1 << EVSYS_INTFLAG_OVR11_Pos)
+#define EVSYS_INTFLAG_OVRp8_Pos     16           /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
+#define EVSYS_INTFLAG_OVRp8_Msk     (_U(0xF) << EVSYS_INTFLAG_OVRp8_Pos)
+#define EVSYS_INTFLAG_OVRp8(value)  (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
+#define EVSYS_INTFLAG_EVD8_Pos      24           /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
+#define EVSYS_INTFLAG_EVD8          (1 << EVSYS_INTFLAG_EVD8_Pos)
+#define EVSYS_INTFLAG_EVD9_Pos      25           /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
+#define EVSYS_INTFLAG_EVD9          (1 << EVSYS_INTFLAG_EVD9_Pos)
+#define EVSYS_INTFLAG_EVD10_Pos     26           /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
+#define EVSYS_INTFLAG_EVD10         (1 << EVSYS_INTFLAG_EVD10_Pos)
+#define EVSYS_INTFLAG_EVD11_Pos     27           /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
+#define EVSYS_INTFLAG_EVD11         (1 << EVSYS_INTFLAG_EVD11_Pos)
+#define EVSYS_INTFLAG_EVDp8_Pos     24           /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
+#define EVSYS_INTFLAG_EVDp8_Msk     (_U(0xF) << EVSYS_INTFLAG_EVDp8_Pos)
+#define EVSYS_INTFLAG_EVDp8(value)  (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
+#define EVSYS_INTFLAG_MASK          _U(0x0F0FFFFF) /**< \brief (EVSYS_INTFLAG) MASK Register */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  EVSYS_CTRL_Type           CTRL;        /**< \brief Offset: 0x00 ( /W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x04 (R/W 32) Channel */
+  __IO EVSYS_USER_Type           USER;        /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+       RoReg8                    Reserved2[0x2];
+  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x0C (R/  32) Channel Status */
+  __IO EVSYS_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+  __IO EVSYS_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+  __IO EVSYS_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EVSYS_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/gclk.h b/uf2-samdx1/lib/samd21/samd21a/include/component/gclk.h
new file mode 100644
index 00000000..67a351c4
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/gclk.h
@@ -0,0 +1,295 @@
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_COMPONENT_
+#define _SAMD21_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAMD21_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2102
+#define REV_GCLK                    0x210
+
+/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRL_OFFSET            0x0          /**< \brief (GCLK_CTRL offset) Control */
+#define GCLK_CTRL_RESETVALUE        _U(0x00)     /**< \brief (GCLK_CTRL reset_value) Control */
+
+#define GCLK_CTRL_SWRST_Pos         0            /**< \brief (GCLK_CTRL) Software Reset */
+#define GCLK_CTRL_SWRST             (_U(0x1) << GCLK_CTRL_SWRST_Pos)
+#define GCLK_CTRL_MASK              _U(0x01)     /**< \brief (GCLK_CTRL) MASK Register */
+
+/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy Status        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_STATUS_OFFSET          0x1          /**< \brief (GCLK_STATUS offset) Status */
+#define GCLK_STATUS_RESETVALUE      _U(0x00)     /**< \brief (GCLK_STATUS reset_value) Status */
+
+#define GCLK_STATUS_SYNCBUSY_Pos    7            /**< \brief (GCLK_STATUS) Synchronization Busy Status */
+#define GCLK_STATUS_SYNCBUSY        (_U(0x1) << GCLK_STATUS_SYNCBUSY_Pos)
+#define GCLK_STATUS_MASK            _U(0x80)     /**< \brief (GCLK_STATUS) MASK Register */
+
+/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ID:6;             /*!< bit:  0.. 5  Generic Clock Selection ID         */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t GEN:4;            /*!< bit:  8..11  Generic Clock Generator            */
+    uint16_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint16_t CLKEN:1;          /*!< bit:     14  Clock Enable                       */
+    uint16_t WRTLOCK:1;        /*!< bit:     15  Write Lock                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} GCLK_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CLKCTRL_OFFSET         0x2          /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
+#define GCLK_CLKCTRL_RESETVALUE     _U(0x0000)   /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
+
+#define GCLK_CLKCTRL_ID_Pos         0            /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
+#define GCLK_CLKCTRL_ID_Msk         (_U(0x3F) << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID(value)      (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
+#define   GCLK_CLKCTRL_ID_DFLL48_Val      _U(0x0)   /**< \brief (GCLK_CLKCTRL) DFLL48 */
+#define   GCLK_CLKCTRL_ID_FDPLL_Val       _U(0x1)   /**< \brief (GCLK_CLKCTRL) FDPLL */
+#define   GCLK_CLKCTRL_ID_FDPLL32K_Val    _U(0x2)   /**< \brief (GCLK_CLKCTRL) FDPLL32K */
+#define   GCLK_CLKCTRL_ID_WDT_Val         _U(0x3)   /**< \brief (GCLK_CLKCTRL) WDT */
+#define   GCLK_CLKCTRL_ID_RTC_Val         _U(0x4)   /**< \brief (GCLK_CLKCTRL) RTC */
+#define   GCLK_CLKCTRL_ID_EIC_Val         _U(0x5)   /**< \brief (GCLK_CLKCTRL) EIC */
+#define   GCLK_CLKCTRL_ID_USB_Val         _U(0x6)   /**< \brief (GCLK_CLKCTRL) USB */
+#define   GCLK_CLKCTRL_ID_EVSYS_0_Val     _U(0x7)   /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
+#define   GCLK_CLKCTRL_ID_EVSYS_1_Val     _U(0x8)   /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
+#define   GCLK_CLKCTRL_ID_EVSYS_2_Val     _U(0x9)   /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
+#define   GCLK_CLKCTRL_ID_EVSYS_3_Val     _U(0xA)   /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
+#define   GCLK_CLKCTRL_ID_EVSYS_4_Val     _U(0xB)   /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
+#define   GCLK_CLKCTRL_ID_EVSYS_5_Val     _U(0xC)   /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
+#define   GCLK_CLKCTRL_ID_EVSYS_6_Val     _U(0xD)   /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
+#define   GCLK_CLKCTRL_ID_EVSYS_7_Val     _U(0xE)   /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
+#define   GCLK_CLKCTRL_ID_EVSYS_8_Val     _U(0xF)   /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
+#define   GCLK_CLKCTRL_ID_EVSYS_9_Val     _U(0x10)   /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
+#define   GCLK_CLKCTRL_ID_EVSYS_10_Val    _U(0x11)   /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
+#define   GCLK_CLKCTRL_ID_EVSYS_11_Val    _U(0x12)   /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
+#define   GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val _U(0x13)   /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
+#define   GCLK_CLKCTRL_ID_SERCOM0_CORE_Val _U(0x14)   /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM1_CORE_Val _U(0x15)   /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM2_CORE_Val _U(0x16)   /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM3_CORE_Val _U(0x17)   /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM4_CORE_Val _U(0x18)   /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM5_CORE_Val _U(0x19)   /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
+#define   GCLK_CLKCTRL_ID_TCC0_TCC1_Val   _U(0x1A)   /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
+#define   GCLK_CLKCTRL_ID_TCC2_TC3_Val    _U(0x1B)   /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
+#define   GCLK_CLKCTRL_ID_TC4_TC5_Val     _U(0x1C)   /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
+#define   GCLK_CLKCTRL_ID_TC6_TC7_Val     _U(0x1D)   /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
+#define   GCLK_CLKCTRL_ID_ADC_Val         _U(0x1E)   /**< \brief (GCLK_CLKCTRL) ADC */
+#define   GCLK_CLKCTRL_ID_AC_DIG_Val      _U(0x1F)   /**< \brief (GCLK_CLKCTRL) AC_DIG */
+#define   GCLK_CLKCTRL_ID_AC_ANA_Val      _U(0x20)   /**< \brief (GCLK_CLKCTRL) AC_ANA */
+#define   GCLK_CLKCTRL_ID_DAC_Val         _U(0x21)   /**< \brief (GCLK_CLKCTRL) DAC */
+#define   GCLK_CLKCTRL_ID_PTC_Val         _U(0x22)   /**< \brief (GCLK_CLKCTRL) PTC */
+#define   GCLK_CLKCTRL_ID_I2S_0_Val       _U(0x23)   /**< \brief (GCLK_CLKCTRL) I2S_0 */
+#define   GCLK_CLKCTRL_ID_I2S_1_Val       _U(0x24)   /**< \brief (GCLK_CLKCTRL) I2S_1 */
+#define GCLK_CLKCTRL_ID_DFLL48      (GCLK_CLKCTRL_ID_DFLL48_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL       (GCLK_CLKCTRL_ID_FDPLL_Val     << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL32K    (GCLK_CLKCTRL_ID_FDPLL32K_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_WDT         (GCLK_CLKCTRL_ID_WDT_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_RTC         (GCLK_CLKCTRL_ID_RTC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EIC         (GCLK_CLKCTRL_ID_EIC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_USB         (GCLK_CLKCTRL_ID_USB_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_0     (GCLK_CLKCTRL_ID_EVSYS_0_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_1     (GCLK_CLKCTRL_ID_EVSYS_1_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_2     (GCLK_CLKCTRL_ID_EVSYS_2_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_3     (GCLK_CLKCTRL_ID_EVSYS_3_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_4     (GCLK_CLKCTRL_ID_EVSYS_4_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_5     (GCLK_CLKCTRL_ID_EVSYS_5_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_6     (GCLK_CLKCTRL_ID_EVSYS_6_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_7     (GCLK_CLKCTRL_ID_EVSYS_7_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_8     (GCLK_CLKCTRL_ID_EVSYS_8_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_9     (GCLK_CLKCTRL_ID_EVSYS_9_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_10    (GCLK_CLKCTRL_ID_EVSYS_10_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_11    (GCLK_CLKCTRL_ID_EVSYS_11_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC0_TCC1   (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC2_TC3    (GCLK_CLKCTRL_ID_TCC2_TC3_Val  << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC4_TC5     (GCLK_CLKCTRL_ID_TC4_TC5_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC6_TC7     (GCLK_CLKCTRL_ID_TC6_TC7_Val   << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_ADC         (GCLK_CLKCTRL_ID_ADC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_DIG      (GCLK_CLKCTRL_ID_AC_DIG_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_ANA      (GCLK_CLKCTRL_ID_AC_ANA_Val    << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_DAC         (GCLK_CLKCTRL_ID_DAC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_PTC         (GCLK_CLKCTRL_ID_PTC_Val       << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_0       (GCLK_CLKCTRL_ID_I2S_0_Val     << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_1       (GCLK_CLKCTRL_ID_I2S_1_Val     << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_GEN_Pos        8            /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
+#define GCLK_CLKCTRL_GEN_Msk        (_U(0xF) << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN(value)     (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
+#define   GCLK_CLKCTRL_GEN_GCLK0_Val      _U(0x0)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
+#define   GCLK_CLKCTRL_GEN_GCLK1_Val      _U(0x1)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
+#define   GCLK_CLKCTRL_GEN_GCLK2_Val      _U(0x2)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
+#define   GCLK_CLKCTRL_GEN_GCLK3_Val      _U(0x3)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
+#define   GCLK_CLKCTRL_GEN_GCLK4_Val      _U(0x4)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
+#define   GCLK_CLKCTRL_GEN_GCLK5_Val      _U(0x5)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
+#define   GCLK_CLKCTRL_GEN_GCLK6_Val      _U(0x6)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
+#define   GCLK_CLKCTRL_GEN_GCLK7_Val      _U(0x7)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
+#define GCLK_CLKCTRL_GEN_GCLK0      (GCLK_CLKCTRL_GEN_GCLK0_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK1      (GCLK_CLKCTRL_GEN_GCLK1_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK2      (GCLK_CLKCTRL_GEN_GCLK2_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK3      (GCLK_CLKCTRL_GEN_GCLK3_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK4      (GCLK_CLKCTRL_GEN_GCLK4_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK5      (GCLK_CLKCTRL_GEN_GCLK5_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK6      (GCLK_CLKCTRL_GEN_GCLK6_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK7      (GCLK_CLKCTRL_GEN_GCLK7_Val    << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_CLKEN_Pos      14           /**< \brief (GCLK_CLKCTRL) Clock Enable */
+#define GCLK_CLKCTRL_CLKEN          (_U(0x1) << GCLK_CLKCTRL_CLKEN_Pos)
+#define GCLK_CLKCTRL_WRTLOCK_Pos    15           /**< \brief (GCLK_CLKCTRL) Write Lock */
+#define GCLK_CLKCTRL_WRTLOCK        (_U(0x1) << GCLK_CLKCTRL_WRTLOCK_Pos)
+#define GCLK_CLKCTRL_MASK           _U(0xCF3F)   /**< \brief (GCLK_CLKCTRL) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t SRC:5;            /*!< bit:  8..12  Source Select                      */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t GENEN:1;          /*!< bit:     16  Generic Clock Generator Enable     */
+    uint32_t IDC:1;            /*!< bit:     17  Improve Duty Cycle                 */
+    uint32_t OOV:1;            /*!< bit:     18  Output Off Value                   */
+    uint32_t OE:1;             /*!< bit:     19  Output Enable                      */
+    uint32_t DIVSEL:1;         /*!< bit:     20  Divide Selection                   */
+    uint32_t RUNSTDBY:1;       /*!< bit:     21  Run in Standby                     */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET         0x4          /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE     _U(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_ID_Pos         0            /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
+#define GCLK_GENCTRL_ID_Msk         (_U(0xF) << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID(value)      (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
+#define GCLK_GENCTRL_SRC_Pos        8            /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk        (_U(0x1F) << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value)     (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
+#define   GCLK_GENCTRL_SRC_XOSC_Val       _U(0x0)   /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
+#define   GCLK_GENCTRL_SRC_GCLKIN_Val     _U(0x1)   /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   _U(0x2)   /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  _U(0x3)   /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC32K_Val     _U(0x4)   /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_XOSC32K_Val    _U(0x5)   /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC8M_Val      _U(0x6)   /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
+#define   GCLK_GENCTRL_SRC_DFLL48M_Val    _U(0x7)   /**< \brief (GCLK_GENCTRL) DFLL48M output */
+#define   GCLK_GENCTRL_SRC_FDPLL_Val      _U(0x8)   /**< \brief (GCLK_GENCTRL) FDPLL output */
+#define GCLK_GENCTRL_SRC_XOSC       (GCLK_GENCTRL_SRC_XOSC_Val     << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN     (GCLK_GENCTRL_SRC_GCLKIN_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1   (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K  (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC32K     (GCLK_GENCTRL_SRC_OSC32K_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K    (GCLK_GENCTRL_SRC_XOSC32K_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC8M      (GCLK_GENCTRL_SRC_OSC8M_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL48M    (GCLK_GENCTRL_SRC_DFLL48M_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_FDPLL      (GCLK_GENCTRL_SRC_FDPLL_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos      16           /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN          (_U(0x1) << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos        17           /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC            (_U(0x1) << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos        18           /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV            (_U(0x1) << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos         19           /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE             (_U(0x1) << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos     20           /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL         (_U(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos   21           /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY       (_U(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_MASK           _U(0x003F1F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ID:4;             /*!< bit:  0.. 3  Generic Clock Generator Selection  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t DIV:16;           /*!< bit:  8..23  Division Factor                    */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENDIV_OFFSET          0x8          /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
+#define GCLK_GENDIV_RESETVALUE      _U(0x00000000) /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
+
+#define GCLK_GENDIV_ID_Pos          0            /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
+#define GCLK_GENDIV_ID_Msk          (_U(0xF) << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID(value)       (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
+#define GCLK_GENDIV_DIV_Pos         8            /**< \brief (GCLK_GENDIV) Division Factor */
+#define GCLK_GENDIV_DIV_Msk         (_U(0xFFFF) << GCLK_GENDIV_DIV_Pos)
+#define GCLK_GENDIV_DIV(value)      (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
+#define GCLK_GENDIV_MASK            _U(0x00FFFF0F) /**< \brief (GCLK_GENDIV) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO GCLK_CTRL_Type            CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+  __I  GCLK_STATUS_Type          STATUS;      /**< \brief Offset: 0x1 (R/   8) Status */
+  __IO GCLK_CLKCTRL_Type         CLKCTRL;     /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+  __IO GCLK_GENCTRL_Type         GENCTRL;     /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+  __IO GCLK_GENDIV_Type          GENDIV;      /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_GCLK_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/hmatrixb.h b/uf2-samdx1/lib/samd21/samd21a/include/component/hmatrixb.h
new file mode 100644
index 00000000..01b0ede0
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/hmatrixb.h
@@ -0,0 +1,103 @@
+/**
+ * \file
+ *
+ * \brief Component description for HMATRIXB
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_HMATRIXB_COMPONENT_
+#define _SAMD21_HMATRIXB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR HMATRIXB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_HMATRIXB HSB Matrix */
+/*@{*/
+
+#define HMATRIXB_I7638
+#define REV_HMATRIXB                0x212
+
+/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_PRAS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRAS_OFFSET        0x080        /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
+#define HMATRIXB_PRAS_RESETVALUE    _U(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
+
+#define HMATRIXB_PRAS_MASK          _U(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
+
+/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_PRBS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRBS_OFFSET        0x084        /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
+#define HMATRIXB_PRBS_RESETVALUE    _U(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
+
+#define HMATRIXB_PRBS_MASK          _U(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
+
+/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SFR:32;           /*!< bit:  0..31  Special Function Register          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_SFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_SFR_OFFSET         0x110        /**< \brief (HMATRIXB_SFR offset) Special Function */
+#define HMATRIXB_SFR_RESETVALUE     _U(0x00000000) /**< \brief (HMATRIXB_SFR reset_value) Special Function */
+
+#define HMATRIXB_SFR_SFR_Pos        0            /**< \brief (HMATRIXB_SFR) Special Function Register */
+#define HMATRIXB_SFR_SFR_Msk        (_U(0xFFFFFFFF) << HMATRIXB_SFR_SFR_Pos)
+#define HMATRIXB_SFR_SFR(value)     (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
+#define HMATRIXB_SFR_MASK           _U(0xFFFFFFFF) /**< \brief (HMATRIXB_SFR) MASK Register */
+
+/** \brief HmatrixbPrs hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO HMATRIXB_PRAS_Type        PRAS;        /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+  __IO HMATRIXB_PRBS_Type        PRBS;        /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+} HmatrixbPrs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief HMATRIXB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       RoReg8                    Reserved1[0x80];
+       HmatrixbPrs               Prs[16];     /**< \brief Offset: 0x080 HmatrixbPrs groups */
+       RoReg8                    Reserved2[0x10];
+  __IO HMATRIXB_SFR_Type         SFR[16];     /**< \brief Offset: 0x110 (R/W 32) Special Function */
+} Hmatrixb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/i2s.h b/uf2-samdx1/lib/samd21/samd21a/include/component/i2s.h
new file mode 100644
index 00000000..c3be7927
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/i2s.h
@@ -0,0 +1,624 @@
+/**
+ * \file
+ *
+ * \brief Component description for I2S
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_COMPONENT_
+#define _SAMD21_I2S_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR I2S */
+/* ========================================================================== */
+/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
+/*@{*/
+
+#define I2S_U2224
+#define REV_I2S                     0x102
+
+/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable                */
+    uint8_t  CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable                */
+    uint8_t  SEREN0:1;         /*!< bit:      4  Serializer 0 Enable                */
+    uint8_t  SEREN1:1;         /*!< bit:      5  Serializer 1 Enable                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable                */
+    uint8_t  SEREN:2;          /*!< bit:  4.. 5  Serializer x Enable                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} I2S_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CTRLA_OFFSET            0x00         /**< \brief (I2S_CTRLA offset) Control A */
+#define I2S_CTRLA_RESETVALUE        _U(0x00)     /**< \brief (I2S_CTRLA reset_value) Control A */
+
+#define I2S_CTRLA_SWRST_Pos         0            /**< \brief (I2S_CTRLA) Software Reset */
+#define I2S_CTRLA_SWRST             (_U(0x1) << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_ENABLE_Pos        1            /**< \brief (I2S_CTRLA) Enable */
+#define I2S_CTRLA_ENABLE            (_U(0x1) << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_CKEN0_Pos         2            /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN0             (1 << I2S_CTRLA_CKEN0_Pos)
+#define I2S_CTRLA_CKEN1_Pos         3            /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
+#define I2S_CTRLA_CKEN1             (1 << I2S_CTRLA_CKEN1_Pos)
+#define I2S_CTRLA_CKEN_Pos          2            /**< \brief (I2S_CTRLA) Clock Unit x Enable */
+#define I2S_CTRLA_CKEN_Msk          (_U(0x3) << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN(value)       (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
+#define I2S_CTRLA_SEREN0_Pos        4            /**< \brief (I2S_CTRLA) Serializer 0 Enable */
+#define I2S_CTRLA_SEREN0            (1 << I2S_CTRLA_SEREN0_Pos)
+#define I2S_CTRLA_SEREN1_Pos        5            /**< \brief (I2S_CTRLA) Serializer 1 Enable */
+#define I2S_CTRLA_SEREN1            (1 << I2S_CTRLA_SEREN1_Pos)
+#define I2S_CTRLA_SEREN_Pos         4            /**< \brief (I2S_CTRLA) Serializer x Enable */
+#define I2S_CTRLA_SEREN_Msk         (_U(0x3) << I2S_CTRLA_SEREN_Pos)
+#define I2S_CTRLA_SEREN(value)      (I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos))
+#define I2S_CTRLA_MASK              _U(0x3F)     /**< \brief (I2S_CTRLA) MASK Register */
+
+/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SLOTSIZE:2;       /*!< bit:  0.. 1  Slot Size                          */
+    uint32_t NBSLOTS:3;        /*!< bit:  2.. 4  Number of Slots in Frame           */
+    uint32_t FSWIDTH:2;        /*!< bit:  5.. 6  Frame Sync Width                   */
+    uint32_t BITDELAY:1;       /*!< bit:      7  Data Delay from Frame Sync         */
+    uint32_t FSSEL:1;          /*!< bit:      8  Frame Sync Select                  */
+    uint32_t :2;               /*!< bit:  9..10  Reserved                           */
+    uint32_t FSINV:1;          /*!< bit:     11  Frame Sync Invert                  */
+    uint32_t SCKSEL:1;         /*!< bit:     12  Serial Clock Select                */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t MCKSEL:1;         /*!< bit:     16  Master Clock Select                */
+    uint32_t :1;               /*!< bit:     17  Reserved                           */
+    uint32_t MCKEN:1;          /*!< bit:     18  Master Clock Enable                */
+    uint32_t MCKDIV:5;         /*!< bit: 19..23  Master Clock Division Factor       */
+    uint32_t MCKOUTDIV:5;      /*!< bit: 24..28  Master Clock Output Division Factor */
+    uint32_t FSOUTINV:1;       /*!< bit:     29  Frame Sync Output Invert           */
+    uint32_t SCKOUTINV:1;      /*!< bit:     30  Serial Clock Output Invert         */
+    uint32_t MCKOUTINV:1;      /*!< bit:     31  Master Clock Output Invert         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CLKCTRL_OFFSET          0x04         /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE      _U(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+
+#define I2S_CLKCTRL_SLOTSIZE_Pos    0            /**< \brief (I2S_CLKCTRL) Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_Msk    (_U(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
+#define   I2S_CLKCTRL_SLOTSIZE_8_Val      _U(0x0)   /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_16_Val     _U(0x1)   /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_24_Val     _U(0x2)   /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_32_Val     _U(0x3)   /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_8      (I2S_CLKCTRL_SLOTSIZE_8_Val    << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_16     (I2S_CLKCTRL_SLOTSIZE_16_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_24     (I2S_CLKCTRL_SLOTSIZE_24_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_32     (I2S_CLKCTRL_SLOTSIZE_32_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Pos     2            /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_Msk     (_U(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS(value)  (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
+#define I2S_CLKCTRL_FSWIDTH_Pos     5            /**< \brief (I2S_CLKCTRL) Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_Msk     (_U(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH(value)  (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
+#define   I2S_CLKCTRL_FSWIDTH_SLOT_Val    _U(0x0)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define   I2S_CLKCTRL_FSWIDTH_HALF_Val    _U(0x1)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define   I2S_CLKCTRL_FSWIDTH_BIT_Val     _U(0x2)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define   I2S_CLKCTRL_FSWIDTH_BURST_Val   _U(0x3)   /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define I2S_CLKCTRL_FSWIDTH_SLOT    (I2S_CLKCTRL_FSWIDTH_SLOT_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_HALF    (I2S_CLKCTRL_FSWIDTH_HALF_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BIT     (I2S_CLKCTRL_FSWIDTH_BIT_Val   << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BURST   (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_BITDELAY_Pos    7            /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
+#define I2S_CLKCTRL_BITDELAY        (_U(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
+#define   I2S_CLKCTRL_BITDELAY_LJ_Val     _U(0x0)   /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define   I2S_CLKCTRL_BITDELAY_I2S_Val    _U(0x1)   /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_LJ     (I2S_CLKCTRL_BITDELAY_LJ_Val   << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_I2S    (I2S_CLKCTRL_BITDELAY_I2S_Val  << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_FSSEL_Pos       8            /**< \brief (I2S_CLKCTRL) Frame Sync Select */
+#define I2S_CLKCTRL_FSSEL           (_U(0x1) << I2S_CLKCTRL_FSSEL_Pos)
+#define   I2S_CLKCTRL_FSSEL_SCKDIV_Val    _U(0x0)   /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define   I2S_CLKCTRL_FSSEL_FSPIN_Val     _U(0x1)   /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_SCKDIV    (I2S_CLKCTRL_FSSEL_SCKDIV_Val  << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_FSPIN     (I2S_CLKCTRL_FSSEL_FSPIN_Val   << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSINV_Pos       11           /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
+#define I2S_CLKCTRL_FSINV           (_U(0x1) << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_SCKSEL_Pos      12           /**< \brief (I2S_CLKCTRL) Serial Clock Select */
+#define I2S_CLKCTRL_SCKSEL          (_U(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
+#define   I2S_CLKCTRL_SCKSEL_MCKDIV_Val   _U(0x0)   /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define   I2S_CLKCTRL_SCKSEL_SCKPIN_Val   _U(0x1)   /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_MCKDIV   (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_SCKPIN   (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_Pos      16           /**< \brief (I2S_CLKCTRL) Master Clock Select */
+#define I2S_CLKCTRL_MCKSEL          (_U(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
+#define   I2S_CLKCTRL_MCKSEL_GCLK_Val     _U(0x0)   /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define   I2S_CLKCTRL_MCKSEL_MCKPIN_Val   _U(0x1)   /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_GCLK     (I2S_CLKCTRL_MCKSEL_GCLK_Val   << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_MCKPIN   (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKEN_Pos       18           /**< \brief (I2S_CLKCTRL) Master Clock Enable */
+#define I2S_CLKCTRL_MCKEN           (_U(0x1) << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKDIV_Pos      19           /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_Msk      (_U(0x1F) << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV(value)   (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
+#define I2S_CLKCTRL_MCKOUTDIV_Pos   24           /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_Msk   (_U(0x1F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
+#define I2S_CLKCTRL_FSOUTINV_Pos    29           /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
+#define I2S_CLKCTRL_FSOUTINV        (_U(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_SCKOUTINV_Pos   30           /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV       (_U(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKOUTINV_Pos   31           /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV       (_U(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MASK            _U(0xFFFD19FF) /**< \brief (I2S_CLKCTRL) MASK Register */
+
+/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
+    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
+    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
+    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
+    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENCLR_OFFSET         0x0C         /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE     _U(0x0000)   /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define I2S_INTENCLR_RXRDY0_Pos     0            /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY0         (1 << I2S_INTENCLR_RXRDY0_Pos)
+#define I2S_INTENCLR_RXRDY1_Pos     1            /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY1         (1 << I2S_INTENCLR_RXRDY1_Pos)
+#define I2S_INTENCLR_RXRDY_Pos      0            /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
+#define I2S_INTENCLR_RXRDY_Msk      (_U(0x3) << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY(value)   (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
+#define I2S_INTENCLR_RXOR0_Pos      4            /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENCLR_RXOR0          (1 << I2S_INTENCLR_RXOR0_Pos)
+#define I2S_INTENCLR_RXOR1_Pos      5            /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENCLR_RXOR1          (1 << I2S_INTENCLR_RXOR1_Pos)
+#define I2S_INTENCLR_RXOR_Pos       4            /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
+#define I2S_INTENCLR_RXOR_Msk       (_U(0x3) << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR(value)    (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
+#define I2S_INTENCLR_TXRDY0_Pos     8            /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY0         (1 << I2S_INTENCLR_TXRDY0_Pos)
+#define I2S_INTENCLR_TXRDY1_Pos     9            /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY1         (1 << I2S_INTENCLR_TXRDY1_Pos)
+#define I2S_INTENCLR_TXRDY_Pos      8            /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
+#define I2S_INTENCLR_TXRDY_Msk      (_U(0x3) << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY(value)   (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
+#define I2S_INTENCLR_TXUR0_Pos      12           /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENCLR_TXUR0          (1 << I2S_INTENCLR_TXUR0_Pos)
+#define I2S_INTENCLR_TXUR1_Pos      13           /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENCLR_TXUR1          (1 << I2S_INTENCLR_TXUR1_Pos)
+#define I2S_INTENCLR_TXUR_Pos       12           /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENCLR_TXUR_Msk       (_U(0x3) << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR(value)    (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
+#define I2S_INTENCLR_MASK           _U(0x3333)   /**< \brief (I2S_INTENCLR) MASK Register */
+
+/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
+    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
+    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
+    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
+    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENSET_OFFSET         0x10         /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE     _U(0x0000)   /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+
+#define I2S_INTENSET_RXRDY0_Pos     0            /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENSET_RXRDY0         (1 << I2S_INTENSET_RXRDY0_Pos)
+#define I2S_INTENSET_RXRDY1_Pos     1            /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENSET_RXRDY1         (1 << I2S_INTENSET_RXRDY1_Pos)
+#define I2S_INTENSET_RXRDY_Pos      0            /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
+#define I2S_INTENSET_RXRDY_Msk      (_U(0x3) << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY(value)   (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
+#define I2S_INTENSET_RXOR0_Pos      4            /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENSET_RXOR0          (1 << I2S_INTENSET_RXOR0_Pos)
+#define I2S_INTENSET_RXOR1_Pos      5            /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENSET_RXOR1          (1 << I2S_INTENSET_RXOR1_Pos)
+#define I2S_INTENSET_RXOR_Pos       4            /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
+#define I2S_INTENSET_RXOR_Msk       (_U(0x3) << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR(value)    (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
+#define I2S_INTENSET_TXRDY0_Pos     8            /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENSET_TXRDY0         (1 << I2S_INTENSET_TXRDY0_Pos)
+#define I2S_INTENSET_TXRDY1_Pos     9            /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENSET_TXRDY1         (1 << I2S_INTENSET_TXRDY1_Pos)
+#define I2S_INTENSET_TXRDY_Pos      8            /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
+#define I2S_INTENSET_TXRDY_Msk      (_U(0x3) << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY(value)   (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
+#define I2S_INTENSET_TXUR0_Pos      12           /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENSET_TXUR0          (1 << I2S_INTENSET_TXUR0_Pos)
+#define I2S_INTENSET_TXUR1_Pos      13           /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENSET_TXUR1          (1 << I2S_INTENSET_TXUR1_Pos)
+#define I2S_INTENSET_TXUR_Pos       12           /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENSET_TXUR_Msk       (_U(0x3) << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR(value)    (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
+#define I2S_INTENSET_MASK           _U(0x3333)   /**< \brief (I2S_INTENSET) MASK Register */
+
+/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0                    */
+    __I uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1                    */
+    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0                  */
+    __I uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1                  */
+    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    __I uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0                   */
+    __I uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1                   */
+    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    __I uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0                */
+    __I uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1                */
+    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x                    */
+    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x                  */
+    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    __I uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x                   */
+    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    __I uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x                */
+    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTFLAG_OFFSET          0x14         /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE      _U(0x0000)   /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define I2S_INTFLAG_RXRDY0_Pos      0            /**< \brief (I2S_INTFLAG) Receive Ready 0 */
+#define I2S_INTFLAG_RXRDY0          (1 << I2S_INTFLAG_RXRDY0_Pos)
+#define I2S_INTFLAG_RXRDY1_Pos      1            /**< \brief (I2S_INTFLAG) Receive Ready 1 */
+#define I2S_INTFLAG_RXRDY1          (1 << I2S_INTFLAG_RXRDY1_Pos)
+#define I2S_INTFLAG_RXRDY_Pos       0            /**< \brief (I2S_INTFLAG) Receive Ready x */
+#define I2S_INTFLAG_RXRDY_Msk       (_U(0x3) << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY(value)    (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
+#define I2S_INTFLAG_RXOR0_Pos       4            /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
+#define I2S_INTFLAG_RXOR0           (1 << I2S_INTFLAG_RXOR0_Pos)
+#define I2S_INTFLAG_RXOR1_Pos       5            /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
+#define I2S_INTFLAG_RXOR1           (1 << I2S_INTFLAG_RXOR1_Pos)
+#define I2S_INTFLAG_RXOR_Pos        4            /**< \brief (I2S_INTFLAG) Receive Overrun x */
+#define I2S_INTFLAG_RXOR_Msk        (_U(0x3) << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR(value)     (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
+#define I2S_INTFLAG_TXRDY0_Pos      8            /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
+#define I2S_INTFLAG_TXRDY0          (1 << I2S_INTFLAG_TXRDY0_Pos)
+#define I2S_INTFLAG_TXRDY1_Pos      9            /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
+#define I2S_INTFLAG_TXRDY1          (1 << I2S_INTFLAG_TXRDY1_Pos)
+#define I2S_INTFLAG_TXRDY_Pos       8            /**< \brief (I2S_INTFLAG) Transmit Ready x */
+#define I2S_INTFLAG_TXRDY_Msk       (_U(0x3) << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY(value)    (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
+#define I2S_INTFLAG_TXUR0_Pos       12           /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
+#define I2S_INTFLAG_TXUR0           (1 << I2S_INTFLAG_TXUR0_Pos)
+#define I2S_INTFLAG_TXUR1_Pos       13           /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
+#define I2S_INTFLAG_TXUR1           (1 << I2S_INTFLAG_TXUR1_Pos)
+#define I2S_INTFLAG_TXUR_Pos        12           /**< \brief (I2S_INTFLAG) Transmit Underrun x */
+#define I2S_INTFLAG_TXUR_Msk        (_U(0x3) << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR(value)     (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
+#define I2S_INTFLAG_MASK            _U(0x3333)   /**< \brief (I2S_INTFLAG) MASK Register */
+
+/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/  16) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Status */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Status      */
+    uint16_t CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable Synchronization Status */
+    uint16_t CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable Synchronization Status */
+    uint16_t SEREN0:1;         /*!< bit:      4  Serializer 0 Enable Synchronization Status */
+    uint16_t SEREN1:1;         /*!< bit:      5  Serializer 1 Enable Synchronization Status */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t DATA0:1;          /*!< bit:      8  Data 0 Synchronization Status      */
+    uint16_t DATA1:1;          /*!< bit:      9  Data 1 Synchronization Status      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable Synchronization Status */
+    uint16_t SEREN:2;          /*!< bit:  4.. 5  Serializer x Enable Synchronization Status */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t DATA:2;           /*!< bit:  8.. 9  Data x Synchronization Status      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SYNCBUSY_OFFSET         0x18         /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE     _U(0x0000)   /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+
+#define I2S_SYNCBUSY_SWRST_Pos      0            /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
+#define I2S_SYNCBUSY_SWRST          (_U(0x1) << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_ENABLE_Pos     1            /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
+#define I2S_SYNCBUSY_ENABLE         (_U(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_CKEN0_Pos      2            /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN0          (1 << I2S_SYNCBUSY_CKEN0_Pos)
+#define I2S_SYNCBUSY_CKEN1_Pos      3            /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN1          (1 << I2S_SYNCBUSY_CKEN1_Pos)
+#define I2S_SYNCBUSY_CKEN_Pos       2            /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN_Msk       (_U(0x3) << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN(value)    (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
+#define I2S_SYNCBUSY_SEREN0_Pos     4            /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN0         (1 << I2S_SYNCBUSY_SEREN0_Pos)
+#define I2S_SYNCBUSY_SEREN1_Pos     5            /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN1         (1 << I2S_SYNCBUSY_SEREN1_Pos)
+#define I2S_SYNCBUSY_SEREN_Pos      4            /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN_Msk      (_U(0x3) << I2S_SYNCBUSY_SEREN_Pos)
+#define I2S_SYNCBUSY_SEREN(value)   (I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos))
+#define I2S_SYNCBUSY_DATA0_Pos      8            /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
+#define I2S_SYNCBUSY_DATA0          (1 << I2S_SYNCBUSY_DATA0_Pos)
+#define I2S_SYNCBUSY_DATA1_Pos      9            /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
+#define I2S_SYNCBUSY_DATA1          (1 << I2S_SYNCBUSY_DATA1_Pos)
+#define I2S_SYNCBUSY_DATA_Pos       8            /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
+#define I2S_SYNCBUSY_DATA_Msk       (_U(0x3) << I2S_SYNCBUSY_DATA_Pos)
+#define I2S_SYNCBUSY_DATA(value)    (I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos))
+#define I2S_SYNCBUSY_MASK           _U(0x033F)   /**< \brief (I2S_SYNCBUSY) MASK Register */
+
+/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SERMODE:2;        /*!< bit:  0.. 1  Serializer Mode                    */
+    uint32_t TXDEFAULT:2;      /*!< bit:  2.. 3  Line Default Line when Slot Disabled */
+    uint32_t TXSAME:1;         /*!< bit:      4  Transmit Data when Underrun        */
+    uint32_t CLKSEL:1;         /*!< bit:      5  Clock Unit Selection               */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t SLOTADJ:1;        /*!< bit:      7  Data Slot Formatting Adjust        */
+    uint32_t DATASIZE:3;       /*!< bit:  8..10  Data Word Size                     */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WORDADJ:1;        /*!< bit:     12  Data Word Formatting Adjust        */
+    uint32_t EXTEND:2;         /*!< bit: 13..14  Data Formatting Bit Extension      */
+    uint32_t BITREV:1;         /*!< bit:     15  Data Formatting Bit Reverse        */
+    uint32_t SLOTDIS0:1;       /*!< bit:     16  Slot 0 Disabled for this Serializer */
+    uint32_t SLOTDIS1:1;       /*!< bit:     17  Slot 1 Disabled for this Serializer */
+    uint32_t SLOTDIS2:1;       /*!< bit:     18  Slot 2 Disabled for this Serializer */
+    uint32_t SLOTDIS3:1;       /*!< bit:     19  Slot 3 Disabled for this Serializer */
+    uint32_t SLOTDIS4:1;       /*!< bit:     20  Slot 4 Disabled for this Serializer */
+    uint32_t SLOTDIS5:1;       /*!< bit:     21  Slot 5 Disabled for this Serializer */
+    uint32_t SLOTDIS6:1;       /*!< bit:     22  Slot 6 Disabled for this Serializer */
+    uint32_t SLOTDIS7:1;       /*!< bit:     23  Slot 7 Disabled for this Serializer */
+    uint32_t MONO:1;           /*!< bit:     24  Mono Mode                          */
+    uint32_t DMA:1;            /*!< bit:     25  Single or Multiple DMA Channels    */
+    uint32_t RXLOOP:1;         /*!< bit:     26  Loop-back Test Mode                */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t SLOTDIS:8;        /*!< bit: 16..23  Slot x Disabled for this Serializer */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_SERCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SERCTRL_OFFSET          0x20         /**< \brief (I2S_SERCTRL offset) Serializer n Control */
+#define I2S_SERCTRL_RESETVALUE      _U(0x00000000) /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
+
+#define I2S_SERCTRL_SERMODE_Pos     0            /**< \brief (I2S_SERCTRL) Serializer Mode */
+#define I2S_SERCTRL_SERMODE_Msk     (_U(0x3) << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE(value)  (I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))
+#define   I2S_SERCTRL_SERMODE_RX_Val      _U(0x0)   /**< \brief (I2S_SERCTRL) Receive */
+#define   I2S_SERCTRL_SERMODE_TX_Val      _U(0x1)   /**< \brief (I2S_SERCTRL) Transmit */
+#define   I2S_SERCTRL_SERMODE_PDM2_Val    _U(0x2)   /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
+#define I2S_SERCTRL_SERMODE_RX      (I2S_SERCTRL_SERMODE_RX_Val    << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_TX      (I2S_SERCTRL_SERMODE_TX_Val    << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_PDM2    (I2S_SERCTRL_SERMODE_PDM2_Val  << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_TXDEFAULT_Pos   2            /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
+#define I2S_SERCTRL_TXDEFAULT_Msk   (_U(0x3) << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT(value) (I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))
+#define   I2S_SERCTRL_TXDEFAULT_ZERO_Val  _U(0x0)   /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
+#define   I2S_SERCTRL_TXDEFAULT_ONE_Val   _U(0x1)   /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
+#define   I2S_SERCTRL_TXDEFAULT_HIZ_Val   _U(0x3)   /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
+#define I2S_SERCTRL_TXDEFAULT_ZERO  (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_ONE   (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_HIZ   (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXSAME_Pos      4            /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
+#define I2S_SERCTRL_TXSAME          (_U(0x1) << I2S_SERCTRL_TXSAME_Pos)
+#define   I2S_SERCTRL_TXSAME_ZERO_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
+#define   I2S_SERCTRL_TXSAME_SAME_Val     _U(0x1)   /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME_ZERO     (I2S_SERCTRL_TXSAME_ZERO_Val   << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_TXSAME_SAME     (I2S_SERCTRL_TXSAME_SAME_Val   << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_CLKSEL_Pos      5            /**< \brief (I2S_SERCTRL) Clock Unit Selection */
+#define I2S_SERCTRL_CLKSEL          (_U(0x1) << I2S_SERCTRL_CLKSEL_Pos)
+#define   I2S_SERCTRL_CLKSEL_CLK0_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
+#define   I2S_SERCTRL_CLKSEL_CLK1_Val     _U(0x1)   /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
+#define I2S_SERCTRL_CLKSEL_CLK0     (I2S_SERCTRL_CLKSEL_CLK0_Val   << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_CLKSEL_CLK1     (I2S_SERCTRL_CLKSEL_CLK1_Val   << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_SLOTADJ_Pos     7            /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
+#define I2S_SERCTRL_SLOTADJ         (_U(0x1) << I2S_SERCTRL_SLOTADJ_Pos)
+#define   I2S_SERCTRL_SLOTADJ_RIGHT_Val   _U(0x0)   /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
+#define   I2S_SERCTRL_SLOTADJ_LEFT_Val    _U(0x1)   /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ_RIGHT   (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_SLOTADJ_LEFT    (I2S_SERCTRL_SLOTADJ_LEFT_Val  << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_DATASIZE_Pos    8            /**< \brief (I2S_SERCTRL) Data Word Size */
+#define I2S_SERCTRL_DATASIZE_Msk    (_U(0x7) << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE(value) (I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))
+#define   I2S_SERCTRL_DATASIZE_32_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) 32 bits */
+#define   I2S_SERCTRL_DATASIZE_24_Val     _U(0x1)   /**< \brief (I2S_SERCTRL) 24 bits */
+#define   I2S_SERCTRL_DATASIZE_20_Val     _U(0x2)   /**< \brief (I2S_SERCTRL) 20 bits */
+#define   I2S_SERCTRL_DATASIZE_18_Val     _U(0x3)   /**< \brief (I2S_SERCTRL) 18 bits */
+#define   I2S_SERCTRL_DATASIZE_16_Val     _U(0x4)   /**< \brief (I2S_SERCTRL) 16 bits */
+#define   I2S_SERCTRL_DATASIZE_16C_Val    _U(0x5)   /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
+#define   I2S_SERCTRL_DATASIZE_8_Val      _U(0x6)   /**< \brief (I2S_SERCTRL) 8 bits */
+#define   I2S_SERCTRL_DATASIZE_8C_Val     _U(0x7)   /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
+#define I2S_SERCTRL_DATASIZE_32     (I2S_SERCTRL_DATASIZE_32_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_24     (I2S_SERCTRL_DATASIZE_24_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_20     (I2S_SERCTRL_DATASIZE_20_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_18     (I2S_SERCTRL_DATASIZE_18_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16     (I2S_SERCTRL_DATASIZE_16_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16C    (I2S_SERCTRL_DATASIZE_16C_Val  << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8      (I2S_SERCTRL_DATASIZE_8_Val    << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8C     (I2S_SERCTRL_DATASIZE_8C_Val   << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_WORDADJ_Pos     12           /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
+#define I2S_SERCTRL_WORDADJ         (_U(0x1) << I2S_SERCTRL_WORDADJ_Pos)
+#define   I2S_SERCTRL_WORDADJ_RIGHT_Val   _U(0x0)   /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
+#define   I2S_SERCTRL_WORDADJ_LEFT_Val    _U(0x1)   /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
+#define I2S_SERCTRL_WORDADJ_RIGHT   (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_WORDADJ_LEFT    (I2S_SERCTRL_WORDADJ_LEFT_Val  << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_EXTEND_Pos      13           /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
+#define I2S_SERCTRL_EXTEND_Msk      (_U(0x3) << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND(value)   (I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))
+#define   I2S_SERCTRL_EXTEND_ZERO_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) Extend with zeroes */
+#define   I2S_SERCTRL_EXTEND_ONE_Val      _U(0x1)   /**< \brief (I2S_SERCTRL) Extend with ones */
+#define   I2S_SERCTRL_EXTEND_MSBIT_Val    _U(0x2)   /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
+#define   I2S_SERCTRL_EXTEND_LSBIT_Val    _U(0x3)   /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
+#define I2S_SERCTRL_EXTEND_ZERO     (I2S_SERCTRL_EXTEND_ZERO_Val   << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_ONE      (I2S_SERCTRL_EXTEND_ONE_Val    << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_MSBIT    (I2S_SERCTRL_EXTEND_MSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_LSBIT    (I2S_SERCTRL_EXTEND_LSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_BITREV_Pos      15           /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
+#define I2S_SERCTRL_BITREV          (_U(0x1) << I2S_SERCTRL_BITREV_Pos)
+#define   I2S_SERCTRL_BITREV_MSBIT_Val    _U(0x0)   /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define   I2S_SERCTRL_BITREV_LSBIT_Val    _U(0x1)   /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_SERCTRL_BITREV_MSBIT    (I2S_SERCTRL_BITREV_MSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_BITREV_LSBIT    (I2S_SERCTRL_BITREV_LSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_SLOTDIS0_Pos    16           /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS0        (1 << I2S_SERCTRL_SLOTDIS0_Pos)
+#define I2S_SERCTRL_SLOTDIS1_Pos    17           /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS1        (1 << I2S_SERCTRL_SLOTDIS1_Pos)
+#define I2S_SERCTRL_SLOTDIS2_Pos    18           /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS2        (1 << I2S_SERCTRL_SLOTDIS2_Pos)
+#define I2S_SERCTRL_SLOTDIS3_Pos    19           /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS3        (1 << I2S_SERCTRL_SLOTDIS3_Pos)
+#define I2S_SERCTRL_SLOTDIS4_Pos    20           /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS4        (1 << I2S_SERCTRL_SLOTDIS4_Pos)
+#define I2S_SERCTRL_SLOTDIS5_Pos    21           /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS5        (1 << I2S_SERCTRL_SLOTDIS5_Pos)
+#define I2S_SERCTRL_SLOTDIS6_Pos    22           /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS6        (1 << I2S_SERCTRL_SLOTDIS6_Pos)
+#define I2S_SERCTRL_SLOTDIS7_Pos    23           /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS7        (1 << I2S_SERCTRL_SLOTDIS7_Pos)
+#define I2S_SERCTRL_SLOTDIS_Pos     16           /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS_Msk     (_U(0xFF) << I2S_SERCTRL_SLOTDIS_Pos)
+#define I2S_SERCTRL_SLOTDIS(value)  (I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos))
+#define I2S_SERCTRL_MONO_Pos        24           /**< \brief (I2S_SERCTRL) Mono Mode */
+#define I2S_SERCTRL_MONO            (_U(0x1) << I2S_SERCTRL_MONO_Pos)
+#define   I2S_SERCTRL_MONO_STEREO_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) Normal mode */
+#define   I2S_SERCTRL_MONO_MONO_Val       _U(0x1)   /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
+#define I2S_SERCTRL_MONO_STEREO     (I2S_SERCTRL_MONO_STEREO_Val   << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_MONO_MONO       (I2S_SERCTRL_MONO_MONO_Val     << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_DMA_Pos         25           /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
+#define I2S_SERCTRL_DMA             (_U(0x1) << I2S_SERCTRL_DMA_Pos)
+#define   I2S_SERCTRL_DMA_SINGLE_Val      _U(0x0)   /**< \brief (I2S_SERCTRL) Single DMA channel */
+#define   I2S_SERCTRL_DMA_MULTIPLE_Val    _U(0x1)   /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
+#define I2S_SERCTRL_DMA_SINGLE      (I2S_SERCTRL_DMA_SINGLE_Val    << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_DMA_MULTIPLE    (I2S_SERCTRL_DMA_MULTIPLE_Val  << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_RXLOOP_Pos      26           /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
+#define I2S_SERCTRL_RXLOOP          (_U(0x1) << I2S_SERCTRL_RXLOOP_Pos)
+#define I2S_SERCTRL_MASK            _U(0x07FFF7BF) /**< \brief (I2S_SERCTRL) MASK Register */
+
+/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Sample Data                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_DATA_OFFSET             0x30         /**< \brief (I2S_DATA offset) Data n */
+#define I2S_DATA_RESETVALUE         _U(0x00000000) /**< \brief (I2S_DATA reset_value) Data n */
+
+#define I2S_DATA_DATA_Pos           0            /**< \brief (I2S_DATA) Sample Data */
+#define I2S_DATA_DATA_Msk           (_U(0xFFFFFFFF) << I2S_DATA_DATA_Pos)
+#define I2S_DATA_DATA(value)        (I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))
+#define I2S_DATA_MASK               _U(0xFFFFFFFF) /**< \brief (I2S_DATA) MASK Register */
+
+/** \brief I2S hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO I2S_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x3];
+  __IO I2S_CLKCTRL_Type          CLKCTRL[2];  /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+  __IO I2S_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x2];
+  __IO I2S_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x2];
+  __IO I2S_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x2];
+  __I  I2S_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x18 (R/  16) Synchronization Status */
+       RoReg8                    Reserved5[0x6];
+  __IO I2S_SERCTRL_Type          SERCTRL[2];  /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
+       RoReg8                    Reserved6[0x8];
+  __IO I2S_DATA_Type             DATA[2];     /**< \brief Offset: 0x30 (R/W 32) Data n */
+} I2s;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_I2S_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/mtb.h b/uf2-samdx1/lib/samd21/samd21a/include/component/mtb.h
new file mode 100644
index 00000000..52ba35ff
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/mtb.h
@@ -0,0 +1,381 @@
+/**
+ * \file
+ *
+ * \brief Component description for MTB
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_COMPONENT_
+#define _SAMD21_MTB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR MTB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
+/*@{*/
+
+#define MTB_U2002
+#define REV_MTB                     0x100
+
+/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t WRAP:1;           /*!< bit:      2  Pointer Value Wraps                */
+    uint32_t POINTER:29;       /*!< bit:  3..31  Trace Packet Location Pointer      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_POSITION_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_POSITION_OFFSET         0x000        /**< \brief (MTB_POSITION offset) MTB Position */
+
+#define MTB_POSITION_WRAP_Pos       2            /**< \brief (MTB_POSITION) Pointer Value Wraps */
+#define MTB_POSITION_WRAP           (_U(0x1) << MTB_POSITION_WRAP_Pos)
+#define MTB_POSITION_POINTER_Pos    3            /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
+#define MTB_POSITION_POINTER_Msk    (_U(0x1FFFFFFF) << MTB_POSITION_POINTER_Pos)
+#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
+#define MTB_POSITION_MASK           _U(0xFFFFFFFC) /**< \brief (MTB_POSITION) MASK Register */
+
+/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MASK:5;           /*!< bit:  0.. 4  Maximum Value of the Trace Buffer in SRAM */
+    uint32_t TSTARTEN:1;       /*!< bit:      5  Trace Start Input Enable           */
+    uint32_t TSTOPEN:1;        /*!< bit:      6  Trace Stop Input Enable            */
+    uint32_t SFRWPRIV:1;       /*!< bit:      7  Special Function Register Write Privilege */
+    uint32_t RAMPRIV:1;        /*!< bit:      8  SRAM Privilege                     */
+    uint32_t HALTREQ:1;        /*!< bit:      9  Halt Request                       */
+    uint32_t :21;              /*!< bit: 10..30  Reserved                           */
+    uint32_t EN:1;             /*!< bit:     31  Main Trace Enable                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_MASTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_MASTER_OFFSET           0x004        /**< \brief (MTB_MASTER offset) MTB Master */
+#define MTB_MASTER_RESETVALUE       _U(0x00000000) /**< \brief (MTB_MASTER reset_value) MTB Master */
+
+#define MTB_MASTER_MASK_Pos         0            /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
+#define MTB_MASTER_MASK_Msk         (_U(0x1F) << MTB_MASTER_MASK_Pos)
+#define MTB_MASTER_MASK(value)      (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
+#define MTB_MASTER_TSTARTEN_Pos     5            /**< \brief (MTB_MASTER) Trace Start Input Enable */
+#define MTB_MASTER_TSTARTEN         (_U(0x1) << MTB_MASTER_TSTARTEN_Pos)
+#define MTB_MASTER_TSTOPEN_Pos      6            /**< \brief (MTB_MASTER) Trace Stop Input Enable */
+#define MTB_MASTER_TSTOPEN          (_U(0x1) << MTB_MASTER_TSTOPEN_Pos)
+#define MTB_MASTER_SFRWPRIV_Pos     7            /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
+#define MTB_MASTER_SFRWPRIV         (_U(0x1) << MTB_MASTER_SFRWPRIV_Pos)
+#define MTB_MASTER_RAMPRIV_Pos      8            /**< \brief (MTB_MASTER) SRAM Privilege */
+#define MTB_MASTER_RAMPRIV          (_U(0x1) << MTB_MASTER_RAMPRIV_Pos)
+#define MTB_MASTER_HALTREQ_Pos      9            /**< \brief (MTB_MASTER) Halt Request */
+#define MTB_MASTER_HALTREQ          (_U(0x1) << MTB_MASTER_HALTREQ_Pos)
+#define MTB_MASTER_EN_Pos           31           /**< \brief (MTB_MASTER) Main Trace Enable */
+#define MTB_MASTER_EN               (_U(0x1) << MTB_MASTER_EN_Pos)
+#define MTB_MASTER_MASK_            _U(0x800003FF) /**< \brief (MTB_MASTER) MASK Register */
+
+/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t AUTOSTOP:1;       /*!< bit:      0  Auto Stop Tracing                  */
+    uint32_t AUTOHALT:1;       /*!< bit:      1  Auto Halt Request                  */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t WATERMARK:29;     /*!< bit:  3..31  Watermark value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_FLOW_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_FLOW_OFFSET             0x008        /**< \brief (MTB_FLOW offset) MTB Flow */
+#define MTB_FLOW_RESETVALUE         _U(0x00000000) /**< \brief (MTB_FLOW reset_value) MTB Flow */
+
+#define MTB_FLOW_AUTOSTOP_Pos       0            /**< \brief (MTB_FLOW) Auto Stop Tracing */
+#define MTB_FLOW_AUTOSTOP           (_U(0x1) << MTB_FLOW_AUTOSTOP_Pos)
+#define MTB_FLOW_AUTOHALT_Pos       1            /**< \brief (MTB_FLOW) Auto Halt Request */
+#define MTB_FLOW_AUTOHALT           (_U(0x1) << MTB_FLOW_AUTOHALT_Pos)
+#define MTB_FLOW_WATERMARK_Pos      3            /**< \brief (MTB_FLOW) Watermark value */
+#define MTB_FLOW_WATERMARK_Msk      (_U(0x1FFFFFFF) << MTB_FLOW_WATERMARK_Pos)
+#define MTB_FLOW_WATERMARK(value)   (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
+#define MTB_FLOW_MASK               _U(0xFFFFFFFB) /**< \brief (MTB_FLOW) MASK Register */
+
+/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/  32) MTB Base -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_BASE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_BASE_OFFSET             0x00C        /**< \brief (MTB_BASE offset) MTB Base */
+#define MTB_BASE_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_BASE) MASK Register */
+
+/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_ITCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_ITCTRL_OFFSET           0xF00        /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
+#define MTB_ITCTRL_MASK             _U(0xFFFFFFFF) /**< \brief (MTB_ITCTRL) MASK Register */
+
+/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CLAIMSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMSET_OFFSET         0xFA0        /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
+#define MTB_CLAIMSET_MASK           _U(0xFFFFFFFF) /**< \brief (MTB_CLAIMSET) MASK Register */
+
+/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CLAIMCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMCLR_OFFSET         0xFA4        /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
+#define MTB_CLAIMCLR_MASK           _U(0xFFFFFFFF) /**< \brief (MTB_CLAIMCLR) MASK Register */
+
+/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_LOCKACCESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKACCESS_OFFSET       0xFB0        /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
+#define MTB_LOCKACCESS_MASK         _U(0xFFFFFFFF) /**< \brief (MTB_LOCKACCESS) MASK Register */
+
+/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/  32) MTB Lock Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_LOCKSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKSTATUS_OFFSET       0xFB4        /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
+#define MTB_LOCKSTATUS_MASK         _U(0xFFFFFFFF) /**< \brief (MTB_LOCKSTATUS) MASK Register */
+
+/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/  32) MTB Authentication Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_AUTHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_AUTHSTATUS_OFFSET       0xFB8        /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
+#define MTB_AUTHSTATUS_MASK         _U(0xFFFFFFFF) /**< \brief (MTB_AUTHSTATUS) MASK Register */
+
+/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/  32) MTB Device Architecture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVARCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVARCH_OFFSET          0xFBC        /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
+#define MTB_DEVARCH_MASK            _U(0xFFFFFFFF) /**< \brief (MTB_DEVARCH) MASK Register */
+
+/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/  32) MTB Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVID_OFFSET            0xFC8        /**< \brief (MTB_DEVID offset) MTB Device Configuration */
+#define MTB_DEVID_MASK              _U(0xFFFFFFFF) /**< \brief (MTB_DEVID) MASK Register */
+
+/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/  32) MTB Device Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVTYPE_OFFSET          0xFCC        /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
+#define MTB_DEVTYPE_MASK            _U(0xFFFFFFFF) /**< \brief (MTB_DEVTYPE) MASK Register */
+
+/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID4_OFFSET             0xFD0        /**< \brief (MTB_PID4 offset) CoreSight */
+#define MTB_PID4_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID4) MASK Register */
+
+/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID5_OFFSET             0xFD4        /**< \brief (MTB_PID5 offset) CoreSight */
+#define MTB_PID5_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID5) MASK Register */
+
+/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID6_OFFSET             0xFD8        /**< \brief (MTB_PID6 offset) CoreSight */
+#define MTB_PID6_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID6) MASK Register */
+
+/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID7_OFFSET             0xFDC        /**< \brief (MTB_PID7 offset) CoreSight */
+#define MTB_PID7_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID7) MASK Register */
+
+/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID0_OFFSET             0xFE0        /**< \brief (MTB_PID0 offset) CoreSight */
+#define MTB_PID0_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID0) MASK Register */
+
+/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID1_OFFSET             0xFE4        /**< \brief (MTB_PID1 offset) CoreSight */
+#define MTB_PID1_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID1) MASK Register */
+
+/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID2_OFFSET             0xFE8        /**< \brief (MTB_PID2 offset) CoreSight */
+#define MTB_PID2_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID2) MASK Register */
+
+/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID3_OFFSET             0xFEC        /**< \brief (MTB_PID3 offset) CoreSight */
+#define MTB_PID3_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID3) MASK Register */
+
+/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID0_OFFSET             0xFF0        /**< \brief (MTB_CID0 offset) CoreSight */
+#define MTB_CID0_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_CID0) MASK Register */
+
+/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID1_OFFSET             0xFF4        /**< \brief (MTB_CID1 offset) CoreSight */
+#define MTB_CID1_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_CID1) MASK Register */
+
+/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID2_OFFSET             0xFF8        /**< \brief (MTB_CID2 offset) CoreSight */
+#define MTB_CID2_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_CID2) MASK Register */
+
+/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/  32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID3_OFFSET             0xFFC        /**< \brief (MTB_CID3 offset) CoreSight */
+#define MTB_CID3_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_CID3) MASK Register */
+
+/** \brief MTB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO MTB_POSITION_Type         POSITION;    /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+  __IO MTB_MASTER_Type           MASTER;      /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+  __IO MTB_FLOW_Type             FLOW;        /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+  __I  MTB_BASE_Type             BASE;        /**< \brief Offset: 0x00C (R/  32) MTB Base */
+       RoReg8                    Reserved1[0xEF0];
+  __IO MTB_ITCTRL_Type           ITCTRL;      /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+       RoReg8                    Reserved2[0x9C];
+  __IO MTB_CLAIMSET_Type         CLAIMSET;    /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+  __IO MTB_CLAIMCLR_Type         CLAIMCLR;    /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+       RoReg8                    Reserved3[0x8];
+  __IO MTB_LOCKACCESS_Type       LOCKACCESS;  /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+  __I  MTB_LOCKSTATUS_Type       LOCKSTATUS;  /**< \brief Offset: 0xFB4 (R/  32) MTB Lock Status */
+  __I  MTB_AUTHSTATUS_Type       AUTHSTATUS;  /**< \brief Offset: 0xFB8 (R/  32) MTB Authentication Status */
+  __I  MTB_DEVARCH_Type          DEVARCH;     /**< \brief Offset: 0xFBC (R/  32) MTB Device Architecture */
+       RoReg8                    Reserved4[0x8];
+  __I  MTB_DEVID_Type            DEVID;       /**< \brief Offset: 0xFC8 (R/  32) MTB Device Configuration */
+  __I  MTB_DEVTYPE_Type          DEVTYPE;     /**< \brief Offset: 0xFCC (R/  32) MTB Device Type */
+  __I  MTB_PID4_Type             PID4;        /**< \brief Offset: 0xFD0 (R/  32) CoreSight */
+  __I  MTB_PID5_Type             PID5;        /**< \brief Offset: 0xFD4 (R/  32) CoreSight */
+  __I  MTB_PID6_Type             PID6;        /**< \brief Offset: 0xFD8 (R/  32) CoreSight */
+  __I  MTB_PID7_Type             PID7;        /**< \brief Offset: 0xFDC (R/  32) CoreSight */
+  __I  MTB_PID0_Type             PID0;        /**< \brief Offset: 0xFE0 (R/  32) CoreSight */
+  __I  MTB_PID1_Type             PID1;        /**< \brief Offset: 0xFE4 (R/  32) CoreSight */
+  __I  MTB_PID2_Type             PID2;        /**< \brief Offset: 0xFE8 (R/  32) CoreSight */
+  __I  MTB_PID3_Type             PID3;        /**< \brief Offset: 0xFEC (R/  32) CoreSight */
+  __I  MTB_CID0_Type             CID0;        /**< \brief Offset: 0xFF0 (R/  32) CoreSight */
+  __I  MTB_CID1_Type             CID1;        /**< \brief Offset: 0xFF4 (R/  32) CoreSight */
+  __I  MTB_CID2_Type             CID2;        /**< \brief Offset: 0xFF8 (R/  32) CoreSight */
+  __I  MTB_CID3_Type             CID3;        /**< \brief Offset: 0xFFC (R/  32) CoreSight */
+} Mtb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_MTB_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/nvmctrl.h b/uf2-samdx1/lib/samd21/samd21a/include/component/nvmctrl.h
new file mode 100644
index 00000000..3a3bfda2
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/nvmctrl.h
@@ -0,0 +1,512 @@
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_COMPONENT_
+#define _SAMD21_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2207
+#define REV_NVMCTRL                 0x106
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE    _U(0x0000)   /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLA) Command */
+#define NVMCTRL_CTRLA_CMD_Msk       (_U(0x7F) << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD(value)    (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
+#define   NVMCTRL_CTRLA_CMD_ER_Val        _U(0x2)   /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_WP_Val        _U(0x4)   /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_EAR_Val       _U(0x5)   /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_WAP_Val       _U(0x6)   /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_SF_Val        _U(0xA)   /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define   NVMCTRL_CTRLA_CMD_WL_Val        _U(0xF)   /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define   NVMCTRL_CTRLA_CMD_LR_Val        _U(0x40)   /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_UR_Val        _U(0x41)   /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_SPRM_Val      _U(0x42)   /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_CPRM_Val      _U(0x43)   /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_PBC_Val       _U(0x44)   /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define   NVMCTRL_CTRLA_CMD_SSB_Val       _U(0x45)   /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define   NVMCTRL_CTRLA_CMD_INVALL_Val    _U(0x46)   /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */
+#define NVMCTRL_CTRLA_CMD_ER        (NVMCTRL_CTRLA_CMD_ER_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WP        (NVMCTRL_CTRLA_CMD_WP_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_EAR       (NVMCTRL_CTRLA_CMD_EAR_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WAP       (NVMCTRL_CTRLA_CMD_WAP_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SF        (NVMCTRL_CTRLA_CMD_SF_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WL        (NVMCTRL_CTRLA_CMD_WL_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_LR        (NVMCTRL_CTRLA_CMD_LR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_UR        (NVMCTRL_CTRLA_CMD_UR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SPRM      (NVMCTRL_CTRLA_CMD_SPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_CPRM      (NVMCTRL_CTRLA_CMD_CPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_PBC       (NVMCTRL_CTRLA_CMD_PBC_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SSB       (NVMCTRL_CTRLA_CMD_SSB_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_INVALL    (NVMCTRL_CTRLA_CMD_INVALL_Val  << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLA) Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_Msk     (_U(0xFF) << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX(value)  (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
+#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     _U(0xA5)   /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define NVMCTRL_CTRLA_CMDEX_KEY     (NVMCTRL_CTRLA_CMDEX_KEY_Val   << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_MASK          _U(0xFF7F)   /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t RWS:4;            /*!< bit:  1.. 4  NVM Read Wait States               */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t MANW:1;           /*!< bit:      7  Manual Write                       */
+    uint32_t SLEEPPRM:2;       /*!< bit:  8.. 9  Power Reduction Mode during Sleep  */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t READMODE:2;       /*!< bit: 16..17  NVMCTRL Read Mode                  */
+    uint32_t CACHEDIS:1;       /*!< bit:     18  Cache Disable                      */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE    _U(0x00000000) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_RWS_Pos       1            /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_Msk       (_U(0xF) << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS(value)    (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
+#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    _U(0x0)   /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_HALF_Val      _U(0x1)   /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_DUAL_Val      _U(0x2)   /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_SINGLE    (NVMCTRL_CTRLB_RWS_SINGLE_Val  << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_HALF      (NVMCTRL_CTRLB_RWS_HALF_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_DUAL      (NVMCTRL_CTRLB_RWS_DUAL_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_MANW_Pos      7            /**< \brief (NVMCTRL_CTRLB) Manual Write */
+#define NVMCTRL_CTRLB_MANW          (_U(0x1) << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos  8            /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (_U(0x3) << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val _U(0x0)   /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val _U(0x1)   /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val _U(0x3)   /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_READMODE_Pos  16           /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_Msk  (_U(0x3) << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
+#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val _U(0x0)   /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val _U(0x1)   /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val _U(0x2)   /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_CACHEDIS_Pos  18           /**< \brief (NVMCTRL_CTRLB) Cache Disable */
+#define NVMCTRL_CTRLB_CACHEDIS      (_U(0x1) << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK          _U(0x0007039E) /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
+    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE    _U(0x00000000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk      (_U(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
+#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk       (_U(0x7) << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
+#define   NVMCTRL_PARAM_PSZ_8_Val         _U(0x0)   /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define   NVMCTRL_PARAM_PSZ_16_Val        _U(0x1)   /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define   NVMCTRL_PARAM_PSZ_32_Val        _U(0x2)   /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define   NVMCTRL_PARAM_PSZ_64_Val        _U(0x3)   /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define   NVMCTRL_PARAM_PSZ_128_Val       _U(0x4)   /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define   NVMCTRL_PARAM_PSZ_256_Val       _U(0x5)   /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define   NVMCTRL_PARAM_PSZ_512_Val       _U(0x6)   /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define   NVMCTRL_PARAM_PSZ_1024_Val      _U(0x7)   /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_MASK          _U(0x0007FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE _U(0x00)     /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_READY_Pos  0            /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENCLR_READY      (_U(0x1) << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
+#define NVMCTRL_INTENCLR_ERROR      (_U(0x1) << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK       _U(0x03)     /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET     0x10         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE _U(0x00)     /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_READY_Pos  0            /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENSET_READY      (_U(0x1) << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ERROR      (_U(0x1) << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK       _U(0x03)     /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  READY:1;          /*!< bit:      0  NVM Ready                          */
+    __I uint8_t  ERROR:1;          /*!< bit:      1  Error                              */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET      0x14         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE  _U(0x00)     /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_READY_Pos   0            /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
+#define NVMCTRL_INTFLAG_READY       (_U(0x1) << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_ERROR_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Error */
+#define NVMCTRL_INTFLAG_ERROR       (_U(0x1) << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK        _U(0x03)     /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PRM:1;            /*!< bit:      0  Power Reduction Mode               */
+    uint16_t LOAD:1;           /*!< bit:      1  NVM Page Buffer Active Loading     */
+    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Status           */
+    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Status                  */
+    uint16_t NVME:1;           /*!< bit:      4  NVM Error                          */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t SB:1;             /*!< bit:      8  Security Bit Status                */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET       0x18         /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE   _U(0x0000)   /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_PRM_Pos      0            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM          (_U(0x1) << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos     1            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD         (_U(0x1) << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_PROGE_Pos    2            /**< \brief (NVMCTRL_STATUS) Programming Error Status */
+#define NVMCTRL_STATUS_PROGE        (_U(0x1) << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_LOCKE_Pos    3            /**< \brief (NVMCTRL_STATUS) Lock Error Status */
+#define NVMCTRL_STATUS_LOCKE        (_U(0x1) << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_NVME_Pos     4            /**< \brief (NVMCTRL_STATUS) NVM Error */
+#define NVMCTRL_STATUS_NVME         (_U(0x1) << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_SB_Pos       8            /**< \brief (NVMCTRL_STATUS) Security Bit Status */
+#define NVMCTRL_STATUS_SB           (_U(0x1) << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK         _U(0x011F)   /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:22;          /*!< bit:  0..21  NVM Address                        */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET         0x1C         /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE     _U(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk       (_U(0x3FFFFF) << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
+#define NVMCTRL_ADDR_MASK           _U(0x003FFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LOCK:16;          /*!< bit:  0..15  Region Lock Bits                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_LOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_LOCK_OFFSET         0x20         /**< \brief (NVMCTRL_LOCK offset) Lock Section */
+
+#define NVMCTRL_LOCK_LOCK_Pos       0            /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
+#define NVMCTRL_LOCK_LOCK_Msk       (_U(0xFFFF) << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK(value)    (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
+#define NVMCTRL_LOCK_MASK           _U(0xFFFF)   /**< \brief (NVMCTRL_LOCK) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+       RoReg8                    Reserved1[0x2];
+  __IO NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
+  __IO NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x3];
+  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x10 (R/W  8) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x3];
+  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x14 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x3];
+  __IO NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x18 (R/W 16) Status */
+       RoReg8                    Reserved5[0x2];
+  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x1C (R/W 32) Address */
+  __IO NVMCTRL_LOCK_Type         LOCK;        /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_NVMCTRL_CAL
+
+#define SECTION_NVMCTRL_LOCKBIT
+
+#define SECTION_NVMCTRL_OTP1
+
+#define SECTION_NVMCTRL_OTP2
+
+#define SECTION_NVMCTRL_OTP4
+
+#define SECTION_NVMCTRL_TEMP_LOG
+
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define ADC_FUSES_BIASCAL_ADDR      (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_BIASCAL_Pos       3            /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
+#define ADC_FUSES_BIASCAL_Msk       (_U(0x7) << ADC_FUSES_BIASCAL_Pos)
+#define ADC_FUSES_BIASCAL(value)    (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
+
+#define ADC_FUSES_LINEARITY_0_ADDR  NVMCTRL_OTP4
+#define ADC_FUSES_LINEARITY_0_Pos   27           /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
+#define ADC_FUSES_LINEARITY_0_Msk   (_U(0x1F) << ADC_FUSES_LINEARITY_0_Pos)
+#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
+
+#define ADC_FUSES_LINEARITY_1_ADDR  (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_LINEARITY_1_Pos   0            /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
+#define ADC_FUSES_LINEARITY_1_Msk   (_U(0x7) << ADC_FUSES_LINEARITY_1_Pos)
+#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
+
+#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos    8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk    (_U(0x3F) << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
+
+#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos      15           /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk      (_U(0x3) << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
+
+#define FUSES_BOD33_EN_ADDR         NVMCTRL_USER
+#define FUSES_BOD33_EN_Pos          14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define FUSES_BOD33_EN_Msk          (_U(0x1) << FUSES_BOD33_EN_Pos)
+
+#define FUSES_BOD33_HYST_ADDR       (NVMCTRL_USER + 4)
+#define FUSES_BOD33_HYST_Pos        8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk        (_U(0x1) << FUSES_BOD33_HYST_Pos)
+
+#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define FUSES_DFLL48M_COARSE_CAL_Msk (_U(0x3F) << FUSES_DFLL48M_COARSE_CAL_Pos)
+#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
+
+#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
+#define FUSES_DFLL48M_FINE_CAL_Pos  0            /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
+#define FUSES_DFLL48M_FINE_CAL_Msk  (_U(0x3FF) << FUSES_DFLL48M_FINE_CAL_Pos)
+#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
+
+#define FUSES_HOT_ADC_VAL_ADDR      (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_ADC_VAL_Pos       20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define FUSES_HOT_ADC_VAL_Msk       (_U(0xFFF) << FUSES_HOT_ADC_VAL_Pos)
+#define FUSES_HOT_ADC_VAL(value)    (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
+
+#define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define FUSES_HOT_INT1V_VAL_Msk     (_U(0xFF) << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
+
+#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define FUSES_HOT_TEMP_VAL_DEC_Msk  (_U(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
+
+#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define FUSES_HOT_TEMP_VAL_INT_Msk  (_U(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
+
+#define FUSES_OSC32K_CAL_ADDR       (NVMCTRL_OTP4 + 4)
+#define FUSES_OSC32K_CAL_Pos        6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define FUSES_OSC32K_CAL_Msk        (_U(0x7F) << FUSES_OSC32K_CAL_Pos)
+#define FUSES_OSC32K_CAL(value)     (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
+
+#define FUSES_ROOM_ADC_VAL_ADDR     (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_ROOM_ADC_VAL_Pos      8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define FUSES_ROOM_ADC_VAL_Msk      (_U(0xFFF) << FUSES_ROOM_ADC_VAL_Pos)
+#define FUSES_ROOM_ADC_VAL(value)   (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
+
+#define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define FUSES_ROOM_INT1V_VAL_Msk    (_U(0xFF) << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (_U(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos  0            /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk  (_U(0x7) << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
+
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4            /**< \brief (NVMCTRL_USER) EEPROM Size */
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (_U(0x7) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
+
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16           /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U(0xFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
+
+#define USB_FUSES_TRANSN_ADDR       (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSN_Pos        13           /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk        (_U(0x1F) << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
+
+#define USB_FUSES_TRANSP_ADDR       (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSP_Pos        18           /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk        (_U(0x1F) << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
+
+#define USB_FUSES_TRIM_ADDR         (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRIM_Pos          23           /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk          (_U(0x7) << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
+
+#define WDT_FUSES_ALWAYSON_ADDR     NVMCTRL_USER
+#define WDT_FUSES_ALWAYSON_Pos      26           /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk      (_U(0x1) << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR       NVMCTRL_USER
+#define WDT_FUSES_ENABLE_Pos        25           /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk        (_U(0x1) << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos      3            /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk      (_U(0xF) << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
+
+#define WDT_FUSES_PER_ADDR          NVMCTRL_USER
+#define WDT_FUSES_PER_Pos           27           /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk           (_U(0xF) << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
+
+#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos           7            /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk           (_U(0x1) << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_0_ADDR     NVMCTRL_USER
+#define WDT_FUSES_WINDOW_0_Pos      31           /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
+#define WDT_FUSES_WINDOW_0_Msk      (_U(0x1) << WDT_FUSES_WINDOW_0_Pos)
+
+#define WDT_FUSES_WINDOW_1_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_1_Pos      0            /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
+#define WDT_FUSES_WINDOW_1_Msk      (_U(0x7) << WDT_FUSES_WINDOW_1_Pos)
+#define WDT_FUSES_WINDOW_1(value)   (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
+
+/*@}*/
+
+#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/pac.h b/uf2-samdx1/lib/samd21/samd21a/include/component/pac.h
new file mode 100644
index 00000000..56a4d6aa
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/pac.h
@@ -0,0 +1,89 @@
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC_COMPONENT_
+#define _SAMD21_PAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2211
+#define REV_PAC                     0x101
+
+/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Clear             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WPCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPCLR_OFFSET            0x0          /**< \brief (PAC_WPCLR offset) Write Protection Clear */
+#define PAC_WPCLR_RESETVALUE        _U(0x00000000) /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
+
+#define PAC_WPCLR_WP_Pos            1            /**< \brief (PAC_WPCLR) Write Protection Clear */
+#define PAC_WPCLR_WP_Msk            (_U(0x7FFFFFFF) << PAC_WPCLR_WP_Pos)
+#define PAC_WPCLR_WP(value)         (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
+#define PAC_WPCLR_MASK              _U(0xFFFFFFFE) /**< \brief (PAC_WPCLR) MASK Register */
+
+/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t WP:31;            /*!< bit:  1..31  Write Protection Set               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WPSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPSET_OFFSET            0x4          /**< \brief (PAC_WPSET offset) Write Protection Set */
+#define PAC_WPSET_RESETVALUE        _U(0x00000000) /**< \brief (PAC_WPSET reset_value) Write Protection Set */
+
+#define PAC_WPSET_WP_Pos            1            /**< \brief (PAC_WPSET) Write Protection Set */
+#define PAC_WPSET_WP_Msk            (_U(0x7FFFFFFF) << PAC_WPSET_WP_Pos)
+#define PAC_WPSET_WP(value)         (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
+#define PAC_WPSET_MASK              _U(0xFFFFFFFE) /**< \brief (PAC_WPSET) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PAC_WPCLR_Type            WPCLR;       /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+  __IO PAC_WPSET_Type            WPSET;       /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PAC_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/pm.h b/uf2-samdx1/lib/samd21/samd21a/include/component/pm.h
new file mode 100644
index 00000000..b504e7e4
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/pm.h
@@ -0,0 +1,518 @@
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_COMPONENT_
+#define _SAMD21_PM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PM Power Manager */
+/*@{*/
+
+#define PM_U2206
+#define REV_PM                      0x201
+
+/* -------- PM_CTRL : (PM Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRL_OFFSET              0x00         /**< \brief (PM_CTRL offset) Control */
+#define PM_CTRL_RESETVALUE          _U(0x00)     /**< \brief (PM_CTRL reset_value) Control */
+
+#define PM_CTRL_MASK                _U(0x00)     /**< \brief (PM_CTRL) MASK Register */
+
+/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W  8) Sleep Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  IDLE:2;           /*!< bit:  0.. 1  Idle Mode Configuration            */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_SLEEP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEP_OFFSET             0x01         /**< \brief (PM_SLEEP offset) Sleep Mode */
+#define PM_SLEEP_RESETVALUE         _U(0x00)     /**< \brief (PM_SLEEP reset_value) Sleep Mode */
+
+#define PM_SLEEP_IDLE_Pos           0            /**< \brief (PM_SLEEP) Idle Mode Configuration */
+#define PM_SLEEP_IDLE_Msk           (_U(0x3) << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE(value)        (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
+#define   PM_SLEEP_IDLE_CPU_Val           _U(0x0)   /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
+#define   PM_SLEEP_IDLE_AHB_Val           _U(0x1)   /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
+#define   PM_SLEEP_IDLE_APB_Val           _U(0x2)   /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
+#define PM_SLEEP_IDLE_CPU           (PM_SLEEP_IDLE_CPU_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_AHB           (PM_SLEEP_IDLE_AHB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_APB           (PM_SLEEP_IDLE_APB_Val         << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_MASK               _U(0x03)     /**< \brief (PM_SLEEP) MASK Register */
+
+/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W  8) CPU Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CPUDIV:3;         /*!< bit:  0.. 2  CPU Prescaler Selection            */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CPUSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CPUSEL_OFFSET            0x08         /**< \brief (PM_CPUSEL offset) CPU Clock Select */
+#define PM_CPUSEL_RESETVALUE        _U(0x00)     /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
+
+#define PM_CPUSEL_CPUDIV_Pos        0            /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
+#define PM_CPUSEL_CPUDIV_Msk        (_U(0x7) << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV(value)     (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
+#define   PM_CPUSEL_CPUDIV_DIV1_Val       _U(0x0)   /**< \brief (PM_CPUSEL) Divide by 1 */
+#define   PM_CPUSEL_CPUDIV_DIV2_Val       _U(0x1)   /**< \brief (PM_CPUSEL) Divide by 2 */
+#define   PM_CPUSEL_CPUDIV_DIV4_Val       _U(0x2)   /**< \brief (PM_CPUSEL) Divide by 4 */
+#define   PM_CPUSEL_CPUDIV_DIV8_Val       _U(0x3)   /**< \brief (PM_CPUSEL) Divide by 8 */
+#define   PM_CPUSEL_CPUDIV_DIV16_Val      _U(0x4)   /**< \brief (PM_CPUSEL) Divide by 16 */
+#define   PM_CPUSEL_CPUDIV_DIV32_Val      _U(0x5)   /**< \brief (PM_CPUSEL) Divide by 32 */
+#define   PM_CPUSEL_CPUDIV_DIV64_Val      _U(0x6)   /**< \brief (PM_CPUSEL) Divide by 64 */
+#define   PM_CPUSEL_CPUDIV_DIV128_Val     _U(0x7)   /**< \brief (PM_CPUSEL) Divide by 128 */
+#define PM_CPUSEL_CPUDIV_DIV1       (PM_CPUSEL_CPUDIV_DIV1_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV2       (PM_CPUSEL_CPUDIV_DIV2_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV4       (PM_CPUSEL_CPUDIV_DIV4_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV8       (PM_CPUSEL_CPUDIV_DIV8_Val     << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV16      (PM_CPUSEL_CPUDIV_DIV16_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV32      (PM_CPUSEL_CPUDIV_DIV32_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV64      (PM_CPUSEL_CPUDIV_DIV64_Val    << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV128     (PM_CPUSEL_CPUDIV_DIV128_Val   << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_MASK              _U(0x07)     /**< \brief (PM_CPUSEL) MASK Register */
+
+/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W  8) APBA Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBADIV:3;        /*!< bit:  0.. 2  APBA Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBASEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBASEL_OFFSET           0x09         /**< \brief (PM_APBASEL offset) APBA Clock Select */
+#define PM_APBASEL_RESETVALUE       _U(0x00)     /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
+
+#define PM_APBASEL_APBADIV_Pos      0            /**< \brief (PM_APBASEL) APBA Prescaler Selection */
+#define PM_APBASEL_APBADIV_Msk      (_U(0x7) << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV(value)   (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
+#define   PM_APBASEL_APBADIV_DIV1_Val     _U(0x0)   /**< \brief (PM_APBASEL) Divide by 1 */
+#define   PM_APBASEL_APBADIV_DIV2_Val     _U(0x1)   /**< \brief (PM_APBASEL) Divide by 2 */
+#define   PM_APBASEL_APBADIV_DIV4_Val     _U(0x2)   /**< \brief (PM_APBASEL) Divide by 4 */
+#define   PM_APBASEL_APBADIV_DIV8_Val     _U(0x3)   /**< \brief (PM_APBASEL) Divide by 8 */
+#define   PM_APBASEL_APBADIV_DIV16_Val    _U(0x4)   /**< \brief (PM_APBASEL) Divide by 16 */
+#define   PM_APBASEL_APBADIV_DIV32_Val    _U(0x5)   /**< \brief (PM_APBASEL) Divide by 32 */
+#define   PM_APBASEL_APBADIV_DIV64_Val    _U(0x6)   /**< \brief (PM_APBASEL) Divide by 64 */
+#define   PM_APBASEL_APBADIV_DIV128_Val   _U(0x7)   /**< \brief (PM_APBASEL) Divide by 128 */
+#define PM_APBASEL_APBADIV_DIV1     (PM_APBASEL_APBADIV_DIV1_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV2     (PM_APBASEL_APBADIV_DIV2_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV4     (PM_APBASEL_APBADIV_DIV4_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV8     (PM_APBASEL_APBADIV_DIV8_Val   << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV16    (PM_APBASEL_APBADIV_DIV16_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV32    (PM_APBASEL_APBADIV_DIV32_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV64    (PM_APBASEL_APBADIV_DIV64_Val  << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV128   (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_MASK             _U(0x07)     /**< \brief (PM_APBASEL) MASK Register */
+
+/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W  8) APBB Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBBDIV:3;        /*!< bit:  0.. 2  APBB Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBBSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBSEL_OFFSET           0x0A         /**< \brief (PM_APBBSEL offset) APBB Clock Select */
+#define PM_APBBSEL_RESETVALUE       _U(0x00)     /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
+
+#define PM_APBBSEL_APBBDIV_Pos      0            /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
+#define PM_APBBSEL_APBBDIV_Msk      (_U(0x7) << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV(value)   (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
+#define   PM_APBBSEL_APBBDIV_DIV1_Val     _U(0x0)   /**< \brief (PM_APBBSEL) Divide by 1 */
+#define   PM_APBBSEL_APBBDIV_DIV2_Val     _U(0x1)   /**< \brief (PM_APBBSEL) Divide by 2 */
+#define   PM_APBBSEL_APBBDIV_DIV4_Val     _U(0x2)   /**< \brief (PM_APBBSEL) Divide by 4 */
+#define   PM_APBBSEL_APBBDIV_DIV8_Val     _U(0x3)   /**< \brief (PM_APBBSEL) Divide by 8 */
+#define   PM_APBBSEL_APBBDIV_DIV16_Val    _U(0x4)   /**< \brief (PM_APBBSEL) Divide by 16 */
+#define   PM_APBBSEL_APBBDIV_DIV32_Val    _U(0x5)   /**< \brief (PM_APBBSEL) Divide by 32 */
+#define   PM_APBBSEL_APBBDIV_DIV64_Val    _U(0x6)   /**< \brief (PM_APBBSEL) Divide by 64 */
+#define   PM_APBBSEL_APBBDIV_DIV128_Val   _U(0x7)   /**< \brief (PM_APBBSEL) Divide by 128 */
+#define PM_APBBSEL_APBBDIV_DIV1     (PM_APBBSEL_APBBDIV_DIV1_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV2     (PM_APBBSEL_APBBDIV_DIV2_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV4     (PM_APBBSEL_APBBDIV_DIV4_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV8     (PM_APBBSEL_APBBDIV_DIV8_Val   << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV16    (PM_APBBSEL_APBBDIV_DIV16_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV32    (PM_APBBSEL_APBBDIV_DIV32_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV64    (PM_APBBSEL_APBBDIV_DIV64_Val  << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV128   (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_MASK             _U(0x07)     /**< \brief (PM_APBBSEL) MASK Register */
+
+/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W  8) APBC Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  APBCDIV:3;        /*!< bit:  0.. 2  APBC Prescaler Selection           */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_APBCSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCSEL_OFFSET           0x0B         /**< \brief (PM_APBCSEL offset) APBC Clock Select */
+#define PM_APBCSEL_RESETVALUE       _U(0x00)     /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
+
+#define PM_APBCSEL_APBCDIV_Pos      0            /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
+#define PM_APBCSEL_APBCDIV_Msk      (_U(0x7) << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV(value)   (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
+#define   PM_APBCSEL_APBCDIV_DIV1_Val     _U(0x0)   /**< \brief (PM_APBCSEL) Divide by 1 */
+#define   PM_APBCSEL_APBCDIV_DIV2_Val     _U(0x1)   /**< \brief (PM_APBCSEL) Divide by 2 */
+#define   PM_APBCSEL_APBCDIV_DIV4_Val     _U(0x2)   /**< \brief (PM_APBCSEL) Divide by 4 */
+#define   PM_APBCSEL_APBCDIV_DIV8_Val     _U(0x3)   /**< \brief (PM_APBCSEL) Divide by 8 */
+#define   PM_APBCSEL_APBCDIV_DIV16_Val    _U(0x4)   /**< \brief (PM_APBCSEL) Divide by 16 */
+#define   PM_APBCSEL_APBCDIV_DIV32_Val    _U(0x5)   /**< \brief (PM_APBCSEL) Divide by 32 */
+#define   PM_APBCSEL_APBCDIV_DIV64_Val    _U(0x6)   /**< \brief (PM_APBCSEL) Divide by 64 */
+#define   PM_APBCSEL_APBCDIV_DIV128_Val   _U(0x7)   /**< \brief (PM_APBCSEL) Divide by 128 */
+#define PM_APBCSEL_APBCDIV_DIV1     (PM_APBCSEL_APBCDIV_DIV1_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV2     (PM_APBCSEL_APBCDIV_DIV2_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV4     (PM_APBCSEL_APBCDIV_DIV4_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV8     (PM_APBCSEL_APBCDIV_DIV8_Val   << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV16    (PM_APBCSEL_APBCDIV_DIV16_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV32    (PM_APBCSEL_APBCDIV_DIV32_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV64    (PM_APBCSEL_APBCDIV_DIV64_Val  << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV128   (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_MASK             _U(0x07)     /**< \brief (PM_APBCSEL) MASK Register */
+
+/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
+    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
+    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
+    uint32_t DSU_:1;           /*!< bit:      3  DSU AHB Clock Mask                 */
+    uint32_t NVMCTRL_:1;       /*!< bit:      4  NVMCTRL AHB Clock Mask             */
+    uint32_t DMAC_:1;          /*!< bit:      5  DMAC AHB Clock Mask                */
+    uint32_t USB_:1;           /*!< bit:      6  USB AHB Clock Mask                 */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_AHBMASK_OFFSET           0x14         /**< \brief (PM_AHBMASK offset) AHB Mask */
+#define PM_AHBMASK_RESETVALUE       _U(0x0000007F) /**< \brief (PM_AHBMASK reset_value) AHB Mask */
+
+#define PM_AHBMASK_HPB0_Pos         0            /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
+#define PM_AHBMASK_HPB0             (_U(0x1) << PM_AHBMASK_HPB0_Pos)
+#define PM_AHBMASK_HPB1_Pos         1            /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
+#define PM_AHBMASK_HPB1             (_U(0x1) << PM_AHBMASK_HPB1_Pos)
+#define PM_AHBMASK_HPB2_Pos         2            /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
+#define PM_AHBMASK_HPB2             (_U(0x1) << PM_AHBMASK_HPB2_Pos)
+#define PM_AHBMASK_DSU_Pos          3            /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
+#define PM_AHBMASK_DSU              (_U(0x1) << PM_AHBMASK_DSU_Pos)
+#define PM_AHBMASK_NVMCTRL_Pos      4            /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
+#define PM_AHBMASK_NVMCTRL          (_U(0x1) << PM_AHBMASK_NVMCTRL_Pos)
+#define PM_AHBMASK_DMAC_Pos         5            /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
+#define PM_AHBMASK_DMAC             (_U(0x1) << PM_AHBMASK_DMAC_Pos)
+#define PM_AHBMASK_USB_Pos          6            /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
+#define PM_AHBMASK_USB              (_U(0x1) << PM_AHBMASK_USB_Pos)
+#define PM_AHBMASK_MASK             _U(0x0000007F) /**< \brief (PM_AHBMASK) MASK Register */
+
+/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC0_:1;          /*!< bit:      0  PAC0 APB Clock Enable              */
+    uint32_t PM_:1;            /*!< bit:      1  PM APB Clock Enable                */
+    uint32_t SYSCTRL_:1;       /*!< bit:      2  SYSCTRL APB Clock Enable           */
+    uint32_t GCLK_:1;          /*!< bit:      3  GCLK APB Clock Enable              */
+    uint32_t WDT_:1;           /*!< bit:      4  WDT APB Clock Enable               */
+    uint32_t RTC_:1;           /*!< bit:      5  RTC APB Clock Enable               */
+    uint32_t EIC_:1;           /*!< bit:      6  EIC APB Clock Enable               */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBAMASK_OFFSET          0x18         /**< \brief (PM_APBAMASK offset) APBA Mask */
+#define PM_APBAMASK_RESETVALUE      _U(0x0000007F) /**< \brief (PM_APBAMASK reset_value) APBA Mask */
+
+#define PM_APBAMASK_PAC0_Pos        0            /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
+#define PM_APBAMASK_PAC0            (_U(0x1) << PM_APBAMASK_PAC0_Pos)
+#define PM_APBAMASK_PM_Pos          1            /**< \brief (PM_APBAMASK) PM APB Clock Enable */
+#define PM_APBAMASK_PM              (_U(0x1) << PM_APBAMASK_PM_Pos)
+#define PM_APBAMASK_SYSCTRL_Pos     2            /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
+#define PM_APBAMASK_SYSCTRL         (_U(0x1) << PM_APBAMASK_SYSCTRL_Pos)
+#define PM_APBAMASK_GCLK_Pos        3            /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
+#define PM_APBAMASK_GCLK            (_U(0x1) << PM_APBAMASK_GCLK_Pos)
+#define PM_APBAMASK_WDT_Pos         4            /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
+#define PM_APBAMASK_WDT             (_U(0x1) << PM_APBAMASK_WDT_Pos)
+#define PM_APBAMASK_RTC_Pos         5            /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
+#define PM_APBAMASK_RTC             (_U(0x1) << PM_APBAMASK_RTC_Pos)
+#define PM_APBAMASK_EIC_Pos         6            /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
+#define PM_APBAMASK_EIC             (_U(0x1) << PM_APBAMASK_EIC_Pos)
+#define PM_APBAMASK_MASK            _U(0x0000007F) /**< \brief (PM_APBAMASK) MASK Register */
+
+/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC1_:1;          /*!< bit:      0  PAC1 APB Clock Enable              */
+    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
+    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
+    uint32_t PORT_:1;          /*!< bit:      3  PORT APB Clock Enable              */
+    uint32_t DMAC_:1;          /*!< bit:      4  DMAC APB Clock Enable              */
+    uint32_t USB_:1;           /*!< bit:      5  USB APB Clock Enable               */
+    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Clock Enable           */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBMASK_OFFSET          0x1C         /**< \brief (PM_APBBMASK offset) APBB Mask */
+#define PM_APBBMASK_RESETVALUE      _U(0x0000007F) /**< \brief (PM_APBBMASK reset_value) APBB Mask */
+
+#define PM_APBBMASK_PAC1_Pos        0            /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
+#define PM_APBBMASK_PAC1            (_U(0x1) << PM_APBBMASK_PAC1_Pos)
+#define PM_APBBMASK_DSU_Pos         1            /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
+#define PM_APBBMASK_DSU             (_U(0x1) << PM_APBBMASK_DSU_Pos)
+#define PM_APBBMASK_NVMCTRL_Pos     2            /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
+#define PM_APBBMASK_NVMCTRL         (_U(0x1) << PM_APBBMASK_NVMCTRL_Pos)
+#define PM_APBBMASK_PORT_Pos        3            /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
+#define PM_APBBMASK_PORT            (_U(0x1) << PM_APBBMASK_PORT_Pos)
+#define PM_APBBMASK_DMAC_Pos        4            /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
+#define PM_APBBMASK_DMAC            (_U(0x1) << PM_APBBMASK_DMAC_Pos)
+#define PM_APBBMASK_USB_Pos         5            /**< \brief (PM_APBBMASK) USB APB Clock Enable */
+#define PM_APBBMASK_USB             (_U(0x1) << PM_APBBMASK_USB_Pos)
+#define PM_APBBMASK_HMATRIX_Pos     6            /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
+#define PM_APBBMASK_HMATRIX         (_U(0x1) << PM_APBBMASK_HMATRIX_Pos)
+#define PM_APBBMASK_MASK            _U(0x0000007F) /**< \brief (PM_APBBMASK) MASK Register */
+
+/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC2_:1;          /*!< bit:      0  PAC2 APB Clock Enable              */
+    uint32_t EVSYS_:1;         /*!< bit:      1  EVSYS APB Clock Enable             */
+    uint32_t SERCOM0_:1;       /*!< bit:      2  SERCOM0 APB Clock Enable           */
+    uint32_t SERCOM1_:1;       /*!< bit:      3  SERCOM1 APB Clock Enable           */
+    uint32_t SERCOM2_:1;       /*!< bit:      4  SERCOM2 APB Clock Enable           */
+    uint32_t SERCOM3_:1;       /*!< bit:      5  SERCOM3 APB Clock Enable           */
+    uint32_t SERCOM4_:1;       /*!< bit:      6  SERCOM4 APB Clock Enable           */
+    uint32_t SERCOM5_:1;       /*!< bit:      7  SERCOM5 APB Clock Enable           */
+    uint32_t TCC0_:1;          /*!< bit:      8  TCC0 APB Clock Enable              */
+    uint32_t TCC1_:1;          /*!< bit:      9  TCC1 APB Clock Enable              */
+    uint32_t TCC2_:1;          /*!< bit:     10  TCC2 APB Clock Enable              */
+    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Clock Enable               */
+    uint32_t TC4_:1;           /*!< bit:     12  TC4 APB Clock Enable               */
+    uint32_t TC5_:1;           /*!< bit:     13  TC5 APB Clock Enable               */
+    uint32_t TC6_:1;           /*!< bit:     14  TC6 APB Clock Enable               */
+    uint32_t TC7_:1;           /*!< bit:     15  TC7 APB Clock Enable               */
+    uint32_t ADC_:1;           /*!< bit:     16  ADC APB Clock Enable               */
+    uint32_t AC_:1;            /*!< bit:     17  AC APB Clock Enable                */
+    uint32_t DAC_:1;           /*!< bit:     18  DAC APB Clock Enable               */
+    uint32_t PTC_:1;           /*!< bit:     19  PTC APB Clock Enable               */
+    uint32_t I2S_:1;           /*!< bit:     20  I2S APB Clock Enable               */
+    uint32_t :11;              /*!< bit: 21..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PM_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCMASK_OFFSET          0x20         /**< \brief (PM_APBCMASK offset) APBC Mask */
+#define PM_APBCMASK_RESETVALUE      _U(0x00010000) /**< \brief (PM_APBCMASK reset_value) APBC Mask */
+
+#define PM_APBCMASK_PAC2_Pos        0            /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
+#define PM_APBCMASK_PAC2            (_U(0x1) << PM_APBCMASK_PAC2_Pos)
+#define PM_APBCMASK_EVSYS_Pos       1            /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
+#define PM_APBCMASK_EVSYS           (_U(0x1) << PM_APBCMASK_EVSYS_Pos)
+#define PM_APBCMASK_SERCOM0_Pos     2            /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
+#define PM_APBCMASK_SERCOM0         (_U(0x1) << PM_APBCMASK_SERCOM0_Pos)
+#define PM_APBCMASK_SERCOM1_Pos     3            /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
+#define PM_APBCMASK_SERCOM1         (_U(0x1) << PM_APBCMASK_SERCOM1_Pos)
+#define PM_APBCMASK_SERCOM2_Pos     4            /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
+#define PM_APBCMASK_SERCOM2         (_U(0x1) << PM_APBCMASK_SERCOM2_Pos)
+#define PM_APBCMASK_SERCOM3_Pos     5            /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
+#define PM_APBCMASK_SERCOM3         (_U(0x1) << PM_APBCMASK_SERCOM3_Pos)
+#define PM_APBCMASK_SERCOM4_Pos     6            /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
+#define PM_APBCMASK_SERCOM4         (_U(0x1) << PM_APBCMASK_SERCOM4_Pos)
+#define PM_APBCMASK_SERCOM5_Pos     7            /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
+#define PM_APBCMASK_SERCOM5         (_U(0x1) << PM_APBCMASK_SERCOM5_Pos)
+#define PM_APBCMASK_TCC0_Pos        8            /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
+#define PM_APBCMASK_TCC0            (_U(0x1) << PM_APBCMASK_TCC0_Pos)
+#define PM_APBCMASK_TCC1_Pos        9            /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
+#define PM_APBCMASK_TCC1            (_U(0x1) << PM_APBCMASK_TCC1_Pos)
+#define PM_APBCMASK_TCC2_Pos        10           /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
+#define PM_APBCMASK_TCC2            (_U(0x1) << PM_APBCMASK_TCC2_Pos)
+#define PM_APBCMASK_TC3_Pos         11           /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
+#define PM_APBCMASK_TC3             (_U(0x1) << PM_APBCMASK_TC3_Pos)
+#define PM_APBCMASK_TC4_Pos         12           /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
+#define PM_APBCMASK_TC4             (_U(0x1) << PM_APBCMASK_TC4_Pos)
+#define PM_APBCMASK_TC5_Pos         13           /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
+#define PM_APBCMASK_TC5             (_U(0x1) << PM_APBCMASK_TC5_Pos)
+#define PM_APBCMASK_TC6_Pos         14           /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
+#define PM_APBCMASK_TC6             (_U(0x1) << PM_APBCMASK_TC6_Pos)
+#define PM_APBCMASK_TC7_Pos         15           /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
+#define PM_APBCMASK_TC7             (_U(0x1) << PM_APBCMASK_TC7_Pos)
+#define PM_APBCMASK_ADC_Pos         16           /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
+#define PM_APBCMASK_ADC             (_U(0x1) << PM_APBCMASK_ADC_Pos)
+#define PM_APBCMASK_AC_Pos          17           /**< \brief (PM_APBCMASK) AC APB Clock Enable */
+#define PM_APBCMASK_AC              (_U(0x1) << PM_APBCMASK_AC_Pos)
+#define PM_APBCMASK_DAC_Pos         18           /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
+#define PM_APBCMASK_DAC             (_U(0x1) << PM_APBCMASK_DAC_Pos)
+#define PM_APBCMASK_PTC_Pos         19           /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
+#define PM_APBCMASK_PTC             (_U(0x1) << PM_APBCMASK_PTC_Pos)
+#define PM_APBCMASK_I2S_Pos         20           /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
+#define PM_APBCMASK_I2S             (_U(0x1) << PM_APBCMASK_I2S_Pos)
+#define PM_APBCMASK_MASK            _U(0x001FFFFF) /**< \brief (PM_APBCMASK) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET          0x34         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE      _U(0x00)     /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_CKRDY_Pos       0            /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
+#define PM_INTENCLR_CKRDY           (_U(0x1) << PM_INTENCLR_CKRDY_Pos)
+#define PM_INTENCLR_MASK            _U(0x01)     /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET          0x35         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE      _U(0x00)     /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_CKRDY_Pos       0            /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
+#define PM_INTENSET_CKRDY           (_U(0x1) << PM_INTENSET_CKRDY_Pos)
+#define PM_INTENSET_MASK            _U(0x01)     /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET           0x36         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE       _U(0x00)     /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_CKRDY_Pos        0            /**< \brief (PM_INTFLAG) Clock Ready */
+#define PM_INTFLAG_CKRDY            (_U(0x1) << PM_INTFLAG_CKRDY_Pos)
+#define PM_INTFLAG_MASK             _U(0x01)     /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/   8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  POR:1;            /*!< bit:      0  Power On Reset                     */
+    uint8_t  BOD12:1;          /*!< bit:      1  Brown Out 12 Detector Reset        */
+    uint8_t  BOD33:1;          /*!< bit:      2  Brown Out 33 Detector Reset        */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EXT:1;            /*!< bit:      4  External Reset                     */
+    uint8_t  WDT:1;            /*!< bit:      5  Watchdog Reset                     */
+    uint8_t  SYST:1;           /*!< bit:      6  System Reset Request               */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_RCAUSE_OFFSET            0x38         /**< \brief (PM_RCAUSE offset) Reset Cause */
+#define PM_RCAUSE_RESETVALUE        _U(0x01)     /**< \brief (PM_RCAUSE reset_value) Reset Cause */
+
+#define PM_RCAUSE_POR_Pos           0            /**< \brief (PM_RCAUSE) Power On Reset */
+#define PM_RCAUSE_POR               (_U(0x1) << PM_RCAUSE_POR_Pos)
+#define PM_RCAUSE_BOD12_Pos         1            /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
+#define PM_RCAUSE_BOD12             (_U(0x1) << PM_RCAUSE_BOD12_Pos)
+#define PM_RCAUSE_BOD33_Pos         2            /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
+#define PM_RCAUSE_BOD33             (_U(0x1) << PM_RCAUSE_BOD33_Pos)
+#define PM_RCAUSE_EXT_Pos           4            /**< \brief (PM_RCAUSE) External Reset */
+#define PM_RCAUSE_EXT               (_U(0x1) << PM_RCAUSE_EXT_Pos)
+#define PM_RCAUSE_WDT_Pos           5            /**< \brief (PM_RCAUSE) Watchdog Reset */
+#define PM_RCAUSE_WDT               (_U(0x1) << PM_RCAUSE_WDT_Pos)
+#define PM_RCAUSE_SYST_Pos          6            /**< \brief (PM_RCAUSE) System Reset Request */
+#define PM_RCAUSE_SYST              (_U(0x1) << PM_RCAUSE_SYST_Pos)
+#define PM_RCAUSE_MASK              _U(0x77)     /**< \brief (PM_RCAUSE) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PM_CTRL_Type              CTRL;        /**< \brief Offset: 0x00 (R/W  8) Control */
+  __IO PM_SLEEP_Type             SLEEP;       /**< \brief Offset: 0x01 (R/W  8) Sleep Mode */
+       RoReg8                    Reserved1[0x6];
+  __IO PM_CPUSEL_Type            CPUSEL;      /**< \brief Offset: 0x08 (R/W  8) CPU Clock Select */
+  __IO PM_APBASEL_Type           APBASEL;     /**< \brief Offset: 0x09 (R/W  8) APBA Clock Select */
+  __IO PM_APBBSEL_Type           APBBSEL;     /**< \brief Offset: 0x0A (R/W  8) APBB Clock Select */
+  __IO PM_APBCSEL_Type           APBCSEL;     /**< \brief Offset: 0x0B (R/W  8) APBC Clock Select */
+       RoReg8                    Reserved2[0x8];
+  __IO PM_AHBMASK_Type           AHBMASK;     /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+  __IO PM_APBAMASK_Type          APBAMASK;    /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+  __IO PM_APBBMASK_Type          APBBMASK;    /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+  __IO PM_APBCMASK_Type          APBCMASK;    /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+       RoReg8                    Reserved3[0x10];
+  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x34 (R/W  8) Interrupt Enable Clear */
+  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x35 (R/W  8) Interrupt Enable Set */
+  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x36 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __I  PM_RCAUSE_Type            RCAUSE;      /**< \brief Offset: 0x38 (R/   8) Reset Cause */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PM_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/port.h b/uf2-samdx1/lib/samd21/samd21a/include/component/port.h
new file mode 100644
index 00000000..ae6e37b7
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/port.h
@@ -0,0 +1,379 @@
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_COMPONENT_
+#define _SAMD21_PORT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT                    0x100
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIR:32;           /*!< bit:  0..31  Port Data Direction                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET             0x00         /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE         _U(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos            0            /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk            (_U(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value)         (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
+#define PORT_DIR_MASK               _U(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRCLR:32;        /*!< bit:  0..31  Port Data Direction Clear          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET          0x04         /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE      _U(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos      0            /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk      (_U(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value)   (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
+#define PORT_DIRCLR_MASK            _U(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRSET:32;        /*!< bit:  0..31  Port Data Direction Set            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET          0x08         /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE      _U(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos      0            /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk      (_U(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value)   (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
+#define PORT_DIRSET_MASK            _U(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRTGL:32;        /*!< bit:  0..31  Port Data Direction Toggle         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET          0x0C         /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE      _U(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos      0            /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk      (_U(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value)   (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
+#define PORT_DIRTGL_MASK            _U(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUT:32;           /*!< bit:  0..31  Port Data Output Value             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET             0x10         /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE         _U(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos            0            /**< \brief (PORT_OUT) Port Data Output Value */
+#define PORT_OUT_OUT_Msk            (_U(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value)         (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
+#define PORT_OUT_MASK               _U(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTCLR:32;        /*!< bit:  0..31  Port Data Output Value Clear       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET          0x14         /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE      _U(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos      0            /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk      (_U(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value)   (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
+#define PORT_OUTCLR_MASK            _U(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTSET:32;        /*!< bit:  0..31  Port Data Output Value Set         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET          0x18         /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE      _U(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos      0            /**< \brief (PORT_OUTSET) Port Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk      (_U(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value)   (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
+#define PORT_OUTSET_MASK            _U(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTTGL:32;        /*!< bit:  0..31  Port Data Output Value Toggle      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET          0x1C         /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE      _U(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos      0            /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk      (_U(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value)   (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
+#define PORT_OUTTGL_MASK            _U(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/  32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t IN:32;            /*!< bit:  0..31  Port Data Input Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET              0x20         /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE          _U(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos              0            /**< \brief (PORT_IN) Port Data Input Value */
+#define PORT_IN_IN_Msk              (_U(0xFFFFFFFF) << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value)           (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
+#define PORT_IN_MASK                _U(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SAMPLING:32;      /*!< bit:  0..31  Input Sampling Mode                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET            0x24         /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE        _U(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos      0            /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk      (_U(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value)   (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
+#define PORT_CTRL_MASK              _U(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PINMASK:16;       /*!< bit:  0..15  Pin Mask for Multiple Pin Configuration */
+    uint32_t PMUXEN:1;         /*!< bit:     16  Peripheral Multiplexer Enable      */
+    uint32_t INEN:1;           /*!< bit:     17  Input Enable                       */
+    uint32_t PULLEN:1;         /*!< bit:     18  Pull Enable                        */
+    uint32_t :3;               /*!< bit: 19..21  Reserved                           */
+    uint32_t DRVSTR:1;         /*!< bit:     22  Output Driver Strength Selection   */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PMUX:4;           /*!< bit: 24..27  Peripheral Multiplexing            */
+    uint32_t WRPMUX:1;         /*!< bit:     28  Write PMUX                         */
+    uint32_t :1;               /*!< bit:     29  Reserved                           */
+    uint32_t WRPINCFG:1;       /*!< bit:     30  Write PINCFG                       */
+    uint32_t HWSEL:1;          /*!< bit:     31  Half-Word Select                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET        0x28         /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE    _U(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos   0            /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk   (_U(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
+#define PORT_WRCONFIG_PMUXEN_Pos    16           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN        (_U(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos      17           /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN          (_U(0x1) << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos    18           /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN        (_U(0x1) << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos    22           /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR        (_U(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos      24           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk      (_U(0xF) << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value)   (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
+#define PORT_WRCONFIG_WRPMUX_Pos    28           /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX        (_U(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos  30           /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG      (_U(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos     31           /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL         (_U(0x1) << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK          _U(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W  8) GROUP Peripheral Multiplexing n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXE:4;          /*!< bit:  0.. 3  Peripheral Multiplexing Even       */
+    uint8_t  PMUXO:4;          /*!< bit:  4.. 7  Peripheral Multiplexing Odd        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET            0x30         /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
+#define PORT_PMUX_RESETVALUE        _U(0x00)     /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
+
+#define PORT_PMUX_PMUXE_Pos         0            /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
+#define PORT_PMUX_PMUXE_Msk         (_U(0xF) << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value)      (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
+#define   PORT_PMUX_PMUXE_A_Val           _U(0x0)   /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define   PORT_PMUX_PMUXE_B_Val           _U(0x1)   /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define   PORT_PMUX_PMUXE_C_Val           _U(0x2)   /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define   PORT_PMUX_PMUXE_D_Val           _U(0x3)   /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define   PORT_PMUX_PMUXE_E_Val           _U(0x4)   /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define   PORT_PMUX_PMUXE_F_Val           _U(0x5)   /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define   PORT_PMUX_PMUXE_G_Val           _U(0x6)   /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define   PORT_PMUX_PMUXE_H_Val           _U(0x7)   /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXE_A           (PORT_PMUX_PMUXE_A_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_B           (PORT_PMUX_PMUXE_B_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_C           (PORT_PMUX_PMUXE_C_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_D           (PORT_PMUX_PMUXE_D_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_E           (PORT_PMUX_PMUXE_E_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_F           (PORT_PMUX_PMUXE_F_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_G           (PORT_PMUX_PMUXE_G_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_H           (PORT_PMUX_PMUXE_H_Val         << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXO_Pos         4            /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
+#define PORT_PMUX_PMUXO_Msk         (_U(0xF) << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value)      (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
+#define   PORT_PMUX_PMUXO_A_Val           _U(0x0)   /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define   PORT_PMUX_PMUXO_B_Val           _U(0x1)   /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define   PORT_PMUX_PMUXO_C_Val           _U(0x2)   /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define   PORT_PMUX_PMUXO_D_Val           _U(0x3)   /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define   PORT_PMUX_PMUXO_E_Val           _U(0x4)   /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define   PORT_PMUX_PMUXO_F_Val           _U(0x5)   /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define   PORT_PMUX_PMUXO_G_Val           _U(0x6)   /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define   PORT_PMUX_PMUXO_H_Val           _U(0x7)   /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXO_A           (PORT_PMUX_PMUXO_A_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_B           (PORT_PMUX_PMUXO_B_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_C           (PORT_PMUX_PMUXO_C_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_D           (PORT_PMUX_PMUXO_D_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_E           (PORT_PMUX_PMUXO_E_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_F           (PORT_PMUX_PMUXO_F_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_G           (PORT_PMUX_PMUXO_G_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_H           (PORT_PMUX_PMUXO_H_Val         << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_MASK              _U(0xFF)     /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W  8) GROUP Pin Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXEN:1;         /*!< bit:      0  Peripheral Multiplexer Enable      */
+    uint8_t  INEN:1;           /*!< bit:      1  Input Enable                       */
+    uint8_t  PULLEN:1;         /*!< bit:      2  Pull Enable                        */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  DRVSTR:1;         /*!< bit:      6  Output Driver Strength Selection   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET          0x40         /**< \brief (PORT_PINCFG offset) Pin Configuration n */
+#define PORT_PINCFG_RESETVALUE      _U(0x00)     /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
+
+#define PORT_PINCFG_PMUXEN_Pos      0            /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN          (_U(0x1) << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos        1            /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN            (_U(0x1) << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos      2            /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN          (_U(0x1) << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos      6            /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR          (_U(0x1) << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK            _U(0x47)     /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PORT_DIR_Type             DIR;         /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+  __IO PORT_DIRCLR_Type          DIRCLR;      /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+  __IO PORT_DIRSET_Type          DIRSET;      /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+  __IO PORT_DIRTGL_Type          DIRTGL;      /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+  __IO PORT_OUT_Type             OUT;         /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+  __IO PORT_OUTCLR_Type          OUTCLR;      /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+  __IO PORT_OUTSET_Type          OUTSET;      /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+  __IO PORT_OUTTGL_Type          OUTTGL;      /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+  __I  PORT_IN_Type              IN;          /**< \brief Offset: 0x20 (R/  32) Data Input Value */
+  __IO PORT_CTRL_Type            CTRL;        /**< \brief Offset: 0x24 (R/W 32) Control */
+  __O  PORT_WRCONFIG_Type        WRCONFIG;    /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+       RoReg8                    Reserved1[0x4];
+  __IO PORT_PMUX_Type            PMUX[16];    /**< \brief Offset: 0x30 (R/W  8) Peripheral Multiplexing n */
+  __IO PORT_PINCFG_Type          PINCFG[32];  /**< \brief Offset: 0x40 (R/W  8) Pin Configuration n */
+       RoReg8                    Reserved2[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       PortGroup                 Group[2];    /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PORT_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/rtc.h b/uf2-samdx1/lib/samd21/samd21a/include/component/rtc.h
new file mode 100644
index 00000000..6d916b3d
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/rtc.h
@@ -0,0 +1,1053 @@
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_COMPONENT_
+#define _SAMD21_RTC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2202
+#define REV_RTC                     0x101
+
+/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
+#define RTC_MODE0_CTRL_RESETVALUE   _U(0x0000)   /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
+
+#define RTC_MODE0_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE0_CTRL) Software Reset */
+#define RTC_MODE0_CTRL_SWRST        (_U(0x1) << RTC_MODE0_CTRL_SWRST_Pos)
+#define RTC_MODE0_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE0_CTRL) Enable */
+#define RTC_MODE0_CTRL_ENABLE       (_U(0x1) << RTC_MODE0_CTRL_ENABLE_Pos)
+#define RTC_MODE0_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE0_CTRL) Operating Mode */
+#define RTC_MODE0_CTRL_MODE_Msk     (_U(0x3) << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE(value)  (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))
+#define   RTC_MODE0_CTRL_MODE_COUNT32_Val _U(0x0)   /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE0_CTRL_MODE_COUNT16_Val _U(0x1)   /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE0_CTRL_MODE_CLOCK_Val   _U(0x2)   /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_CLOCK   (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE0_CTRL) Clear on Match */
+#define RTC_MODE0_CTRL_MATCHCLR     (_U(0x1) << RTC_MODE0_CTRL_MATCHCLR_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE0_CTRL) Prescaler */
+#define RTC_MODE0_CTRL_PRESCALER_Msk (_U(0xF) << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))
+#define   RTC_MODE0_CTRL_PRESCALER_DIV1_Val _U(0x0)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV2_Val _U(0x1)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV4_Val _U(0x2)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV8_Val _U(0x3)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV16_Val _U(0x4)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV32_Val _U(0x5)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV64_Val _U(0x6)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV128_Val _U(0x7)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV256_Val _U(0x8)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV512_Val _U(0x9)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE0_CTRL_PRESCALER_DIV1024_Val _U(0xA)   /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_MASK         _U(0x0F8F)   /**< \brief (RTC_MODE0_CTRL) MASK Register */
+
+/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
+#define RTC_MODE1_CTRL_RESETVALUE   _U(0x0000)   /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
+
+#define RTC_MODE1_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE1_CTRL) Software Reset */
+#define RTC_MODE1_CTRL_SWRST        (_U(0x1) << RTC_MODE1_CTRL_SWRST_Pos)
+#define RTC_MODE1_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE1_CTRL) Enable */
+#define RTC_MODE1_CTRL_ENABLE       (_U(0x1) << RTC_MODE1_CTRL_ENABLE_Pos)
+#define RTC_MODE1_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE1_CTRL) Operating Mode */
+#define RTC_MODE1_CTRL_MODE_Msk     (_U(0x3) << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE(value)  (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))
+#define   RTC_MODE1_CTRL_MODE_COUNT32_Val _U(0x0)   /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE1_CTRL_MODE_COUNT16_Val _U(0x1)   /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE1_CTRL_MODE_CLOCK_Val   _U(0x2)   /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_CLOCK   (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE1_CTRL) Prescaler */
+#define RTC_MODE1_CTRL_PRESCALER_Msk (_U(0xF) << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))
+#define   RTC_MODE1_CTRL_PRESCALER_DIV1_Val _U(0x0)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV2_Val _U(0x1)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV4_Val _U(0x2)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV8_Val _U(0x3)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV16_Val _U(0x4)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV32_Val _U(0x5)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV64_Val _U(0x6)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV128_Val _U(0x7)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV256_Val _U(0x8)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV512_Val _U(0x9)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE1_CTRL_PRESCALER_DIV1024_Val _U(0xA)   /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_MASK         _U(0x0F0F)   /**< \brief (RTC_MODE1_CTRL) MASK Register */
+
+/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint16_t CLKREP:1;         /*!< bit:      6  Clock Representation               */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRL_OFFSET       0x00         /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
+#define RTC_MODE2_CTRL_RESETVALUE   _U(0x0000)   /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
+
+#define RTC_MODE2_CTRL_SWRST_Pos    0            /**< \brief (RTC_MODE2_CTRL) Software Reset */
+#define RTC_MODE2_CTRL_SWRST        (_U(0x1) << RTC_MODE2_CTRL_SWRST_Pos)
+#define RTC_MODE2_CTRL_ENABLE_Pos   1            /**< \brief (RTC_MODE2_CTRL) Enable */
+#define RTC_MODE2_CTRL_ENABLE       (_U(0x1) << RTC_MODE2_CTRL_ENABLE_Pos)
+#define RTC_MODE2_CTRL_MODE_Pos     2            /**< \brief (RTC_MODE2_CTRL) Operating Mode */
+#define RTC_MODE2_CTRL_MODE_Msk     (_U(0x3) << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE(value)  (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))
+#define   RTC_MODE2_CTRL_MODE_COUNT32_Val _U(0x0)   /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
+#define   RTC_MODE2_CTRL_MODE_COUNT16_Val _U(0x1)   /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
+#define   RTC_MODE2_CTRL_MODE_CLOCK_Val   _U(0x2)   /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_CLOCK   (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_CLKREP_Pos   6            /**< \brief (RTC_MODE2_CTRL) Clock Representation */
+#define RTC_MODE2_CTRL_CLKREP       (_U(0x1) << RTC_MODE2_CTRL_CLKREP_Pos)
+#define RTC_MODE2_CTRL_MATCHCLR_Pos 7            /**< \brief (RTC_MODE2_CTRL) Clear on Match */
+#define RTC_MODE2_CTRL_MATCHCLR     (_U(0x1) << RTC_MODE2_CTRL_MATCHCLR_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_Pos 8            /**< \brief (RTC_MODE2_CTRL) Prescaler */
+#define RTC_MODE2_CTRL_PRESCALER_Msk (_U(0xF) << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))
+#define   RTC_MODE2_CTRL_PRESCALER_DIV1_Val _U(0x0)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV2_Val _U(0x1)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV4_Val _U(0x2)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV8_Val _U(0x3)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV16_Val _U(0x4)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV32_Val _U(0x5)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV64_Val _U(0x6)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV128_Val _U(0x7)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV256_Val _U(0x8)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV512_Val _U(0x9)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE2_CTRL_PRESCALER_DIV1024_Val _U(0xA)   /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_MASK         _U(0x0FCF)   /**< \brief (RTC_MODE2_CTRL) MASK Register */
+
+/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ADDR:6;           /*!< bit:  0.. 5  Address                            */
+    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
+    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
+    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_READREQ_OFFSET          0x02         /**< \brief (RTC_READREQ offset) Read Request */
+#define RTC_READREQ_RESETVALUE      _U(0x0010)   /**< \brief (RTC_READREQ reset_value) Read Request */
+
+#define RTC_READREQ_ADDR_Pos        0            /**< \brief (RTC_READREQ) Address */
+#define RTC_READREQ_ADDR_Msk        (_U(0x3F) << RTC_READREQ_ADDR_Pos)
+#define RTC_READREQ_ADDR(value)     (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))
+#define RTC_READREQ_RCONT_Pos       14           /**< \brief (RTC_READREQ) Read Continuously */
+#define RTC_READREQ_RCONT           (_U(0x1) << RTC_READREQ_RCONT_Pos)
+#define RTC_READREQ_RREQ_Pos        15           /**< \brief (RTC_READREQ) Read Request */
+#define RTC_READREQ_RREQ            (_U(0x1) << RTC_READREQ_RREQ_Pos)
+#define RTC_READREQ_MASK            _U(0xC03F)   /**< \brief (RTC_READREQ) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t CMPEO:1;          /*!< bit:      8  Compare x Event Output Enable      */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE _U(0x0000)   /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0     (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1     (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2     (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3     (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4     (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5     (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6     (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7     (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk  (_U(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0     (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk  (_U(0x1) << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
+#define RTC_MODE0_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO      (_U(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_MASK       _U(0x81FF)   /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint16_t CMPEO1:1;         /*!< bit:      9  Compare 1 Event Output Enable      */
+    uint16_t :5;               /*!< bit: 10..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t CMPEO:2;          /*!< bit:  8.. 9  Compare x Event Output Enable      */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE _U(0x0000)   /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0     (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1     (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2     (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3     (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4     (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5     (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6     (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7     (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk  (_U(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0     (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9            /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1     (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk  (_U(0x3) << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
+#define RTC_MODE1_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO      (_U(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_MASK       _U(0x83FF)   /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint16_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint16_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint16_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint16_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint16_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint16_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint16_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint16_t ALARMEO0:1;       /*!< bit:      8  Alarm 0 Event Output Enable        */
+    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint16_t ALARMEO:1;        /*!< bit:      8  Alarm x Event Output Enable        */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE _U(0x0000)   /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0     (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1     (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2     (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3     (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4     (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5     (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6     (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7     (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk  (_U(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0   (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U(0x1) << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
+#define RTC_MODE2_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO      (_U(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_MASK       _U(0x81FF)   /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE _U(0x00)     /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0     (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk  (_U(0x1) << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
+#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENCLR_SYNCRDY  (_U(0x1) << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF      (_U(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK     _U(0xC1)     /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE _U(0x00)     /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0     (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1     (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk  (_U(0x3) << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
+#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENCLR_SYNCRDY  (_U(0x1) << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF      (_U(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK     _U(0xC3)     /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W  8) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET   0x06         /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE _U(0x00)     /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0   (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (_U(0x1) << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
+#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENCLR_SYNCRDY  (_U(0x1) << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF      (_U(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK     _U(0xC1)     /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:1;            /*!< bit:      0  Compare x Interrupt Enable         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE _U(0x00)     /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0     (1 << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk  (_U(0x1) << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
+#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENSET_SYNCRDY  (_U(0x1) << RTC_MODE0_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF      (_U(0x1) << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK     _U(0xC1)     /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMP0:1;           /*!< bit:      0  Compare 0 Interrupt Enable         */
+    uint8_t  CMP1:1;           /*!< bit:      1  Compare 1 Interrupt Enable         */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x Interrupt Enable         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE _U(0x00)     /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_CMP0_Pos 0            /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0     (1 << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 1            /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1     (1 << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos  0            /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk  (_U(0x3) << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
+#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENSET_SYNCRDY  (_U(0x1) << RTC_MODE1_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF      (_U(0x1) << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK     _U(0xC3)     /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W  8) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0 Interrupt Enable           */
+    uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready Interrupt Enable */
+    uint8_t  OVF:1;            /*!< bit:      7  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  ALARM:1;          /*!< bit:      0  Alarm x Interrupt Enable           */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET   0x07         /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE _U(0x00)     /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0   (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (_U(0x1) << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
+#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENSET_SYNCRDY  (_U(0x1) << RTC_MODE2_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos  7            /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF      (_U(0x1) << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK     _U(0xC1)     /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
+    __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  CMP:1;            /*!< bit:      0  Compare x                          */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE _U(0x00)     /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0      (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk   (_U(0x1) << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
+#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
+#define RTC_MODE0_INTFLAG_SYNCRDY   (_U(0x1) << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF       (_U(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK      _U(0xC1)     /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
+    __I uint8_t  CMP1:1;           /*!< bit:      1  Compare 1                          */
+    __I uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  CMP:2;            /*!< bit:  0.. 1  Compare x                          */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE _U(0x00)     /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_CMP0_Pos  0            /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0      (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos  1            /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1      (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos   0            /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk   (_U(0x3) << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
+#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
+#define RTC_MODE1_INTFLAG_SYNCRDY   (_U(0x1) << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF       (_U(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK      _U(0xC3)     /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0                            */
+    __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      6  Synchronization Ready              */
+    __I uint8_t  OVF:1;            /*!< bit:      7  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  ALARM:1;          /*!< bit:      0  Alarm x                            */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET    0x08         /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE _U(0x00)     /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0    (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 0            /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (_U(0x1) << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
+#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6            /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
+#define RTC_MODE2_INTFLAG_SYNCRDY   (_U(0x1) << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos   7            /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF       (_U(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK      _U(0xC1)     /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W  8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_STATUS_OFFSET           0x0A         /**< \brief (RTC_STATUS offset) Status */
+#define RTC_STATUS_RESETVALUE       _U(0x00)     /**< \brief (RTC_STATUS reset_value) Status */
+
+#define RTC_STATUS_SYNCBUSY_Pos     7            /**< \brief (RTC_STATUS) Synchronization Busy */
+#define RTC_STATUS_SYNCBUSY         (_U(0x1) << RTC_STATUS_SYNCBUSY_Pos)
+#define RTC_STATUS_MASK             _U(0x80)     /**< \brief (RTC_STATUS) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Run During Debug                   */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET          0x0B         /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE      _U(0x00)     /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN          (_U(0x1) << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK            _U(0x01)     /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W  8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:7;          /*!< bit:  0.. 6  Correction Value                   */
+    uint8_t  SIGN:1;           /*!< bit:      7  Correction Sign                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET         0x0C         /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE     _U(0x00)     /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos      0            /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk      (_U(0x7F) << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value)   (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
+#define RTC_FREQCORR_SIGN_Pos       7            /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN           (_U(0x1) << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK           _U(0xFF)     /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE  _U(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk   (_U(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
+#define RTC_MODE0_COUNT_MASK        _U(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET      0x10         /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE  _U(0x0000)   /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk   (_U(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
+#define RTC_MODE1_COUNT_MASK        _U(0xFFFF)   /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET      0x10         /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE  _U(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos  0            /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk  (_U(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
+#define RTC_MODE2_CLOCK_MINUTE_Pos  6            /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk  (_U(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
+#define RTC_MODE2_CLOCK_HOUR_Pos    12           /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk    (_U(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
+#define   RTC_MODE2_CLOCK_HOUR_AM_Val     _U(0x0)   /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
+#define   RTC_MODE2_CLOCK_HOUR_PM_Val     _U(0x10)   /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
+#define RTC_MODE2_CLOCK_HOUR_AM     (RTC_MODE2_CLOCK_HOUR_AM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR_PM     (RTC_MODE2_CLOCK_HOUR_PM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos     17           /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk     (_U(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value)  (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
+#define RTC_MODE2_CLOCK_MONTH_Pos   22           /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk   (_U(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
+#define RTC_MODE2_CLOCK_YEAR_Pos    26           /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk    (_U(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
+#define RTC_MODE2_CLOCK_MASK        _U(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER:16;           /*!< bit:  0..15  Counter Period                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET        0x14         /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE    _U(0x0000)   /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos       0            /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk       (_U(0xFFFF) << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value)    (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
+#define RTC_MODE1_PER_MASK          _U(0xFFFF)   /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COMP:32;          /*!< bit:  0..31  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET       0x18         /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE   _U(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos     0            /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk     (_U(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value)  (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
+#define RTC_MODE0_COMP_MASK         _U(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMP:16;          /*!< bit:  0..15  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET       0x18         /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE   _U(0x0000)   /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos     0            /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk     (_U(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value)  (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
+#define RTC_MODE1_COMP_MASK         _U(0xFFFF)   /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET      0x18         /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE  _U(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos  0            /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk  (_U(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
+#define RTC_MODE2_ALARM_MINUTE_Pos  6            /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk  (_U(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
+#define RTC_MODE2_ALARM_HOUR_Pos    12           /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk    (_U(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
+#define   RTC_MODE2_ALARM_HOUR_AM_Val     _U(0x0)   /**< \brief (RTC_MODE2_ALARM) Morning hour */
+#define   RTC_MODE2_ALARM_HOUR_PM_Val     _U(0x10)   /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
+#define RTC_MODE2_ALARM_HOUR_AM     (RTC_MODE2_ALARM_HOUR_AM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR_PM     (RTC_MODE2_ALARM_HOUR_PM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_DAY_Pos     17           /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk     (_U(0x1F) << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value)  (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
+#define RTC_MODE2_ALARM_MONTH_Pos   22           /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk   (_U(0xF) << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
+#define RTC_MODE2_ALARM_YEAR_Pos    26           /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk    (_U(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
+#define RTC_MODE2_ALARM_MASK        _U(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W  8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SEL:3;            /*!< bit:  0.. 2  Alarm Mask Selection               */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET       0x1C         /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE   _U(0x00)     /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos      0            /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk      (_U(0x7) << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value)   (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
+#define   RTC_MODE2_MASK_SEL_OFF_Val      _U(0x0)   /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define   RTC_MODE2_MASK_SEL_SS_Val       _U(0x1)   /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define   RTC_MODE2_MASK_SEL_MMSS_Val     _U(0x2)   /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define   RTC_MODE2_MASK_SEL_HHMMSS_Val   _U(0x3)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U(0x4)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U(0x5)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U(0x6)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF      (RTC_MODE2_MASK_SEL_OFF_Val    << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS       (RTC_MODE2_MASK_SEL_SS_Val     << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS     (RTC_MODE2_MASK_SEL_MMSS_Val   << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS   (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK         _U(0x07)     /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO RTC_MODE2_ALARM_Type      ALARM;       /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+  __IO RTC_MODE2_MASK_Type       MASK;        /**< \brief Offset: 0x04 (R/W  8) MODE2_ALARM Alarm n Mask */
+       RoReg8                    Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+  __IO RTC_MODE0_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE0_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+  __IO RTC_MODE0_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE0 Interrupt Enable Clear */
+  __IO RTC_MODE0_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE0 Interrupt Enable Set */
+  __IO RTC_MODE0_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE0 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE0_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+       RoReg8                    Reserved3[0x4];
+  __IO RTC_MODE0_COMP_Type       COMP[1];     /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+  __IO RTC_MODE1_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE1_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+  __IO RTC_MODE1_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE1 Interrupt Enable Clear */
+  __IO RTC_MODE1_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE1 Interrupt Enable Set */
+  __IO RTC_MODE1_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE1 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE1_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+       RoReg8                    Reserved3[0x2];
+  __IO RTC_MODE1_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+       RoReg8                    Reserved4[0x2];
+  __IO RTC_MODE1_COMP_Type       COMP[2];     /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+  __IO RTC_MODE2_CTRL_Type       CTRL;        /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+  __IO RTC_READREQ_Type          READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO RTC_MODE2_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+  __IO RTC_MODE2_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x06 (R/W  8) MODE2 Interrupt Enable Clear */
+  __IO RTC_MODE2_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x07 (R/W  8) MODE2 Interrupt Enable Set */
+  __IO RTC_MODE2_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x08 (R/W  8) MODE2 Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO RTC_STATUS_Type           STATUS;      /**< \brief Offset: 0x0A (R/W  8) Status */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0B (R/W  8) Debug Control */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x0C (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE2_CLOCK_Type      CLOCK;       /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+       RoReg8                    Reserved3[0x4];
+       RtcMode2Alarm             Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       RtcMode0                  MODE0;       /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+       RtcMode1                  MODE1;       /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+       RtcMode2                  MODE2;       /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_RTC_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/sercom.h b/uf2-samdx1/lib/samd21/samd21a/include/component/sercom.h
new file mode 100644
index 00000000..d300f6b6
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/sercom.h
@@ -0,0 +1,1493 @@
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM_COMPONENT_
+#define _SAMD21_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM                  0x200
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run in Standby                     */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t MEXTTOEN:1;       /*!< bit:     22  Master SCL Low Extend Timeout      */
+    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
+    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
+    uint32_t :1;               /*!< bit:     26  Reserved                           */
+    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
+    uint32_t INACTOUT:2;       /*!< bit: 28..29  Inactive Time-Out                  */
+    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST     (_U(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE    (_U(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk  (_U(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
+#define   SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val _U(0x0)   /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val _U(0x1)   /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val _U(0x2)   /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val _U(0x3)   /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val _U(0x4)   /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val _U(0x5)   /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY  (_U(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT    (_U(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22           /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN  (_U(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN  (_U(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk (_U(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CM_CTRLA_SCLSM     (_U(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28           /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CM_CTRLA_MASK      _U(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
+    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
+    uint32_t :1;               /*!< bit:     26  Reserved                           */
+    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
+    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
+    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST     (_U(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE    (_U(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk  (_U(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
+#define   SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val _U(0x0)   /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val _U(0x1)   /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val _U(0x2)   /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val _U(0x3)   /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val _U(0x4)   /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val _U(0x5)   /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY  (_U(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT    (_U(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN  (_U(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk (_U(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CS_CTRLA_SCLSM     (_U(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CS_CTRLA_MASK      _U(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t DOPO:2;           /*!< bit: 16..17  Data Out Pinout                    */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t DIPO:2;           /*!< bit: 20..21  Data In Pinout                     */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CPHA:1;           /*!< bit:     28  Clock Phase                        */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET     0x00         /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos  0            /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST      (_U(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE     (_U(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos   2            /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk   (_U(0x7) << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
+#define   SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val _U(0x0)   /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val _U(0x1)   /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
+#define   SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val _U(0x2)   /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val _U(0x3)   /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
+#define   SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val _U(0x4)   /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
+#define   SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val _U(0x5)   /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY   (_U(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos   8            /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON       (_U(0x1) << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos   16           /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk   (_U(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
+#define SERCOM_SPI_CTRLA_DIPO_Pos   20           /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk   (_U(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
+#define SERCOM_SPI_CTRLA_FORM_Pos   24           /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk   (_U(0xF) << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
+#define SERCOM_SPI_CTRLA_CPHA_Pos   28           /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA       (_U(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos   29           /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL       (_U(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos   30           /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD       (_U(0x1) << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK       _U(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t :4;               /*!< bit:  9..12  Reserved                           */
+    uint32_t SAMPR:3;          /*!< bit: 13..15  Sample                             */
+    uint32_t TXPO:2;           /*!< bit: 16..17  Transmit Data Pinout               */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t RXPO:2;           /*!< bit: 20..21  Receive Data Pinout                */
+    uint32_t SAMPA:2;          /*!< bit: 22..23  Sample Adjustment                  */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CMODE:1;          /*!< bit:     28  Communication Mode                 */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET   0x00         /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST    (_U(0x1) << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE   (_U(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2            /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (_U(0x7) << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
+#define   SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val _U(0x0)   /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val _U(0x1)   /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
+#define   SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val _U(0x2)   /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val _U(0x3)   /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
+#define   SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val _U(0x4)   /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
+#define   SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val _U(0x5)   /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (_U(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8            /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON     (_U(0x1) << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_SAMPR_Pos 13           /**< \brief (SERCOM_USART_CTRLA) Sample */
+#define SERCOM_USART_CTRLA_SAMPR_Msk (_U(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos)
+#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
+#define SERCOM_USART_CTRLA_TXPO_Pos 16           /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (_U(0x3) << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
+#define SERCOM_USART_CTRLA_RXPO_Pos 20           /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (_U(0x3) << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
+#define SERCOM_USART_CTRLA_SAMPA_Pos 22           /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
+#define SERCOM_USART_CTRLA_SAMPA_Msk (_U(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos)
+#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
+#define SERCOM_USART_CTRLA_FORM_Pos 24           /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (_U(0xF) << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
+#define SERCOM_USART_CTRLA_CMODE_Pos 28           /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE    (_U(0x1) << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29           /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL     (_U(0x1) << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30           /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD     (_U(0x1) << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK     _U(0x7FF3E19F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t QCEN:1;           /*!< bit:      9  Quick Command Enable               */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN      (_U(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos  9            /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN      (_U(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk   (_U(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT    (_U(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK      _U(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t GCMD:1;           /*!< bit:      9  PMBus Group Command                */
+    uint32_t AACKEN:1;         /*!< bit:     10  Automatic Address Acknowledge      */
+    uint32_t :3;               /*!< bit: 11..13  Reserved                           */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN      (_U(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_GCMD_Pos  9            /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
+#define SERCOM_I2CS_CTRLB_GCMD      (_U(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10           /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
+#define SERCOM_I2CS_CTRLB_AACKEN    (_U(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14           /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (_U(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
+#define SERCOM_I2CS_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk   (_U(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT    (_U(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK      _U(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t PLOADEN:1;        /*!< bit:      6  Data Preload Enable                */
+    uint32_t :2;               /*!< bit:  7.. 8  Reserved                           */
+    uint32_t SSDE:1;           /*!< bit:      9  Slave Select Low Detect Enable     */
+    uint32_t :3;               /*!< bit: 10..12  Reserved                           */
+    uint32_t MSSEN:1;          /*!< bit:     13  Master Slave Select Enable         */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t :1;               /*!< bit:     16  Reserved                           */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET     0x04         /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6            /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN    (_U(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_SSDE_Pos   9            /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
+#define SERCOM_SPI_CTRLB_SSDE       (_U(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos)
+#define SERCOM_SPI_CTRLB_MSSEN_Pos  13           /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
+#define SERCOM_SPI_CTRLB_MSSEN      (_U(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos  14           /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk  (_U(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
+#define SERCOM_SPI_CTRLB_RXEN_Pos   17           /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN       (_U(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK       _U(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t SBMODE:1;         /*!< bit:      6  Stop Bit Mode                      */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t COLDEN:1;         /*!< bit:      8  Collision Detection Enable         */
+    uint32_t SFDE:1;           /*!< bit:      9  Start of Frame Detection Enable    */
+    uint32_t ENC:1;            /*!< bit:     10  Encoding Format                    */
+    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint32_t PMODE:1;          /*!< bit:     13  Parity Mode                        */
+    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
+    uint32_t TXEN:1;           /*!< bit:     16  Transmitter Enable                 */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET   0x04         /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (_U(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6            /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE   (_U(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_COLDEN_Pos 8            /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
+#define SERCOM_USART_CTRLB_COLDEN   (_U(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9            /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE     (_U(0x1) << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_ENC_Pos  10           /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
+#define SERCOM_USART_CTRLB_ENC      (_U(0x1) << SERCOM_USART_CTRLB_ENC_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13           /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE    (_U(0x1) << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16           /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN     (_U(0x1) << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17           /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN     (_U(0x1) << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_MASK     _U(0x00032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
+    uint32_t BAUDLOW:8;        /*!< bit:  8..15  Baud Rate Value Low                */
+    uint32_t HSBAUD:8;         /*!< bit: 16..23  High Speed Baud Rate Value         */
+    uint32_t HSBAUDLOW:8;      /*!< bit: 24..31  High Speed Baud Rate Value Low     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET     0x0C         /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos   0            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
+#define SERCOM_I2CM_BAUD_BAUD_Msk   (_U(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_MASK       _U(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W  8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET      0x0C         /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE  _U(0x00)     /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos    0            /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
+#define SERCOM_SPI_BAUD_BAUD_Msk    (_U(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
+#define SERCOM_SPI_BAUD_MASK        _U(0xFF)     /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // FRAC mode
+    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
+    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
+  } FRAC;                      /*!< Structure used for FRAC                         */
+  struct { // FRACFP mode
+    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
+    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
+  } FRACFP;                    /*!< Structure used for FRACFP                       */
+  struct { // USARTFP mode
+    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
+  } USARTFP;                   /*!< Structure used for USARTFP                      */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET    0x0C         /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
+#define SERCOM_USART_BAUD_RESETVALUE _U(0x0000)   /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
+
+#define SERCOM_USART_BAUD_BAUD_Pos  0            /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
+#define SERCOM_USART_BAUD_BAUD_Msk  (_U(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
+#define SERCOM_USART_BAUD_MASK      _U(0xFFFF)   /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+// FRAC mode
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk (_U(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos)
+#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_BAUD_FRAC_MASK _U(0xFFFF)   /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
+
+// FRACFP mode
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos)
+#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_BAUD_FRACFP_MASK _U(0xFFFF)   /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
+
+// USARTFP mode
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_USARTFP_MASK _U(0xFFFF)   /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W  8) USART USART Receive Pulse Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RXPL:8;           /*!< bit:  0.. 7  Receive Pulse Length               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_RXPL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXPL_OFFSET    0x0E         /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
+#define SERCOM_USART_RXPL_RESETVALUE _U(0x00)     /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
+
+#define SERCOM_USART_RXPL_RXPL_Pos  0            /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
+#define SERCOM_USART_RXPL_RXPL_Msk  (_U(0xFF) << SERCOM_USART_RXPL_RXPL_Pos)
+#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
+#define SERCOM_USART_RXPL_MASK      _U(0xFF)     /**< \brief (SERCOM_USART_RXPL) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Disable    */
+    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Disable     */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE _U(0x00)     /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_MB     (_U(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_SB     (_U(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_ERROR  (_U(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK   _U(0x83)     /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Disable    */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Disable    */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Disable             */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE _U(0x00)     /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_PREC   (_U(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (_U(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_DRDY   (_U(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_ERROR  (_U(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK   _U(0x87)     /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
+    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Disable */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET  0x14         /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE _U(0x00)     /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_DRE     (_U(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_TXC     (_U(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_RXC     (_U(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_SSL     (_U(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos)
+#define SERCOM_SPI_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_ERROR   (_U(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos)
+#define SERCOM_SPI_INTENCLR_MASK    _U(0x8F)     /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Disable    */
+    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Disable */
+    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE _U(0x00)     /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_USART_INTENCLR_DRE   (_U(0x1) << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_TXC   (_U(0x1) << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXC   (_U(0x1) << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS   (_U(0x1) << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
+#define SERCOM_USART_INTENCLR_CTSIC (_U(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos)
+#define SERCOM_USART_INTENCLR_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXBRK (_U(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos)
+#define SERCOM_USART_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_USART_INTENCLR_ERROR (_U(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos)
+#define SERCOM_USART_INTENCLR_MASK  _U(0xBF)     /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Enable     */
+    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Enable      */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE _U(0x00)     /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB     (_U(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB     (_U(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_ERROR  (_U(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)
+#define SERCOM_I2CM_INTENSET_MASK   _U(0x83)     /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Enable     */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Enable     */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Enable              */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE _U(0x00)     /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC   (_U(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (_U(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY   (_U(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_ERROR  (_U(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)
+#define SERCOM_I2CS_INTENSET_MASK   _U(0x87)     /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W  8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Enable  */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET  0x16         /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE _U(0x00)     /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE     (_U(0x1) << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC     (_U(0x1) << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC     (_U(0x1) << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
+#define SERCOM_SPI_INTENSET_SSL     (_U(0x1) << SERCOM_SPI_INTENSET_SSL_Pos)
+#define SERCOM_SPI_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_SPI_INTENSET_ERROR   (_U(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos)
+#define SERCOM_SPI_INTENSET_MASK    _U(0x8F)     /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W  8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Enable     */
+    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Enable */
+    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Enable    */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE _U(0x00)     /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE   (_U(0x1) << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC   (_U(0x1) << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC   (_U(0x1) << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS   (_U(0x1) << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
+#define SERCOM_USART_INTENSET_CTSIC (_U(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos)
+#define SERCOM_USART_INTENSET_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXBRK (_U(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos)
+#define SERCOM_USART_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_USART_INTENSET_ERROR (_U(0x1) << SERCOM_USART_INTENSET_ERROR_Pos)
+#define SERCOM_USART_INTENSET_MASK  _U(0xBF)     /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt            */
+    __I uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt             */
+    __I uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE _U(0x00)     /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos  0            /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_MB      (_U(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos  1            /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_SB      (_U(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CM_INTFLAG_ERROR   (_U(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK    _U(0x83)     /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt            */
+    __I uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt            */
+    __I uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt                     */
+    __I uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE _U(0x00)     /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
+#define SERCOM_I2CS_INTFLAG_PREC    (_U(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
+#define SERCOM_I2CS_INTFLAG_AMATCH  (_U(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
+#define SERCOM_I2CS_INTFLAG_DRDY    (_U(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CS_INTFLAG_ERROR   (_U(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK    _U(0x87)     /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
+    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
+    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
+    __I uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Flag    */
+    __I uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET   0x18         /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE _U(0x00)     /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos  0            /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_SPI_INTFLAG_DRE      (_U(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos  1            /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_TXC      (_U(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos  2            /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_RXC      (_U(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_SSL_Pos  3            /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
+#define SERCOM_SPI_INTFLAG_SSL      (_U(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos)
+#define SERCOM_SPI_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
+#define SERCOM_SPI_INTFLAG_ERROR    (_U(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos)
+#define SERCOM_SPI_INTFLAG_MASK     _U(0x8F)     /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
+    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
+    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
+    __I uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt            */
+    __I uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt */
+    __I uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt           */
+    __I uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x18         /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE _U(0x00)     /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0            /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_USART_INTFLAG_DRE    (_U(0x1) << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1            /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_USART_INTFLAG_TXC    (_U(0x1) << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2            /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_USART_INTFLAG_RXC    (_U(0x1) << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3            /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS    (_U(0x1) << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
+#define SERCOM_USART_INTFLAG_CTSIC  (_U(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos)
+#define SERCOM_USART_INTFLAG_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
+#define SERCOM_USART_INTFLAG_RXBRK  (_U(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos)
+#define SERCOM_USART_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
+#define SERCOM_USART_INTFLAG_ERROR  (_U(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos)
+#define SERCOM_USART_INTFLAG_MASK   _U(0xBF)     /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t ARBLOST:1;        /*!< bit:      1  Arbitration Lost                   */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t BUSSTATE:2;       /*!< bit:  4.. 5  Bus State                          */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t MEXTTOUT:1;       /*!< bit:      8  Master SCL Low Extend Timeout      */
+    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
+    uint16_t LENERR:1;         /*!< bit:     10  Length Error                       */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE _U(0x0000)   /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR   (_U(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1            /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST  (_U(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK   (_U(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4            /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
+#define SERCOM_I2CM_STATUS_LOWTOUT  (_U(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD  (_U(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8            /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_MEXTTOUT (_U(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_SEXTTOUT (_U(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_LENERR_Pos 10           /**< \brief (SERCOM_I2CM_STATUS) Length Error */
+#define SERCOM_I2CM_STATUS_LENERR   (_U(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)
+#define SERCOM_I2CM_STATUS_MASK     _U(0x07F7)   /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t COLL:1;           /*!< bit:      1  Transmit Collision                 */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t DIR:1;            /*!< bit:      3  Read/Write Direction               */
+    uint16_t SR:1;             /*!< bit:      4  Repeated Start                     */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t :1;               /*!< bit:      8  Reserved                           */
+    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
+    uint16_t HS:1;             /*!< bit:     10  High Speed                         */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE _U(0x0000)   /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR   (_U(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1            /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL     (_U(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK   (_U(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos  3            /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
+#define SERCOM_I2CS_STATUS_DIR      (_U(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos   4            /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR       (_U(0x1) << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
+#define SERCOM_I2CS_STATUS_LOWTOUT  (_U(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD  (_U(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_STATUS_SEXTTOUT (_U(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CS_STATUS_HS_Pos   10           /**< \brief (SERCOM_I2CS_STATUS) High Speed */
+#define SERCOM_I2CS_STATUS_HS       (_U(0x1) << SERCOM_I2CS_STATUS_HS_Pos)
+#define SERCOM_I2CS_STATUS_MASK     _U(0x06DF)   /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t :13;              /*!< bit:  3..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET    0x1A         /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE _U(0x0000)   /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF    (_U(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_MASK      _U(0x0004)   /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PERR:1;           /*!< bit:      0  Parity Error                       */
+    uint16_t FERR:1;           /*!< bit:      1  Frame Error                        */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t CTS:1;            /*!< bit:      3  Clear To Send                      */
+    uint16_t ISF:1;            /*!< bit:      4  Inconsistent Sync Field            */
+    uint16_t COLL:1;           /*!< bit:      5  Collision Detected                 */
+    uint16_t :10;              /*!< bit:  6..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET  0x1A         /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE _U(0x0000)   /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0            /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR    (_U(0x1) << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1            /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR    (_U(0x1) << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF  (_U(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_CTS_Pos 3            /**< \brief (SERCOM_USART_STATUS) Clear To Send */
+#define SERCOM_USART_STATUS_CTS     (_U(0x1) << SERCOM_USART_STATUS_CTS_Pos)
+#define SERCOM_USART_STATUS_ISF_Pos 4            /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
+#define SERCOM_USART_STATUS_ISF     (_U(0x1) << SERCOM_USART_STATUS_ISF_Pos)
+#define SERCOM_USART_STATUS_COLL_Pos 5            /**< \brief (SERCOM_USART_STATUS) Collision Detected */
+#define SERCOM_USART_STATUS_COLL    (_U(0x1) << SERCOM_USART_STATUS_COLL_Pos)
+#define SERCOM_USART_STATUS_MASK    _U(0x003F)   /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CM I2CM Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t SYSOP:1;          /*!< bit:      2  System Operation Synchronization Busy */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SWRST  (_U(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE (_U(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2            /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP  (_U(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
+#define SERCOM_I2CM_SYNCBUSY_MASK   _U(0x00000007) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CS I2CS Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_SWRST  (_U(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE (_U(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CS_SYNCBUSY_MASK   _U(0x00000003) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) SPI SPI Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_SYNCBUSY_OFFSET  0x1C         /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_SWRST   (_U(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_ENABLE  (_U(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_CTRLB   (_U(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_SPI_SYNCBUSY_MASK    _U(0x00000007) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) USART USART Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_SWRST (_U(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos)
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_ENABLE (_U(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_CTRLB (_U(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_USART_SYNCBUSY_MASK  _U(0x00000007) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:11;          /*!< bit:  0..10  Address Value                      */
+    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint32_t LENEN:1;          /*!< bit:     13  Length Enable                      */
+    uint32_t HS:1;             /*!< bit:     14  High Speed Mode                    */
+    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
+    uint32_t LEN:8;            /*!< bit: 16..23  Length                             */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos   0            /**< \brief (SERCOM_I2CM_ADDR) Address Value */
+#define SERCOM_I2CM_ADDR_ADDR_Msk   (_U(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
+#define SERCOM_I2CM_ADDR_LENEN_Pos  13           /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
+#define SERCOM_I2CM_ADDR_LENEN      (_U(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)
+#define SERCOM_I2CM_ADDR_HS_Pos     14           /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
+#define SERCOM_I2CM_ADDR_HS         (_U(0x1) << SERCOM_I2CM_ADDR_HS_Pos)
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CM_ADDR_TENBITEN   (_U(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN_Pos    16           /**< \brief (SERCOM_I2CM_ADDR) Length */
+#define SERCOM_I2CM_ADDR_LEN_Msk    (_U(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
+#define SERCOM_I2CM_ADDR_MASK       _U(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t GENCEN:1;         /*!< bit:      0  General Call Address Enable        */
+    uint32_t ADDR:10;          /*!< bit:  1..10  Address Value                      */
+    uint32_t :4;               /*!< bit: 11..14  Reserved                           */
+    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
+    uint32_t :1;               /*!< bit:     16  Reserved                           */
+    uint32_t ADDRMASK:10;      /*!< bit: 17..26  Address Mask                       */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0            /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN     (_U(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos   1            /**< \brief (SERCOM_I2CS_ADDR) Address Value */
+#define SERCOM_I2CS_ADDR_ADDR_Msk   (_U(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CS_ADDR_TENBITEN   (_U(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17           /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
+#define SERCOM_I2CS_ADDR_MASK       _U(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:8;           /*!< bit:  0.. 7  Address Value                      */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t ADDRMASK:8;       /*!< bit: 16..23  Address Mask                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET      0x24         /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE  _U(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos    0            /**< \brief (SERCOM_SPI_ADDR) Address Value */
+#define SERCOM_SPI_ADDR_ADDR_Msk    (_U(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16           /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
+#define SERCOM_SPI_ADDR_MASK        _U(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W  8) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE _U(0x00)     /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CM_DATA) Data Value */
+#define SERCOM_I2CM_DATA_DATA_Msk   (_U(0xFF) << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
+#define SERCOM_I2CM_DATA_MASK       _U(0xFF)     /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W  8) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATA:8;           /*!< bit:  0.. 7  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE _U(0x00)     /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CS_DATA) Data Value */
+#define SERCOM_I2CS_DATA_DATA_Msk   (_U(0xFF) << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
+#define SERCOM_I2CS_DATA_MASK       _U(0xFF)     /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:9;           /*!< bit:  0.. 8  Data Value                         */
+    uint32_t :23;              /*!< bit:  9..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET      0x28         /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE  _U(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos    0            /**< \brief (SERCOM_SPI_DATA) Data Value */
+#define SERCOM_SPI_DATA_DATA_Msk    (_U(0x1FF) << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
+#define SERCOM_SPI_DATA_MASK        _U(0x000001FF) /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:9;           /*!< bit:  0.. 8  Data Value                         */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET    0x28         /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE _U(0x0000)   /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos  0            /**< \brief (SERCOM_USART_DATA) Data Value */
+#define SERCOM_USART_DATA_DATA_Msk  (_U(0x1FF) << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
+#define SERCOM_USART_DATA_MASK      _U(0x01FF)   /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET  0x30         /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE _U(0x00)     /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK    _U(0x01)     /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET   0x30         /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE _U(0x00)     /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP  (_U(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK     _U(0x01)     /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x30         /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE _U(0x00)     /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (_U(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK   _U(0x01)     /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+  __IO SERCOM_I2CM_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+  __IO SERCOM_I2CM_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_I2CM_BAUD_Type     BAUD;        /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+       RoReg8                    Reserved2[0x4];
+  __IO SERCOM_I2CM_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_I2CM_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_I2CM_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_I2CM_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+  __I  SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CM Syncbusy */
+       RoReg8                    Reserved6[0x4];
+  __IO SERCOM_I2CM_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+  __IO SERCOM_I2CM_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W  8) I2CM Data */
+       RoReg8                    Reserved7[0x7];
+  __IO SERCOM_I2CM_DBGCTRL_Type  DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) I2CM Debug Control */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+  __IO SERCOM_I2CS_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+  __IO SERCOM_I2CS_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+       RoReg8                    Reserved1[0xC];
+  __IO SERCOM_I2CS_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_I2CS_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_I2CS_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_I2CS_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+  __I  SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CS Syncbusy */
+       RoReg8                    Reserved5[0x4];
+  __IO SERCOM_I2CS_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+  __IO SERCOM_I2CS_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W  8) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+  __IO SERCOM_SPI_CTRLA_Type     CTRLA;       /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+  __IO SERCOM_SPI_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_SPI_BAUD_Type      BAUD;        /**< \brief Offset: 0x0C (R/W  8) SPI Baud Rate */
+       RoReg8                    Reserved2[0x7];
+  __IO SERCOM_SPI_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) SPI Interrupt Enable Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_SPI_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x16 (R/W  8) SPI Interrupt Enable Set */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_SPI_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) SPI Interrupt Flag Status and Clear */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_SPI_STATUS_Type    STATUS;      /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+  __I  SERCOM_SPI_SYNCBUSY_Type  SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) SPI Syncbusy */
+       RoReg8                    Reserved6[0x4];
+  __IO SERCOM_SPI_ADDR_Type      ADDR;        /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+  __IO SERCOM_SPI_DATA_Type      DATA;        /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+       RoReg8                    Reserved7[0x4];
+  __IO SERCOM_SPI_DBGCTRL_Type   DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) SPI Debug Control */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+  __IO SERCOM_USART_CTRLA_Type   CTRLA;       /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+  __IO SERCOM_USART_CTRLB_Type   CTRLB;       /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_USART_BAUD_Type    BAUD;        /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+  __IO SERCOM_USART_RXPL_Type    RXPL;        /**< \brief Offset: 0x0E (R/W  8) USART Receive Pulse Length */
+       RoReg8                    Reserved2[0x5];
+  __IO SERCOM_USART_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) USART Interrupt Enable Clear */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_USART_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) USART Interrupt Enable Set */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_USART_INTFLAG_Type INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) USART Interrupt Flag Status and Clear */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_USART_STATUS_Type  STATUS;      /**< \brief Offset: 0x1A (R/W 16) USART Status */
+  __I  SERCOM_USART_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) USART Syncbusy */
+       RoReg8                    Reserved6[0x8];
+  __IO SERCOM_USART_DATA_Type    DATA;        /**< \brief Offset: 0x28 (R/W 16) USART Data */
+       RoReg8                    Reserved7[0x6];
+  __IO SERCOM_USART_DBGCTRL_Type DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) USART Debug Control */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       SercomI2cm                I2CM;        /**< \brief Offset: 0x00 I2C Master Mode */
+       SercomI2cs                I2CS;        /**< \brief Offset: 0x00 I2C Slave Mode */
+       SercomSpi                 SPI;         /**< \brief Offset: 0x00 SPI Mode */
+       SercomUsart               USART;       /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SERCOM_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/sysctrl.h b/uf2-samdx1/lib/samd21/samd21a/include/component/sysctrl.h
new file mode 100644
index 00000000..c02b1344
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/sysctrl.h
@@ -0,0 +1,933 @@
+/**
+ * \file
+ *
+ * \brief Component description for SYSCTRL
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_COMPONENT_
+#define _SAMD21_SYSCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SYSCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SYSCTRL System Control */
+/*@{*/
+
+#define SYSCTRL_U2100
+#define REV_SYSCTRL                 0x201
+
+/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready Interrupt Enable     */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready Interrupt Enable      */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready Interrupt Enable       */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready Interrupt Enable       */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection Interrupt Enable   */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready Interrupt Enable */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise Interrupt Enable    */
+    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall Interrupt Enable    */
+    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout Interrupt Enable */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENCLR_OFFSET     0x00         /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define SYSCTRL_INTENCLR_RESETVALUE _U(0x00000000) /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSCRDY    (_U(0x1) << SYSCTRL_INTENCLR_XOSCRDY_Pos)
+#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSC32KRDY (_U(0x1) << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC32KRDY  (_U(0x1) << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC8MRDY   (_U(0x1) << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRDY    (_U(0x1) << SYSCTRL_INTENCLR_DFLLRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLOOB    (_U(0x1) << SYSCTRL_INTENCLR_DFLLOOB_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKF   (_U(0x1) << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKC   (_U(0x1) << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
+#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRCS    (_U(0x1) << SYSCTRL_INTENCLR_DFLLRCS_Pos)
+#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33RDY   (_U(0x1) << SYSCTRL_INTENCLR_BOD33RDY_Pos)
+#define SYSCTRL_INTENCLR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33DET   (_U(0x1) << SYSCTRL_INTENCLR_BOD33DET_Pos)
+#define SYSCTRL_INTENCLR_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_B33SRDY    (_U(0x1) << SYSCTRL_INTENCLR_B33SRDY_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKR   (_U(0x1) << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKF   (_U(0x1) << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLTO    (_U(0x1) << SYSCTRL_INTENCLR_DPLLLTO_Pos)
+#define SYSCTRL_INTENCLR_MASK       _U(0x00038FFF) /**< \brief (SYSCTRL_INTENCLR) MASK Register */
+
+/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready Interrupt Enable     */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready Interrupt Enable      */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready Interrupt Enable       */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready Interrupt Enable       */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection Interrupt Enable   */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready Interrupt Enable */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise Interrupt Enable    */
+    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall Interrupt Enable    */
+    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout Interrupt Enable */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENSET_OFFSET     0x04         /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
+#define SYSCTRL_INTENSET_RESETVALUE _U(0x00000000) /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define SYSCTRL_INTENSET_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSCRDY    (_U(0x1) << SYSCTRL_INTENSET_XOSCRDY_Pos)
+#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSC32KRDY (_U(0x1) << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC32KRDY  (_U(0x1) << SYSCTRL_INTENSET_OSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC8MRDY   (_U(0x1) << SYSCTRL_INTENSET_OSC8MRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRDY    (_U(0x1) << SYSCTRL_INTENSET_DFLLRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLOOB    (_U(0x1) << SYSCTRL_INTENSET_DFLLOOB_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKF   (_U(0x1) << SYSCTRL_INTENSET_DFLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKC   (_U(0x1) << SYSCTRL_INTENSET_DFLLLCKC_Pos)
+#define SYSCTRL_INTENSET_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRCS    (_U(0x1) << SYSCTRL_INTENSET_DFLLRCS_Pos)
+#define SYSCTRL_INTENSET_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33RDY   (_U(0x1) << SYSCTRL_INTENSET_BOD33RDY_Pos)
+#define SYSCTRL_INTENSET_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33DET   (_U(0x1) << SYSCTRL_INTENSET_BOD33DET_Pos)
+#define SYSCTRL_INTENSET_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_B33SRDY    (_U(0x1) << SYSCTRL_INTENSET_B33SRDY_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKR   (_U(0x1) << SYSCTRL_INTENSET_DPLLLCKR_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKF   (_U(0x1) << SYSCTRL_INTENSET_DPLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLTO    (_U(0x1) << SYSCTRL_INTENSET_DPLLLTO_Pos)
+#define SYSCTRL_INTENSET_MASK       _U(0x00038FFF) /**< \brief (SYSCTRL_INTENSET) MASK Register */
+
+/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    __I uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    __I uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    __I uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    __I uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    __I uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    __I uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    __I uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    __I uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    __I uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    __I uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    __I uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    __I uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    __I uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise                     */
+    __I uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall                     */
+    __I uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout                  */
+    __I uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTFLAG_OFFSET      0x08         /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define SYSCTRL_INTFLAG_RESETVALUE  _U(0x00000000) /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0            /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
+#define SYSCTRL_INTFLAG_XOSCRDY     (_U(0x1) << SYSCTRL_INTFLAG_XOSCRDY_Pos)
+#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
+#define SYSCTRL_INTFLAG_XOSC32KRDY  (_U(0x1) << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
+#define SYSCTRL_INTFLAG_OSC32KRDY   (_U(0x1) << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
+#define SYSCTRL_INTFLAG_OSC8MRDY    (_U(0x1) << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4            /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
+#define SYSCTRL_INTFLAG_DFLLRDY     (_U(0x1) << SYSCTRL_INTFLAG_DFLLRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5            /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
+#define SYSCTRL_INTFLAG_DFLLOOB     (_U(0x1) << SYSCTRL_INTFLAG_DFLLOOB_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
+#define SYSCTRL_INTFLAG_DFLLLCKF    (_U(0x1) << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
+#define SYSCTRL_INTFLAG_DFLLLCKC    (_U(0x1) << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
+#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8            /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define SYSCTRL_INTFLAG_DFLLRCS     (_U(0x1) << SYSCTRL_INTFLAG_DFLLRCS_Pos)
+#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
+#define SYSCTRL_INTFLAG_BOD33RDY    (_U(0x1) << SYSCTRL_INTFLAG_BOD33RDY_Pos)
+#define SYSCTRL_INTFLAG_BOD33DET_Pos 10           /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
+#define SYSCTRL_INTFLAG_BOD33DET    (_U(0x1) << SYSCTRL_INTFLAG_BOD33DET_Pos)
+#define SYSCTRL_INTFLAG_B33SRDY_Pos 11           /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
+#define SYSCTRL_INTFLAG_B33SRDY     (_U(0x1) << SYSCTRL_INTFLAG_B33SRDY_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
+#define SYSCTRL_INTFLAG_DPLLLCKR    (_U(0x1) << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
+#define SYSCTRL_INTFLAG_DPLLLCKF    (_U(0x1) << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17           /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
+#define SYSCTRL_INTFLAG_DPLLLTO     (_U(0x1) << SYSCTRL_INTFLAG_DPLLLTO_Pos)
+#define SYSCTRL_INTFLAG_MASK        _U(0x00038FFF) /**< \brief (SYSCTRL_INTFLAG) MASK Register */
+
+/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
+    uint32_t OSC32KRDY:1;      /*!< bit:      2  OSC32K Ready                       */
+    uint32_t OSC8MRDY:1;       /*!< bit:      3  OSC8M Ready                        */
+    uint32_t DFLLRDY:1;        /*!< bit:      4  DFLL Ready                         */
+    uint32_t DFLLOOB:1;        /*!< bit:      5  DFLL Out Of Bounds                 */
+    uint32_t DFLLLCKF:1;       /*!< bit:      6  DFLL Lock Fine                     */
+    uint32_t DFLLLCKC:1;       /*!< bit:      7  DFLL Lock Coarse                   */
+    uint32_t DFLLRCS:1;        /*!< bit:      8  DFLL Reference Clock Stopped       */
+    uint32_t BOD33RDY:1;       /*!< bit:      9  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:     10  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:     11  BOD33 Synchronization Ready        */
+    uint32_t :3;               /*!< bit: 12..14  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     15  DPLL Lock Rise                     */
+    uint32_t DPLLLCKF:1;       /*!< bit:     16  DPLL Lock Fall                     */
+    uint32_t DPLLLTO:1;        /*!< bit:     17  DPLL Lock Timeout                  */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_PCLKSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_PCLKSR_OFFSET       0x0C         /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
+#define SYSCTRL_PCLKSR_RESETVALUE   _U(0x00000000) /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
+
+#define SYSCTRL_PCLKSR_XOSCRDY_Pos  0            /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
+#define SYSCTRL_PCLKSR_XOSCRDY      (_U(0x1) << SYSCTRL_PCLKSR_XOSCRDY_Pos)
+#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1            /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
+#define SYSCTRL_PCLKSR_XOSC32KRDY   (_U(0x1) << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2            /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
+#define SYSCTRL_PCLKSR_OSC32KRDY    (_U(0x1) << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3            /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
+#define SYSCTRL_PCLKSR_OSC8MRDY     (_U(0x1) << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLRDY_Pos  4            /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
+#define SYSCTRL_PCLKSR_DFLLRDY      (_U(0x1) << SYSCTRL_PCLKSR_DFLLRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLOOB_Pos  5            /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
+#define SYSCTRL_PCLKSR_DFLLOOB      (_U(0x1) << SYSCTRL_PCLKSR_DFLLOOB_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
+#define SYSCTRL_PCLKSR_DFLLLCKF     (_U(0x1) << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7            /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
+#define SYSCTRL_PCLKSR_DFLLLCKC     (_U(0x1) << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
+#define SYSCTRL_PCLKSR_DFLLRCS_Pos  8            /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
+#define SYSCTRL_PCLKSR_DFLLRCS      (_U(0x1) << SYSCTRL_PCLKSR_DFLLRCS_Pos)
+#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9            /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
+#define SYSCTRL_PCLKSR_BOD33RDY     (_U(0x1) << SYSCTRL_PCLKSR_BOD33RDY_Pos)
+#define SYSCTRL_PCLKSR_BOD33DET_Pos 10           /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
+#define SYSCTRL_PCLKSR_BOD33DET     (_U(0x1) << SYSCTRL_PCLKSR_BOD33DET_Pos)
+#define SYSCTRL_PCLKSR_B33SRDY_Pos  11           /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
+#define SYSCTRL_PCLKSR_B33SRDY      (_U(0x1) << SYSCTRL_PCLKSR_B33SRDY_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
+#define SYSCTRL_PCLKSR_DPLLLCKR     (_U(0x1) << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
+#define SYSCTRL_PCLKSR_DPLLLCKF     (_U(0x1) << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DPLLLTO_Pos  17           /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
+#define SYSCTRL_PCLKSR_DPLLLTO      (_U(0x1) << SYSCTRL_PCLKSR_DPLLLTO_Pos)
+#define SYSCTRL_PCLKSR_MASK         _U(0x00038FFF) /**< \brief (SYSCTRL_PCLKSR) MASK Register */
+
+/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t GAIN:3;           /*!< bit:  8..10  Oscillator Gain                    */
+    uint16_t AMPGC:1;          /*!< bit:     11  Automatic Amplitude Gain Control   */
+    uint16_t STARTUP:4;        /*!< bit: 12..15  Start-Up Time                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_XOSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC_OFFSET         0x10         /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define SYSCTRL_XOSC_RESETVALUE     _U(0x0080)   /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
+
+#define SYSCTRL_XOSC_ENABLE_Pos     1            /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
+#define SYSCTRL_XOSC_ENABLE         (_U(0x1) << SYSCTRL_XOSC_ENABLE_Pos)
+#define SYSCTRL_XOSC_XTALEN_Pos     2            /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC_XTALEN         (_U(0x1) << SYSCTRL_XOSC_XTALEN_Pos)
+#define SYSCTRL_XOSC_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_XOSC) Run in Standby */
+#define SYSCTRL_XOSC_RUNSTDBY       (_U(0x1) << SYSCTRL_XOSC_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC_ONDEMAND_Pos   7            /**< \brief (SYSCTRL_XOSC) On Demand Control */
+#define SYSCTRL_XOSC_ONDEMAND       (_U(0x1) << SYSCTRL_XOSC_ONDEMAND_Pos)
+#define SYSCTRL_XOSC_GAIN_Pos       8            /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
+#define SYSCTRL_XOSC_GAIN_Msk       (_U(0x7) << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN(value)    (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos))
+#define   SYSCTRL_XOSC_GAIN_0_Val         _U(0x0)   /**< \brief (SYSCTRL_XOSC) 2MHz */
+#define   SYSCTRL_XOSC_GAIN_1_Val         _U(0x1)   /**< \brief (SYSCTRL_XOSC) 4MHz */
+#define   SYSCTRL_XOSC_GAIN_2_Val         _U(0x2)   /**< \brief (SYSCTRL_XOSC) 8MHz */
+#define   SYSCTRL_XOSC_GAIN_3_Val         _U(0x3)   /**< \brief (SYSCTRL_XOSC) 16MHz */
+#define   SYSCTRL_XOSC_GAIN_4_Val         _U(0x4)   /**< \brief (SYSCTRL_XOSC) 30MHz */
+#define SYSCTRL_XOSC_GAIN_0         (SYSCTRL_XOSC_GAIN_0_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_1         (SYSCTRL_XOSC_GAIN_1_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_2         (SYSCTRL_XOSC_GAIN_2_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_3         (SYSCTRL_XOSC_GAIN_3_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_4         (SYSCTRL_XOSC_GAIN_4_Val       << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_AMPGC_Pos      11           /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
+#define SYSCTRL_XOSC_AMPGC          (_U(0x1) << SYSCTRL_XOSC_AMPGC_Pos)
+#define SYSCTRL_XOSC_STARTUP_Pos    12           /**< \brief (SYSCTRL_XOSC) Start-Up Time */
+#define SYSCTRL_XOSC_STARTUP_Msk    (_U(0xF) << SYSCTRL_XOSC_STARTUP_Pos)
+#define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos))
+#define SYSCTRL_XOSC_MASK           _U(0xFFC6)   /**< \brief (SYSCTRL_XOSC) MASK Register */
+
+/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t EN32K:1;          /*!< bit:      3  32kHz Output Enable                */
+    uint16_t EN1K:1;           /*!< bit:      4  1kHz Output Enable                 */
+    uint16_t AAMPEN:1;         /*!< bit:      5  Automatic Amplitude Control Enable */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC32K_OFFSET      0x14         /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define SYSCTRL_XOSC32K_RESETVALUE  _U(0x0080)   /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define SYSCTRL_XOSC32K_ENABLE_Pos  1            /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
+#define SYSCTRL_XOSC32K_ENABLE      (_U(0x1) << SYSCTRL_XOSC32K_ENABLE_Pos)
+#define SYSCTRL_XOSC32K_XTALEN_Pos  2            /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC32K_XTALEN      (_U(0x1) << SYSCTRL_XOSC32K_XTALEN_Pos)
+#define SYSCTRL_XOSC32K_EN32K_Pos   3            /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN32K       (_U(0x1) << SYSCTRL_XOSC32K_EN32K_Pos)
+#define SYSCTRL_XOSC32K_EN1K_Pos    4            /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN1K        (_U(0x1) << SYSCTRL_XOSC32K_EN1K_Pos)
+#define SYSCTRL_XOSC32K_AAMPEN_Pos  5            /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
+#define SYSCTRL_XOSC32K_AAMPEN      (_U(0x1) << SYSCTRL_XOSC32K_AAMPEN_Pos)
+#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
+#define SYSCTRL_XOSC32K_RUNSTDBY    (_U(0x1) << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
+#define SYSCTRL_XOSC32K_ONDEMAND    (_U(0x1) << SYSCTRL_XOSC32K_ONDEMAND_Pos)
+#define SYSCTRL_XOSC32K_STARTUP_Pos 8            /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_XOSC32K_STARTUP_Msk (_U(0x7) << SYSCTRL_XOSC32K_STARTUP_Pos)
+#define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos))
+#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12           /**< \brief (SYSCTRL_XOSC32K) Write Lock */
+#define SYSCTRL_XOSC32K_WRTLOCK     (_U(0x1) << SYSCTRL_XOSC32K_WRTLOCK_Pos)
+#define SYSCTRL_XOSC32K_MASK        _U(0x17FE)   /**< \brief (SYSCTRL_XOSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint32_t EN32K:1;          /*!< bit:      2  32kHz Output Enable                */
+    uint32_t EN1K:1;           /*!< bit:      3  1kHz Output Enable                 */
+    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint32_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t CALIB:7;          /*!< bit: 16..22  Oscillator Calibration             */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_OSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC32K_OFFSET       0x18         /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
+#define SYSCTRL_OSC32K_RESETVALUE   _U(0x003F0080) /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
+
+#define SYSCTRL_OSC32K_ENABLE_Pos   1            /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
+#define SYSCTRL_OSC32K_ENABLE       (_U(0x1) << SYSCTRL_OSC32K_ENABLE_Pos)
+#define SYSCTRL_OSC32K_EN32K_Pos    2            /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
+#define SYSCTRL_OSC32K_EN32K        (_U(0x1) << SYSCTRL_OSC32K_EN32K_Pos)
+#define SYSCTRL_OSC32K_EN1K_Pos     3            /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
+#define SYSCTRL_OSC32K_EN1K         (_U(0x1) << SYSCTRL_OSC32K_EN1K_Pos)
+#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_OSC32K) Run in Standby */
+#define SYSCTRL_OSC32K_RUNSTDBY     (_U(0x1) << SYSCTRL_OSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_OSC32K_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_OSC32K) On Demand Control */
+#define SYSCTRL_OSC32K_ONDEMAND     (_U(0x1) << SYSCTRL_OSC32K_ONDEMAND_Pos)
+#define SYSCTRL_OSC32K_STARTUP_Pos  8            /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_OSC32K_STARTUP_Msk  (_U(0x7) << SYSCTRL_OSC32K_STARTUP_Pos)
+#define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos))
+#define SYSCTRL_OSC32K_WRTLOCK_Pos  12           /**< \brief (SYSCTRL_OSC32K) Write Lock */
+#define SYSCTRL_OSC32K_WRTLOCK      (_U(0x1) << SYSCTRL_OSC32K_WRTLOCK_Pos)
+#define SYSCTRL_OSC32K_CALIB_Pos    16           /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
+#define SYSCTRL_OSC32K_CALIB_Msk    (_U(0x7F) << SYSCTRL_OSC32K_CALIB_Pos)
+#define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos))
+#define SYSCTRL_OSC32K_MASK         _U(0x007F17CE) /**< \brief (SYSCTRL_OSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W  8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CALIB:5;          /*!< bit:  0.. 4  Oscillator Calibration             */
+    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint8_t  WRTLOCK:1;        /*!< bit:      7  Write Lock                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSCULP32K_OFFSET    0x1C         /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define SYSCTRL_OSCULP32K_RESETVALUE _U(0x1F)     /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define SYSCTRL_OSCULP32K_CALIB_Pos 0            /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
+#define SYSCTRL_OSCULP32K_CALIB_Msk (_U(0x1F) << SYSCTRL_OSCULP32K_CALIB_Pos)
+#define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos))
+#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7            /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
+#define SYSCTRL_OSCULP32K_WRTLOCK   (_U(0x1) << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
+#define SYSCTRL_OSCULP32K_MASK      _U(0x9F)     /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
+
+/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint32_t :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint32_t PRESC:2;          /*!< bit:  8.. 9  Oscillator Prescaler               */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t CALIB:12;         /*!< bit: 16..27  Oscillator Calibration             */
+    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
+    uint32_t FRANGE:2;         /*!< bit: 30..31  Oscillator Frequency Range         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_OSC8M_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC8M_OFFSET        0x20         /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
+#define SYSCTRL_OSC8M_RESETVALUE    _U(0x87070382) /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
+
+#define SYSCTRL_OSC8M_ENABLE_Pos    1            /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
+#define SYSCTRL_OSC8M_ENABLE        (_U(0x1) << SYSCTRL_OSC8M_ENABLE_Pos)
+#define SYSCTRL_OSC8M_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_OSC8M) Run in Standby */
+#define SYSCTRL_OSC8M_RUNSTDBY      (_U(0x1) << SYSCTRL_OSC8M_RUNSTDBY_Pos)
+#define SYSCTRL_OSC8M_ONDEMAND_Pos  7            /**< \brief (SYSCTRL_OSC8M) On Demand Control */
+#define SYSCTRL_OSC8M_ONDEMAND      (_U(0x1) << SYSCTRL_OSC8M_ONDEMAND_Pos)
+#define SYSCTRL_OSC8M_PRESC_Pos     8            /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
+#define SYSCTRL_OSC8M_PRESC_Msk     (_U(0x3) << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC(value)  (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos))
+#define   SYSCTRL_OSC8M_PRESC_0_Val       _U(0x0)   /**< \brief (SYSCTRL_OSC8M) 1 */
+#define   SYSCTRL_OSC8M_PRESC_1_Val       _U(0x1)   /**< \brief (SYSCTRL_OSC8M) 2 */
+#define   SYSCTRL_OSC8M_PRESC_2_Val       _U(0x2)   /**< \brief (SYSCTRL_OSC8M) 4 */
+#define   SYSCTRL_OSC8M_PRESC_3_Val       _U(0x3)   /**< \brief (SYSCTRL_OSC8M) 8 */
+#define SYSCTRL_OSC8M_PRESC_0       (SYSCTRL_OSC8M_PRESC_0_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_1       (SYSCTRL_OSC8M_PRESC_1_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_2       (SYSCTRL_OSC8M_PRESC_2_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_3       (SYSCTRL_OSC8M_PRESC_3_Val     << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_CALIB_Pos     16           /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
+#define SYSCTRL_OSC8M_CALIB_Msk     (_U(0xFFF) << SYSCTRL_OSC8M_CALIB_Pos)
+#define SYSCTRL_OSC8M_CALIB(value)  (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos))
+#define SYSCTRL_OSC8M_FRANGE_Pos    30           /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
+#define SYSCTRL_OSC8M_FRANGE_Msk    (_U(0x3) << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos))
+#define   SYSCTRL_OSC8M_FRANGE_0_Val      _U(0x0)   /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
+#define   SYSCTRL_OSC8M_FRANGE_1_Val      _U(0x1)   /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
+#define   SYSCTRL_OSC8M_FRANGE_2_Val      _U(0x2)   /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
+#define   SYSCTRL_OSC8M_FRANGE_3_Val      _U(0x3)   /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
+#define SYSCTRL_OSC8M_FRANGE_0      (SYSCTRL_OSC8M_FRANGE_0_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_1      (SYSCTRL_OSC8M_FRANGE_1_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_2      (SYSCTRL_OSC8M_FRANGE_2_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_3      (SYSCTRL_OSC8M_FRANGE_3_Val    << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_MASK          _U(0xCFFF03C2) /**< \brief (SYSCTRL_OSC8M) MASK Register */
+
+/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  DFLL Enable                        */
+    uint16_t MODE:1;           /*!< bit:      2  Operating Mode Selection           */
+    uint16_t STABLE:1;         /*!< bit:      3  Stable DFLL Frequency              */
+    uint16_t LLAW:1;           /*!< bit:      4  Lose Lock After Wake               */
+    uint16_t USBCRM:1;         /*!< bit:      5  USB Clock Recovery Mode            */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t CCDIS:1;          /*!< bit:      8  Chill Cycle Disable                */
+    uint16_t QLDIS:1;          /*!< bit:      9  Quick Lock Disable                 */
+    uint16_t BPLCKC:1;         /*!< bit:     10  Bypass Coarse Lock                 */
+    uint16_t WAITLOCK:1;       /*!< bit:     11  Wait Lock                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLCTRL_OFFSET     0x24         /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
+#define SYSCTRL_DFLLCTRL_RESETVALUE _U(0x0080)   /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
+
+#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1            /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
+#define SYSCTRL_DFLLCTRL_ENABLE     (_U(0x1) << SYSCTRL_DFLLCTRL_ENABLE_Pos)
+#define SYSCTRL_DFLLCTRL_MODE_Pos   2            /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
+#define SYSCTRL_DFLLCTRL_MODE       (_U(0x1) << SYSCTRL_DFLLCTRL_MODE_Pos)
+#define SYSCTRL_DFLLCTRL_STABLE_Pos 3            /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
+#define SYSCTRL_DFLLCTRL_STABLE     (_U(0x1) << SYSCTRL_DFLLCTRL_STABLE_Pos)
+#define SYSCTRL_DFLLCTRL_LLAW_Pos   4            /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
+#define SYSCTRL_DFLLCTRL_LLAW       (_U(0x1) << SYSCTRL_DFLLCTRL_LLAW_Pos)
+#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5            /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
+#define SYSCTRL_DFLLCTRL_USBCRM     (_U(0x1) << SYSCTRL_DFLLCTRL_USBCRM_Pos)
+#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
+#define SYSCTRL_DFLLCTRL_RUNSTDBY   (_U(0x1) << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
+#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
+#define SYSCTRL_DFLLCTRL_ONDEMAND   (_U(0x1) << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
+#define SYSCTRL_DFLLCTRL_CCDIS_Pos  8            /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
+#define SYSCTRL_DFLLCTRL_CCDIS      (_U(0x1) << SYSCTRL_DFLLCTRL_CCDIS_Pos)
+#define SYSCTRL_DFLLCTRL_QLDIS_Pos  9            /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
+#define SYSCTRL_DFLLCTRL_QLDIS      (_U(0x1) << SYSCTRL_DFLLCTRL_QLDIS_Pos)
+#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10           /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
+#define SYSCTRL_DFLLCTRL_BPLCKC     (_U(0x1) << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
+#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11           /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
+#define SYSCTRL_DFLLCTRL_WAITLOCK   (_U(0x1) << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
+#define SYSCTRL_DFLLCTRL_MASK       _U(0x0FFE)   /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
+
+/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FINE:10;          /*!< bit:  0.. 9  Fine Value                         */
+    uint32_t COARSE:6;         /*!< bit: 10..15  Coarse Value                       */
+    uint32_t DIFF:16;          /*!< bit: 16..31  Multiplication Ratio Difference    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLVAL_OFFSET      0x28         /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
+#define SYSCTRL_DFLLVAL_RESETVALUE  _U(0x00000000) /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define SYSCTRL_DFLLVAL_FINE_Pos    0            /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
+#define SYSCTRL_DFLLVAL_FINE_Msk    (_U(0x3FF) << SYSCTRL_DFLLVAL_FINE_Pos)
+#define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos))
+#define SYSCTRL_DFLLVAL_COARSE_Pos  10           /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
+#define SYSCTRL_DFLLVAL_COARSE_Msk  (_U(0x3F) << SYSCTRL_DFLLVAL_COARSE_Pos)
+#define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos))
+#define SYSCTRL_DFLLVAL_DIFF_Pos    16           /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define SYSCTRL_DFLLVAL_DIFF_Msk    (_U(0xFFFF) << SYSCTRL_DFLLVAL_DIFF_Pos)
+#define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos))
+#define SYSCTRL_DFLLVAL_MASK        _U(0xFFFFFFFF) /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
+
+/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUL:16;           /*!< bit:  0..15  DFLL Multiply Factor               */
+    uint32_t FSTEP:10;         /*!< bit: 16..25  Fine Maximum Step                  */
+    uint32_t CSTEP:6;          /*!< bit: 26..31  Coarse Maximum Step                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLMUL_OFFSET      0x2C         /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define SYSCTRL_DFLLMUL_RESETVALUE  _U(0x00000000) /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define SYSCTRL_DFLLMUL_MUL_Pos     0            /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
+#define SYSCTRL_DFLLMUL_MUL_Msk     (_U(0xFFFF) << SYSCTRL_DFLLMUL_MUL_Pos)
+#define SYSCTRL_DFLLMUL_MUL(value)  (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos))
+#define SYSCTRL_DFLLMUL_FSTEP_Pos   16           /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
+#define SYSCTRL_DFLLMUL_FSTEP_Msk   (_U(0x3FF) << SYSCTRL_DFLLMUL_FSTEP_Pos)
+#define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos))
+#define SYSCTRL_DFLLMUL_CSTEP_Pos   26           /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
+#define SYSCTRL_DFLLMUL_CSTEP_Msk   (_U(0x3F) << SYSCTRL_DFLLMUL_CSTEP_Pos)
+#define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos))
+#define SYSCTRL_DFLLMUL_MASK        _U(0xFFFFFFFF) /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
+
+/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W  8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  READREQ:1;        /*!< bit:      7  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLSYNC_OFFSET     0x30         /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define SYSCTRL_DFLLSYNC_RESETVALUE _U(0x00)     /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define SYSCTRL_DFLLSYNC_READREQ_Pos 7            /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
+#define SYSCTRL_DFLLSYNC_READREQ    (_U(0x1) << SYSCTRL_DFLLSYNC_READREQ_Pos)
+#define SYSCTRL_DFLLSYNC_MASK       _U(0x80)     /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
+
+/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t HYST:1;           /*!< bit:      2  Hysteresis                         */
+    uint32_t ACTION:2;         /*!< bit:  3.. 4  BOD33 Action                       */
+    uint32_t :1;               /*!< bit:      5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MODE:1;           /*!< bit:      8  Operation Mode                     */
+    uint32_t CEN:1;            /*!< bit:      9  Clock Enable                       */
+    uint32_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint32_t PSEL:4;           /*!< bit: 12..15  Prescaler Select                   */
+    uint32_t LEVEL:6;          /*!< bit: 16..21  BOD33 Threshold Level              */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_BOD33_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_BOD33_OFFSET        0x34         /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
+#define SYSCTRL_BOD33_RESETVALUE    _U(0x00000000) /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
+
+#define SYSCTRL_BOD33_ENABLE_Pos    1            /**< \brief (SYSCTRL_BOD33) Enable */
+#define SYSCTRL_BOD33_ENABLE        (_U(0x1) << SYSCTRL_BOD33_ENABLE_Pos)
+#define SYSCTRL_BOD33_HYST_Pos      2            /**< \brief (SYSCTRL_BOD33) Hysteresis */
+#define SYSCTRL_BOD33_HYST          (_U(0x1) << SYSCTRL_BOD33_HYST_Pos)
+#define SYSCTRL_BOD33_ACTION_Pos    3            /**< \brief (SYSCTRL_BOD33) BOD33 Action */
+#define SYSCTRL_BOD33_ACTION_Msk    (_U(0x3) << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos))
+#define   SYSCTRL_BOD33_ACTION_NONE_Val   _U(0x0)   /**< \brief (SYSCTRL_BOD33) No action */
+#define   SYSCTRL_BOD33_ACTION_RESET_Val  _U(0x1)   /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
+#define   SYSCTRL_BOD33_ACTION_INTERRUPT_Val _U(0x2)   /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
+#define SYSCTRL_BOD33_ACTION_NONE   (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_RESET  (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_RUNSTDBY_Pos  6            /**< \brief (SYSCTRL_BOD33) Run in Standby */
+#define SYSCTRL_BOD33_RUNSTDBY      (_U(0x1) << SYSCTRL_BOD33_RUNSTDBY_Pos)
+#define SYSCTRL_BOD33_MODE_Pos      8            /**< \brief (SYSCTRL_BOD33) Operation Mode */
+#define SYSCTRL_BOD33_MODE          (_U(0x1) << SYSCTRL_BOD33_MODE_Pos)
+#define SYSCTRL_BOD33_CEN_Pos       9            /**< \brief (SYSCTRL_BOD33) Clock Enable */
+#define SYSCTRL_BOD33_CEN           (_U(0x1) << SYSCTRL_BOD33_CEN_Pos)
+#define SYSCTRL_BOD33_PSEL_Pos      12           /**< \brief (SYSCTRL_BOD33) Prescaler Select */
+#define SYSCTRL_BOD33_PSEL_Msk      (_U(0xF) << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL(value)   (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos))
+#define   SYSCTRL_BOD33_PSEL_DIV2_Val     _U(0x0)   /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
+#define   SYSCTRL_BOD33_PSEL_DIV4_Val     _U(0x1)   /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
+#define   SYSCTRL_BOD33_PSEL_DIV8_Val     _U(0x2)   /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
+#define   SYSCTRL_BOD33_PSEL_DIV16_Val    _U(0x3)   /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
+#define   SYSCTRL_BOD33_PSEL_DIV32_Val    _U(0x4)   /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
+#define   SYSCTRL_BOD33_PSEL_DIV64_Val    _U(0x5)   /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
+#define   SYSCTRL_BOD33_PSEL_DIV128_Val   _U(0x6)   /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
+#define   SYSCTRL_BOD33_PSEL_DIV256_Val   _U(0x7)   /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
+#define   SYSCTRL_BOD33_PSEL_DIV512_Val   _U(0x8)   /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
+#define   SYSCTRL_BOD33_PSEL_DIV1K_Val    _U(0x9)   /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
+#define   SYSCTRL_BOD33_PSEL_DIV2K_Val    _U(0xA)   /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
+#define   SYSCTRL_BOD33_PSEL_DIV4K_Val    _U(0xB)   /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
+#define   SYSCTRL_BOD33_PSEL_DIV8K_Val    _U(0xC)   /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
+#define   SYSCTRL_BOD33_PSEL_DIV16K_Val   _U(0xD)   /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
+#define   SYSCTRL_BOD33_PSEL_DIV32K_Val   _U(0xE)   /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
+#define   SYSCTRL_BOD33_PSEL_DIV64K_Val   _U(0xF)   /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
+#define SYSCTRL_BOD33_PSEL_DIV2     (SYSCTRL_BOD33_PSEL_DIV2_Val   << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4     (SYSCTRL_BOD33_PSEL_DIV4_Val   << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8     (SYSCTRL_BOD33_PSEL_DIV8_Val   << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16    (SYSCTRL_BOD33_PSEL_DIV16_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32    (SYSCTRL_BOD33_PSEL_DIV32_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64    (SYSCTRL_BOD33_PSEL_DIV64_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV128   (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV256   (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV512   (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV1K    (SYSCTRL_BOD33_PSEL_DIV1K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV2K    (SYSCTRL_BOD33_PSEL_DIV2K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4K    (SYSCTRL_BOD33_PSEL_DIV4K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8K    (SYSCTRL_BOD33_PSEL_DIV8K_Val  << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16K   (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32K   (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64K   (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_LEVEL_Pos     16           /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
+#define SYSCTRL_BOD33_LEVEL_Msk     (_U(0x3F) << SYSCTRL_BOD33_LEVEL_Pos)
+#define SYSCTRL_BOD33_LEVEL(value)  (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos))
+#define SYSCTRL_BOD33_MASK          _U(0x003FF35E) /**< \brief (SYSCTRL_BOD33) MASK Register */
+
+/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t :6;               /*!< bit:  7..12  Reserved                           */
+    uint16_t FORCELDO:1;       /*!< bit:     13  Force LDO Voltage Regulator        */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_VREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREG_OFFSET         0x3C         /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
+#define SYSCTRL_VREG_RESETVALUE     _U(0x0000)   /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
+
+#define SYSCTRL_VREG_RUNSTDBY_Pos   6            /**< \brief (SYSCTRL_VREG) Run in Standby */
+#define SYSCTRL_VREG_RUNSTDBY       (_U(0x1) << SYSCTRL_VREG_RUNSTDBY_Pos)
+#define SYSCTRL_VREG_FORCELDO_Pos   13           /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
+#define SYSCTRL_VREG_FORCELDO       (_U(0x1) << SYSCTRL_VREG_FORCELDO_Pos)
+#define SYSCTRL_VREG_MASK           _U(0x2040)   /**< \brief (SYSCTRL_VREG) MASK Register */
+
+/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t TSEN:1;           /*!< bit:      1  Temperature Sensor Enable          */
+    uint32_t BGOUTEN:1;        /*!< bit:      2  Bandgap Output Enable              */
+    uint32_t :13;              /*!< bit:  3..15  Reserved                           */
+    uint32_t CALIB:11;         /*!< bit: 16..26  Bandgap Voltage Generator Calibration */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_VREF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREF_OFFSET         0x40         /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
+#define SYSCTRL_VREF_RESETVALUE     _U(0x00000000) /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
+
+#define SYSCTRL_VREF_TSEN_Pos       1            /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
+#define SYSCTRL_VREF_TSEN           (_U(0x1) << SYSCTRL_VREF_TSEN_Pos)
+#define SYSCTRL_VREF_BGOUTEN_Pos    2            /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
+#define SYSCTRL_VREF_BGOUTEN        (_U(0x1) << SYSCTRL_VREF_BGOUTEN_Pos)
+#define SYSCTRL_VREF_CALIB_Pos      16           /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
+#define SYSCTRL_VREF_CALIB_Msk      (_U(0x7FF) << SYSCTRL_VREF_CALIB_Pos)
+#define SYSCTRL_VREF_CALIB(value)   (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos))
+#define SYSCTRL_VREF_MASK           _U(0x07FF0006) /**< \brief (SYSCTRL_VREF) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W  8) DPLL Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  DPLL Enable                        */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Clock Activation         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLA_OFFSET    0x44         /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
+#define SYSCTRL_DPLLCTRLA_RESETVALUE _U(0x80)     /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
+
+#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1            /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
+#define SYSCTRL_DPLLCTRLA_ENABLE    (_U(0x1) << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6            /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY  (_U(0x1) << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7            /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
+#define SYSCTRL_DPLLCTRLA_ONDEMAND  (_U(0x1) << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define SYSCTRL_DPLLCTRLA_MASK      _U(0xC2)     /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LDR:12;           /*!< bit:  0..11  Loop Divider Ratio                 */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t LDRFRAC:4;        /*!< bit: 16..19  Loop Divider Ratio Fractional Part */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLRATIO_OFFSET    0x48         /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define SYSCTRL_DPLLRATIO_RESETVALUE _U(0x00000000) /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define SYSCTRL_DPLLRATIO_LDR_Pos   0            /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
+#define SYSCTRL_DPLLRATIO_LDR_Msk   (_U(0xFFF) << SYSCTRL_DPLLRATIO_LDR_Pos)
+#define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos))
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16           /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (_U(0xF) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos))
+#define SYSCTRL_DPLLRATIO_MASK      _U(0x000F0FFF) /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FILTER:2;         /*!< bit:  0.. 1  Proportional Integral Filter Selection */
+    uint32_t LPEN:1;           /*!< bit:      2  Low-Power Enable                   */
+    uint32_t WUF:1;            /*!< bit:      3  Wake Up Fast                       */
+    uint32_t REFCLK:2;         /*!< bit:  4.. 5  Reference Clock Selection          */
+    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint32_t LTIME:3;          /*!< bit:  8..10  Lock Time                          */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t LBYPASS:1;        /*!< bit:     12  Lock Bypass                        */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DIV:11;           /*!< bit: 16..26  Clock Divider                      */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SYSCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLB_OFFSET    0x4C         /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
+#define SYSCTRL_DPLLCTRLB_RESETVALUE _U(0x00000000) /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
+
+#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0            /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define SYSCTRL_DPLLCTRLB_FILTER_Msk (_U(0x3) << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos))
+#define   SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val _U(0x0)   /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
+#define   SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val _U(0x1)   /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
+#define   SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val _U(0x2)   /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
+#define   SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val _U(0x3)   /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_LPEN_Pos  2            /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
+#define SYSCTRL_DPLLCTRLB_LPEN      (_U(0x1) << SYSCTRL_DPLLCTRLB_LPEN_Pos)
+#define SYSCTRL_DPLLCTRLB_WUF_Pos   3            /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
+#define SYSCTRL_DPLLCTRLB_WUF       (_U(0x1) << SYSCTRL_DPLLCTRLB_WUF_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4            /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
+#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (_U(0x3) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos))
+#define   SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val _U(0x0)   /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
+#define   SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val _U(0x1)   /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
+#define   SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U(0x2)   /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8            /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
+#define SYSCTRL_DPLLCTRLB_LTIME_Msk (_U(0x7) << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos))
+#define   SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U(0x0)   /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
+#define   SYSCTRL_DPLLCTRLB_LTIME_8MS_Val _U(0x4)   /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
+#define   SYSCTRL_DPLLCTRLB_LTIME_9MS_Val _U(0x5)   /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
+#define   SYSCTRL_DPLLCTRLB_LTIME_10MS_Val _U(0x6)   /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
+#define   SYSCTRL_DPLLCTRLB_LTIME_11MS_Val _U(0x7)   /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12           /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
+#define SYSCTRL_DPLLCTRLB_LBYPASS   (_U(0x1) << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV_Pos   16           /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
+#define SYSCTRL_DPLLCTRLB_DIV_Msk   (_U(0x7FF) << SYSCTRL_DPLLCTRLB_DIV_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos))
+#define SYSCTRL_DPLLCTRLB_MASK      _U(0x07FF173F) /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/   8) DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  LOCK:1;           /*!< bit:      0  DPLL Lock Status                   */
+    uint8_t  CLKRDY:1;         /*!< bit:      1  Output Clock Ready                 */
+    uint8_t  ENABLE:1;         /*!< bit:      2  DPLL Enable                        */
+    uint8_t  DIV:1;            /*!< bit:      3  Divider Enable                     */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SYSCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLSTATUS_OFFSET   0x50         /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
+#define SYSCTRL_DPLLSTATUS_RESETVALUE _U(0x00)     /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0            /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
+#define SYSCTRL_DPLLSTATUS_LOCK     (_U(0x1) << SYSCTRL_DPLLSTATUS_LOCK_Pos)
+#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1            /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
+#define SYSCTRL_DPLLSTATUS_CLKRDY   (_U(0x1) << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2            /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
+#define SYSCTRL_DPLLSTATUS_ENABLE   (_U(0x1) << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
+#define SYSCTRL_DPLLSTATUS_DIV_Pos  3            /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
+#define SYSCTRL_DPLLSTATUS_DIV      (_U(0x1) << SYSCTRL_DPLLSTATUS_DIV_Pos)
+#define SYSCTRL_DPLLSTATUS_MASK     _U(0x0F)     /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief SYSCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO SYSCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+  __IO SYSCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+  __IO SYSCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+  __I  SYSCTRL_PCLKSR_Type       PCLKSR;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
+  __IO SYSCTRL_XOSC_Type         XOSC;        /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+       RoReg8                    Reserved1[0x2];
+  __IO SYSCTRL_XOSC32K_Type      XOSC32K;     /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+       RoReg8                    Reserved2[0x2];
+  __IO SYSCTRL_OSC32K_Type       OSC32K;      /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+  __IO SYSCTRL_OSCULP32K_Type    OSCULP32K;   /**< \brief Offset: 0x1C (R/W  8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+       RoReg8                    Reserved3[0x3];
+  __IO SYSCTRL_OSC8M_Type        OSC8M;       /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+  __IO SYSCTRL_DFLLCTRL_Type     DFLLCTRL;    /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+       RoReg8                    Reserved4[0x2];
+  __IO SYSCTRL_DFLLVAL_Type      DFLLVAL;     /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+  __IO SYSCTRL_DFLLMUL_Type      DFLLMUL;     /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+  __IO SYSCTRL_DFLLSYNC_Type     DFLLSYNC;    /**< \brief Offset: 0x30 (R/W  8) DFLL48M Synchronization */
+       RoReg8                    Reserved5[0x3];
+  __IO SYSCTRL_BOD33_Type        BOD33;       /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+       RoReg8                    Reserved6[0x4];
+  __IO SYSCTRL_VREG_Type         VREG;        /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+       RoReg8                    Reserved7[0x2];
+  __IO SYSCTRL_VREF_Type         VREF;        /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+  __IO SYSCTRL_DPLLCTRLA_Type    DPLLCTRLA;   /**< \brief Offset: 0x44 (R/W  8) DPLL Control A */
+       RoReg8                    Reserved8[0x3];
+  __IO SYSCTRL_DPLLRATIO_Type    DPLLRATIO;   /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+  __IO SYSCTRL_DPLLCTRLB_Type    DPLLCTRLB;   /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+  __I  SYSCTRL_DPLLSTATUS_Type   DPLLSTATUS;  /**< \brief Offset: 0x50 (R/   8) DPLL Status */
+} Sysctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/tc.h b/uf2-samdx1/lib/samd21/samd21a/include/component/tc.h
new file mode 100644
index 00000000..bc114922
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/tc.h
@@ -0,0 +1,669 @@
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC_COMPONENT_
+#define _SAMD21_TC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2212
+#define REV_TC                      0x121
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  TC Mode                            */
+    uint16_t :1;               /*!< bit:      4  Reserved                           */
+    uint16_t WAVEGEN:2;        /*!< bit:  5.. 6  Waveform Generation Operation      */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint16_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint16_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET             0x00         /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE         _U(0x0000)   /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos          0            /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST              (_U(0x1) << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos         1            /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE             (_U(0x1) << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos           2            /**< \brief (TC_CTRLA) TC Mode */
+#define TC_CTRLA_MODE_Msk           (_U(0x3) << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value)        (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
+#define   TC_CTRLA_MODE_COUNT16_Val       _U(0x0)   /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define   TC_CTRLA_MODE_COUNT8_Val        _U(0x1)   /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define   TC_CTRLA_MODE_COUNT32_Val       _U(0x2)   /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16       (TC_CTRLA_MODE_COUNT16_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8        (TC_CTRLA_MODE_COUNT8_Val      << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32       (TC_CTRLA_MODE_COUNT32_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_WAVEGEN_Pos        5            /**< \brief (TC_CTRLA) Waveform Generation Operation */
+#define TC_CTRLA_WAVEGEN_Msk        (_U(0x3) << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN(value)     (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
+#define   TC_CTRLA_WAVEGEN_NFRQ_Val       _U(0x0)   /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_MFRQ_Val       _U(0x1)   /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_NPWM_Val       _U(0x2)   /**< \brief (TC_CTRLA)  */
+#define   TC_CTRLA_WAVEGEN_MPWM_Val       _U(0x3)   /**< \brief (TC_CTRLA)  */
+#define TC_CTRLA_WAVEGEN_NFRQ       (TC_CTRLA_WAVEGEN_NFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MFRQ       (TC_CTRLA_WAVEGEN_MFRQ_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_NPWM       (TC_CTRLA_WAVEGEN_NPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MPWM       (TC_CTRLA_WAVEGEN_MPWM_Val     << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_PRESCALER_Pos      8            /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk      (_U(0x7) << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value)   (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
+#define   TC_CTRLA_PRESCALER_DIV1_Val     _U(0x0)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
+#define   TC_CTRLA_PRESCALER_DIV2_Val     _U(0x1)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
+#define   TC_CTRLA_PRESCALER_DIV4_Val     _U(0x2)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
+#define   TC_CTRLA_PRESCALER_DIV8_Val     _U(0x3)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
+#define   TC_CTRLA_PRESCALER_DIV16_Val    _U(0x4)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
+#define   TC_CTRLA_PRESCALER_DIV64_Val    _U(0x5)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
+#define   TC_CTRLA_PRESCALER_DIV256_Val   _U(0x6)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
+#define   TC_CTRLA_PRESCALER_DIV1024_Val  _U(0x7)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1     (TC_CTRLA_PRESCALER_DIV1_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2     (TC_CTRLA_PRESCALER_DIV2_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4     (TC_CTRLA_PRESCALER_DIV4_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8     (TC_CTRLA_PRESCALER_DIV8_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16    (TC_CTRLA_PRESCALER_DIV16_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64    (TC_CTRLA_PRESCALER_DIV64_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256   (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024  (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos       11           /**< \brief (TC_CTRLA) Run in Standby */
+#define TC_CTRLA_RUNSTDBY           (_U(0x1) << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos      12           /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk      (_U(0x3) << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value)   (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
+#define   TC_CTRLA_PRESCSYNC_GCLK_Val     _U(0x0)   /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
+#define   TC_CTRLA_PRESCSYNC_PRESC_Val    _U(0x1)   /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
+#define   TC_CTRLA_PRESCSYNC_RESYNC_Val   _U(0x2)   /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK     (TC_CTRLA_PRESCSYNC_GCLK_Val   << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC    (TC_CTRLA_PRESCSYNC_PRESC_Val  << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC   (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_MASK               _U(0x3F6F)   /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ADDR:5;           /*!< bit:  0.. 4  Address                            */
+    uint16_t :9;               /*!< bit:  5..13  Reserved                           */
+    uint16_t RCONT:1;          /*!< bit:     14  Read Continuously                  */
+    uint16_t RREQ:1;           /*!< bit:     15  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_READREQ_OFFSET           0x02         /**< \brief (TC_READREQ offset) Read Request */
+#define TC_READREQ_RESETVALUE       _U(0x0000)   /**< \brief (TC_READREQ reset_value) Read Request */
+
+#define TC_READREQ_ADDR_Pos         0            /**< \brief (TC_READREQ) Address */
+#define TC_READREQ_ADDR_Msk         (_U(0x1F) << TC_READREQ_ADDR_Pos)
+#define TC_READREQ_ADDR(value)      (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
+#define TC_READREQ_RCONT_Pos        14           /**< \brief (TC_READREQ) Read Continuously */
+#define TC_READREQ_RCONT            (_U(0x1) << TC_READREQ_RCONT_Pos)
+#define TC_READREQ_RREQ_Pos         15           /**< \brief (TC_READREQ) Read Request */
+#define TC_READREQ_RREQ             (_U(0x1) << TC_READREQ_RREQ_Pos)
+#define TC_READREQ_MASK             _U(0xC01F)   /**< \brief (TC_READREQ) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET          0x04         /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE      _U(0x02)     /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos         0            /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR             (_U(0x1) << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos     2            /**< \brief (TC_CTRLBCLR) One-Shot */
+#define TC_CTRLBCLR_ONESHOT         (_U(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos         6            /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk         (_U(0x3) << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value)      (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
+#define   TC_CTRLBCLR_CMD_NONE_Val        _U(0x0)   /**< \brief (TC_CTRLBCLR) No action */
+#define   TC_CTRLBCLR_CMD_RETRIGGER_Val   _U(0x1)   /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
+#define   TC_CTRLBCLR_CMD_STOP_Val        _U(0x2)   /**< \brief (TC_CTRLBCLR) Force a stop */
+#define TC_CTRLBCLR_CMD_NONE        (TC_CTRLBCLR_CMD_NONE_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER   (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP        (TC_CTRLBCLR_CMD_STOP_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK            _U(0xC5)     /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  CMD:2;            /*!< bit:  6.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET          0x05         /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE      _U(0x00)     /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos         0            /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR             (_U(0x1) << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos     2            /**< \brief (TC_CTRLBSET) One-Shot */
+#define TC_CTRLBSET_ONESHOT         (_U(0x1) << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos         6            /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk         (_U(0x3) << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value)      (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
+#define   TC_CTRLBSET_CMD_NONE_Val        _U(0x0)   /**< \brief (TC_CTRLBSET) No action */
+#define   TC_CTRLBSET_CMD_RETRIGGER_Val   _U(0x1)   /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
+#define   TC_CTRLBSET_CMD_STOP_Val        _U(0x2)   /**< \brief (TC_CTRLBSET) Force a stop */
+#define TC_CTRLBSET_CMD_NONE        (TC_CTRLBSET_CMD_NONE_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER   (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP        (TC_CTRLBSET_CMD_STOP_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK            _U(0xC5)     /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W  8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  INVEN0:1;         /*!< bit:      0  Output Waveform 0 Invert Enable    */
+    uint8_t  INVEN1:1;         /*!< bit:      1  Output Waveform 1 Invert Enable    */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CPTEN0:1;         /*!< bit:      4  Capture Channel 0 Enable           */
+    uint8_t  CPTEN1:1;         /*!< bit:      5  Capture Channel 1 Enable           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  INVEN:2;          /*!< bit:  0.. 1  Output Waveform x Invert Enable    */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CPTEN:2;          /*!< bit:  4.. 5  Capture Channel x Enable           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLC_OFFSET             0x06         /**< \brief (TC_CTRLC offset) Control C */
+#define TC_CTRLC_RESETVALUE         _U(0x00)     /**< \brief (TC_CTRLC reset_value) Control C */
+
+#define TC_CTRLC_INVEN0_Pos         0            /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
+#define TC_CTRLC_INVEN0             (1 << TC_CTRLC_INVEN0_Pos)
+#define TC_CTRLC_INVEN1_Pos         1            /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
+#define TC_CTRLC_INVEN1             (1 << TC_CTRLC_INVEN1_Pos)
+#define TC_CTRLC_INVEN_Pos          0            /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
+#define TC_CTRLC_INVEN_Msk          (_U(0x3) << TC_CTRLC_INVEN_Pos)
+#define TC_CTRLC_INVEN(value)       (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
+#define TC_CTRLC_CPTEN0_Pos         4            /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
+#define TC_CTRLC_CPTEN0             (1 << TC_CTRLC_CPTEN0_Pos)
+#define TC_CTRLC_CPTEN1_Pos         5            /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
+#define TC_CTRLC_CPTEN1             (1 << TC_CTRLC_CPTEN1_Pos)
+#define TC_CTRLC_CPTEN_Pos          4            /**< \brief (TC_CTRLC) Capture Channel x Enable */
+#define TC_CTRLC_CPTEN_Msk          (_U(0x3) << TC_CTRLC_CPTEN_Pos)
+#define TC_CTRLC_CPTEN(value)       (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
+#define TC_CTRLC_MASK               _U(0x33)     /**< \brief (TC_CTRLC) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run Mode                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET           0x08         /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE       _U(0x00)     /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (TC_DBGCTRL) Debug Run Mode */
+#define TC_DBGCTRL_DBGRUN           (_U(0x1) << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK             _U(0x01)     /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EVACT:3;          /*!< bit:  0.. 2  Event Action                       */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t TCINV:1;          /*!< bit:      4  TC Inverted Event Input            */
+    uint16_t TCEI:1;           /*!< bit:      5  TC Event Input                     */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Event Output Enable */
+    uint16_t :3;               /*!< bit:  9..11  Reserved                           */
+    uint16_t MCEO0:1;          /*!< bit:     12  Match or Capture Channel 0 Event Output Enable */
+    uint16_t MCEO1:1;          /*!< bit:     13  Match or Capture Channel 1 Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint16_t MCEO:2;           /*!< bit: 12..13  Match or Capture Channel x Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET            0x0A         /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE        _U(0x0000)   /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos         0            /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk         (_U(0x7) << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value)      (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
+#define   TC_EVCTRL_EVACT_OFF_Val         _U(0x0)   /**< \brief (TC_EVCTRL) Event action disabled */
+#define   TC_EVCTRL_EVACT_RETRIGGER_Val   _U(0x1)   /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define   TC_EVCTRL_EVACT_COUNT_Val       _U(0x2)   /**< \brief (TC_EVCTRL) Count on event */
+#define   TC_EVCTRL_EVACT_START_Val       _U(0x3)   /**< \brief (TC_EVCTRL) Start TC on event */
+#define   TC_EVCTRL_EVACT_PPW_Val         _U(0x5)   /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
+#define   TC_EVCTRL_EVACT_PWP_Val         _U(0x6)   /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
+#define TC_EVCTRL_EVACT_OFF         (TC_EVCTRL_EVACT_OFF_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER   (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT       (TC_EVCTRL_EVACT_COUNT_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START       (TC_EVCTRL_EVACT_START_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW         (TC_EVCTRL_EVACT_PPW_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP         (TC_EVCTRL_EVACT_PWP_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos         4            /**< \brief (TC_EVCTRL) TC Inverted Event Input */
+#define TC_EVCTRL_TCINV             (_U(0x1) << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos          5            /**< \brief (TC_EVCTRL) TC Event Input */
+#define TC_EVCTRL_TCEI              (_U(0x1) << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos         8            /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
+#define TC_EVCTRL_OVFEO             (_U(0x1) << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos         12           /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TC_EVCTRL_MCEO0             (1 << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos         13           /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TC_EVCTRL_MCEO1             (1 << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos          12           /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TC_EVCTRL_MCEO_Msk          (_U(0x3) << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value)       (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
+#define TC_EVCTRL_MASK              _U(0x3137)   /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
+    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET          0x0C         /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE      _U(0x00)     /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos         0            /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
+#define TC_INTENCLR_OVF             (_U(0x1) << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos         1            /**< \brief (TC_INTENCLR) Error Interrupt Enable */
+#define TC_INTENCLR_ERR             (_U(0x1) << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_SYNCRDY_Pos     3            /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define TC_INTENCLR_SYNCRDY         (_U(0x1) << TC_INTENCLR_SYNCRDY_Pos)
+#define TC_INTENCLR_MC0_Pos         4            /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENCLR_MC0             (1 << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos         5            /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENCLR_MC1             (1 << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos          4            /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENCLR_MC_Msk          (_U(0x3) << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value)       (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
+#define TC_INTENCLR_MASK            _U(0x3B)     /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready Interrupt Enable */
+    uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0 Interrupt Enable */
+    uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1 Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x Interrupt Enable */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET          0x0D         /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE      _U(0x00)     /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos         0            /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
+#define TC_INTENSET_OVF             (_U(0x1) << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos         1            /**< \brief (TC_INTENSET) Error Interrupt Enable */
+#define TC_INTENSET_ERR             (_U(0x1) << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_SYNCRDY_Pos     3            /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
+#define TC_INTENSET_SYNCRDY         (_U(0x1) << TC_INTENSET_SYNCRDY_Pos)
+#define TC_INTENSET_MC0_Pos         4            /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENSET_MC0             (1 << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos         5            /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENSET_MC1             (1 << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos          4            /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENSET_MC_Msk          (_U(0x3) << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value)       (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
+#define TC_INTENSET_MASK            _U(0x3B)     /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint8_t  ERR:1;            /*!< bit:      1  Error                              */
+    __I uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    __I uint8_t  SYNCRDY:1;        /*!< bit:      3  Synchronization Ready              */
+    __I uint8_t  MC0:1;            /*!< bit:      4  Match or Capture Channel 0         */
+    __I uint8_t  MC1:1;            /*!< bit:      5  Match or Capture Channel 1         */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    __I uint8_t  MC:2;             /*!< bit:  4.. 5  Match or Capture Channel x         */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET           0x0E         /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE       _U(0x00)     /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos          0            /**< \brief (TC_INTFLAG) Overflow */
+#define TC_INTFLAG_OVF              (_U(0x1) << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos          1            /**< \brief (TC_INTFLAG) Error */
+#define TC_INTFLAG_ERR              (_U(0x1) << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_SYNCRDY_Pos      3            /**< \brief (TC_INTFLAG) Synchronization Ready */
+#define TC_INTFLAG_SYNCRDY          (_U(0x1) << TC_INTFLAG_SYNCRDY_Pos)
+#define TC_INTFLAG_MC0_Pos          4            /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
+#define TC_INTFLAG_MC0              (1 << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos          5            /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
+#define TC_INTFLAG_MC1              (1 << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos           4            /**< \brief (TC_INTFLAG) Match or Capture Channel x */
+#define TC_INTFLAG_MC_Msk           (_U(0x3) << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value)        (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
+#define TC_INTFLAG_MASK             _U(0x3B)     /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0F) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :3;               /*!< bit:  0.. 2  Reserved                           */
+    uint8_t  STOP:1;           /*!< bit:      3  Stop                               */
+    uint8_t  SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET            0x0F         /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE        _U(0x08)     /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos          3            /**< \brief (TC_STATUS) Stop */
+#define TC_STATUS_STOP              (_U(0x1) << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos         4            /**< \brief (TC_STATUS) Slave */
+#define TC_STATUS_SLAVE             (_U(0x1) << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_SYNCBUSY_Pos      7            /**< \brief (TC_STATUS) Synchronization Busy */
+#define TC_STATUS_SYNCBUSY          (_U(0x1) << TC_STATUS_SYNCBUSY_Pos)
+#define TC_STATUS_MASK              _U(0x98)     /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Count Value                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
+#define TC_COUNT16_COUNT_RESETVALUE _U(0x0000)   /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
+
+#define TC_COUNT16_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT16_COUNT) Count Value */
+#define TC_COUNT16_COUNT_COUNT_Msk  (_U(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
+#define TC_COUNT16_COUNT_MASK       _U(0xFFFF)   /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Count Value                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET     0x10         /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
+#define TC_COUNT32_COUNT_RESETVALUE _U(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
+
+#define TC_COUNT32_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT32_COUNT) Count Value */
+#define TC_COUNT32_COUNT_COUNT_Msk  (_U(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
+#define TC_COUNT32_COUNT_MASK       _U(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W  8) COUNT8 COUNT8 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COUNT:8;          /*!< bit:  0.. 7  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET      0x10         /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
+#define TC_COUNT8_COUNT_RESETVALUE  _U(0x00)     /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
+
+#define TC_COUNT8_COUNT_COUNT_Pos   0            /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk   (_U(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
+#define TC_COUNT8_COUNT_MASK        _U(0xFF)     /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W  8) COUNT8 COUNT8 Period Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:8;            /*!< bit:  0.. 7  Period Value                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET        0x14         /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
+#define TC_COUNT8_PER_RESETVALUE    _U(0xFF)     /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
+
+#define TC_COUNT8_PER_PER_Pos       0            /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk       (_U(0xFF) << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value)    (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
+#define TC_COUNT8_PER_MASK          _U(0xFF)     /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CC:16;            /*!< bit:  0..15  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET        0x18         /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
+#define TC_COUNT16_CC_RESETVALUE    _U(0x0000)   /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
+
+#define TC_COUNT16_CC_CC_Pos        0            /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
+#define TC_COUNT16_CC_CC_Msk        (_U(0xFFFF) << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value)     (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
+#define TC_COUNT16_CC_MASK          _U(0xFFFF)   /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CC:32;            /*!< bit:  0..31  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET        0x18         /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
+#define TC_COUNT32_CC_RESETVALUE    _U(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
+
+#define TC_COUNT32_CC_CC_Pos        0            /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
+#define TC_COUNT32_CC_CC_Msk        (_U(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value)     (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
+#define TC_COUNT32_CC_MASK          _U(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W  8) COUNT8 COUNT8 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CC:8;             /*!< bit:  0.. 7  Compare/Capture Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET         0x18         /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
+#define TC_COUNT8_CC_RESETVALUE     _U(0x00)     /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
+
+#define TC_COUNT8_CC_CC_Pos         0            /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
+#define TC_COUNT8_CC_CC_Msk         (_U(0xFF) << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value)      (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
+#define TC_COUNT8_CC_MASK           _U(0xFF)     /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT8_COUNT_Type      COUNT;       /**< \brief Offset: 0x10 (R/W  8) COUNT8 Counter Value */
+       RoReg8                    Reserved3[0x3];
+  __IO TC_COUNT8_PER_Type        PER;         /**< \brief Offset: 0x14 (R/W  8) COUNT8 Period Value */
+       RoReg8                    Reserved4[0x3];
+  __IO TC_COUNT8_CC_Type         CC[2];       /**< \brief Offset: 0x18 (R/W  8) COUNT8 Compare/Capture */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT16_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+       RoReg8                    Reserved3[0x6];
+  __IO TC_COUNT16_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO TC_READREQ_Type           READREQ;     /**< \brief Offset: 0x02 (R/W 16) Read Request */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_CTRLC_Type             CTRLC;       /**< \brief Offset: 0x06 (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x08 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x1];
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x0A (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x0D (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
+  __I  TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0F (R/   8) Status */
+  __IO TC_COUNT32_COUNT_Type     COUNT;       /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+       RoReg8                    Reserved3[0x4];
+  __IO TC_COUNT32_CC_Type        CC[2];       /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       TcCount8                  COUNT8;      /**< \brief Offset: 0x00 8-bit Counter Mode */
+       TcCount16                 COUNT16;     /**< \brief Offset: 0x00 16-bit Counter Mode */
+       TcCount32                 COUNT32;     /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TC_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/tcc.h b/uf2-samdx1/lib/samd21/samd21a/include/component/tcc.h
new file mode 100644
index 00000000..8aa99003
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/tcc.h
@@ -0,0 +1,1802 @@
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC_COMPONENT_
+#define _SAMD21_TCC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC                     0x101
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
+    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
+    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
+    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
+    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
+    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
+    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
+    uint32_t CPTEN:4;          /*!< bit: 24..27  Capture Channel x Enable           */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE        _U(0x00000000) /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST             (_U(0x1) << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE            (_U(0x1) << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk    (_U(0x3) << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define   TCC_CTRLA_RESOLUTION_NONE_Val   _U(0x0)   /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define   TCC_CTRLA_RESOLUTION_DITH4_Val  _U(0x1)   /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH5_Val  _U(0x2)   /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH6_Val  _U(0x3)   /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk     (_U(0x7) << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define   TCC_CTRLA_PRESCALER_DIV1_Val    _U(0x0)   /**< \brief (TCC_CTRLA) No division */
+#define   TCC_CTRLA_PRESCALER_DIV2_Val    _U(0x1)   /**< \brief (TCC_CTRLA) Divide by 2 */
+#define   TCC_CTRLA_PRESCALER_DIV4_Val    _U(0x2)   /**< \brief (TCC_CTRLA) Divide by 4 */
+#define   TCC_CTRLA_PRESCALER_DIV8_Val    _U(0x3)   /**< \brief (TCC_CTRLA) Divide by 8 */
+#define   TCC_CTRLA_PRESCALER_DIV16_Val   _U(0x4)   /**< \brief (TCC_CTRLA) Divide by 16 */
+#define   TCC_CTRLA_PRESCALER_DIV64_Val   _U(0x5)   /**< \brief (TCC_CTRLA) Divide by 64 */
+#define   TCC_CTRLA_PRESCALER_DIV256_Val  _U(0x6)   /**< \brief (TCC_CTRLA) Divide by 256 */
+#define   TCC_CTRLA_PRESCALER_DIV1024_Val _U(0x7)   /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY          (_U(0x1) << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk     (_U(0x3) << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    _U(0x0)   /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   _U(0x1)   /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  _U(0x2)   /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK             (_U(0x1) << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0            (1 << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1            (1 << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2            (1 << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3            (1 << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk         (_U(0xF) << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK              _U(0x0F007F63) /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE     _U(0x00)     /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR            (_U(0x1) << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD           (_U(0x1) << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT        (_U(0x1) << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk     (_U(0x3) << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val _U(0x0)   /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBCLR_IDXCMD_SET_Val     _U(0x1)   /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   _U(0x2)   /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    _U(0x3)   /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk        (_U(0x7) << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define   TCC_CTRLBCLR_CMD_NONE_Val       _U(0x0)   /**< \brief (TCC_CTRLBCLR) No action */
+#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  _U(0x1)   /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define   TCC_CTRLBCLR_CMD_STOP_Val       _U(0x2)   /**< \brief (TCC_CTRLBCLR) Force stop */
+#define   TCC_CTRLBCLR_CMD_UPDATE_Val     _U(0x3)   /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
+#define   TCC_CTRLBCLR_CMD_READSYNC_Val   _U(0x4)   /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK           _U(0xFF)     /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE     _U(0x00)     /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR            (_U(0x1) << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD           (_U(0x1) << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT        (_U(0x1) << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk     (_U(0x3) << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val _U(0x0)   /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBSET_IDXCMD_SET_Val     _U(0x1)   /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   _U(0x2)   /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    _U(0x3)   /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk        (_U(0x7) << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define   TCC_CTRLBSET_CMD_NONE_Val       _U(0x0)   /**< \brief (TCC_CTRLBSET) No action */
+#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  _U(0x1)   /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define   TCC_CTRLBSET_CMD_STOP_Val       _U(0x2)   /**< \brief (TCC_CTRLBSET) Force stop */
+#define   TCC_CTRLBSET_CMD_UPDATE_Val     _U(0x3)   /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
+#define   TCC_CTRLBSET_CMD_READSYNC_Val   _U(0x4)   /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK           _U(0xFF)     /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
+    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
+    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
+    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
+    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
+    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
+    uint32_t PER:1;            /*!< bit:      7  Period busy                        */
+    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
+    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
+    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
+    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t PATTB:1;          /*!< bit:     16  Pattern Buffer Busy                */
+    uint32_t WAVEB:1;          /*!< bit:     17  Wave Buffer Busy                   */
+    uint32_t PERB:1;           /*!< bit:     18  Period Buffer Busy                 */
+    uint32_t CCB0:1;           /*!< bit:     19  Compare Channel Buffer 0 Busy      */
+    uint32_t CCB1:1;           /*!< bit:     20  Compare Channel Buffer 1 Busy      */
+    uint32_t CCB2:1;           /*!< bit:     21  Compare Channel Buffer 2 Busy      */
+    uint32_t CCB3:1;           /*!< bit:     22  Compare Channel Buffer 3 Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CC:4;             /*!< bit:  8..11  Compare Channel x Busy             */
+    uint32_t :7;               /*!< bit: 12..18  Reserved                           */
+    uint32_t CCB:4;            /*!< bit: 19..22  Compare Channel Buffer x Busy      */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE     _U(0x00000000) /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST          (_U(0x1) << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE         (_U(0x1) << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB          (_U(0x1) << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS         (_U(0x1) << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT          (_U(0x1) << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT           (_U(0x1) << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE           (_U(0x1) << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period busy */
+#define TCC_SYNCBUSY_PER            (_U(0x1) << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0            (1 << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1            (1 << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2            (1 << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3            (1 << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk         (_U(0xF) << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_PATTB_Pos      16           /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
+#define TCC_SYNCBUSY_PATTB          (_U(0x1) << TCC_SYNCBUSY_PATTB_Pos)
+#define TCC_SYNCBUSY_WAVEB_Pos      17           /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
+#define TCC_SYNCBUSY_WAVEB          (_U(0x1) << TCC_SYNCBUSY_WAVEB_Pos)
+#define TCC_SYNCBUSY_PERB_Pos       18           /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
+#define TCC_SYNCBUSY_PERB           (_U(0x1) << TCC_SYNCBUSY_PERB_Pos)
+#define TCC_SYNCBUSY_CCB0_Pos       19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CCB0           (1 << TCC_SYNCBUSY_CCB0_Pos)
+#define TCC_SYNCBUSY_CCB1_Pos       20           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CCB1           (1 << TCC_SYNCBUSY_CCB1_Pos)
+#define TCC_SYNCBUSY_CCB2_Pos       21           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CCB2           (1 << TCC_SYNCBUSY_CCB2_Pos)
+#define TCC_SYNCBUSY_CCB3_Pos       22           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CCB3           (1 << TCC_SYNCBUSY_CCB3_Pos)
+#define TCC_SYNCBUSY_CCB_Pos        19           /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CCB_Msk        (_U(0xF) << TCC_SYNCBUSY_CCB_Pos)
+#define TCC_SYNCBUSY_CCB(value)     (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
+#define TCC_SYNCBUSY_MASK           _U(0x007F0FFF) /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE       _U(0x00000000) /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk          (_U(0x3) << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define   TCC_FCTRLA_SRC_DISABLE_Val      _U(0x0)   /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define   TCC_FCTRLA_SRC_ENABLE_Val       _U(0x1)   /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_INVERT_Val       _U(0x2)   /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_ALTFAULT_Val     _U(0x3)   /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP             (_U(0x1) << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL             (_U(0x1) << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk        (_U(0x3) << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define   TCC_FCTRLA_BLANK_NONE_Val       _U(0x0)   /**< \brief (TCC_FCTRLA) No blanking applied */
+#define   TCC_FCTRLA_BLANK_RISE_Val       _U(0x1)   /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_FALL_Val       _U(0x2)   /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_BOTH_Val       _U(0x3)   /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_NONE       (TCC_FCTRLA_BLANK_NONE_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART          (_U(0x1) << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk         (_U(0x3) << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define   TCC_FCTRLA_HALT_DISABLE_Val     _U(0x0)   /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define   TCC_FCTRLA_HALT_HW_Val          _U(0x1)   /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define   TCC_FCTRLA_HALT_SW_Val          _U(0x2)   /**< \brief (TCC_FCTRLA) Software halt action */
+#define   TCC_FCTRLA_HALT_NR_Val          _U(0x3)   /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk        (_U(0x3) << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define   TCC_FCTRLA_CHSEL_CC0_Val        _U(0x0)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define   TCC_FCTRLA_CHSEL_CC1_Val        _U(0x1)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define   TCC_FCTRLA_CHSEL_CC2_Val        _U(0x2)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define   TCC_FCTRLA_CHSEL_CC3_Val        _U(0x3)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk      (_U(0x7) << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  _U(0x0)   /**< \brief (TCC_FCTRLA) No capture */
+#define   TCC_FCTRLA_CAPTURE_CAPT_Val     _U(0x1)   /**< \brief (TCC_FCTRLA) Capture on fault */
+#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  _U(0x2)   /**< \brief (TCC_FCTRLA) Minimum capture */
+#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  _U(0x3)   /**< \brief (TCC_FCTRLA) Maximum capture */
+#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   _U(0x4)   /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   _U(0x5)   /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   _U(0x6)   /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk     (_U(0xFF) << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk    (_U(0xF) << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK             _U(0x0FFF7FFB) /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE       _U(0x00000000) /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk          (_U(0x3) << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define   TCC_FCTRLB_SRC_DISABLE_Val      _U(0x0)   /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define   TCC_FCTRLB_SRC_ENABLE_Val       _U(0x1)   /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_INVERT_Val       _U(0x2)   /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_ALTFAULT_Val     _U(0x3)   /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP             (_U(0x1) << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL             (_U(0x1) << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk        (_U(0x3) << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define   TCC_FCTRLB_BLANK_NONE_Val       _U(0x0)   /**< \brief (TCC_FCTRLB) No blanking applied */
+#define   TCC_FCTRLB_BLANK_RISE_Val       _U(0x1)   /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_FALL_Val       _U(0x2)   /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_BOTH_Val       _U(0x3)   /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_NONE       (TCC_FCTRLB_BLANK_NONE_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART          (_U(0x1) << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk         (_U(0x3) << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define   TCC_FCTRLB_HALT_DISABLE_Val     _U(0x0)   /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define   TCC_FCTRLB_HALT_HW_Val          _U(0x1)   /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define   TCC_FCTRLB_HALT_SW_Val          _U(0x2)   /**< \brief (TCC_FCTRLB) Software halt action */
+#define   TCC_FCTRLB_HALT_NR_Val          _U(0x3)   /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk        (_U(0x3) << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define   TCC_FCTRLB_CHSEL_CC0_Val        _U(0x0)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define   TCC_FCTRLB_CHSEL_CC1_Val        _U(0x1)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define   TCC_FCTRLB_CHSEL_CC2_Val        _U(0x2)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define   TCC_FCTRLB_CHSEL_CC3_Val        _U(0x3)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk      (_U(0x7) << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  _U(0x0)   /**< \brief (TCC_FCTRLB) No capture */
+#define   TCC_FCTRLB_CAPTURE_CAPT_Val     _U(0x1)   /**< \brief (TCC_FCTRLB) Capture on fault */
+#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  _U(0x2)   /**< \brief (TCC_FCTRLB) Minimum capture */
+#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  _U(0x3)   /**< \brief (TCC_FCTRLB) Maximum capture */
+#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   _U(0x4)   /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   _U(0x5)   /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   _U(0x6)   /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk     (_U(0xFF) << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk    (_U(0xF) << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK             _U(0x0FFF7FFB) /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
+    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
+    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
+    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
+    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
+    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE      _U(0x00000000) /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk        (_U(0x3) << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0          (1 << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1          (1 << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2          (1 << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3          (1 << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk       (_U(0xF) << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk        (_U(0xFF) << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk        (_U(0xFF) << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK            _U(0xFFFF0F03) /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
+    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
+    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
+    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
+    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
+    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
+    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
+    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
+    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
+    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
+    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
+    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
+    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
+    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
+    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
+    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
+    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
+    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
+    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
+    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
+    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
+    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
+    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
+    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
+    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
+    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
+    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
+    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE      _U(0x00000000) /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0            (1 << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1            (1 << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2            (1 << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3            (1 << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4            (1 << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5            (1 << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6            (1 << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7            (1 << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk         (_U(0xFF) << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0            (1 << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1            (1 << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2            (1 << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3            (1 << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4            (1 << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5            (1 << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6            (1 << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7            (1 << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk         (_U(0xFF) << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0          (1 << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1          (1 << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2          (1 << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3          (1 << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4          (1 << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5          (1 << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6          (1 << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7          (1 << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk       (_U(0xFF) << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk  (_U(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk  (_U(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK            _U(0xFFFFFFFF) /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE      _U(0x00)     /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN          (_U(0x1) << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD           (_U(0x1) << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK            _U(0x05)     /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
+    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
+    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
+    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
+    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
+    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
+    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
+    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
+    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
+    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
+    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
+    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
+    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
+    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
+    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
+    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
+    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
+    uint32_t MCEI:4;           /*!< bit: 16..19  Match or Capture Channel x Event Input Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t MCEO:4;           /*!< bit: 24..27  Match or Capture Channel x Event Output Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE       _U(0x00000000) /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk       (_U(0x7) << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define   TCC_EVCTRL_EVACT0_OFF_Val       _U(0x0)   /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val _U(0x1)   /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   _U(0x2)   /**< \brief (TCC_EVCTRL) Count on event */
+#define   TCC_EVCTRL_EVACT0_START_Val     _U(0x3)   /**< \brief (TCC_EVCTRL) Start counter on event */
+#define   TCC_EVCTRL_EVACT0_INC_Val       _U(0x4)   /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNT_Val     _U(0x5)   /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define   TCC_EVCTRL_EVACT0_FAULT_Val     _U(0x7)   /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk       (_U(0x7) << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define   TCC_EVCTRL_EVACT1_OFF_Val       _U(0x0)   /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val _U(0x1)   /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT1_DIR_Val       _U(0x2)   /**< \brief (TCC_EVCTRL) Direction control */
+#define   TCC_EVCTRL_EVACT1_STOP_Val      _U(0x3)   /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define   TCC_EVCTRL_EVACT1_DEC_Val       _U(0x4)   /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define   TCC_EVCTRL_EVACT1_PPW_Val       _U(0x5)   /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define   TCC_EVCTRL_EVACT1_PWP_Val       _U(0x6)   /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define   TCC_EVCTRL_EVACT1_FAULT_Val     _U(0x7)   /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk       (_U(0x3) << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define   TCC_EVCTRL_CNTSEL_START_Val     _U(0x0)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define   TCC_EVCTRL_CNTSEL_END_Val       _U(0x1)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   _U(0x2)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  _U(0x3)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO            (_U(0x1) << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO            (_U(0x1) << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO            (_U(0x1) << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0           (1 << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1           (1 << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk        (_U(0x3) << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0            (1 << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1            (1 << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk         (_U(0x3) << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0            (1 << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1            (1 << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2            (1 << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3            (1 << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk         (_U(0xF) << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0            (1 << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1            (1 << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2            (1 << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3            (1 << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk         (_U(0xF) << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK             _U(0x0F0FF7FF) /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :7;               /*!< bit:  4..10  Reserved                           */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE     _U(0x00000000) /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF            (_U(0x1) << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG            (_U(0x1) << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT            (_U(0x1) << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR            (_U(0x1) << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS            (_U(0x1) << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA         (_U(0x1) << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB         (_U(0x1) << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0         (_U(0x1) << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1         (_U(0x1) << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0            (1 << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1            (1 << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2            (1 << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3            (1 << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk         (_U(0xF) << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK           _U(0x000FF80F) /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :7;               /*!< bit:  4..10  Reserved                           */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:4;             /*!< bit: 16..19  Match or Capture Channel x Interrupt Enable */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE     _U(0x00000000) /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF            (_U(0x1) << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG            (_U(0x1) << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT            (_U(0x1) << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR            (_U(0x1) << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS            (_U(0x1) << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA         (_U(0x1) << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB         (_U(0x1) << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0         (_U(0x1) << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1         (_U(0x1) << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0            (1 << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1            (1 << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2            (1 << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3            (1 << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk         (_U(0xF) << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK           _U(0x000FF80F) /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
+    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
+    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
+    __I uint32_t :7;               /*!< bit:  4..10  Reserved                           */
+    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
+    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
+    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
+    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
+    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
+    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
+    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
+    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
+    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    __I uint32_t MC:4;             /*!< bit: 16..19  Match or Capture x                 */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE      _U(0x00000000) /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF             (_U(0x1) << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG             (_U(0x1) << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT             (_U(0x1) << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR             (_U(0x1) << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS             (_U(0x1) << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA          (_U(0x1) << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB          (_U(0x1) << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0          (_U(0x1) << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1          (_U(0x1) << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0             (1 << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1             (1 << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2             (1 << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3             (1 << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk          (_U(0xF) << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK            _U(0x000FF80F) /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
+    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
+    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint32_t PATTBV:1;         /*!< bit:      5  Pattern Buffer Valid               */
+    uint32_t WAVEBV:1;         /*!< bit:      6  Wave Buffer Valid                  */
+    uint32_t PERBV:1;          /*!< bit:      7  Period Buffer Valid                */
+    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
+    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
+    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
+    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
+    uint32_t CCBV0:1;          /*!< bit:     16  Compare Channel 0 Buffer Valid     */
+    uint32_t CCBV1:1;          /*!< bit:     17  Compare Channel 1 Buffer Valid     */
+    uint32_t CCBV2:1;          /*!< bit:     18  Compare Channel 2 Buffer Valid     */
+    uint32_t CCBV3:1;          /*!< bit:     19  Compare Channel 3 Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
+    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
+    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
+    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t CCBV:4;           /*!< bit: 16..19  Compare Channel x Buffer Valid     */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t CMP:4;            /*!< bit: 24..27  Compare Channel x Value            */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE       _U(0x00000001) /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP             (_U(0x1) << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX              (_U(0x1) << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS              (_U(0x1) << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE            (_U(0x1) << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBV_Pos       5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBV           (_U(0x1) << TCC_STATUS_PATTBV_Pos)
+#define TCC_STATUS_WAVEBV_Pos       6            /**< \brief (TCC_STATUS) Wave Buffer Valid */
+#define TCC_STATUS_WAVEBV           (_U(0x1) << TCC_STATUS_WAVEBV_Pos)
+#define TCC_STATUS_PERBV_Pos        7            /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBV            (_U(0x1) << TCC_STATUS_PERBV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN         (_U(0x1) << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN         (_U(0x1) << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN         (_U(0x1) << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN         (_U(0x1) << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA           (_U(0x1) << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB           (_U(0x1) << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0           (_U(0x1) << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1           (_U(0x1) << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBV0_Pos        16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBV0            (1 << TCC_STATUS_CCBV0_Pos)
+#define TCC_STATUS_CCBV1_Pos        17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBV1            (1 << TCC_STATUS_CCBV1_Pos)
+#define TCC_STATUS_CCBV2_Pos        18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBV2            (1 << TCC_STATUS_CCBV2_Pos)
+#define TCC_STATUS_CCBV3_Pos        19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBV3            (1 << TCC_STATUS_CCBV3_Pos)
+#define TCC_STATUS_CCBV_Pos         16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBV_Msk         (_U(0xF) << TCC_STATUS_CCBV_Pos)
+#define TCC_STATUS_CCBV(value)      (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
+#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0             (1 << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1             (1 << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2             (1 << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3             (1 << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk          (_U(0xF) << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK             _U(0x0F0FFFFB) /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE        _U(0x00000000) /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk   (_U(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK        _U(0x00FFFFF0) /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk   (_U(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK        _U(0x00FFFFE0) /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk   (_U(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK        _U(0x00FFFFC0) /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk         (_U(0xFFFFFF) << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK              _U(0x00FFFFFF) /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
+    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
+    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
+    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
+    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
+    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
+    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
+    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
+    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
+    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
+    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
+    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
+    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
+    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
+    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
+    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
+    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE         _U(0x0000)   /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0               (1 << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1               (1 << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2               (1 << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3               (1 << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4               (1 << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5               (1 << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6               (1 << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7               (1 << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk            (_U(0xFF) << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0               (1 << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1               (1 << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2               (1 << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3               (1 << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4               (1 << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5               (1 << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6               (1 << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7               (1 << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk            (_U(0xFF) << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK               _U(0xFFFF)   /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
+    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
+    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
+    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
+    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
+    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
+    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
+    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
+    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
+    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
+    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL:4;            /*!< bit: 16..19  Channel x Polarity                 */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE         _U(0x00000000) /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk        (_U(0x7) << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define   TCC_WAVE_WAVEGEN_NFRQ_Val       _U(0x0)   /**< \brief (TCC_WAVE) Normal frequency */
+#define   TCC_WAVE_WAVEGEN_MFRQ_Val       _U(0x1)   /**< \brief (TCC_WAVE) Match frequency */
+#define   TCC_WAVE_WAVEGEN_NPWM_Val       _U(0x2)   /**< \brief (TCC_WAVE) Normal PWM */
+#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val _U(0x4)   /**< \brief (TCC_WAVE) Dual-slope critical */
+#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   _U(0x5)   /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     _U(0x6)   /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVE_WAVEGEN_DSTOP_Val      _U(0x7)   /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk           (_U(0x3) << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define   TCC_WAVE_RAMP_RAMP1_Val         _U(0x0)   /**< \brief (TCC_WAVE) RAMP1 operation */
+#define   TCC_WAVE_RAMP_RAMP2A_Val        _U(0x1)   /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2_Val         _U(0x2)   /**< \brief (TCC_WAVE) RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN            (_U(0x1) << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0            (1 << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1            (1 << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2            (1 << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3            (1 << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk         (_U(0xF) << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0               (1 << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1               (1 << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2               (1 << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3               (1 << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk            (_U(0xF) << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0              (1 << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1              (1 << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2              (1 << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3              (1 << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk           (_U(0xF) << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK               _U(0x0F0F0FB7) /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE          _U(0xFFFFFFFF) /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHERCY_Msk  (_U(0xF) << TCC_PER_DITH4_DITHERCY_Pos)
+#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
+#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk       (_U(0xFFFFF) << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK          _U(0x00FFFFFF) /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHERCY_Msk  (_U(0x1F) << TCC_PER_DITH5_DITHERCY_Pos)
+#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
+#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk       (_U(0x7FFFF) << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK          _U(0x00FFFFFF) /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHERCY_Msk  (_U(0x3F) << TCC_PER_DITH6_DITHERCY_Pos)
+#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
+#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk       (_U(0x3FFFF) << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK          _U(0x00FFFFFF) /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk             (_U(0xFFFFFF) << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK                _U(0x00FFFFFF) /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE           _U(0x00000000) /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHERCY_Msk   (_U(0xF) << TCC_CC_DITH4_DITHERCY_Pos)
+#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
+#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk         (_U(0xFFFFF) << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK           _U(0x00FFFFFF) /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHERCY_Msk   (_U(0x1F) << TCC_CC_DITH5_DITHERCY_Pos)
+#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
+#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk         (_U(0x7FFFF) << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK           _U(0x00FFFFFF) /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHERCY_Msk   (_U(0x3F) << TCC_CC_DITH6_DITHERCY_Pos)
+#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
+#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk         (_U(0x3FFFF) << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK           _U(0x00FFFFFF) /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk               (_U(0xFFFFFF) << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK                 _U(0x00FFFFFF) /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
+    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
+    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
+    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
+    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
+    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
+    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
+    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
+    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
+    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
+    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
+    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
+    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
+    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
+    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
+    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
+    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATTB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTB_OFFSET            0x64         /**< \brief (TCC_PATTB offset) Pattern Buffer */
+#define TCC_PATTB_RESETVALUE        _U(0x0000)   /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
+
+#define TCC_PATTB_PGEB0_Pos         0            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTB_PGEB0             (1 << TCC_PATTB_PGEB0_Pos)
+#define TCC_PATTB_PGEB1_Pos         1            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTB_PGEB1             (1 << TCC_PATTB_PGEB1_Pos)
+#define TCC_PATTB_PGEB2_Pos         2            /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTB_PGEB2             (1 << TCC_PATTB_PGEB2_Pos)
+#define TCC_PATTB_PGEB3_Pos         3            /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTB_PGEB3             (1 << TCC_PATTB_PGEB3_Pos)
+#define TCC_PATTB_PGEB4_Pos         4            /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTB_PGEB4             (1 << TCC_PATTB_PGEB4_Pos)
+#define TCC_PATTB_PGEB5_Pos         5            /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTB_PGEB5             (1 << TCC_PATTB_PGEB5_Pos)
+#define TCC_PATTB_PGEB6_Pos         6            /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTB_PGEB6             (1 << TCC_PATTB_PGEB6_Pos)
+#define TCC_PATTB_PGEB7_Pos         7            /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTB_PGEB7             (1 << TCC_PATTB_PGEB7_Pos)
+#define TCC_PATTB_PGEB_Pos          0            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTB_PGEB_Msk          (_U(0xFF) << TCC_PATTB_PGEB_Pos)
+#define TCC_PATTB_PGEB(value)       (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
+#define TCC_PATTB_PGVB0_Pos         8            /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
+#define TCC_PATTB_PGVB0             (1 << TCC_PATTB_PGVB0_Pos)
+#define TCC_PATTB_PGVB1_Pos         9            /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
+#define TCC_PATTB_PGVB1             (1 << TCC_PATTB_PGVB1_Pos)
+#define TCC_PATTB_PGVB2_Pos         10           /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
+#define TCC_PATTB_PGVB2             (1 << TCC_PATTB_PGVB2_Pos)
+#define TCC_PATTB_PGVB3_Pos         11           /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
+#define TCC_PATTB_PGVB3             (1 << TCC_PATTB_PGVB3_Pos)
+#define TCC_PATTB_PGVB4_Pos         12           /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
+#define TCC_PATTB_PGVB4             (1 << TCC_PATTB_PGVB4_Pos)
+#define TCC_PATTB_PGVB5_Pos         13           /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
+#define TCC_PATTB_PGVB5             (1 << TCC_PATTB_PGVB5_Pos)
+#define TCC_PATTB_PGVB6_Pos         14           /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
+#define TCC_PATTB_PGVB6             (1 << TCC_PATTB_PGVB6_Pos)
+#define TCC_PATTB_PGVB7_Pos         15           /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
+#define TCC_PATTB_PGVB7             (1 << TCC_PATTB_PGVB7_Pos)
+#define TCC_PATTB_PGVB_Pos          8            /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
+#define TCC_PATTB_PGVB_Msk          (_U(0xFF) << TCC_PATTB_PGVB_Pos)
+#define TCC_PATTB_PGVB(value)       (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
+#define TCC_PATTB_MASK              _U(0xFFFF)   /**< \brief (TCC_PATTB) MASK Register */
+
+/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGENB:3;       /*!< bit:  0.. 2  Waveform Generation Buffer         */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMPB:2;          /*!< bit:  4.. 5  Ramp Mode Buffer                   */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPERENB:1;       /*!< bit:      7  Circular Period Enable Buffer      */
+    uint32_t CICCENB0:1;       /*!< bit:      8  Circular Channel 0 Enable Buffer   */
+    uint32_t CICCENB1:1;       /*!< bit:      9  Circular Channel 1 Enable Buffer   */
+    uint32_t CICCENB2:1;       /*!< bit:     10  Circular Channel 2 Enable Buffer   */
+    uint32_t CICCENB3:1;       /*!< bit:     11  Circular Channel 3 Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB0:1;          /*!< bit:     16  Channel 0 Polarity Buffer          */
+    uint32_t POLB1:1;          /*!< bit:     17  Channel 1 Polarity Buffer          */
+    uint32_t POLB2:1;          /*!< bit:     18  Channel 2 Polarity Buffer          */
+    uint32_t POLB3:1;          /*!< bit:     19  Channel 3 Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB0:1;         /*!< bit:     24  Swap DTI Output Pair 0 Buffer      */
+    uint32_t SWAPB1:1;         /*!< bit:     25  Swap DTI Output Pair 1 Buffer      */
+    uint32_t SWAPB2:1;         /*!< bit:     26  Swap DTI Output Pair 2 Buffer      */
+    uint32_t SWAPB3:1;         /*!< bit:     27  Swap DTI Output Pair 3 Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCENB:4;        /*!< bit:  8..11  Circular Channel x Enable Buffer   */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POLB:4;           /*!< bit: 16..19  Channel x Polarity Buffer          */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t SWAPB:4;          /*!< bit: 24..27  Swap DTI Output Pair x Buffer      */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVEB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVEB_OFFSET            0x68         /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
+#define TCC_WAVEB_RESETVALUE        _U(0x00000000) /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
+
+#define TCC_WAVEB_WAVEGENB_Pos      0            /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
+#define TCC_WAVEB_WAVEGENB_Msk      (_U(0x7) << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB(value)   (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
+#define   TCC_WAVEB_WAVEGENB_NFRQ_Val     _U(0x0)   /**< \brief (TCC_WAVEB) Normal frequency */
+#define   TCC_WAVEB_WAVEGENB_MFRQ_Val     _U(0x1)   /**< \brief (TCC_WAVEB) Match frequency */
+#define   TCC_WAVEB_WAVEGENB_NPWM_Val     _U(0x2)   /**< \brief (TCC_WAVEB) Normal PWM */
+#define   TCC_WAVEB_WAVEGENB_DSCRITICAL_Val _U(0x4)   /**< \brief (TCC_WAVEB) Dual-slope critical */
+#define   TCC_WAVEB_WAVEGENB_DSBOTTOM_Val _U(0x5)   /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVEB_WAVEGENB_DSBOTH_Val   _U(0x6)   /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVEB_WAVEGENB_DSTOP_Val    _U(0x7)   /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVEB_WAVEGENB_NFRQ     (TCC_WAVEB_WAVEGENB_NFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_MFRQ     (TCC_WAVEB_WAVEGENB_MFRQ_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_NPWM     (TCC_WAVEB_WAVEGENB_NPWM_Val   << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTH   (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSTOP    (TCC_WAVEB_WAVEGENB_DSTOP_Val  << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_RAMPB_Pos         4            /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
+#define TCC_WAVEB_RAMPB_Msk         (_U(0x3) << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB(value)      (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
+#define   TCC_WAVEB_RAMPB_RAMP1_Val       _U(0x0)   /**< \brief (TCC_WAVEB) RAMP1 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2A_Val      _U(0x1)   /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
+#define   TCC_WAVEB_RAMPB_RAMP2_Val       _U(0x2)   /**< \brief (TCC_WAVEB) RAMP2 operation */
+#define TCC_WAVEB_RAMPB_RAMP1       (TCC_WAVEB_RAMPB_RAMP1_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2A      (TCC_WAVEB_RAMPB_RAMP2A_Val    << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2       (TCC_WAVEB_RAMPB_RAMP2_Val     << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_CIPERENB_Pos      7            /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
+#define TCC_WAVEB_CIPERENB          (_U(0x1) << TCC_WAVEB_CIPERENB_Pos)
+#define TCC_WAVEB_CICCENB0_Pos      8            /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
+#define TCC_WAVEB_CICCENB0          (1 << TCC_WAVEB_CICCENB0_Pos)
+#define TCC_WAVEB_CICCENB1_Pos      9            /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
+#define TCC_WAVEB_CICCENB1          (1 << TCC_WAVEB_CICCENB1_Pos)
+#define TCC_WAVEB_CICCENB2_Pos      10           /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
+#define TCC_WAVEB_CICCENB2          (1 << TCC_WAVEB_CICCENB2_Pos)
+#define TCC_WAVEB_CICCENB3_Pos      11           /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
+#define TCC_WAVEB_CICCENB3          (1 << TCC_WAVEB_CICCENB3_Pos)
+#define TCC_WAVEB_CICCENB_Pos       8            /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
+#define TCC_WAVEB_CICCENB_Msk       (_U(0xF) << TCC_WAVEB_CICCENB_Pos)
+#define TCC_WAVEB_CICCENB(value)    (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
+#define TCC_WAVEB_POLB0_Pos         16           /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
+#define TCC_WAVEB_POLB0             (1 << TCC_WAVEB_POLB0_Pos)
+#define TCC_WAVEB_POLB1_Pos         17           /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
+#define TCC_WAVEB_POLB1             (1 << TCC_WAVEB_POLB1_Pos)
+#define TCC_WAVEB_POLB2_Pos         18           /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
+#define TCC_WAVEB_POLB2             (1 << TCC_WAVEB_POLB2_Pos)
+#define TCC_WAVEB_POLB3_Pos         19           /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
+#define TCC_WAVEB_POLB3             (1 << TCC_WAVEB_POLB3_Pos)
+#define TCC_WAVEB_POLB_Pos          16           /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
+#define TCC_WAVEB_POLB_Msk          (_U(0xF) << TCC_WAVEB_POLB_Pos)
+#define TCC_WAVEB_POLB(value)       (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
+#define TCC_WAVEB_SWAPB0_Pos        24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
+#define TCC_WAVEB_SWAPB0            (1 << TCC_WAVEB_SWAPB0_Pos)
+#define TCC_WAVEB_SWAPB1_Pos        25           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
+#define TCC_WAVEB_SWAPB1            (1 << TCC_WAVEB_SWAPB1_Pos)
+#define TCC_WAVEB_SWAPB2_Pos        26           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
+#define TCC_WAVEB_SWAPB2            (1 << TCC_WAVEB_SWAPB2_Pos)
+#define TCC_WAVEB_SWAPB3_Pos        27           /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
+#define TCC_WAVEB_SWAPB3            (1 << TCC_WAVEB_SWAPB3_Pos)
+#define TCC_WAVEB_SWAPB_Pos         24           /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
+#define TCC_WAVEB_SWAPB_Msk         (_U(0xF) << TCC_WAVEB_SWAPB_Pos)
+#define TCC_WAVEB_SWAPB(value)      (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
+#define TCC_WAVEB_MASK              _U(0x0F0F0FB7) /**< \brief (TCC_WAVEB) MASK Register */
+
+/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PERB:24;          /*!< bit:  0..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PERB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
+#define TCC_PERB_RESETVALUE         _U(0xFFFFFFFF) /**< \brief (TCC_PERB reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH4_DITHERCYB_Msk (_U(0xF) << TCC_PERB_DITH4_DITHERCYB_Pos)
+#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
+#define TCC_PERB_DITH4_PERB_Pos     4            /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
+#define TCC_PERB_DITH4_PERB_Msk     (_U(0xFFFFF) << TCC_PERB_DITH4_PERB_Pos)
+#define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
+#define TCC_PERB_DITH4_MASK         _U(0x00FFFFFF) /**< \brief (TCC_PERB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH5_DITHERCYB_Msk (_U(0x1F) << TCC_PERB_DITH5_DITHERCYB_Pos)
+#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
+#define TCC_PERB_DITH5_PERB_Pos     5            /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
+#define TCC_PERB_DITH5_PERB_Msk     (_U(0x7FFFF) << TCC_PERB_DITH5_PERB_Pos)
+#define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
+#define TCC_PERB_DITH5_MASK         _U(0x00FFFFFF) /**< \brief (TCC_PERB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH6_DITHERCYB_Msk (_U(0x3F) << TCC_PERB_DITH6_DITHERCYB_Pos)
+#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
+#define TCC_PERB_DITH6_PERB_Pos     6            /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
+#define TCC_PERB_DITH6_PERB_Msk     (_U(0x3FFFF) << TCC_PERB_DITH6_PERB_Pos)
+#define TCC_PERB_DITH6_PERB(value)  (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
+#define TCC_PERB_DITH6_MASK         _U(0x00FFFFFF) /**< \brief (TCC_PERB_DITH6) MASK Register */
+
+#define TCC_PERB_PERB_Pos           0            /**< \brief (TCC_PERB) Period Buffer Value */
+#define TCC_PERB_PERB_Msk           (_U(0xFFFFFF) << TCC_PERB_PERB_Pos)
+#define TCC_PERB_PERB(value)        (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
+#define TCC_PERB_MASK               _U(0x00FFFFFF) /**< \brief (TCC_PERB) MASK Register */
+
+/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CCB:24;           /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CCB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
+#define TCC_CCB_RESETVALUE          _U(0x00000000) /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH4_DITHERCYB_Msk (_U(0xF) << TCC_CCB_DITH4_DITHERCYB_Pos)
+#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
+#define TCC_CCB_DITH4_CCB_Pos       4            /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH4_CCB_Msk       (_U(0xFFFFF) << TCC_CCB_DITH4_CCB_Pos)
+#define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
+#define TCC_CCB_DITH4_MASK          _U(0x00FFFFFF) /**< \brief (TCC_CCB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH5_DITHERCYB_Msk (_U(0x1F) << TCC_CCB_DITH5_DITHERCYB_Pos)
+#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
+#define TCC_CCB_DITH5_CCB_Pos       5            /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH5_CCB_Msk       (_U(0x7FFFF) << TCC_CCB_DITH5_CCB_Pos)
+#define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
+#define TCC_CCB_DITH5_MASK          _U(0x00FFFFFF) /**< \brief (TCC_CCB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH6_DITHERCYB_Msk (_U(0x3F) << TCC_CCB_DITH6_DITHERCYB_Pos)
+#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
+#define TCC_CCB_DITH6_CCB_Pos       6            /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH6_CCB_Msk       (_U(0x3FFFF) << TCC_CCB_DITH6_CCB_Pos)
+#define TCC_CCB_DITH6_CCB(value)    (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
+#define TCC_CCB_DITH6_MASK          _U(0x00FFFFFF) /**< \brief (TCC_CCB_DITH6) MASK Register */
+
+#define TCC_CCB_CCB_Pos             0            /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_CCB_Msk             (_U(0xFFFFFF) << TCC_CCB_CCB_Pos)
+#define TCC_CCB_CCB(value)          (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
+#define TCC_CCB_MASK                _U(0x00FFFFFF) /**< \brief (TCC_CCB) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+       RoReg8                    Reserved1[0x2];
+  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
+  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+       RoReg8                    Reserved2[0x2];
+  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
+       RoReg8                    Reserved3[0x1];
+  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
+  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
+  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
+  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
+       RoReg8                    Reserved4[0x2];
+  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
+  __IO TCC_CC_Type               CC[4];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+       RoReg8                    Reserved5[0x10];
+  __IO TCC_PATTB_Type            PATTB;       /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+       RoReg8                    Reserved6[0x2];
+  __IO TCC_WAVEB_Type            WAVEB;       /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+  __IO TCC_PERB_Type             PERB;        /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+  __IO TCC_CCB_Type              CCB[4];      /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TCC_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/usb.h b/uf2-samdx1/lib/samd21/samd21a/include/component/usb.h
new file mode 100644
index 00000000..bf9b14bb
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/usb.h
@@ -0,0 +1,1790 @@
+/**
+ * \file
+ *
+ * \brief Component description for USB
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_COMPONENT_
+#define _SAMD21_USB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR USB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_USB Universal Serial Bus */
+/*@{*/
+
+#define USB_U2222
+#define REV_USB                     0x101
+
+/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby Mode                */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  MODE:1;           /*!< bit:      7  Operating Mode                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_CTRLA_OFFSET            0x000        /**< \brief (USB_CTRLA offset) Control A */
+#define USB_CTRLA_RESETVALUE        _U(0x00)     /**< \brief (USB_CTRLA reset_value) Control A */
+
+#define USB_CTRLA_SWRST_Pos         0            /**< \brief (USB_CTRLA) Software Reset */
+#define USB_CTRLA_SWRST             (_U(0x1) << USB_CTRLA_SWRST_Pos)
+#define USB_CTRLA_ENABLE_Pos        1            /**< \brief (USB_CTRLA) Enable */
+#define USB_CTRLA_ENABLE            (_U(0x1) << USB_CTRLA_ENABLE_Pos)
+#define USB_CTRLA_RUNSTDBY_Pos      2            /**< \brief (USB_CTRLA) Run in Standby Mode */
+#define USB_CTRLA_RUNSTDBY          (_U(0x1) << USB_CTRLA_RUNSTDBY_Pos)
+#define USB_CTRLA_MODE_Pos          7            /**< \brief (USB_CTRLA) Operating Mode */
+#define USB_CTRLA_MODE              (_U(0x1) << USB_CTRLA_MODE_Pos)
+#define   USB_CTRLA_MODE_DEVICE_Val       _U(0x0)   /**< \brief (USB_CTRLA) Device Mode */
+#define   USB_CTRLA_MODE_HOST_Val         _U(0x1)   /**< \brief (USB_CTRLA) Host Mode */
+#define USB_CTRLA_MODE_DEVICE       (USB_CTRLA_MODE_DEVICE_Val     << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_HOST         (USB_CTRLA_MODE_HOST_Val       << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MASK              _U(0x87)     /**< \brief (USB_CTRLA) MASK Register */
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/   8) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_SYNCBUSY_OFFSET         0x002        /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
+#define USB_SYNCBUSY_RESETVALUE     _U(0x00)     /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
+
+#define USB_SYNCBUSY_SWRST_Pos      0            /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
+#define USB_SYNCBUSY_SWRST          (_U(0x1) << USB_SYNCBUSY_SWRST_Pos)
+#define USB_SYNCBUSY_ENABLE_Pos     1            /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
+#define USB_SYNCBUSY_ENABLE         (_U(0x1) << USB_SYNCBUSY_ENABLE_Pos)
+#define USB_SYNCBUSY_MASK           _U(0x03)     /**< \brief (USB_SYNCBUSY) MASK Register */
+
+/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W  8) USB Quality Of Service -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CQOS:2;           /*!< bit:  0.. 1  Configuration Quality of Service   */
+    uint8_t  DQOS:2;           /*!< bit:  2.. 3  Data Quality of Service            */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_QOSCTRL_OFFSET          0x003        /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
+#define USB_QOSCTRL_RESETVALUE      _U(0x05)     /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
+
+#define USB_QOSCTRL_CQOS_Pos        0            /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
+#define USB_QOSCTRL_CQOS_Msk        (_U(0x3) << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS(value)     (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
+#define   USB_QOSCTRL_CQOS_DISABLE_Val    _U(0x0)   /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define   USB_QOSCTRL_CQOS_LOW_Val        _U(0x1)   /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define   USB_QOSCTRL_CQOS_MEDIUM_Val     _U(0x2)   /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define   USB_QOSCTRL_CQOS_HIGH_Val       _U(0x3)   /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_CQOS_DISABLE    (USB_QOSCTRL_CQOS_DISABLE_Val  << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_LOW        (USB_QOSCTRL_CQOS_LOW_Val      << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_MEDIUM     (USB_QOSCTRL_CQOS_MEDIUM_Val   << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_HIGH       (USB_QOSCTRL_CQOS_HIGH_Val     << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_DQOS_Pos        2            /**< \brief (USB_QOSCTRL) Data Quality of Service */
+#define USB_QOSCTRL_DQOS_Msk        (_U(0x3) << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS(value)     (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
+#define   USB_QOSCTRL_DQOS_DISABLE_Val    _U(0x0)   /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define   USB_QOSCTRL_DQOS_LOW_Val        _U(0x1)   /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define   USB_QOSCTRL_DQOS_MEDIUM_Val     _U(0x2)   /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define   USB_QOSCTRL_DQOS_HIGH_Val       _U(0x3)   /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_DQOS_DISABLE    (USB_QOSCTRL_DQOS_DISABLE_Val  << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_LOW        (USB_QOSCTRL_DQOS_LOW_Val      << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_MEDIUM     (USB_QOSCTRL_DQOS_MEDIUM_Val   << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_HIGH       (USB_QOSCTRL_DQOS_HIGH_Val     << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_MASK            _U(0x0F)     /**< \brief (USB_QOSCTRL) MASK Register */
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DETACH:1;         /*!< bit:      0  Detach                             */
+    uint16_t UPRSM:1;          /*!< bit:      1  Upstream Resume                    */
+    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration                */
+    uint16_t NREPLY:1;         /*!< bit:      4  No Reply                           */
+    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
+    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
+    uint16_t TSTPCKT:1;        /*!< bit:      7  Test packet mode                   */
+    uint16_t OPMODE2:1;        /*!< bit:      8  Specific Operational Mode          */
+    uint16_t GNAK:1;           /*!< bit:      9  Global NAK                         */
+    uint16_t LPMHDSK:2;        /*!< bit: 10..11  Link Power Management Handshake    */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_CTRLB_OFFSET     0x008        /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
+#define USB_DEVICE_CTRLB_RESETVALUE _U(0x0001)   /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos 0            /**< \brief (USB_DEVICE_CTRLB) Detach */
+#define USB_DEVICE_CTRLB_DETACH     (_U(0x1) << USB_DEVICE_CTRLB_DETACH_Pos)
+#define USB_DEVICE_CTRLB_UPRSM_Pos  1            /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
+#define USB_DEVICE_CTRLB_UPRSM      (_U(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_Pos 2            /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk (_U(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
+#define   USB_DEVICE_CTRLB_SPDCONF_FS_Val _U(0x0)   /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
+#define   USB_DEVICE_CTRLB_SPDCONF_LS_Val _U(0x1)   /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
+#define   USB_DEVICE_CTRLB_SPDCONF_HS_Val _U(0x2)   /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
+#define   USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U(0x3)   /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
+#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_NREPLY_Pos 4            /**< \brief (USB_DEVICE_CTRLB) No Reply */
+#define USB_DEVICE_CTRLB_NREPLY     (_U(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos)
+#define USB_DEVICE_CTRLB_TSTJ_Pos   5            /**< \brief (USB_DEVICE_CTRLB) Test mode J */
+#define USB_DEVICE_CTRLB_TSTJ       (_U(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos)
+#define USB_DEVICE_CTRLB_TSTK_Pos   6            /**< \brief (USB_DEVICE_CTRLB) Test mode K */
+#define USB_DEVICE_CTRLB_TSTK       (_U(0x1) << USB_DEVICE_CTRLB_TSTK_Pos)
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7            /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
+#define USB_DEVICE_CTRLB_TSTPCKT    (_U(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos)
+#define USB_DEVICE_CTRLB_OPMODE2_Pos 8            /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE2    (_U(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos)
+#define USB_DEVICE_CTRLB_GNAK_Pos   9            /**< \brief (USB_DEVICE_CTRLB) Global NAK */
+#define USB_DEVICE_CTRLB_GNAK       (_U(0x1) << USB_DEVICE_CTRLB_GNAK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10           /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
+#define   USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U(0x0)   /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
+#define   USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U(0x1)   /**< \brief (USB_DEVICE_CTRLB) ACK */
+#define   USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U(0x2)   /**< \brief (USB_DEVICE_CTRLB) NYET */
+#define   USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U(0x3)   /**< \brief (USB_DEVICE_CTRLB) STALL */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_MASK       _U(0x0FFF)   /**< \brief (USB_DEVICE_CTRLB) MASK Register */
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t RESUME:1;         /*!< bit:      1  Send USB Resume                    */
+    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration for Host       */
+    uint16_t :1;               /*!< bit:      4  Reserved                           */
+    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
+    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t SOFE:1;           /*!< bit:      8  Start of Frame Generation Enable   */
+    uint16_t BUSRESET:1;       /*!< bit:      9  Send USB Reset                     */
+    uint16_t VBUSOK:1;         /*!< bit:     10  VBUS is OK                         */
+    uint16_t L1RESUME:1;       /*!< bit:     11  Send L1 Resume                     */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRLB_OFFSET       0x008        /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
+#define USB_HOST_CTRLB_RESETVALUE   _U(0x0000)   /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
+
+#define USB_HOST_CTRLB_RESUME_Pos   1            /**< \brief (USB_HOST_CTRLB) Send USB Resume */
+#define USB_HOST_CTRLB_RESUME       (_U(0x1) << USB_HOST_CTRLB_RESUME_Pos)
+#define USB_HOST_CTRLB_SPDCONF_Pos  2            /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
+#define USB_HOST_CTRLB_SPDCONF_Msk  (_U(0x3) << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
+#define   USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U(0x0)   /**< \brief (USB_HOST_CTRLB) Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
+#define   USB_HOST_CTRLB_SPDCONF_FS_Val   _U(0x3)   /**< \brief (USB_HOST_CTRLB) Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
+#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_FS   (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_TSTJ_Pos     5            /**< \brief (USB_HOST_CTRLB) Test mode J */
+#define USB_HOST_CTRLB_TSTJ         (_U(0x1) << USB_HOST_CTRLB_TSTJ_Pos)
+#define USB_HOST_CTRLB_TSTK_Pos     6            /**< \brief (USB_HOST_CTRLB) Test mode K */
+#define USB_HOST_CTRLB_TSTK         (_U(0x1) << USB_HOST_CTRLB_TSTK_Pos)
+#define USB_HOST_CTRLB_SOFE_Pos     8            /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
+#define USB_HOST_CTRLB_SOFE         (_U(0x1) << USB_HOST_CTRLB_SOFE_Pos)
+#define USB_HOST_CTRLB_BUSRESET_Pos 9            /**< \brief (USB_HOST_CTRLB) Send USB Reset */
+#define USB_HOST_CTRLB_BUSRESET     (_U(0x1) << USB_HOST_CTRLB_BUSRESET_Pos)
+#define USB_HOST_CTRLB_VBUSOK_Pos   10           /**< \brief (USB_HOST_CTRLB) VBUS is OK */
+#define USB_HOST_CTRLB_VBUSOK       (_U(0x1) << USB_HOST_CTRLB_VBUSOK_Pos)
+#define USB_HOST_CTRLB_L1RESUME_Pos 11           /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
+#define USB_HOST_CTRLB_L1RESUME     (_U(0x1) << USB_HOST_CTRLB_L1RESUME_Pos)
+#define USB_HOST_CTRLB_MASK         _U(0x0F6E)   /**< \brief (USB_HOST_CTRLB) MASK Register */
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE Device Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DADD:7;           /*!< bit:  0.. 6  Device Address                     */
+    uint8_t  ADDEN:1;          /*!< bit:      7  Device Address Enable              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_DADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_DADD_OFFSET      0x00A        /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
+#define USB_DEVICE_DADD_RESETVALUE  _U(0x00)     /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
+
+#define USB_DEVICE_DADD_DADD_Pos    0            /**< \brief (USB_DEVICE_DADD) Device Address */
+#define USB_DEVICE_DADD_DADD_Msk    (_U(0x7F) << USB_DEVICE_DADD_DADD_Pos)
+#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
+#define USB_DEVICE_DADD_ADDEN_Pos   7            /**< \brief (USB_DEVICE_DADD) Device Address Enable */
+#define USB_DEVICE_DADD_ADDEN       (_U(0x1) << USB_DEVICE_DADD_ADDEN_Pos)
+#define USB_DEVICE_DADD_MASK        _U(0xFF)     /**< \brief (USB_DEVICE_DADD) MASK Register */
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W  8) HOST HOST Host Start Of Frame Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLENC:4;          /*!< bit:  0.. 3  Frame Length Control               */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  FLENCE:1;         /*!< bit:      7  Frame Length Control Enable        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_HSOFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_HSOFC_OFFSET       0x00A        /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
+#define USB_HOST_HSOFC_RESETVALUE   _U(0x00)     /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
+
+#define USB_HOST_HSOFC_FLENC_Pos    0            /**< \brief (USB_HOST_HSOFC) Frame Length Control */
+#define USB_HOST_HSOFC_FLENC_Msk    (_U(0xF) << USB_HOST_HSOFC_FLENC_Pos)
+#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
+#define USB_HOST_HSOFC_FLENCE_Pos   7            /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
+#define USB_HOST_HSOFC_FLENCE       (_U(0x1) << USB_HOST_HSOFC_FLENCE_Pos)
+#define USB_HOST_HSOFC_MASK         _U(0x8F)     /**< \brief (USB_HOST_HSOFC) MASK Register */
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/   8) DEVICE DEVICE Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_OFFSET    0x00C        /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
+#define USB_DEVICE_STATUS_RESETVALUE _U(0x40)     /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
+
+#define USB_DEVICE_STATUS_SPEED_Pos 2            /**< \brief (USB_DEVICE_STATUS) Speed Status */
+#define USB_DEVICE_STATUS_SPEED_Msk (_U(0x3) << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
+#define   USB_DEVICE_STATUS_SPEED_FS_Val  _U(0x0)   /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
+#define   USB_DEVICE_STATUS_SPEED_HS_Val  _U(0x1)   /**< \brief (USB_DEVICE_STATUS) High-speed mode */
+#define   USB_DEVICE_STATUS_SPEED_LS_Val  _U(0x2)   /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
+#define USB_DEVICE_STATUS_SPEED_FS  (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_HS  (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_LS  (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_Pos 6            /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
+#define USB_DEVICE_STATUS_LINESTATE_Msk (_U(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
+#define   USB_DEVICE_STATUS_LINESTATE_0_Val _U(0x0)   /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
+#define   USB_DEVICE_STATUS_LINESTATE_1_Val _U(0x1)   /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
+#define   USB_DEVICE_STATUS_LINESTATE_2_Val _U(0x2)   /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
+#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_MASK      _U(0xCC)     /**< \brief (USB_DEVICE_STATUS) MASK Register */
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W  8) HOST HOST Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_OFFSET      0x00C        /**< \brief (USB_HOST_STATUS offset) HOST Status */
+#define USB_HOST_STATUS_RESETVALUE  _U(0x00)     /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
+
+#define USB_HOST_STATUS_SPEED_Pos   2            /**< \brief (USB_HOST_STATUS) Speed Status */
+#define USB_HOST_STATUS_SPEED_Msk   (_U(0x3) << USB_HOST_STATUS_SPEED_Pos)
+#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
+#define USB_HOST_STATUS_LINESTATE_Pos 6            /**< \brief (USB_HOST_STATUS) USB Line State Status */
+#define USB_HOST_STATUS_LINESTATE_Msk (_U(0x3) << USB_HOST_STATUS_LINESTATE_Pos)
+#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
+#define USB_HOST_STATUS_MASK        _U(0xCC)     /**< \brief (USB_HOST_STATUS) MASK Register */
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/   8) Finite State Machine Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FSMSTATE:7;       /*!< bit:  0.. 6  Fine State Machine Status          */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_FSMSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_FSMSTATUS_OFFSET        0x00D        /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
+#define USB_FSMSTATUS_RESETVALUE    _U(0x01)     /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos  0            /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
+#define USB_FSMSTATUS_FSMSTATE_Msk  (_U(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
+#define   USB_FSMSTATUS_FSMSTATE_OFF_Val  _U(0x1)   /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
+#define   USB_FSMSTATUS_FSMSTATE_ON_Val   _U(0x2)   /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
+#define   USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U(0x4)   /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
+#define   USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U(0x8)   /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
+#define   USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U(0x10)   /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
+#define   USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U(0x20)   /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
+#define   USB_FSMSTATUS_FSMSTATE_RESET_Val _U(0x40)   /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
+#define USB_FSMSTATUS_FSMSTATE_OFF  (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_ON   (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_MASK          _U(0x7F)     /**< \brief (USB_FSMSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/  16) DEVICE DEVICE Device Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
+    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
+    uint16_t :1;               /*!< bit:     14  Reserved                           */
+    uint16_t FNCERR:1;         /*!< bit:     15  Frame Number CRC Error             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_FNUM_OFFSET      0x010        /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
+#define USB_DEVICE_FNUM_RESETVALUE  _U(0x0000)   /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos   0            /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
+#define USB_DEVICE_FNUM_MFNUM_Msk   (_U(0x7) << USB_DEVICE_FNUM_MFNUM_Pos)
+#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
+#define USB_DEVICE_FNUM_FNUM_Pos    3            /**< \brief (USB_DEVICE_FNUM) Frame Number */
+#define USB_DEVICE_FNUM_FNUM_Msk    (_U(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos)
+#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
+#define USB_DEVICE_FNUM_FNCERR_Pos  15           /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
+#define USB_DEVICE_FNUM_FNCERR      (_U(0x1) << USB_DEVICE_FNUM_FNCERR_Pos)
+#define USB_DEVICE_FNUM_MASK        _U(0xBFFF)   /**< \brief (USB_DEVICE_FNUM) MASK Register */
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
+    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FNUM_OFFSET        0x010        /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
+#define USB_HOST_FNUM_RESETVALUE    _U(0x0000)   /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
+
+#define USB_HOST_FNUM_MFNUM_Pos     0            /**< \brief (USB_HOST_FNUM) Micro Frame Number */
+#define USB_HOST_FNUM_MFNUM_Msk     (_U(0x7) << USB_HOST_FNUM_MFNUM_Pos)
+#define USB_HOST_FNUM_MFNUM(value)  (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
+#define USB_HOST_FNUM_FNUM_Pos      3            /**< \brief (USB_HOST_FNUM) Frame Number */
+#define USB_HOST_FNUM_FNUM_Msk      (_U(0x7FF) << USB_HOST_FNUM_FNUM_Pos)
+#define USB_HOST_FNUM_FNUM(value)   (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
+#define USB_HOST_FNUM_MASK          _U(0x3FFF)   /**< \brief (USB_HOST_FNUM) MASK Register */
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/   8) HOST HOST Host Frame Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLENHIGH:8;       /*!< bit:  0.. 7  Frame Length                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_FLENHIGH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FLENHIGH_OFFSET    0x012        /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
+#define USB_HOST_FLENHIGH_RESETVALUE _U(0x00)     /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0            /**< \brief (USB_HOST_FLENHIGH) Frame Length */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos)
+#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
+#define USB_HOST_FLENHIGH_MASK      _U(0xFF)     /**< \brief (USB_HOST_FLENHIGH) MASK Register */
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
+    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
+    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
+    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
+    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENCLR_OFFSET  0x014        /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
+#define USB_DEVICE_INTENCLR_RESETVALUE _U(0x0000)   /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SUSPEND (_U(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos)
+#define USB_DEVICE_INTENCLR_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENCLR_MSOF    (_U(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos)
+#define USB_DEVICE_INTENCLR_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SOF     (_U(0x1) << USB_DEVICE_INTENCLR_SOF_Pos)
+#define USB_DEVICE_INTENCLR_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORST   (_U(0x1) << USB_DEVICE_INTENCLR_EORST_Pos)
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENCLR_WAKEUP  (_U(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos)
+#define USB_DEVICE_INTENCLR_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORSM   (_U(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos)
+#define USB_DEVICE_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_UPRSM   (_U(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos)
+#define USB_DEVICE_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENCLR_RAMACER (_U(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos)
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMNYET (_U(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos)
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMSUSP (_U(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
+#define USB_DEVICE_INTENCLR_MASK    _U(0x03FF)   /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Disable */
+    uint16_t RST:1;            /*!< bit:      3  BUS Reset Interrupt Disable        */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Disable          */
+    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to Device Interrupt Disable */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from Device Interrupt Disable */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Disable       */
+    uint16_t DCONN:1;          /*!< bit:      8  Device Connection Interrupt Disable */
+    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Disable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENCLR_OFFSET    0x014        /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
+#define USB_HOST_INTENCLR_RESETVALUE _U(0x0000)   /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
+
+#define USB_HOST_INTENCLR_HSOF_Pos  2            /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
+#define USB_HOST_INTENCLR_HSOF      (_U(0x1) << USB_HOST_INTENCLR_HSOF_Pos)
+#define USB_HOST_INTENCLR_RST_Pos   3            /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
+#define USB_HOST_INTENCLR_RST       (_U(0x1) << USB_HOST_INTENCLR_RST_Pos)
+#define USB_HOST_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
+#define USB_HOST_INTENCLR_WAKEUP    (_U(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos)
+#define USB_HOST_INTENCLR_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
+#define USB_HOST_INTENCLR_DNRSM     (_U(0x1) << USB_HOST_INTENCLR_DNRSM_Pos)
+#define USB_HOST_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
+#define USB_HOST_INTENCLR_UPRSM     (_U(0x1) << USB_HOST_INTENCLR_UPRSM_Pos)
+#define USB_HOST_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
+#define USB_HOST_INTENCLR_RAMACER   (_U(0x1) << USB_HOST_INTENCLR_RAMACER_Pos)
+#define USB_HOST_INTENCLR_DCONN_Pos 8            /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
+#define USB_HOST_INTENCLR_DCONN     (_U(0x1) << USB_HOST_INTENCLR_DCONN_Pos)
+#define USB_HOST_INTENCLR_DDISC_Pos 9            /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
+#define USB_HOST_INTENCLR_DDISC     (_U(0x1) << USB_HOST_INTENCLR_DDISC_Pos)
+#define USB_HOST_INTENCLR_MASK      _U(0x03FC)   /**< \brief (USB_HOST_INTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
+    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
+    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
+    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
+    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENSET_OFFSET  0x018        /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
+#define USB_DEVICE_INTENSET_RESETVALUE _U(0x0000)   /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_SUSPEND (_U(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos)
+#define USB_DEVICE_INTENSET_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENSET_MSOF    (_U(0x1) << USB_DEVICE_INTENSET_MSOF_Pos)
+#define USB_DEVICE_INTENSET_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENSET_SOF     (_U(0x1) << USB_DEVICE_INTENSET_SOF_Pos)
+#define USB_DEVICE_INTENSET_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORST   (_U(0x1) << USB_DEVICE_INTENSET_EORST_Pos)
+#define USB_DEVICE_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENSET_WAKEUP  (_U(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos)
+#define USB_DEVICE_INTENSET_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORSM   (_U(0x1) << USB_DEVICE_INTENSET_EORSM_Pos)
+#define USB_DEVICE_INTENSET_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_UPRSM   (_U(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos)
+#define USB_DEVICE_INTENSET_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENSET_RAMACER (_U(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos)
+#define USB_DEVICE_INTENSET_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMNYET (_U(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos)
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMSUSP (_U(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos)
+#define USB_DEVICE_INTENSET_MASK    _U(0x03FF)   /**< \brief (USB_DEVICE_INTENSET) MASK Register */
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Enable */
+    uint16_t RST:1;            /*!< bit:      3  Bus Reset Interrupt Enable         */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to the Device Interrupt Enable */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume fromthe device Interrupt Enable */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t DCONN:1;          /*!< bit:      8  Link Power Management Interrupt Enable */
+    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENSET_OFFSET    0x018        /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
+#define USB_HOST_INTENSET_RESETVALUE _U(0x0000)   /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
+
+#define USB_HOST_INTENSET_HSOF_Pos  2            /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
+#define USB_HOST_INTENSET_HSOF      (_U(0x1) << USB_HOST_INTENSET_HSOF_Pos)
+#define USB_HOST_INTENSET_RST_Pos   3            /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
+#define USB_HOST_INTENSET_RST       (_U(0x1) << USB_HOST_INTENSET_RST_Pos)
+#define USB_HOST_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
+#define USB_HOST_INTENSET_WAKEUP    (_U(0x1) << USB_HOST_INTENSET_WAKEUP_Pos)
+#define USB_HOST_INTENSET_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
+#define USB_HOST_INTENSET_DNRSM     (_U(0x1) << USB_HOST_INTENSET_DNRSM_Pos)
+#define USB_HOST_INTENSET_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
+#define USB_HOST_INTENSET_UPRSM     (_U(0x1) << USB_HOST_INTENSET_UPRSM_Pos)
+#define USB_HOST_INTENSET_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
+#define USB_HOST_INTENSET_RAMACER   (_U(0x1) << USB_HOST_INTENSET_RAMACER_Pos)
+#define USB_HOST_INTENSET_DCONN_Pos 8            /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
+#define USB_HOST_INTENSET_DCONN     (_U(0x1) << USB_HOST_INTENSET_DCONN_Pos)
+#define USB_HOST_INTENSET_DDISC_Pos 9            /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
+#define USB_HOST_INTENSET_DDISC     (_U(0x1) << USB_HOST_INTENSET_DDISC_Pos)
+#define USB_HOST_INTENSET_MASK      _U(0x03FC)   /**< \brief (USB_HOST_INTENSET) MASK Register */
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t SUSPEND:1;        /*!< bit:      0  Suspend                            */
+    __I uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame in High Speed Mode */
+    __I uint16_t SOF:1;            /*!< bit:      2  Start Of Frame                     */
+    __I uint16_t EORST:1;          /*!< bit:      3  End of Reset                       */
+    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
+    __I uint16_t EORSM:1;          /*!< bit:      5  End Of Resume                      */
+    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume                    */
+    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
+    __I uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet      */
+    __I uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend      */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTFLAG_OFFSET   0x01C        /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
+#define USB_DEVICE_INTFLAG_RESETVALUE _U(0x0000)   /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTFLAG) Suspend */
+#define USB_DEVICE_INTFLAG_SUSPEND  (_U(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos)
+#define USB_DEVICE_INTFLAG_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
+#define USB_DEVICE_INTFLAG_MSOF     (_U(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos)
+#define USB_DEVICE_INTFLAG_SOF_Pos  2            /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
+#define USB_DEVICE_INTFLAG_SOF      (_U(0x1) << USB_DEVICE_INTFLAG_SOF_Pos)
+#define USB_DEVICE_INTFLAG_EORST_Pos 3            /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
+#define USB_DEVICE_INTFLAG_EORST    (_U(0x1) << USB_DEVICE_INTFLAG_EORST_Pos)
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
+#define USB_DEVICE_INTFLAG_WAKEUP   (_U(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos)
+#define USB_DEVICE_INTFLAG_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
+#define USB_DEVICE_INTFLAG_EORSM    (_U(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos)
+#define USB_DEVICE_INTFLAG_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
+#define USB_DEVICE_INTFLAG_UPRSM    (_U(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos)
+#define USB_DEVICE_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
+#define USB_DEVICE_INTFLAG_RAMACER  (_U(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos)
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
+#define USB_DEVICE_INTFLAG_LPMNYET  (_U(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos)
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
+#define USB_DEVICE_INTFLAG_LPMSUSP  (_U(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
+#define USB_DEVICE_INTFLAG_MASK     _U(0x03FF)   /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    __I uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame                */
+    __I uint16_t RST:1;            /*!< bit:      3  Bus Reset                          */
+    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
+    __I uint16_t DNRSM:1;          /*!< bit:      5  Downstream                         */
+    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from the Device    */
+    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
+    __I uint16_t DCONN:1;          /*!< bit:      8  Device Connection                  */
+    __I uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection               */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTFLAG_OFFSET     0x01C        /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
+#define USB_HOST_INTFLAG_RESETVALUE _U(0x0000)   /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
+
+#define USB_HOST_INTFLAG_HSOF_Pos   2            /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
+#define USB_HOST_INTFLAG_HSOF       (_U(0x1) << USB_HOST_INTFLAG_HSOF_Pos)
+#define USB_HOST_INTFLAG_RST_Pos    3            /**< \brief (USB_HOST_INTFLAG) Bus Reset */
+#define USB_HOST_INTFLAG_RST        (_U(0x1) << USB_HOST_INTFLAG_RST_Pos)
+#define USB_HOST_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTFLAG) Wake Up */
+#define USB_HOST_INTFLAG_WAKEUP     (_U(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos)
+#define USB_HOST_INTFLAG_DNRSM_Pos  5            /**< \brief (USB_HOST_INTFLAG) Downstream */
+#define USB_HOST_INTFLAG_DNRSM      (_U(0x1) << USB_HOST_INTFLAG_DNRSM_Pos)
+#define USB_HOST_INTFLAG_UPRSM_Pos  6            /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
+#define USB_HOST_INTFLAG_UPRSM      (_U(0x1) << USB_HOST_INTFLAG_UPRSM_Pos)
+#define USB_HOST_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_HOST_INTFLAG) Ram Access */
+#define USB_HOST_INTFLAG_RAMACER    (_U(0x1) << USB_HOST_INTFLAG_RAMACER_Pos)
+#define USB_HOST_INTFLAG_DCONN_Pos  8            /**< \brief (USB_HOST_INTFLAG) Device Connection */
+#define USB_HOST_INTFLAG_DCONN      (_U(0x1) << USB_HOST_INTFLAG_DCONN_Pos)
+#define USB_HOST_INTFLAG_DDISC_Pos  9            /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
+#define USB_HOST_INTFLAG_DDISC      (_U(0x1) << USB_HOST_INTFLAG_DDISC_Pos)
+#define USB_HOST_INTFLAG_MASK       _U(0x03FC)   /**< \brief (USB_HOST_INTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/  16) DEVICE DEVICE End Point Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EPINT0:1;         /*!< bit:      0  End Point 0 Interrupt              */
+    uint16_t EPINT1:1;         /*!< bit:      1  End Point 1 Interrupt              */
+    uint16_t EPINT2:1;         /*!< bit:      2  End Point 2 Interrupt              */
+    uint16_t EPINT3:1;         /*!< bit:      3  End Point 3 Interrupt              */
+    uint16_t EPINT4:1;         /*!< bit:      4  End Point 4 Interrupt              */
+    uint16_t EPINT5:1;         /*!< bit:      5  End Point 5 Interrupt              */
+    uint16_t EPINT6:1;         /*!< bit:      6  End Point 6 Interrupt              */
+    uint16_t EPINT7:1;         /*!< bit:      7  End Point 7 Interrupt              */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t EPINT:8;          /*!< bit:  0.. 7  End Point x Interrupt              */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_EPINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTSMRY_OFFSET 0x020        /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE _U(0x0000)   /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
+#define USB_DEVICE_EPINTSMRY_MASK   _U(0x00FF)   /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/  16) HOST HOST Pipe Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EPINT0:1;         /*!< bit:      0  Pipe 0 Interrupt                   */
+    uint16_t EPINT1:1;         /*!< bit:      1  Pipe 1 Interrupt                   */
+    uint16_t EPINT2:1;         /*!< bit:      2  Pipe 2 Interrupt                   */
+    uint16_t EPINT3:1;         /*!< bit:      3  Pipe 3 Interrupt                   */
+    uint16_t EPINT4:1;         /*!< bit:      4  Pipe 4 Interrupt                   */
+    uint16_t EPINT5:1;         /*!< bit:      5  Pipe 5 Interrupt                   */
+    uint16_t EPINT6:1;         /*!< bit:      6  Pipe 6 Interrupt                   */
+    uint16_t EPINT7:1;         /*!< bit:      7  Pipe 7 Interrupt                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t EPINT:8;          /*!< bit:  0.. 7  Pipe x Interrupt                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_PINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTSMRY_OFFSET    0x020        /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
+#define USB_HOST_PINTSMRY_RESETVALUE _U(0x0000)   /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT0    (1 << USB_HOST_PINTSMRY_EPINT0_Pos)
+#define USB_HOST_PINTSMRY_EPINT1_Pos 1            /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT1    (1 << USB_HOST_PINTSMRY_EPINT1_Pos)
+#define USB_HOST_PINTSMRY_EPINT2_Pos 2            /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT2    (1 << USB_HOST_PINTSMRY_EPINT2_Pos)
+#define USB_HOST_PINTSMRY_EPINT3_Pos 3            /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT3    (1 << USB_HOST_PINTSMRY_EPINT3_Pos)
+#define USB_HOST_PINTSMRY_EPINT4_Pos 4            /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT4    (1 << USB_HOST_PINTSMRY_EPINT4_Pos)
+#define USB_HOST_PINTSMRY_EPINT5_Pos 5            /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT5    (1 << USB_HOST_PINTSMRY_EPINT5_Pos)
+#define USB_HOST_PINTSMRY_EPINT6_Pos 6            /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT6    (1 << USB_HOST_PINTSMRY_EPINT6_Pos)
+#define USB_HOST_PINTSMRY_EPINT7_Pos 7            /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT7    (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
+#define USB_HOST_PINTSMRY_EPINT_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk (_U(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos)
+#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
+#define USB_HOST_PINTSMRY_MASK      _U(0x00FF)   /**< \brief (USB_HOST_PINTSMRY) MASK Register */
+
+/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DESCADD:32;       /*!< bit:  0..31  Descriptor Address Value           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DESCADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DESCADD_OFFSET          0x024        /**< \brief (USB_DESCADD offset) Descriptor Address */
+#define USB_DESCADD_RESETVALUE      _U(0x00000000) /**< \brief (USB_DESCADD reset_value) Descriptor Address */
+
+#define USB_DESCADD_DESCADD_Pos     0            /**< \brief (USB_DESCADD) Descriptor Address Value */
+#define USB_DESCADD_DESCADD_Msk     (_U(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos)
+#define USB_DESCADD_DESCADD(value)  (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
+#define USB_DESCADD_MASK            _U(0xFFFFFFFF) /**< \brief (USB_DESCADD) MASK Register */
+
+/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t TRANSP:5;         /*!< bit:  0.. 4  USB Pad Transp calibration         */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t TRANSN:5;         /*!< bit:  6..10  USB Pad Transn calibration         */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t TRIM:3;           /*!< bit: 12..14  USB Pad Trim calibration           */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_PADCAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_PADCAL_OFFSET           0x028        /**< \brief (USB_PADCAL offset) USB PAD Calibration */
+#define USB_PADCAL_RESETVALUE       _U(0x0000)   /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
+
+#define USB_PADCAL_TRANSP_Pos       0            /**< \brief (USB_PADCAL) USB Pad Transp calibration */
+#define USB_PADCAL_TRANSP_Msk       (_U(0x1F) << USB_PADCAL_TRANSP_Pos)
+#define USB_PADCAL_TRANSP(value)    (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
+#define USB_PADCAL_TRANSN_Pos       6            /**< \brief (USB_PADCAL) USB Pad Transn calibration */
+#define USB_PADCAL_TRANSN_Msk       (_U(0x1F) << USB_PADCAL_TRANSN_Pos)
+#define USB_PADCAL_TRANSN(value)    (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
+#define USB_PADCAL_TRIM_Pos         12           /**< \brief (USB_PADCAL) USB Pad Trim calibration */
+#define USB_PADCAL_TRIM_Msk         (_U(0x7) << USB_PADCAL_TRIM_Pos)
+#define USB_PADCAL_TRIM(value)      (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
+#define USB_PADCAL_MASK             _U(0x77DF)   /**< \brief (USB_PADCAL) MASK Register */
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EPTYPE0:3;        /*!< bit:  0.. 2  End Point Type0                    */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EPTYPE1:3;        /*!< bit:  4.. 6  End Point Type1                    */
+    uint8_t  NYETDIS:1;        /*!< bit:      7  NYET Token Disable                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPCFG_OFFSET     0x100        /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
+#define USB_DEVICE_EPCFG_RESETVALUE _U(0x00)     /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0            /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4            /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
+#define USB_DEVICE_EPCFG_NYETDIS_Pos 7            /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
+#define USB_DEVICE_EPCFG_NYETDIS    (_U(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos)
+#define USB_DEVICE_EPCFG_MASK       _U(0xF7)     /**< \brief (USB_DEVICE_EPCFG) MASK Register */
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W  8) HOST HOST_PIPE End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PTOKEN:2;         /*!< bit:  0.. 1  Pipe Token                         */
+    uint8_t  BK:1;             /*!< bit:      2  Pipe Bank                          */
+    uint8_t  PTYPE:3;          /*!< bit:  3.. 5  Pipe Type                          */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCFG_OFFSET        0x100        /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
+#define USB_HOST_PCFG_RESETVALUE    _U(0x00)     /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
+
+#define USB_HOST_PCFG_PTOKEN_Pos    0            /**< \brief (USB_HOST_PCFG) Pipe Token */
+#define USB_HOST_PCFG_PTOKEN_Msk    (_U(0x3) << USB_HOST_PCFG_PTOKEN_Pos)
+#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
+#define USB_HOST_PCFG_BK_Pos        2            /**< \brief (USB_HOST_PCFG) Pipe Bank */
+#define USB_HOST_PCFG_BK            (_U(0x1) << USB_HOST_PCFG_BK_Pos)
+#define USB_HOST_PCFG_PTYPE_Pos     3            /**< \brief (USB_HOST_PCFG) Pipe Type */
+#define USB_HOST_PCFG_PTYPE_Msk     (_U(0x7) << USB_HOST_PCFG_PTYPE_Pos)
+#define USB_HOST_PCFG_PTYPE(value)  (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
+#define USB_HOST_PCFG_MASK          _U(0x3F)     /**< \brief (USB_HOST_PCFG) MASK Register */
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W  8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BITINTERVAL:8;    /*!< bit:  0.. 7  Bit Interval                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_BINTERVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_BINTERVAL_OFFSET   0x103        /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
+#define USB_HOST_BINTERVAL_RESETVALUE _U(0x00)     /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0            /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
+#define USB_HOST_BINTERVAL_MASK     _U(0xFF)     /**< \brief (USB_HOST_BINTERVAL) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Clear              */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Clear               */
+    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank Clear                  */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Clear              */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Clear              */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Clear              */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104        /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U(0x00)     /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */
+#define USB_DEVICE_EPSTATUSCLR_CURBK (_U(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_MASK _U(0xF7)     /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W  8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle clear                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank clear                  */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Clear                  */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSCLR_OFFSET  0x104        /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
+#define USB_HOST_PSTATUSCLR_RESETVALUE _U(0x00)     /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
+#define USB_HOST_PSTATUSCLR_DTGL    (_U(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos)
+#define USB_HOST_PSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
+#define USB_HOST_PSTATUSCLR_CURBK   (_U(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos)
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
+#define USB_HOST_PSTATUSCLR_PFREEZE (_U(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK0RDY  (_U(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK1RDY  (_U(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
+#define USB_HOST_PSTATUSCLR_MASK    _U(0xD5)     /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Set                */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Set                 */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Set                */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Set                */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Set                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105        /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE _U(0x00)     /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN (_U(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
+#define USB_DEVICE_EPSTATUSSET_CURBK (_U(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY (_U(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY (_U(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_MASK _U(0xF7)     /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W  8) HOST HOST_PIPE End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle Set                    */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Set                    */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSSET_OFFSET  0x105        /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
+#define USB_HOST_PSTATUSSET_RESETVALUE _U(0x00)     /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
+#define USB_HOST_PSTATUSSET_DTGL    (_U(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos)
+#define USB_HOST_PSTATUSSET_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
+#define USB_HOST_PSTATUSSET_CURBK   (_U(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos)
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
+#define USB_HOST_PSTATUSSET_PFREEZE (_U(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos)
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
+#define USB_HOST_PSTATUSSET_BK0RDY  (_U(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos)
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
+#define USB_HOST_PSTATUSSET_BK1RDY  (_U(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos)
+#define USB_HOST_PSTATUSSET_MASK    _U(0xD5)     /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/   8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle Out                    */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle In                     */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request                    */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request                    */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request                    */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUS_OFFSET  0x106        /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
+#define USB_DEVICE_EPSTATUS_RESETVALUE _U(0x00)     /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
+#define USB_DEVICE_EPSTATUS_DTGLOUT (_U(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
+#define USB_DEVICE_EPSTATUS_DTGLIN  (_U(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUS_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
+#define USB_DEVICE_EPSTATUS_CURBK   (_U(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
+#define USB_DEVICE_EPSTATUS_BK0RDY  (_U(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
+#define USB_DEVICE_EPSTATUS_BK1RDY  (_U(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUS_MASK    _U(0xF7)     /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/   8) HOST HOST_PIPE End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle                        */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze                        */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUS_OFFSET     0x106        /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
+#define USB_HOST_PSTATUS_RESETVALUE _U(0x00)     /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
+
+#define USB_HOST_PSTATUS_DTGL_Pos   0            /**< \brief (USB_HOST_PSTATUS) Data Toggle */
+#define USB_HOST_PSTATUS_DTGL       (_U(0x1) << USB_HOST_PSTATUS_DTGL_Pos)
+#define USB_HOST_PSTATUS_CURBK_Pos  2            /**< \brief (USB_HOST_PSTATUS) Current Bank */
+#define USB_HOST_PSTATUS_CURBK      (_U(0x1) << USB_HOST_PSTATUS_CURBK_Pos)
+#define USB_HOST_PSTATUS_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
+#define USB_HOST_PSTATUS_PFREEZE    (_U(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos)
+#define USB_HOST_PSTATUS_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
+#define USB_HOST_PSTATUS_BK0RDY     (_U(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos)
+#define USB_HOST_PSTATUS_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
+#define USB_HOST_PSTATUS_BK1RDY     (_U(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos)
+#define USB_HOST_PSTATUS_MASK       _U(0xD5)     /**< \brief (USB_HOST_PSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0                */
+    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1                */
+    __I uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0                       */
+    __I uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1                       */
+    __I uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup                     */
+    __I uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out                     */
+    __I uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out                     */
+    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x                */
+    __I uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x                       */
+    __I uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    __I uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out                     */
+    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTFLAG_OFFSET 0x107        /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE _U(0x00)     /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
+#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
+#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
+#define USB_DEVICE_EPINTFLAG_RXSTP  (_U(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk (_U(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
+#define USB_DEVICE_EPINTFLAG_MASK   _U(0x7F)     /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Flag */
+    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Flag */
+    __I uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Flag          */
+    __I uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Flag          */
+    __I uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Flag     */
+    __I uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Flag               */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Flag */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTFLAG_OFFSET    0x107        /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
+#define USB_HOST_PINTFLAG_RESETVALUE _U(0x00)     /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT0    (1 << USB_HOST_PINTFLAG_TRCPT0_Pos)
+#define USB_HOST_PINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT1    (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
+#define USB_HOST_PINTFLAG_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk (_U(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos)
+#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
+#define USB_HOST_PINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRFAIL    (_U(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos)
+#define USB_HOST_PINTFLAG_PERR_Pos  3            /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
+#define USB_HOST_PINTFLAG_PERR      (_U(0x1) << USB_HOST_PINTFLAG_PERR_Pos)
+#define USB_HOST_PINTFLAG_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTFLAG) Transmit  Setup Interrupt Flag */
+#define USB_HOST_PINTFLAG_TXSTP     (_U(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos)
+#define USB_HOST_PINTFLAG_STALL_Pos 5            /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
+#define USB_HOST_PINTFLAG_STALL     (_U(0x1) << USB_HOST_PINTFLAG_STALL_Pos)
+#define USB_HOST_PINTFLAG_MASK      _U(0x3F)     /**< \brief (USB_HOST_PINTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Disable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Disable */
+    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Disable     */
+    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Disable     */
+    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Disable   */
+    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/Out Interrupt Disable   */
+    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/Out Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Disable */
+    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Disable     */
+    uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/Out Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENCLR_OFFSET 0x108        /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE _U(0x00)     /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_RXSTP (_U(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk (_U(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
+#define USB_DEVICE_EPINTENCLR_MASK  _U(0x7F)     /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Disable        */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Disable        */
+    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Disable       */
+    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Disable       */
+    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Disable  */
+    uint8_t  STALL:1;          /*!< bit:      5  Stall Inetrrupt Disable            */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Disable        */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENCLR_OFFSET   0x108        /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
+#define USB_HOST_PINTENCLR_RESETVALUE _U(0x00)     /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
+#define USB_HOST_PINTENCLR_TRCPT0   (1 << USB_HOST_PINTENCLR_TRCPT0_Pos)
+#define USB_HOST_PINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
+#define USB_HOST_PINTENCLR_TRCPT1   (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
+#define USB_HOST_PINTENCLR_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk (_U(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos)
+#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
+#define USB_HOST_PINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
+#define USB_HOST_PINTENCLR_TRFAIL   (_U(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos)
+#define USB_HOST_PINTENCLR_PERR_Pos 3            /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
+#define USB_HOST_PINTENCLR_PERR     (_U(0x1) << USB_HOST_PINTENCLR_PERR_Pos)
+#define USB_HOST_PINTENCLR_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENCLR) Transmit  Setup Interrupt Disable */
+#define USB_HOST_PINTENCLR_TXSTP    (_U(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos)
+#define USB_HOST_PINTENCLR_STALL_Pos 5            /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
+#define USB_HOST_PINTENCLR_STALL    (_U(0x1) << USB_HOST_PINTENCLR_STALL_Pos)
+#define USB_HOST_PINTENCLR_MASK     _U(0x3F)     /**< \brief (USB_HOST_PINTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
+    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Enable      */
+    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Enable      */
+    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Enable    */
+    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out Interrupt enable    */
+    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out Interrupt enable    */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
+    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Enable      */
+    uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out Interrupt enable    */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENSET_OFFSET 0x109        /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+#define USB_DEVICE_EPINTENSET_RESETVALUE _U(0x00)     /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_RXSTP (_U(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos)
+#define USB_DEVICE_EPINTENSET_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos)
+#define USB_DEVICE_EPINTENSET_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
+#define USB_DEVICE_EPINTENSET_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk (_U(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos)
+#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
+#define USB_DEVICE_EPINTENSET_MASK  _U(0x7F)     /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
+    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Enable        */
+    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Enable        */
+    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Enable   */
+    uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Enable             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENSET_OFFSET   0x109        /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
+#define USB_HOST_PINTENSET_RESETVALUE _U(0x00)     /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT0   (1 << USB_HOST_PINTENSET_TRCPT0_Pos)
+#define USB_HOST_PINTENSET_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT1   (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
+#define USB_HOST_PINTENSET_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk (_U(0x3) << USB_HOST_PINTENSET_TRCPT_Pos)
+#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
+#define USB_HOST_PINTENSET_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
+#define USB_HOST_PINTENSET_TRFAIL   (_U(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos)
+#define USB_HOST_PINTENSET_PERR_Pos 3            /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
+#define USB_HOST_PINTENSET_PERR     (_U(0x1) << USB_HOST_PINTENSET_PERR_Pos)
+#define USB_HOST_PINTENSET_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENSET) Transmit  Setup Interrupt Enable */
+#define USB_HOST_PINTENSET_TXSTP    (_U(0x1) << USB_HOST_PINTENSET_TXSTP_Pos)
+#define USB_HOST_PINTENSET_STALL_Pos 5            /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
+#define USB_HOST_PINTENSET_STALL    (_U(0x1) << USB_HOST_PINTENSET_STALL_Pos)
+#define USB_HOST_PINTENSET_MASK     _U(0x3F)     /**< \brief (USB_HOST_PINTENSET) MASK Register */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_ADDR_OFFSET      0x000        /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+
+#define USB_DEVICE_ADDR_ADDR_Pos    0            /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
+#define USB_DEVICE_ADDR_ADDR_Msk    (_U(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos)
+#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
+#define USB_DEVICE_ADDR_MASK        _U(0xFFFFFFFF) /**< \brief (USB_DEVICE_ADDR) MASK Register */
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_HOST_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_ADDR_OFFSET        0x000        /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+
+#define USB_HOST_ADDR_ADDR_Pos      0            /**< \brief (USB_HOST_ADDR) Adress of data buffer */
+#define USB_HOST_ADDR_ADDR_Msk      (_U(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos)
+#define USB_HOST_ADDR_ADDR(value)   (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
+#define USB_HOST_ADDR_MASK          _U(0xFFFFFFFF) /**< \brief (USB_HOST_ADDR) MASK Register */
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
+    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
+    uint32_t SIZE:3;           /*!< bit: 28..30  Enpoint size                       */
+    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_PCKSIZE_OFFSET   0x004        /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_SIZE_Pos 28           /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk (_U(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_DEVICE_PCKSIZE_MASK     _U(0xFFFFFFFF) /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
+    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
+    uint32_t SIZE:3;           /*!< bit: 28..30  Pipe size                          */
+    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_HOST_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCKSIZE_OFFSET     0x004        /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
+
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_HOST_PCKSIZE) Byte Count */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_HOST_PCKSIZE_SIZE_Pos   28           /**< \brief (USB_HOST_PCKSIZE) Pipe size */
+#define USB_HOST_PCKSIZE_SIZE_Msk   (_U(0x7) << USB_HOST_PCKSIZE_SIZE_Pos)
+#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
+#define USB_HOST_PCKSIZE_AUTO_ZLP   (_U(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_HOST_PCKSIZE_MASK       _U(0xFFFFFFFF) /**< \brief (USB_HOST_PCKSIZE) MASK Register */
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
+    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EXTREG_OFFSET    0x008        /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
+
+#define USB_DEVICE_EXTREG_SUBPID_Pos 0            /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
+#define USB_DEVICE_EXTREG_SUBPID_Msk (_U(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos)
+#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
+#define USB_DEVICE_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk (_U(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos)
+#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
+#define USB_DEVICE_EXTREG_MASK      _U(0x7FFF)   /**< \brief (USB_DEVICE_EXTREG) MASK Register */
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
+    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_EXTREG_OFFSET      0x008        /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
+
+#define USB_HOST_EXTREG_SUBPID_Pos  0            /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
+#define USB_HOST_EXTREG_SUBPID_Msk  (_U(0xF) << USB_HOST_EXTREG_SUBPID_Pos)
+#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
+#define USB_HOST_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
+#define USB_HOST_EXTREG_VARIABLE_Msk (_U(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos)
+#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
+#define USB_HOST_EXTREG_MASK        _U(0x7FFF)   /**< \brief (USB_HOST_EXTREG) MASK Register */
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
+    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_BK_OFFSET 0x00A        /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
+#define USB_DEVICE_STATUS_BK_CRCERR (_U(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos)
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW (_U(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
+#define USB_DEVICE_STATUS_BK_MASK   _U(0x03)     /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W  8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
+    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_BK_OFFSET   0x00A        /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
+
+#define USB_HOST_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
+#define USB_HOST_STATUS_BK_CRCERR   (_U(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos)
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
+#define USB_HOST_STATUS_BK_ERRORFLOW (_U(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
+#define USB_HOST_STATUS_BK_MASK     _U(0x03)     /**< \brief (USB_HOST_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PDADDR:7;         /*!< bit:  0.. 6  Pipe Device Adress                 */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t PEPNUM:4;         /*!< bit:  8..11  Pipe Endpoint Number               */
+    uint16_t PERMAX:4;         /*!< bit: 12..15  Pipe Error Max Number              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_CTRL_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRL_PIPE_OFFSET   0x00C        /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
+#define USB_HOST_CTRL_PIPE_RESETVALUE _U(0x0000)   /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos)
+#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
+#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12           /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos)
+#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
+#define USB_HOST_CTRL_PIPE_MASK     _U(0xFF7F)   /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DTGLER:1;         /*!< bit:      0  Data Toggle Error                  */
+    uint16_t DAPIDER:1;        /*!< bit:      1  Data PID Error                     */
+    uint16_t PIDER:1;          /*!< bit:      2  PID Error                          */
+    uint16_t TOUTER:1;         /*!< bit:      3  Time Out Error                     */
+    uint16_t CRC16ER:1;        /*!< bit:      4  CRC16 Error                        */
+    uint16_t ERCNT:3;          /*!< bit:  5.. 7  Pipe Error Count                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_STATUS_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_PIPE_OFFSET 0x00E        /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
+
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0            /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
+#define USB_HOST_STATUS_PIPE_DTGLER (_U(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos)
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1            /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
+#define USB_HOST_STATUS_PIPE_DAPIDER (_U(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
+#define USB_HOST_STATUS_PIPE_PIDER_Pos 2            /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
+#define USB_HOST_STATUS_PIPE_PIDER  (_U(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos)
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3            /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
+#define USB_HOST_STATUS_PIPE_TOUTER (_U(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos)
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4            /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
+#define USB_HOST_STATUS_PIPE_CRC16ER (_U(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5            /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
+#define USB_HOST_STATUS_PIPE_MASK   _U(0x00FF)   /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
+
+/** \brief UsbDeviceDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_DEVICE_ADDR_Type      ADDR;        /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+  __IO USB_DEVICE_PCKSIZE_Type   PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+  __IO USB_DEVICE_EXTREG_Type    EXTREG;      /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+  __IO USB_DEVICE_STATUS_BK_Type STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+       RoReg8                    Reserved1[0x5];
+} UsbDeviceDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_HOST_ADDR_Type        ADDR;        /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+  __IO USB_HOST_PCKSIZE_Type     PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+  __IO USB_HOST_EXTREG_Type      EXTREG;      /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+  __IO USB_HOST_STATUS_BK_Type   STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) HOST_DESC_BANK Host Bank, Status of Bank */
+       RoReg8                    Reserved1[0x1];
+  __IO USB_HOST_CTRL_PIPE_Type   CTRL_PIPE;   /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+  __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} UsbHostDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbDeviceEndpoint hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_DEVICE_EPCFG_Type     EPCFG;       /**< \brief Offset: 0x000 (R/W  8) DEVICE_ENDPOINT End Point Configuration */
+       RoReg8                    Reserved1[0x3];
+  __O  USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+  __O  USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Set */
+  __I  USB_DEVICE_EPSTATUS_Type  EPSTATUS;    /**< \brief Offset: 0x006 (R/   8) DEVICE_ENDPOINT End Point Pipe Status */
+  __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG;   /**< \brief Offset: 0x007 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Flag */
+  __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR;  /**< \brief Offset: 0x008 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+  __IO USB_DEVICE_EPINTENSET_Type EPINTENSET;  /**< \brief Offset: 0x009 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+       RoReg8                    Reserved2[0x16];
+} UsbDeviceEndpoint;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostPipe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_HOST_PCFG_Type        PCFG;        /**< \brief Offset: 0x000 (R/W  8) HOST_PIPE End Point Configuration */
+       RoReg8                    Reserved1[0x2];
+  __IO USB_HOST_BINTERVAL_Type   BINTERVAL;   /**< \brief Offset: 0x003 (R/W  8) HOST_PIPE Bus Access Period of Pipe */
+  __O  USB_HOST_PSTATUSCLR_Type  PSTATUSCLR;  /**< \brief Offset: 0x004 ( /W  8) HOST_PIPE End Point Pipe Status Clear */
+  __O  USB_HOST_PSTATUSSET_Type  PSTATUSSET;  /**< \brief Offset: 0x005 ( /W  8) HOST_PIPE End Point Pipe Status Set */
+  __I  USB_HOST_PSTATUS_Type     PSTATUS;     /**< \brief Offset: 0x006 (R/   8) HOST_PIPE End Point Pipe Status */
+  __IO USB_HOST_PINTFLAG_Type    PINTFLAG;    /**< \brief Offset: 0x007 (R/W  8) HOST_PIPE Pipe Interrupt Flag */
+  __IO USB_HOST_PINTENCLR_Type   PINTENCLR;   /**< \brief Offset: 0x008 (R/W  8) HOST_PIPE Pipe Interrupt Flag Clear */
+  __IO USB_HOST_PINTENSET_Type   PINTENSET;   /**< \brief Offset: 0x009 (R/W  8) HOST_PIPE Pipe Interrupt Flag Set */
+       RoReg8                    Reserved2[0x16];
+} UsbHostPipe;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x1];
+  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
+  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
+       RoReg8                    Reserved2[0x4];
+  __IO USB_DEVICE_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+  __IO USB_DEVICE_DADD_Type      DADD;        /**< \brief Offset: 0x00A (R/W  8) DEVICE Device Address */
+       RoReg8                    Reserved3[0x1];
+  __I  USB_DEVICE_STATUS_Type    STATUS;      /**< \brief Offset: 0x00C (R/   8) DEVICE Status */
+  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
+       RoReg8                    Reserved4[0x2];
+  __I  USB_DEVICE_FNUM_Type      FNUM;        /**< \brief Offset: 0x010 (R/  16) DEVICE Device Frame Number */
+       RoReg8                    Reserved5[0x2];
+  __IO USB_DEVICE_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+       RoReg8                    Reserved6[0x2];
+  __IO USB_DEVICE_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+       RoReg8                    Reserved7[0x2];
+  __IO USB_DEVICE_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+       RoReg8                    Reserved8[0x2];
+  __I  USB_DEVICE_EPINTSMRY_Type EPINTSMRY;   /**< \brief Offset: 0x020 (R/  16) DEVICE End Point Interrupt Summary */
+       RoReg8                    Reserved9[0x2];
+  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+       RoReg8                    Reserved10[0xD6];
+       UsbDeviceEndpoint         DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+} UsbDevice;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x1];
+  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
+  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
+       RoReg8                    Reserved2[0x4];
+  __IO USB_HOST_CTRLB_Type       CTRLB;       /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+  __IO USB_HOST_HSOFC_Type       HSOFC;       /**< \brief Offset: 0x00A (R/W  8) HOST Host Start Of Frame Control */
+       RoReg8                    Reserved3[0x1];
+  __IO USB_HOST_STATUS_Type      STATUS;      /**< \brief Offset: 0x00C (R/W  8) HOST Status */
+  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
+       RoReg8                    Reserved4[0x2];
+  __IO USB_HOST_FNUM_Type        FNUM;        /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+  __I  USB_HOST_FLENHIGH_Type    FLENHIGH;    /**< \brief Offset: 0x012 (R/   8) HOST Host Frame Length */
+       RoReg8                    Reserved5[0x1];
+  __IO USB_HOST_INTENCLR_Type    INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+       RoReg8                    Reserved6[0x2];
+  __IO USB_HOST_INTENSET_Type    INTENSET;    /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+       RoReg8                    Reserved7[0x2];
+  __IO USB_HOST_INTFLAG_Type     INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+       RoReg8                    Reserved8[0x2];
+  __I  USB_HOST_PINTSMRY_Type    PINTSMRY;    /**< \brief Offset: 0x020 (R/  16) HOST Pipe Interrupt Summary */
+       RoReg8                    Reserved9[0x2];
+  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+       RoReg8                    Reserved10[0xD6];
+       UsbHostPipe               HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
+} UsbHost;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+       UsbDeviceDescBank         DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+} UsbDeviceDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+       UsbHostDescBank           HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+} UsbHostDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_USB_DESCRIPTOR
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       UsbDevice                 DEVICE;      /**< \brief Offset: 0x000 USB is Device */
+       UsbHost                   HOST;        /**< \brief Offset: 0x000 USB is Host */
+} Usb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_USB_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/component/wdt.h b/uf2-samdx1/lib/samd21/samd21a/include/component/wdt.h
new file mode 100644
index 00000000..ccb8bc32
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/component/wdt.h
@@ -0,0 +1,288 @@
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_COMPONENT_
+#define _SAMD21_WDT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2203
+#define REV_WDT                     0x200
+
+/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  WEN:1;            /*!< bit:      2  Watchdog Timer Window Mode Enable  */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ALWAYSON:1;       /*!< bit:      7  Always-On                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRL_OFFSET             0x0          /**< \brief (WDT_CTRL offset) Control */
+#define WDT_CTRL_RESETVALUE         _U(0x00)     /**< \brief (WDT_CTRL reset_value) Control */
+
+#define WDT_CTRL_ENABLE_Pos         1            /**< \brief (WDT_CTRL) Enable */
+#define WDT_CTRL_ENABLE             (_U(0x1) << WDT_CTRL_ENABLE_Pos)
+#define WDT_CTRL_WEN_Pos            2            /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
+#define WDT_CTRL_WEN                (_U(0x1) << WDT_CTRL_WEN_Pos)
+#define WDT_CTRL_ALWAYSON_Pos       7            /**< \brief (WDT_CTRL) Always-On */
+#define WDT_CTRL_ALWAYSON           (_U(0x1) << WDT_CTRL_ALWAYSON_Pos)
+#define WDT_CTRL_MASK               _U(0x86)     /**< \brief (WDT_CTRL) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W  8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:4;            /*!< bit:  0.. 3  Time-Out Period                    */
+    uint8_t  WINDOW:4;         /*!< bit:  4.. 7  Window Mode Time-Out Period        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET           0x1          /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE       _U(0xBB)     /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos          0            /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk          (_U(0xF) << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value)       (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
+#define   WDT_CONFIG_PER_8_Val            _U(0x0)   /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_PER_16_Val           _U(0x1)   /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_PER_32_Val           _U(0x2)   /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_PER_64_Val           _U(0x3)   /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_PER_128_Val          _U(0x4)   /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_PER_256_Val          _U(0x5)   /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_PER_512_Val          _U(0x6)   /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_PER_1K_Val           _U(0x7)   /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_PER_2K_Val           _U(0x8)   /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_PER_4K_Val           _U(0x9)   /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_PER_8K_Val           _U(0xA)   /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_PER_16K_Val          _U(0xB)   /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_8            (WDT_CONFIG_PER_8_Val          << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16           (WDT_CONFIG_PER_16_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_32           (WDT_CONFIG_PER_32_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_64           (WDT_CONFIG_PER_64_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_128          (WDT_CONFIG_PER_128_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_256          (WDT_CONFIG_PER_256_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_512          (WDT_CONFIG_PER_512_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_1K           (WDT_CONFIG_PER_1K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_2K           (WDT_CONFIG_PER_2K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_4K           (WDT_CONFIG_PER_4K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_8K           (WDT_CONFIG_PER_8K_Val         << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16K          (WDT_CONFIG_PER_16K_Val        << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos       4            /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk       (_U(0xF) << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value)    (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
+#define   WDT_CONFIG_WINDOW_8_Val         _U(0x0)   /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_WINDOW_16_Val        _U(0x1)   /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_WINDOW_32_Val        _U(0x2)   /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_WINDOW_64_Val        _U(0x3)   /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_WINDOW_128_Val       _U(0x4)   /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_WINDOW_256_Val       _U(0x5)   /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_WINDOW_512_Val       _U(0x6)   /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_WINDOW_1K_Val        _U(0x7)   /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_WINDOW_2K_Val        _U(0x8)   /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_WINDOW_4K_Val        _U(0x9)   /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_WINDOW_8K_Val        _U(0xA)   /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_WINDOW_16K_Val       _U(0xB)   /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_8         (WDT_CONFIG_WINDOW_8_Val       << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16        (WDT_CONFIG_WINDOW_16_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_32        (WDT_CONFIG_WINDOW_32_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_64        (WDT_CONFIG_WINDOW_64_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_128       (WDT_CONFIG_WINDOW_128_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_256       (WDT_CONFIG_WINDOW_256_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_512       (WDT_CONFIG_WINDOW_512_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_1K        (WDT_CONFIG_WINDOW_1K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_2K        (WDT_CONFIG_WINDOW_2K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_4K        (WDT_CONFIG_WINDOW_4K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_8K        (WDT_CONFIG_WINDOW_8K_Val      << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16K       (WDT_CONFIG_WINDOW_16K_Val     << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK             _U(0xFF)     /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W  8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EWOFFSET:4;       /*!< bit:  0.. 3  Early Warning Interrupt Time Offset */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET           0x2          /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE       _U(0x0B)     /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos     0            /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk     (_U(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value)  (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
+#define   WDT_EWCTRL_EWOFFSET_8_Val       _U(0x0)   /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_16_Val      _U(0x1)   /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_32_Val      _U(0x2)   /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_64_Val      _U(0x3)   /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_128_Val     _U(0x4)   /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_256_Val     _U(0x5)   /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_512_Val     _U(0x6)   /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_1K_Val      _U(0x7)   /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_2K_Val      _U(0x8)   /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_4K_Val      _U(0x9)   /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_8K_Val      _U(0xA)   /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_16K_Val     _U(0xB)   /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_8       (WDT_EWCTRL_EWOFFSET_8_Val     << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16      (WDT_EWCTRL_EWOFFSET_16_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_32      (WDT_EWCTRL_EWOFFSET_32_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_64      (WDT_EWCTRL_EWOFFSET_64_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_128     (WDT_EWCTRL_EWOFFSET_128_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_256     (WDT_EWCTRL_EWOFFSET_256_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_512     (WDT_EWCTRL_EWOFFSET_512_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_1K      (WDT_EWCTRL_EWOFFSET_1K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_2K      (WDT_EWCTRL_EWOFFSET_2K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_4K      (WDT_EWCTRL_EWOFFSET_4K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_8K      (WDT_EWCTRL_EWOFFSET_8K_Val    << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16K     (WDT_EWCTRL_EWOFFSET_16K_Val   << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK             _U(0x0F)     /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET         0x4          /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE     _U(0x00)     /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos         0            /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW             (_U(0x1) << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK           _U(0x01)     /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET         0x5          /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE     _U(0x00)     /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos         0            /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW             (_U(0x1) << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK           _U(0x01)     /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  EW:1;             /*!< bit:      0  Early Warning                      */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET          0x6          /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE      _U(0x00)     /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos          0            /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW              (_U(0x1) << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK            _U(0x01)     /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  SYNCBUSY:1;       /*!< bit:      7  Synchronization Busy               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_STATUS_OFFSET           0x7          /**< \brief (WDT_STATUS offset) Status */
+#define WDT_STATUS_RESETVALUE       _U(0x00)     /**< \brief (WDT_STATUS reset_value) Status */
+
+#define WDT_STATUS_SYNCBUSY_Pos     7            /**< \brief (WDT_STATUS) Synchronization Busy */
+#define WDT_STATUS_SYNCBUSY         (_U(0x1) << WDT_STATUS_SYNCBUSY_Pos)
+#define WDT_STATUS_MASK             _U(0x80)     /**< \brief (WDT_STATUS) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W  8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CLEAR:8;          /*!< bit:  0.. 7  Watchdog Clear                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET            0x8          /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE        _U(0x00)     /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos         0            /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk         (_U(0xFF) << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value)      (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
+#define   WDT_CLEAR_CLEAR_KEY_Val         _U(0xA5)   /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY         (WDT_CLEAR_CLEAR_KEY_Val       << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK              _U(0xFF)     /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO WDT_CTRL_Type             CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+  __IO WDT_CONFIG_Type           CONFIG;      /**< \brief Offset: 0x1 (R/W  8) Configuration */
+  __IO WDT_EWCTRL_Type           EWCTRL;      /**< \brief Offset: 0x2 (R/W  8) Early Warning Interrupt Control */
+       RoReg8                    Reserved1[0x1];
+  __IO WDT_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
+  __IO WDT_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
+  __IO WDT_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
+  __I  WDT_STATUS_Type           STATUS;      /**< \brief Offset: 0x7 (R/   8) Status */
+  __O  WDT_CLEAR_Type            CLEAR;       /**< \brief Offset: 0x8 ( /W  8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_WDT_COMPONENT_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/ac.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/ac.h
new file mode 100644
index 00000000..af6120f6
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/ac.h
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_INSTANCE_
+#define _SAMD21_AC_INSTANCE_
+
+/* ========== Register definition for AC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC_CTRLA               (0x42004400) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (0x42004401) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (0x42004402) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (0x42004404) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (0x42004405) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (0x42004406) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (0x42004408) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (0x42004409) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC             (0x4200440A) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL             (0x4200440C) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0           (0x42004410) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (0x42004414) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0             (0x42004420) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (0x42004421) /**< \brief (AC) Scaler 1 */
+#else
+#define REG_AC_CTRLA               (*(RwReg8 *)0x42004400UL) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (*(WoReg8 *)0x42004401UL) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (*(RwReg16*)0x42004402UL) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (*(RwReg8 *)0x42004404UL) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (*(RwReg8 *)0x42004405UL) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (*(RwReg8 *)0x42004406UL) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (*(RoReg8 *)0x42004408UL) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (*(RoReg8 *)0x42004409UL) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC             (*(RoReg8 *)0x4200440AUL) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL             (*(RwReg8 *)0x4200440CUL) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0           (*(RwReg  *)0x42004410UL) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (*(RwReg  *)0x42004414UL) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0             (*(RwReg8 *)0x42004420UL) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (*(RwReg8 *)0x42004421UL) /**< \brief (AC) Scaler 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC peripheral ========== */
+#define AC_CMP_NUM                  2        // Number of comparators
+#define AC_GCLK_ID_ANA              32       // Index of Generic Clock for analog
+#define AC_GCLK_ID_DIG              31       // Index of Generic Clock for digital
+#define AC_NUM_CMP                  2       
+#define AC_PAIRS                    1        // Number of pairs of comparators
+
+#endif /* _SAMD21_AC_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/adc.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/adc.h
new file mode 100644
index 00000000..9b2b2282
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/adc.h
@@ -0,0 +1,84 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ADC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_INSTANCE_
+#define _SAMD21_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CTRLA              (0x42004000) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL            (0x42004001) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL            (0x42004002) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL           (0x42004003) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB              (0x42004004) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL            (0x42004008) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG             (0x4200400C) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL          (0x42004010) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL             (0x42004014) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR           (0x42004016) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET           (0x42004017) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG            (0x42004018) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS             (0x42004019) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT             (0x4200401A) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT              (0x4200401C) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT              (0x42004020) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR           (0x42004024) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR         (0x42004026) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB              (0x42004028) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL            (0x4200402A) /**< \brief (ADC) Debug Control */
+#else
+#define REG_ADC_CTRLA              (*(RwReg8 *)0x42004000UL) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL            (*(RwReg8 *)0x42004001UL) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL            (*(RwReg8 *)0x42004002UL) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL           (*(RwReg8 *)0x42004003UL) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB              (*(RwReg16*)0x42004004UL) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL            (*(RwReg8 *)0x42004008UL) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG             (*(RwReg8 *)0x4200400CUL) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL          (*(RwReg  *)0x42004010UL) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL             (*(RwReg8 *)0x42004014UL) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR           (*(RwReg8 *)0x42004016UL) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET           (*(RwReg8 *)0x42004017UL) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG            (*(RwReg8 *)0x42004018UL) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS             (*(RoReg8 *)0x42004019UL) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT             (*(RoReg16*)0x4200401AUL) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT              (*(RwReg16*)0x4200401CUL) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT              (*(RwReg16*)0x42004020UL) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR           (*(RwReg16*)0x42004024UL) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR         (*(RwReg16*)0x42004026UL) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB              (*(RwReg16*)0x42004028UL) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL            (*(RwReg8 *)0x4200402AUL) /**< \brief (ADC) Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC peripheral ========== */
+#define ADC_DMAC_ID_RESRDY          39       // Index of DMA RESRDY trigger
+#define ADC_EXTCHANNEL_MSB          19       // Number of external channels
+#define ADC_GCLK_ID                 30       // Index of Generic Clock
+#define ADC_RESULT_BITS             16       // Size of RESULT.RESULT bitfield
+#define ADC_RESULT_MSB              15       // Size of Result
+
+#endif /* _SAMD21_ADC_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/dac.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/dac.h
new file mode 100644
index 00000000..c034a56a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/dac.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DAC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_INSTANCE_
+#define _SAMD21_DAC_INSTANCE_
+
+/* ========== Register definition for DAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DAC_CTRLA              (0x42004800) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (0x42004801) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (0x42004802) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (0x42004804) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (0x42004805) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (0x42004806) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (0x42004807) /**< \brief (DAC) Status */
+#define REG_DAC_DATA               (0x42004808) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF            (0x4200480C) /**< \brief (DAC) Data Buffer */
+#else
+#define REG_DAC_CTRLA              (*(RwReg8 *)0x42004800UL) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (*(RwReg8 *)0x42004801UL) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (*(RwReg8 *)0x42004802UL) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (*(RwReg8 *)0x42004804UL) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (*(RwReg8 *)0x42004805UL) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (*(RwReg8 *)0x42004806UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (*(RoReg8 *)0x42004807UL) /**< \brief (DAC) Status */
+#define REG_DAC_DATA               (*(RwReg16*)0x42004808UL) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF            (*(RwReg16*)0x4200480CUL) /**< \brief (DAC) Data Buffer */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DAC peripheral ========== */
+#define DAC_DMAC_ID_EMPTY           40       // Index of DMAC EMPTY trigger
+#define DAC_GCLK_ID                 33       // Index of Generic Clock
+
+#endif /* _SAMD21_DAC_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/dmac.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/dmac.h
new file mode 100644
index 00000000..bd71ed85
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/dmac.h
@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DMAC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_INSTANCE_
+#define _SAMD21_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_CTRL              (0x41004800) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL           (0x41004802) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN         (0x41004804) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM         (0x41004808) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS         (0x4100480C) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL           (0x4100480D) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_QOSCTRL           (0x4100480E) /**< \brief (DMAC) QOS Control */
+#define REG_DMAC_SWTRIGCTRL        (0x41004810) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0          (0x41004814) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND           (0x41004820) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS         (0x41004824) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH            (0x41004828) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH            (0x4100482C) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE            (0x41004830) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR          (0x41004834) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR           (0x41004838) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID              (0x4100483F) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA           (0x41004840) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB           (0x41004844) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR        (0x4100484C) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET        (0x4100484D) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG         (0x4100484E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS          (0x4100484F) /**< \brief (DMAC) Channel Status */
+#else
+#define REG_DMAC_CTRL              (*(RwReg16*)0x41004800UL) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL           (*(RwReg16*)0x41004802UL) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN         (*(RwReg  *)0x41004804UL) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM         (*(RwReg  *)0x41004808UL) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS         (*(RwReg8 *)0x4100480CUL) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL           (*(RwReg8 *)0x4100480DUL) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_QOSCTRL           (*(RwReg8 *)0x4100480EUL) /**< \brief (DMAC) QOS Control */
+#define REG_DMAC_SWTRIGCTRL        (*(RwReg  *)0x41004810UL) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0          (*(RwReg  *)0x41004814UL) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND           (*(RwReg16*)0x41004820UL) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS         (*(RoReg  *)0x41004824UL) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH            (*(RoReg  *)0x41004828UL) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH            (*(RoReg  *)0x4100482CUL) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE            (*(RoReg  *)0x41004830UL) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR          (*(RwReg  *)0x41004834UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR           (*(RwReg  *)0x41004838UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID              (*(RwReg8 *)0x4100483FUL) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA           (*(RwReg8 *)0x41004840UL) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB           (*(RwReg  *)0x41004844UL) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR        (*(RwReg8 *)0x4100484CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET        (*(RwReg8 *)0x4100484DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG         (*(RwReg8 *)0x4100484EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS          (*(RoReg8 *)0x4100484FUL) /**< \brief (DMAC) Channel Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DMAC peripheral ========== */
+#define DMAC_CH_BITS                4        // Number of bits to select channel
+#define DMAC_CH_NUM                 12       // Number of channels
+#define DMAC_CLK_AHB_ID             5        // AHB clock index
+#define DMAC_EVIN_NUM               4        // Number of input events
+#define DMAC_EVOUT_NUM              4        // Number of output events
+#define DMAC_LVL_BITS               2        // Number of bit to select level priority
+#define DMAC_LVL_NUM                4        // Enable priority level number
+#define DMAC_TRIG_BITS              6        // Number of bits to select trigger source
+#define DMAC_TRIG_NUM               45       // Number of peripheral triggers
+
+#endif /* _SAMD21_DMAC_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/dsu.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/dsu.h
new file mode 100644
index 00000000..3db525a2
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/dsu.h
@@ -0,0 +1,84 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DSU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_INSTANCE_
+#define _SAMD21_DSU_INSTANCE_
+
+/* ========== Register definition for DSU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DSU_CTRL               (0x41002000) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (0x41002001) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (0x41002002) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (0x41002004) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (0x41002008) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (0x4100200C) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (0x41002018) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0             (0x41003000) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (0x41003004) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END                (0x41003008) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE            (0x41003FCC) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4               (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0               (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
+#else
+#define REG_DSU_CTRL               (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (*(RwReg  *)0x41002004UL) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (*(RwReg  *)0x41002008UL) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (*(RwReg  *)0x4100200CUL) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (*(RwReg  *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (*(RwReg  *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (*(RoReg  *)0x41002018UL) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0             (*(RoReg  *)0x41003000UL) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (*(RoReg  *)0x41003004UL) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END                (*(RoReg  *)0x41003008UL) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE            (*(RoReg  *)0x41003FCCUL) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4               (*(RoReg  *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0               (*(RoReg  *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (*(RoReg  *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (*(RoReg  *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (*(RoReg  *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (*(RoReg  *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (*(RoReg  *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (*(RoReg  *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (*(RoReg  *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DSU peripheral ========== */
+#define DSU_CLK_HSB_ID              3        // Index of AHB clock in PM.AHBMASK register
+
+#endif /* _SAMD21_DSU_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/eic.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/eic.h
new file mode 100644
index 00000000..55e761ce
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/eic.h
@@ -0,0 +1,63 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EIC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_INSTANCE_
+#define _SAMD21_EIC_INSTANCE_
+
+/* ========== Register definition for EIC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EIC_CTRL               (0x40001800) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS             (0x40001801) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL            (0x40001802) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (0x40001803) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL             (0x40001804) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (0x40001808) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (0x4000180C) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (0x40001810) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP             (0x40001814) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0            (0x40001818) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1            (0x4000181C) /**< \brief (EIC) Configuration 1 */
+#else
+#define REG_EIC_CTRL               (*(RwReg8 *)0x40001800UL) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS             (*(RoReg8 *)0x40001801UL) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL            (*(RwReg8 *)0x40001802UL) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (*(RwReg8 *)0x40001803UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL             (*(RwReg  *)0x40001804UL) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (*(RwReg  *)0x40001808UL) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (*(RwReg  *)0x4000180CUL) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (*(RwReg  *)0x40001810UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP             (*(RwReg  *)0x40001814UL) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0            (*(RwReg  *)0x40001818UL) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1            (*(RwReg  *)0x4000181CUL) /**< \brief (EIC) Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EIC peripheral ========== */
+#define EIC_CONFIG_NUM              2        // Number of CONFIG registers
+#define EIC_GCLK_ID                 5        // Index of Generic Clock
+
+#endif /* _SAMD21_EIC_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/evsys.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/evsys.h
new file mode 100644
index 00000000..e6256acf
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/evsys.h
@@ -0,0 +1,179 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_INSTANCE_
+#define _SAMD21_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRL             (0x42000400) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (0x42000404) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (0x42000408) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (0x4200040C) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (0x42000410) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (0x42000414) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (0x42000418) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#else
+#define REG_EVSYS_CTRL             (*(WoReg8 *)0x42000400UL) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL          (*(RwReg  *)0x42000404UL) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER             (*(RwReg16*)0x42000408UL) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS         (*(RoReg  *)0x4200040CUL) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR         (*(RwReg  *)0x42000410UL) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET         (*(RwReg  *)0x42000414UL) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG          (*(RwReg  *)0x42000418UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_CHANNELS              12       // Number of Channels
+#define EVSYS_CHANNELS_BITS         4        // Number of bits to select Channel
+#define EVSYS_CHANNELS_MSB          11       // Number of Channels - 1
+#define EVSYS_EXTEVT_NUM            0        // Number of External Event Generators
+#define EVSYS_GCLK_ID_0             7
+#define EVSYS_GCLK_ID_1             8
+#define EVSYS_GCLK_ID_2             9
+#define EVSYS_GCLK_ID_3             10
+#define EVSYS_GCLK_ID_4             11
+#define EVSYS_GCLK_ID_5             12
+#define EVSYS_GCLK_ID_6             13
+#define EVSYS_GCLK_ID_7             14
+#define EVSYS_GCLK_ID_8             15
+#define EVSYS_GCLK_ID_9             16
+#define EVSYS_GCLK_ID_10            17
+#define EVSYS_GCLK_ID_11            18
+#define EVSYS_GCLK_ID_LSB           7
+#define EVSYS_GCLK_ID_MSB           18
+#define EVSYS_GCLK_ID_SIZE          12
+#define EVSYS_GENERATORS            73       // Total Number of Event Generators
+#define EVSYS_GENERATORS_BITS       7        // Number of bits to select Event Generator
+#define EVSYS_USERS                 29       // Total Number of Event Users
+#define EVSYS_USERS_BITS            5        // Number of bits to select Event User
+
+// GENERATORS
+#define EVSYS_ID_GEN_RTC_CMP_0      1
+#define EVSYS_ID_GEN_RTC_CMP_1      2
+#define EVSYS_ID_GEN_RTC_OVF        3
+#define EVSYS_ID_GEN_RTC_PER_0      4
+#define EVSYS_ID_GEN_RTC_PER_1      5
+#define EVSYS_ID_GEN_RTC_PER_2      6
+#define EVSYS_ID_GEN_RTC_PER_3      7
+#define EVSYS_ID_GEN_RTC_PER_4      8
+#define EVSYS_ID_GEN_RTC_PER_5      9
+#define EVSYS_ID_GEN_RTC_PER_6      10
+#define EVSYS_ID_GEN_RTC_PER_7      11
+#define EVSYS_ID_GEN_EIC_EXTINT_0   12
+#define EVSYS_ID_GEN_EIC_EXTINT_1   13
+#define EVSYS_ID_GEN_EIC_EXTINT_2   14
+#define EVSYS_ID_GEN_EIC_EXTINT_3   15
+#define EVSYS_ID_GEN_EIC_EXTINT_4   16
+#define EVSYS_ID_GEN_EIC_EXTINT_5   17
+#define EVSYS_ID_GEN_EIC_EXTINT_6   18
+#define EVSYS_ID_GEN_EIC_EXTINT_7   19
+#define EVSYS_ID_GEN_EIC_EXTINT_8   20
+#define EVSYS_ID_GEN_EIC_EXTINT_9   21
+#define EVSYS_ID_GEN_EIC_EXTINT_10  22
+#define EVSYS_ID_GEN_EIC_EXTINT_11  23
+#define EVSYS_ID_GEN_EIC_EXTINT_12  24
+#define EVSYS_ID_GEN_EIC_EXTINT_13  25
+#define EVSYS_ID_GEN_EIC_EXTINT_14  26
+#define EVSYS_ID_GEN_EIC_EXTINT_15  27
+#define EVSYS_ID_GEN_EIC_EXTINT_16  28
+#define EVSYS_ID_GEN_EIC_EXTINT_17  29
+#define EVSYS_ID_GEN_DMAC_CH_0      30
+#define EVSYS_ID_GEN_DMAC_CH_1      31
+#define EVSYS_ID_GEN_DMAC_CH_2      32
+#define EVSYS_ID_GEN_DMAC_CH_3      33
+#define EVSYS_ID_GEN_TCC0_OVF       34
+#define EVSYS_ID_GEN_TCC0_TRG       35
+#define EVSYS_ID_GEN_TCC0_CNT       36
+#define EVSYS_ID_GEN_TCC0_MCX_0     37
+#define EVSYS_ID_GEN_TCC0_MCX_1     38
+#define EVSYS_ID_GEN_TCC0_MCX_2     39
+#define EVSYS_ID_GEN_TCC0_MCX_3     40
+#define EVSYS_ID_GEN_TCC1_OVF       41
+#define EVSYS_ID_GEN_TCC1_TRG       42
+#define EVSYS_ID_GEN_TCC1_CNT       43
+#define EVSYS_ID_GEN_TCC1_MCX_0     44
+#define EVSYS_ID_GEN_TCC1_MCX_1     45
+#define EVSYS_ID_GEN_TCC2_OVF       46
+#define EVSYS_ID_GEN_TCC2_TRG       47
+#define EVSYS_ID_GEN_TCC2_CNT       48
+#define EVSYS_ID_GEN_TCC2_MCX_0     49
+#define EVSYS_ID_GEN_TCC2_MCX_1     50
+#define EVSYS_ID_GEN_TC3_OVF        51
+#define EVSYS_ID_GEN_TC3_MCX_0      52
+#define EVSYS_ID_GEN_TC3_MCX_1      53
+#define EVSYS_ID_GEN_TC4_OVF        54
+#define EVSYS_ID_GEN_TC4_MCX_0      55
+#define EVSYS_ID_GEN_TC4_MCX_1      56
+#define EVSYS_ID_GEN_TC5_OVF        57
+#define EVSYS_ID_GEN_TC5_MCX_0      58
+#define EVSYS_ID_GEN_TC5_MCX_1      59
+#define EVSYS_ID_GEN_TC6_OVF        60
+#define EVSYS_ID_GEN_TC6_MCX_0      61
+#define EVSYS_ID_GEN_TC6_MCX_1      62
+#define EVSYS_ID_GEN_TC7_OVF        63
+#define EVSYS_ID_GEN_TC7_MCX_0      64
+#define EVSYS_ID_GEN_TC7_MCX_1      65
+#define EVSYS_ID_GEN_ADC_RESRDY     66
+#define EVSYS_ID_GEN_ADC_WINMON     67
+#define EVSYS_ID_GEN_AC_COMP_0      68
+#define EVSYS_ID_GEN_AC_COMP_1      69
+#define EVSYS_ID_GEN_AC_WIN_0       70
+#define EVSYS_ID_GEN_DAC_EMPTY      71
+
+// USERS
+#define EVSYS_ID_USER_DMAC_CH_0     0
+#define EVSYS_ID_USER_DMAC_CH_1     1
+#define EVSYS_ID_USER_DMAC_CH_2     2
+#define EVSYS_ID_USER_DMAC_CH_3     3
+#define EVSYS_ID_USER_TCC0_EV_0     4
+#define EVSYS_ID_USER_TCC0_EV_1     5
+#define EVSYS_ID_USER_TCC0_MC_0     6
+#define EVSYS_ID_USER_TCC0_MC_1     7
+#define EVSYS_ID_USER_TCC0_MC_2     8
+#define EVSYS_ID_USER_TCC0_MC_3     9
+#define EVSYS_ID_USER_TCC1_EV_0     10
+#define EVSYS_ID_USER_TCC1_EV_1     11
+#define EVSYS_ID_USER_TCC1_MC_0     12
+#define EVSYS_ID_USER_TCC1_MC_1     13
+#define EVSYS_ID_USER_TCC2_EV_0     14
+#define EVSYS_ID_USER_TCC2_EV_1     15
+#define EVSYS_ID_USER_TCC2_MC_0     16
+#define EVSYS_ID_USER_TCC2_MC_1     17
+#define EVSYS_ID_USER_TC3_EVU       18
+#define EVSYS_ID_USER_TC4_EVU       19
+#define EVSYS_ID_USER_TC5_EVU       20
+#define EVSYS_ID_USER_TC6_EVU       21
+#define EVSYS_ID_USER_TC7_EVU       22
+#define EVSYS_ID_USER_ADC_START     23
+#define EVSYS_ID_USER_ADC_SYNC      24
+#define EVSYS_ID_USER_AC_SOC_0      25
+#define EVSYS_ID_USER_AC_SOC_1      26
+#define EVSYS_ID_USER_DAC_START     27
+
+#endif /* _SAMD21_EVSYS_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/gclk.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/gclk.h
new file mode 100644
index 00000000..e75ad3b5
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/gclk.h
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Instance description for GCLK
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_INSTANCE_
+#define _SAMD21_GCLK_INSTANCE_
+
+/* ========== Register definition for GCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GCLK_CTRL              (0x40000C00) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS            (0x40000C01) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL           (0x40000C02) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL           (0x40000C04) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV            (0x40000C08) /**< \brief (GCLK) Generic Clock Generator Division */
+#else
+#define REG_GCLK_CTRL              (*(RwReg8 *)0x40000C00UL) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS            (*(RoReg8 *)0x40000C01UL) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL           (*(RwReg16*)0x40000C02UL) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL           (*(RwReg  *)0x40000C04UL) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV            (*(RwReg  *)0x40000C08UL) /**< \brief (GCLK) Generic Clock Generator Division */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GCLK peripheral ========== */
+#define GCLK_GENDIV_BITS            16      
+#define GCLK_GEN_NUM                9        // Number of Generic Clock Generators
+#define GCLK_GEN_NUM_MSB            8        // Number of Generic Clock Generators - 1
+#define GCLK_GEN_SOURCE_NUM_MSB     8        // Number of Generic Clock Sources - 1
+#define GCLK_NUM                    37       // Number of Generic Clock Users
+#define GCLK_SOURCE_DFLL48M         7       
+#define GCLK_SOURCE_FDPLL           8       
+#define GCLK_SOURCE_GCLKGEN1        2       
+#define GCLK_SOURCE_GCLKIN          1       
+#define GCLK_SOURCE_NUM             9        // Number of Generic Clock Sources
+#define GCLK_SOURCE_OSCULP32K       3       
+#define GCLK_SOURCE_OSC8M           6       
+#define GCLK_SOURCE_OSC32K          4       
+#define GCLK_SOURCE_XOSC            0       
+#define GCLK_SOURCE_XOSC32K         5       
+
+#endif /* _SAMD21_GCLK_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/i2s.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/i2s.h
new file mode 100644
index 00000000..4df326ee
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/i2s.h
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Instance description for I2S
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_INSTANCE_
+#define _SAMD21_I2S_INSTANCE_
+
+/* ========== Register definition for I2S peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_I2S_CTRLA              (0x42005000) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0           (0x42005004) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1           (0x42005008) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR           (0x4200500C) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET           (0x42005010) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG            (0x42005014) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY           (0x42005018) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0           (0x42005020) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1           (0x42005024) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0              (0x42005030) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1              (0x42005034) /**< \brief (I2S) Data 1 */
+#else
+#define REG_I2S_CTRLA              (*(RwReg8 *)0x42005000UL) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0           (*(RwReg  *)0x42005004UL) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1           (*(RwReg  *)0x42005008UL) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR           (*(RwReg16*)0x4200500CUL) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET           (*(RwReg16*)0x42005010UL) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG            (*(RwReg16*)0x42005014UL) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY           (*(RoReg16*)0x42005018UL) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0           (*(RwReg  *)0x42005020UL) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1           (*(RwReg  *)0x42005024UL) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0              (*(RwReg  *)0x42005030UL) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1              (*(RwReg  *)0x42005034UL) /**< \brief (I2S) Data 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for I2S peripheral ========== */
+#define I2S_CLK_NUM                 2        // Number of clock units
+#define I2S_DMAC_ID_RX_0            41
+#define I2S_DMAC_ID_RX_1            42
+#define I2S_DMAC_ID_RX_LSB          41
+#define I2S_DMAC_ID_RX_MSB          42
+#define I2S_DMAC_ID_RX_SIZE         2
+#define I2S_DMAC_ID_TX_0            43
+#define I2S_DMAC_ID_TX_1            44
+#define I2S_DMAC_ID_TX_LSB          43
+#define I2S_DMAC_ID_TX_MSB          44
+#define I2S_DMAC_ID_TX_SIZE         2
+#define I2S_GCLK_ID_0               35
+#define I2S_GCLK_ID_1               36
+#define I2S_GCLK_ID_LSB             35
+#define I2S_GCLK_ID_MSB             36
+#define I2S_GCLK_ID_SIZE            2
+#define I2S_MAX_SLOTS               8        // Max number of data slots in frame
+#define I2S_SER_NUM                 2        // Number of serializers
+
+#endif /* _SAMD21_I2S_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/mtb.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/mtb.h
new file mode 100644
index 00000000..76b047f2
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/mtb.h
@@ -0,0 +1,88 @@
+/**
+ * \file
+ *
+ * \brief Instance description for MTB
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_INSTANCE_
+#define _SAMD21_MTB_INSTANCE_
+
+/* ========== Register definition for MTB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MTB_POSITION           (0x41006000) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER             (0x41006004) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW               (0x41006008) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE               (0x4100600C) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL             (0x41006F00) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET           (0x41006FA0) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR           (0x41006FA4) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS         (0x41006FB0) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS         (0x41006FB4) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS         (0x41006FB8) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH            (0x41006FBC) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID              (0x41006FC8) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE            (0x41006FCC) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4               (0x41006FD0) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5               (0x41006FD4) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6               (0x41006FD8) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7               (0x41006FDC) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0               (0x41006FE0) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1               (0x41006FE4) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2               (0x41006FE8) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3               (0x41006FEC) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0               (0x41006FF0) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1               (0x41006FF4) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2               (0x41006FF8) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3               (0x41006FFC) /**< \brief (MTB) CoreSight */
+#else
+#define REG_MTB_POSITION           (*(RwReg  *)0x41006000UL) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER             (*(RwReg  *)0x41006004UL) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW               (*(RwReg  *)0x41006008UL) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE               (*(RoReg  *)0x4100600CUL) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL             (*(RwReg  *)0x41006F00UL) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET           (*(RwReg  *)0x41006FA0UL) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR           (*(RwReg  *)0x41006FA4UL) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS         (*(RwReg  *)0x41006FB0UL) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS         (*(RoReg  *)0x41006FB4UL) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS         (*(RoReg  *)0x41006FB8UL) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH            (*(RoReg  *)0x41006FBCUL) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID              (*(RoReg  *)0x41006FC8UL) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE            (*(RoReg  *)0x41006FCCUL) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4               (*(RoReg  *)0x41006FD0UL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5               (*(RoReg  *)0x41006FD4UL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6               (*(RoReg  *)0x41006FD8UL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7               (*(RoReg  *)0x41006FDCUL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0               (*(RoReg  *)0x41006FE0UL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1               (*(RoReg  *)0x41006FE4UL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2               (*(RoReg  *)0x41006FE8UL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3               (*(RoReg  *)0x41006FECUL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0               (*(RoReg  *)0x41006FF0UL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1               (*(RoReg  *)0x41006FF4UL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2               (*(RoReg  *)0x41006FF8UL) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3               (*(RoReg  *)0x41006FFCUL) /**< \brief (MTB) CoreSight */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAMD21_MTB_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/nvmctrl.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/nvmctrl.h
new file mode 100644
index 00000000..7636f034
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/nvmctrl.h
@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_INSTANCE_
+#define _SAMD21_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA          (0x41004000) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (0x41004004) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (0x41004018) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (0x4100401C) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (0x41004020) /**< \brief (NVMCTRL) Lock Section */
+#else
+#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (*(RwReg  *)0x41004004UL) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (*(RwReg  *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x4100401CUL) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK           (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_AUX0_ADDRESS        0x00804000
+#define NVMCTRL_AUX1_ADDRESS        0x00806000
+#define NVMCTRL_AUX2_ADDRESS        0x00808000
+#define NVMCTRL_AUX3_ADDRESS        0x0080A000
+#define NVMCTRL_CLK_AHB_ID          4        // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
+#define NVMCTRL_FLASH_SIZE          262144  
+#define NVMCTRL_LOCKBIT_ADDRESS     0x00802000
+#define NVMCTRL_PAGE_HW             32      
+#define NVMCTRL_PAGE_SIZE           64      
+#define NVMCTRL_PAGE_W              16      
+#define NVMCTRL_PMSB                3       
+#define NVMCTRL_PSZ_BITS            6       
+#define NVMCTRL_ROW_PAGES           4       
+#define NVMCTRL_ROW_SIZE            256     
+#define NVMCTRL_TEMP_LOG_ADDRESS    0x00806030
+#define NVMCTRL_USER_PAGE_ADDRESS   0x00800000
+#define NVMCTRL_USER_PAGE_OFFSET    0x00800000
+#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
+
+#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/pac0.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/pac0.h
new file mode 100644
index 00000000..fe59d372
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/pac0.h
@@ -0,0 +1,44 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC0
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC0_INSTANCE_
+#define _SAMD21_PAC0_INSTANCE_
+
+/* ========== Register definition for PAC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC0_WPCLR             (0x40000000) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET             (0x40000004) /**< \brief (PAC0) Write Protection Set */
+#else
+#define REG_PAC0_WPCLR             (*(RwReg  *)0x40000000UL) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET             (*(RwReg  *)0x40000004UL) /**< \brief (PAC0) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC0 peripheral ========== */
+#define PAC0_WPROT_DEFAULT_VAL      0x00000000 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC0_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/pac1.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/pac1.h
new file mode 100644
index 00000000..ad4e7815
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/pac1.h
@@ -0,0 +1,44 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC1
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC1_INSTANCE_
+#define _SAMD21_PAC1_INSTANCE_
+
+/* ========== Register definition for PAC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC1_WPCLR             (0x41000000) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET             (0x41000004) /**< \brief (PAC1) Write Protection Set */
+#else
+#define REG_PAC1_WPCLR             (*(RwReg  *)0x41000000UL) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET             (*(RwReg  *)0x41000004UL) /**< \brief (PAC1) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC1 peripheral ========== */
+#define PAC1_WPROT_DEFAULT_VAL      0x00000002 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC1_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/pac2.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/pac2.h
new file mode 100644
index 00000000..8f2bd50f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/pac2.h
@@ -0,0 +1,44 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC2
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC2_INSTANCE_
+#define _SAMD21_PAC2_INSTANCE_
+
+/* ========== Register definition for PAC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC2_WPCLR             (0x42000000) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET             (0x42000004) /**< \brief (PAC2) Write Protection Set */
+#else
+#define REG_PAC2_WPCLR             (*(RwReg  *)0x42000000UL) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET             (*(RwReg  *)0x42000004UL) /**< \brief (PAC2) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC2 peripheral ========== */
+#define PAC2_WPROT_DEFAULT_VAL      0x00800000 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC2_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/pm.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/pm.h
new file mode 100644
index 00000000..feca8a6f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/pm.h
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PM
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_INSTANCE_
+#define _SAMD21_PM_INSTANCE_
+
+/* ========== Register definition for PM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PM_CTRL                (0x40000400) /**< \brief (PM) Control */
+#define REG_PM_SLEEP               (0x40000401) /**< \brief (PM) Sleep Mode */
+#define REG_PM_CPUSEL              (0x40000408) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL             (0x40000409) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL             (0x4000040A) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL             (0x4000040B) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK             (0x40000414) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK            (0x40000418) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK            (0x4000041C) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK            (0x40000420) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR            (0x40000434) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (0x40000435) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (0x40000436) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE              (0x40000438) /**< \brief (PM) Reset Cause */
+#else
+#define REG_PM_CTRL                (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control */
+#define REG_PM_SLEEP               (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Mode */
+#define REG_PM_CPUSEL              (*(RwReg8 *)0x40000408UL) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL             (*(RwReg8 *)0x40000409UL) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL             (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL             (*(RwReg8 *)0x4000040BUL) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK             (*(RwReg  *)0x40000414UL) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK            (*(RwReg  *)0x40000418UL) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK            (*(RwReg  *)0x4000041CUL) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK            (*(RwReg  *)0x40000420UL) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR            (*(RwReg8 *)0x40000434UL) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (*(RwReg8 *)0x40000435UL) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (*(RwReg8 *)0x40000436UL) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE              (*(RoReg8 *)0x40000438UL) /**< \brief (PM) Reset Cause */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PM peripheral ========== */
+#define PM_CTRL_MCSEL_DFLL48M       3       
+#define PM_CTRL_MCSEL_GCLK          0       
+#define PM_CTRL_MCSEL_OSC8M         1       
+#define PM_CTRL_MCSEL_XOSC          2       
+#define PM_PM_CLK_APB_NUM           2       
+
+#endif /* _SAMD21_PM_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/port.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/port.h
new file mode 100644
index 00000000..ab9c40bf
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/port.h
@@ -0,0 +1,121 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_INSTANCE_
+#define _SAMD21_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0              (0x41004400) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (0x41004404) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (0x41004408) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (0x4100440C) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (0x41004410) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (0x41004414) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (0x41004418) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (0x4100441C) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (0x41004420) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (0x41004424) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (0x41004428) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (0x41004430) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (0x41004440) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (0x41004480) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (0x41004484) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (0x41004488) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (0x4100448C) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (0x41004490) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (0x41004494) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (0x41004498) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (0x4100449C) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (0x410044A0) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (0x410044A4) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (0x410044A8) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (0x410044B0) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (0x410044C0) /**< \brief (PORT) Pin Configuration 1 */
+#else
+#define REG_PORT_DIR0              (*(RwReg  *)0x41004400UL) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (*(RwReg  *)0x41004404UL) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (*(RwReg  *)0x41004408UL) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100440CUL) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (*(RwReg  *)0x41004410UL) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (*(RwReg  *)0x41004414UL) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (*(RwReg  *)0x41004418UL) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100441CUL) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (*(RoReg  *)0x41004420UL) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (*(RwReg  *)0x41004424UL) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41004428UL) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0             (*(RwReg  *)0x41004430UL) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (*(RwReg  *)0x41004440UL) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (*(RwReg  *)0x41004480UL) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (*(RwReg  *)0x41004484UL) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (*(RwReg  *)0x41004488UL) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100448CUL) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (*(RwReg  *)0x41004490UL) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (*(RwReg  *)0x41004494UL) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (*(RwReg  *)0x41004498UL) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100449CUL) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (*(RoReg  *)0x410044A0UL) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (*(RwReg  *)0x410044A4UL) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410044A8UL) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1             (*(RwReg  *)0x410044B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (*(RwReg  *)0x410044C0UL) /**< \brief (PORT) Pin Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS                   84       // Number of PORT pins
+#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
+#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
+#define PORT_DRVSTR                 1        // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL     { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
+#define PORT_DRVSTR_IMPLEMENTED     { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
+#define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
+#define PORT_INEN_IMPLEMENTED       { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
+#define PORT_ODRAIN                 0        // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
+#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
+#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
+#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins
+#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins
+#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
+#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins
+#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins
+#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins
+#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins
+#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins
+#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
+#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
+#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins
+#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins
+#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
+#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins
+#define PORT_SLEWLIM                0        // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
+#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
+
+#endif /* _SAMD21_PORT_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/rtc.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/rtc.h
new file mode 100644
index 00000000..7a974e5e
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/rtc.h
@@ -0,0 +1,102 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RTC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_INSTANCE_
+#define _SAMD21_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_READREQ            (0x40001402) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS             (0x4000140A) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL            (0x4000140B) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (0x4000140C) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL         (0x40001400) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL       (0x40001404) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (0x40001406) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (0x40001407) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (0x40001408) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT        (0x40001410) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (0x40001418) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL         (0x40001400) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL       (0x40001404) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (0x40001406) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (0x40001407) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (0x40001408) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT        (0x40001410) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (0x40001414) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (0x40001418) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (0x4000141A) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL         (0x40001400) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL       (0x40001404) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (0x40001406) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (0x40001407) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (0x40001408) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK        (0x40001410) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (0x4000141C) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#else
+#define REG_RTC_READREQ            (*(RwReg16*)0x40001402UL) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS             (*(RwReg8 *)0x4000140AUL) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL            (*(RwReg8 *)0x4000140BUL) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (*(RwReg8 *)0x4000140CUL) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL         (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL       (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT        (*(RwReg  *)0x40001410UL) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (*(RwReg  *)0x40001418UL) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL         (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL       (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT        (*(RwReg16*)0x40001410UL) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (*(RwReg16*)0x40001414UL) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (*(RwReg16*)0x40001418UL) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (*(RwReg16*)0x4000141AUL) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL         (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL       (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK        (*(RwReg  *)0x40001410UL) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg  *)0x40001418UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (*(RwReg  *)0x4000141CUL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RTC peripheral ========== */
+#define RTC_ALARM_NUM               1        // Number of Alarms
+#define RTC_COMP16_NUM              2        // Number of 16-bit Comparators
+#define RTC_COMP32_NUM              1        // Number of 32-bit Comparators
+#define RTC_GCLK_ID                 4        // Index of Generic Clock
+#define RTC_NUM_OF_ALARMS           1        // Number of Alarms (obsolete)
+#define RTC_NUM_OF_COMP16           2        // Number of 16-bit Comparators (obsolete)
+#define RTC_NUM_OF_COMP32           1        // Number of 32-bit Comparators (obsolete)
+
+#endif /* _SAMD21_RTC_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/sbmatrix.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/sbmatrix.h
new file mode 100644
index 00000000..bdc4651a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/sbmatrix.h
@@ -0,0 +1,150 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SBMATRIX
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SBMATRIX_INSTANCE_
+#define _SAMD21_SBMATRIX_INSTANCE_
+
+/* ========== Register definition for SBMATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SBMATRIX_PRAS0         (0x41007080) /**< \brief (SBMATRIX) Priority A for Slave 0 */
+#define REG_SBMATRIX_PRBS0         (0x41007084) /**< \brief (SBMATRIX) Priority B for Slave 0 */
+#define REG_SBMATRIX_PRAS1         (0x41007088) /**< \brief (SBMATRIX) Priority A for Slave 1 */
+#define REG_SBMATRIX_PRBS1         (0x4100708C) /**< \brief (SBMATRIX) Priority B for Slave 1 */
+#define REG_SBMATRIX_PRAS2         (0x41007090) /**< \brief (SBMATRIX) Priority A for Slave 2 */
+#define REG_SBMATRIX_PRBS2         (0x41007094) /**< \brief (SBMATRIX) Priority B for Slave 2 */
+#define REG_SBMATRIX_PRAS3         (0x41007098) /**< \brief (SBMATRIX) Priority A for Slave 3 */
+#define REG_SBMATRIX_PRBS3         (0x4100709C) /**< \brief (SBMATRIX) Priority B for Slave 3 */
+#define REG_SBMATRIX_PRAS4         (0x410070A0) /**< \brief (SBMATRIX) Priority A for Slave 4 */
+#define REG_SBMATRIX_PRBS4         (0x410070A4) /**< \brief (SBMATRIX) Priority B for Slave 4 */
+#define REG_SBMATRIX_PRAS5         (0x410070A8) /**< \brief (SBMATRIX) Priority A for Slave 5 */
+#define REG_SBMATRIX_PRBS5         (0x410070AC) /**< \brief (SBMATRIX) Priority B for Slave 5 */
+#define REG_SBMATRIX_PRAS6         (0x410070B0) /**< \brief (SBMATRIX) Priority A for Slave 6 */
+#define REG_SBMATRIX_PRBS6         (0x410070B4) /**< \brief (SBMATRIX) Priority B for Slave 6 */
+#define REG_SBMATRIX_PRAS7         (0x410070B8) /**< \brief (SBMATRIX) Priority A for Slave 7 */
+#define REG_SBMATRIX_PRBS7         (0x410070BC) /**< \brief (SBMATRIX) Priority B for Slave 7 */
+#define REG_SBMATRIX_PRAS8         (0x410070C0) /**< \brief (SBMATRIX) Priority A for Slave 8 */
+#define REG_SBMATRIX_PRBS8         (0x410070C4) /**< \brief (SBMATRIX) Priority B for Slave 8 */
+#define REG_SBMATRIX_PRAS9         (0x410070C8) /**< \brief (SBMATRIX) Priority A for Slave 9 */
+#define REG_SBMATRIX_PRBS9         (0x410070CC) /**< \brief (SBMATRIX) Priority B for Slave 9 */
+#define REG_SBMATRIX_PRAS10        (0x410070D0) /**< \brief (SBMATRIX) Priority A for Slave 10 */
+#define REG_SBMATRIX_PRBS10        (0x410070D4) /**< \brief (SBMATRIX) Priority B for Slave 10 */
+#define REG_SBMATRIX_PRAS11        (0x410070D8) /**< \brief (SBMATRIX) Priority A for Slave 11 */
+#define REG_SBMATRIX_PRBS11        (0x410070DC) /**< \brief (SBMATRIX) Priority B for Slave 11 */
+#define REG_SBMATRIX_PRAS12        (0x410070E0) /**< \brief (SBMATRIX) Priority A for Slave 12 */
+#define REG_SBMATRIX_PRBS12        (0x410070E4) /**< \brief (SBMATRIX) Priority B for Slave 12 */
+#define REG_SBMATRIX_PRAS13        (0x410070E8) /**< \brief (SBMATRIX) Priority A for Slave 13 */
+#define REG_SBMATRIX_PRBS13        (0x410070EC) /**< \brief (SBMATRIX) Priority B for Slave 13 */
+#define REG_SBMATRIX_PRAS14        (0x410070F0) /**< \brief (SBMATRIX) Priority A for Slave 14 */
+#define REG_SBMATRIX_PRBS14        (0x410070F4) /**< \brief (SBMATRIX) Priority B for Slave 14 */
+#define REG_SBMATRIX_PRAS15        (0x410070F8) /**< \brief (SBMATRIX) Priority A for Slave 15 */
+#define REG_SBMATRIX_PRBS15        (0x410070FC) /**< \brief (SBMATRIX) Priority B for Slave 15 */
+#define REG_SBMATRIX_SFR0          (0x41007110) /**< \brief (SBMATRIX) Special Function 0 */
+#define REG_SBMATRIX_SFR1          (0x41007114) /**< \brief (SBMATRIX) Special Function 1 */
+#define REG_SBMATRIX_SFR2          (0x41007118) /**< \brief (SBMATRIX) Special Function 2 */
+#define REG_SBMATRIX_SFR3          (0x4100711C) /**< \brief (SBMATRIX) Special Function 3 */
+#define REG_SBMATRIX_SFR4          (0x41007120) /**< \brief (SBMATRIX) Special Function 4 */
+#define REG_SBMATRIX_SFR5          (0x41007124) /**< \brief (SBMATRIX) Special Function 5 */
+#define REG_SBMATRIX_SFR6          (0x41007128) /**< \brief (SBMATRIX) Special Function 6 */
+#define REG_SBMATRIX_SFR7          (0x4100712C) /**< \brief (SBMATRIX) Special Function 7 */
+#define REG_SBMATRIX_SFR8          (0x41007130) /**< \brief (SBMATRIX) Special Function 8 */
+#define REG_SBMATRIX_SFR9          (0x41007134) /**< \brief (SBMATRIX) Special Function 9 */
+#define REG_SBMATRIX_SFR10         (0x41007138) /**< \brief (SBMATRIX) Special Function 10 */
+#define REG_SBMATRIX_SFR11         (0x4100713C) /**< \brief (SBMATRIX) Special Function 11 */
+#define REG_SBMATRIX_SFR12         (0x41007140) /**< \brief (SBMATRIX) Special Function 12 */
+#define REG_SBMATRIX_SFR13         (0x41007144) /**< \brief (SBMATRIX) Special Function 13 */
+#define REG_SBMATRIX_SFR14         (0x41007148) /**< \brief (SBMATRIX) Special Function 14 */
+#define REG_SBMATRIX_SFR15         (0x4100714C) /**< \brief (SBMATRIX) Special Function 15 */
+#else
+#define REG_SBMATRIX_PRAS0         (*(RwReg  *)0x41007080UL) /**< \brief (SBMATRIX) Priority A for Slave 0 */
+#define REG_SBMATRIX_PRBS0         (*(RwReg  *)0x41007084UL) /**< \brief (SBMATRIX) Priority B for Slave 0 */
+#define REG_SBMATRIX_PRAS1         (*(RwReg  *)0x41007088UL) /**< \brief (SBMATRIX) Priority A for Slave 1 */
+#define REG_SBMATRIX_PRBS1         (*(RwReg  *)0x4100708CUL) /**< \brief (SBMATRIX) Priority B for Slave 1 */
+#define REG_SBMATRIX_PRAS2         (*(RwReg  *)0x41007090UL) /**< \brief (SBMATRIX) Priority A for Slave 2 */
+#define REG_SBMATRIX_PRBS2         (*(RwReg  *)0x41007094UL) /**< \brief (SBMATRIX) Priority B for Slave 2 */
+#define REG_SBMATRIX_PRAS3         (*(RwReg  *)0x41007098UL) /**< \brief (SBMATRIX) Priority A for Slave 3 */
+#define REG_SBMATRIX_PRBS3         (*(RwReg  *)0x4100709CUL) /**< \brief (SBMATRIX) Priority B for Slave 3 */
+#define REG_SBMATRIX_PRAS4         (*(RwReg  *)0x410070A0UL) /**< \brief (SBMATRIX) Priority A for Slave 4 */
+#define REG_SBMATRIX_PRBS4         (*(RwReg  *)0x410070A4UL) /**< \brief (SBMATRIX) Priority B for Slave 4 */
+#define REG_SBMATRIX_PRAS5         (*(RwReg  *)0x410070A8UL) /**< \brief (SBMATRIX) Priority A for Slave 5 */
+#define REG_SBMATRIX_PRBS5         (*(RwReg  *)0x410070ACUL) /**< \brief (SBMATRIX) Priority B for Slave 5 */
+#define REG_SBMATRIX_PRAS6         (*(RwReg  *)0x410070B0UL) /**< \brief (SBMATRIX) Priority A for Slave 6 */
+#define REG_SBMATRIX_PRBS6         (*(RwReg  *)0x410070B4UL) /**< \brief (SBMATRIX) Priority B for Slave 6 */
+#define REG_SBMATRIX_PRAS7         (*(RwReg  *)0x410070B8UL) /**< \brief (SBMATRIX) Priority A for Slave 7 */
+#define REG_SBMATRIX_PRBS7         (*(RwReg  *)0x410070BCUL) /**< \brief (SBMATRIX) Priority B for Slave 7 */
+#define REG_SBMATRIX_PRAS8         (*(RwReg  *)0x410070C0UL) /**< \brief (SBMATRIX) Priority A for Slave 8 */
+#define REG_SBMATRIX_PRBS8         (*(RwReg  *)0x410070C4UL) /**< \brief (SBMATRIX) Priority B for Slave 8 */
+#define REG_SBMATRIX_PRAS9         (*(RwReg  *)0x410070C8UL) /**< \brief (SBMATRIX) Priority A for Slave 9 */
+#define REG_SBMATRIX_PRBS9         (*(RwReg  *)0x410070CCUL) /**< \brief (SBMATRIX) Priority B for Slave 9 */
+#define REG_SBMATRIX_PRAS10        (*(RwReg  *)0x410070D0UL) /**< \brief (SBMATRIX) Priority A for Slave 10 */
+#define REG_SBMATRIX_PRBS10        (*(RwReg  *)0x410070D4UL) /**< \brief (SBMATRIX) Priority B for Slave 10 */
+#define REG_SBMATRIX_PRAS11        (*(RwReg  *)0x410070D8UL) /**< \brief (SBMATRIX) Priority A for Slave 11 */
+#define REG_SBMATRIX_PRBS11        (*(RwReg  *)0x410070DCUL) /**< \brief (SBMATRIX) Priority B for Slave 11 */
+#define REG_SBMATRIX_PRAS12        (*(RwReg  *)0x410070E0UL) /**< \brief (SBMATRIX) Priority A for Slave 12 */
+#define REG_SBMATRIX_PRBS12        (*(RwReg  *)0x410070E4UL) /**< \brief (SBMATRIX) Priority B for Slave 12 */
+#define REG_SBMATRIX_PRAS13        (*(RwReg  *)0x410070E8UL) /**< \brief (SBMATRIX) Priority A for Slave 13 */
+#define REG_SBMATRIX_PRBS13        (*(RwReg  *)0x410070ECUL) /**< \brief (SBMATRIX) Priority B for Slave 13 */
+#define REG_SBMATRIX_PRAS14        (*(RwReg  *)0x410070F0UL) /**< \brief (SBMATRIX) Priority A for Slave 14 */
+#define REG_SBMATRIX_PRBS14        (*(RwReg  *)0x410070F4UL) /**< \brief (SBMATRIX) Priority B for Slave 14 */
+#define REG_SBMATRIX_PRAS15        (*(RwReg  *)0x410070F8UL) /**< \brief (SBMATRIX) Priority A for Slave 15 */
+#define REG_SBMATRIX_PRBS15        (*(RwReg  *)0x410070FCUL) /**< \brief (SBMATRIX) Priority B for Slave 15 */
+#define REG_SBMATRIX_SFR0          (*(RwReg  *)0x41007110UL) /**< \brief (SBMATRIX) Special Function 0 */
+#define REG_SBMATRIX_SFR1          (*(RwReg  *)0x41007114UL) /**< \brief (SBMATRIX) Special Function 1 */
+#define REG_SBMATRIX_SFR2          (*(RwReg  *)0x41007118UL) /**< \brief (SBMATRIX) Special Function 2 */
+#define REG_SBMATRIX_SFR3          (*(RwReg  *)0x4100711CUL) /**< \brief (SBMATRIX) Special Function 3 */
+#define REG_SBMATRIX_SFR4          (*(RwReg  *)0x41007120UL) /**< \brief (SBMATRIX) Special Function 4 */
+#define REG_SBMATRIX_SFR5          (*(RwReg  *)0x41007124UL) /**< \brief (SBMATRIX) Special Function 5 */
+#define REG_SBMATRIX_SFR6          (*(RwReg  *)0x41007128UL) /**< \brief (SBMATRIX) Special Function 6 */
+#define REG_SBMATRIX_SFR7          (*(RwReg  *)0x4100712CUL) /**< \brief (SBMATRIX) Special Function 7 */
+#define REG_SBMATRIX_SFR8          (*(RwReg  *)0x41007130UL) /**< \brief (SBMATRIX) Special Function 8 */
+#define REG_SBMATRIX_SFR9          (*(RwReg  *)0x41007134UL) /**< \brief (SBMATRIX) Special Function 9 */
+#define REG_SBMATRIX_SFR10         (*(RwReg  *)0x41007138UL) /**< \brief (SBMATRIX) Special Function 10 */
+#define REG_SBMATRIX_SFR11         (*(RwReg  *)0x4100713CUL) /**< \brief (SBMATRIX) Special Function 11 */
+#define REG_SBMATRIX_SFR12         (*(RwReg  *)0x41007140UL) /**< \brief (SBMATRIX) Special Function 12 */
+#define REG_SBMATRIX_SFR13         (*(RwReg  *)0x41007144UL) /**< \brief (SBMATRIX) Special Function 13 */
+#define REG_SBMATRIX_SFR14         (*(RwReg  *)0x41007148UL) /**< \brief (SBMATRIX) Special Function 14 */
+#define REG_SBMATRIX_SFR15         (*(RwReg  *)0x4100714CUL) /**< \brief (SBMATRIX) Special Function 15 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SBMATRIX peripheral ========== */
+#define SBMATRIX_DEFINED                    
+/* ========== Instance parameters for SBMATRIX ========== */
+#define SBMATRIX_SLAVE_FLASH        0
+#define SBMATRIX_SLAVE_HPB0         1
+#define SBMATRIX_SLAVE_HPB1         2
+#define SBMATRIX_SLAVE_HPB2         3
+#define SBMATRIX_SLAVE_HMCRAMC0     4
+#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5
+#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6
+#define SBMATRIX_SLAVE_NUM          7
+
+#define SBMATRIX_MASTER_CM0PLUS     0
+#define SBMATRIX_MASTER_DSU         1
+#define SBMATRIX_MASTER_DMAC        2
+#define SBMATRIX_MASTER_NUM         3
+
+#endif /* _SAMD21_SBMATRIX_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom0.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom0.h
new file mode 100644
index 00000000..b7065f8d
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom0.h
@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM0
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM0_INSTANCE_
+#define _SAMD21_SERCOM0_INSTANCE_
+
+/* ========== Register definition for SERCOM0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM0_I2CM_CTRLA     (0x42000800) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (0x42000804) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD      (0x4200080C) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (0x42000814) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (0x42000816) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (0x42000818) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (0x4200081A) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY  (0x4200081C) /**< \brief (SERCOM0) I2CM Syncbusy */
+#define REG_SERCOM0_I2CM_ADDR      (0x42000824) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (0x42000828) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL   (0x42000830) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA     (0x42000800) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (0x42000804) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR  (0x42000814) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (0x42000816) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (0x42000818) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (0x4200081A) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY  (0x4200081C) /**< \brief (SERCOM0) I2CS Syncbusy */
+#define REG_SERCOM0_I2CS_ADDR      (0x42000824) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (0x42000828) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (0x42000800) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (0x42000804) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD       (0x4200080C) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (0x42000814) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (0x42000816) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (0x42000818) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (0x4200081A) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY   (0x4200081C) /**< \brief (SERCOM0) SPI Syncbusy */
+#define REG_SERCOM0_SPI_ADDR       (0x42000824) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (0x42000828) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL    (0x42000830) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA    (0x42000800) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (0x42000804) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD     (0x4200080C) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL     (0x4200080E) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (0x42000814) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (0x42000816) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (0x42000818) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (0x4200081A) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) USART Syncbusy */
+#define REG_SERCOM0_USART_DATA     (0x42000828) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL  (0x42000830) /**< \brief (SERCOM0) USART Debug Control */
+#else
+#define REG_SERCOM0_I2CM_CTRLA     (*(RwReg  *)0x42000800UL) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (*(RwReg  *)0x42000804UL) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD      (*(RwReg  *)0x4200080CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY  (*(RoReg  *)0x4200081CUL) /**< \brief (SERCOM0) I2CM Syncbusy */
+#define REG_SERCOM0_I2CM_ADDR      (*(RwReg  *)0x42000824UL) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL   (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA     (*(RwReg  *)0x42000800UL) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (*(RwReg  *)0x42000804UL) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR  (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY  (*(RoReg  *)0x4200081CUL) /**< \brief (SERCOM0) I2CS Syncbusy */
+#define REG_SERCOM0_I2CS_ADDR      (*(RwReg  *)0x42000824UL) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (*(RwReg  *)0x42000800UL) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (*(RwReg  *)0x42000804UL) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD       (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY   (*(RoReg  *)0x4200081CUL) /**< \brief (SERCOM0) SPI Syncbusy */
+#define REG_SERCOM0_SPI_ADDR       (*(RwReg  *)0x42000824UL) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (*(RwReg  *)0x42000828UL) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL    (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA    (*(RwReg  *)0x42000800UL) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (*(RwReg  *)0x42000804UL) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD     (*(RwReg16*)0x4200080CUL) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL     (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg  *)0x4200081CUL) /**< \brief (SERCOM0) USART Syncbusy */
+#define REG_SERCOM0_USART_DATA     (*(RwReg16*)0x42000828UL) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL  (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM0 peripheral ========== */
+#define SERCOM0_DMAC_ID_RX          1        // Index of DMA RX trigger
+#define SERCOM0_DMAC_ID_TX          2        // Index of DMA TX trigger
+#define SERCOM0_GCLK_ID_CORE        20       // Index of Generic Clock for Core
+#define SERCOM0_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM0_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM0_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom1.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom1.h
new file mode 100644
index 00000000..12500b9e
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom1.h
@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM1
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM1_INSTANCE_
+#define _SAMD21_SERCOM1_INSTANCE_
+
+/* ========== Register definition for SERCOM1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM1_I2CM_CTRLA     (0x42000C00) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (0x42000C04) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD      (0x42000C0C) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (0x42000C14) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (0x42000C16) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (0x42000C18) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (0x42000C1A) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY  (0x42000C1C) /**< \brief (SERCOM1) I2CM Syncbusy */
+#define REG_SERCOM1_I2CM_ADDR      (0x42000C24) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (0x42000C28) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL   (0x42000C30) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA     (0x42000C00) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (0x42000C04) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR  (0x42000C14) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (0x42000C16) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (0x42000C18) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (0x42000C1A) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY  (0x42000C1C) /**< \brief (SERCOM1) I2CS Syncbusy */
+#define REG_SERCOM1_I2CS_ADDR      (0x42000C24) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (0x42000C28) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (0x42000C00) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (0x42000C04) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD       (0x42000C0C) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (0x42000C14) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (0x42000C16) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (0x42000C18) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (0x42000C1A) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY   (0x42000C1C) /**< \brief (SERCOM1) SPI Syncbusy */
+#define REG_SERCOM1_SPI_ADDR       (0x42000C24) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (0x42000C28) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL    (0x42000C30) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA    (0x42000C00) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (0x42000C04) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD     (0x42000C0C) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL     (0x42000C0E) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (0x42000C16) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (0x42000C18) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (0x42000C1A) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) USART Syncbusy */
+#define REG_SERCOM1_USART_DATA     (0x42000C28) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL  (0x42000C30) /**< \brief (SERCOM1) USART Debug Control */
+#else
+#define REG_SERCOM1_I2CM_CTRLA     (*(RwReg  *)0x42000C00UL) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (*(RwReg  *)0x42000C04UL) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD      (*(RwReg  *)0x42000C0CUL) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY  (*(RoReg  *)0x42000C1CUL) /**< \brief (SERCOM1) I2CM Syncbusy */
+#define REG_SERCOM1_I2CM_ADDR      (*(RwReg  *)0x42000C24UL) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL   (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA     (*(RwReg  *)0x42000C00UL) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (*(RwReg  *)0x42000C04UL) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR  (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY  (*(RoReg  *)0x42000C1CUL) /**< \brief (SERCOM1) I2CS Syncbusy */
+#define REG_SERCOM1_I2CS_ADDR      (*(RwReg  *)0x42000C24UL) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (*(RwReg  *)0x42000C00UL) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (*(RwReg  *)0x42000C04UL) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD       (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY   (*(RoReg  *)0x42000C1CUL) /**< \brief (SERCOM1) SPI Syncbusy */
+#define REG_SERCOM1_SPI_ADDR       (*(RwReg  *)0x42000C24UL) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (*(RwReg  *)0x42000C28UL) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL    (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA    (*(RwReg  *)0x42000C00UL) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (*(RwReg  *)0x42000C04UL) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD     (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL     (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg  *)0x42000C1CUL) /**< \brief (SERCOM1) USART Syncbusy */
+#define REG_SERCOM1_USART_DATA     (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL  (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM1 peripheral ========== */
+#define SERCOM1_DMAC_ID_RX          3        // Index of DMA RX trigger
+#define SERCOM1_DMAC_ID_TX          4        // Index of DMA TX trigger
+#define SERCOM1_GCLK_ID_CORE        21       // Index of Generic Clock for Core
+#define SERCOM1_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM1_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM1_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom2.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom2.h
new file mode 100644
index 00000000..e1816e24
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom2.h
@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM2
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM2_INSTANCE_
+#define _SAMD21_SERCOM2_INSTANCE_
+
+/* ========== Register definition for SERCOM2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM2_I2CM_CTRLA     (0x42001000) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (0x42001004) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD      (0x4200100C) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (0x42001014) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (0x42001016) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (0x42001018) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (0x4200101A) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY  (0x4200101C) /**< \brief (SERCOM2) I2CM Syncbusy */
+#define REG_SERCOM2_I2CM_ADDR      (0x42001024) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (0x42001028) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL   (0x42001030) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA     (0x42001000) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (0x42001004) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR  (0x42001014) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (0x42001016) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (0x42001018) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (0x4200101A) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY  (0x4200101C) /**< \brief (SERCOM2) I2CS Syncbusy */
+#define REG_SERCOM2_I2CS_ADDR      (0x42001024) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (0x42001028) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (0x42001000) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (0x42001004) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD       (0x4200100C) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (0x42001014) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (0x42001016) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (0x42001018) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (0x4200101A) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY   (0x4200101C) /**< \brief (SERCOM2) SPI Syncbusy */
+#define REG_SERCOM2_SPI_ADDR       (0x42001024) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (0x42001028) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL    (0x42001030) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA    (0x42001000) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (0x42001004) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD     (0x4200100C) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL     (0x4200100E) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (0x42001014) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (0x42001016) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (0x42001018) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (0x4200101A) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) USART Syncbusy */
+#define REG_SERCOM2_USART_DATA     (0x42001028) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL  (0x42001030) /**< \brief (SERCOM2) USART Debug Control */
+#else
+#define REG_SERCOM2_I2CM_CTRLA     (*(RwReg  *)0x42001000UL) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (*(RwReg  *)0x42001004UL) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD      (*(RwReg  *)0x4200100CUL) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY  (*(RoReg  *)0x4200101CUL) /**< \brief (SERCOM2) I2CM Syncbusy */
+#define REG_SERCOM2_I2CM_ADDR      (*(RwReg  *)0x42001024UL) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL   (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA     (*(RwReg  *)0x42001000UL) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (*(RwReg  *)0x42001004UL) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR  (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY  (*(RoReg  *)0x4200101CUL) /**< \brief (SERCOM2) I2CS Syncbusy */
+#define REG_SERCOM2_I2CS_ADDR      (*(RwReg  *)0x42001024UL) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (*(RwReg  *)0x42001000UL) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (*(RwReg  *)0x42001004UL) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD       (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY   (*(RoReg  *)0x4200101CUL) /**< \brief (SERCOM2) SPI Syncbusy */
+#define REG_SERCOM2_SPI_ADDR       (*(RwReg  *)0x42001024UL) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (*(RwReg  *)0x42001028UL) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL    (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA    (*(RwReg  *)0x42001000UL) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (*(RwReg  *)0x42001004UL) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD     (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL     (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg  *)0x4200101CUL) /**< \brief (SERCOM2) USART Syncbusy */
+#define REG_SERCOM2_USART_DATA     (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL  (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM2 peripheral ========== */
+#define SERCOM2_DMAC_ID_RX          5        // Index of DMA RX trigger
+#define SERCOM2_DMAC_ID_TX          6        // Index of DMA TX trigger
+#define SERCOM2_GCLK_ID_CORE        22       // Index of Generic Clock for Core
+#define SERCOM2_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM2_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM2_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom3.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom3.h
new file mode 100644
index 00000000..ad4d85d3
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom3.h
@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM3
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM3_INSTANCE_
+#define _SAMD21_SERCOM3_INSTANCE_
+
+/* ========== Register definition for SERCOM3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM3_I2CM_CTRLA     (0x42001400) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (0x42001404) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD      (0x4200140C) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (0x42001414) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (0x42001416) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (0x42001418) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (0x4200141A) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY  (0x4200141C) /**< \brief (SERCOM3) I2CM Syncbusy */
+#define REG_SERCOM3_I2CM_ADDR      (0x42001424) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (0x42001428) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL   (0x42001430) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA     (0x42001400) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (0x42001404) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR  (0x42001414) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (0x42001416) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (0x42001418) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (0x4200141A) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY  (0x4200141C) /**< \brief (SERCOM3) I2CS Syncbusy */
+#define REG_SERCOM3_I2CS_ADDR      (0x42001424) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (0x42001428) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (0x42001400) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (0x42001404) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD       (0x4200140C) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (0x42001414) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (0x42001416) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (0x42001418) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (0x4200141A) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY   (0x4200141C) /**< \brief (SERCOM3) SPI Syncbusy */
+#define REG_SERCOM3_SPI_ADDR       (0x42001424) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (0x42001428) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL    (0x42001430) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA    (0x42001400) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (0x42001404) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD     (0x4200140C) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL     (0x4200140E) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (0x42001414) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (0x42001416) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (0x42001418) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (0x4200141A) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) USART Syncbusy */
+#define REG_SERCOM3_USART_DATA     (0x42001428) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL  (0x42001430) /**< \brief (SERCOM3) USART Debug Control */
+#else
+#define REG_SERCOM3_I2CM_CTRLA     (*(RwReg  *)0x42001400UL) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (*(RwReg  *)0x42001404UL) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD      (*(RwReg  *)0x4200140CUL) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY  (*(RoReg  *)0x4200141CUL) /**< \brief (SERCOM3) I2CM Syncbusy */
+#define REG_SERCOM3_I2CM_ADDR      (*(RwReg  *)0x42001424UL) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL   (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA     (*(RwReg  *)0x42001400UL) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (*(RwReg  *)0x42001404UL) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR  (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY  (*(RoReg  *)0x4200141CUL) /**< \brief (SERCOM3) I2CS Syncbusy */
+#define REG_SERCOM3_I2CS_ADDR      (*(RwReg  *)0x42001424UL) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (*(RwReg  *)0x42001400UL) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (*(RwReg  *)0x42001404UL) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD       (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY   (*(RoReg  *)0x4200141CUL) /**< \brief (SERCOM3) SPI Syncbusy */
+#define REG_SERCOM3_SPI_ADDR       (*(RwReg  *)0x42001424UL) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (*(RwReg  *)0x42001428UL) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL    (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA    (*(RwReg  *)0x42001400UL) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (*(RwReg  *)0x42001404UL) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD     (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL     (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg  *)0x4200141CUL) /**< \brief (SERCOM3) USART Syncbusy */
+#define REG_SERCOM3_USART_DATA     (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL  (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM3 peripheral ========== */
+#define SERCOM3_DMAC_ID_RX          7        // Index of DMA RX trigger
+#define SERCOM3_DMAC_ID_TX          8        // Index of DMA TX trigger
+#define SERCOM3_GCLK_ID_CORE        23       // Index of Generic Clock for Core
+#define SERCOM3_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM3_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM3_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom4.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom4.h
new file mode 100644
index 00000000..b51c4626
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom4.h
@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM4
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM4_INSTANCE_
+#define _SAMD21_SERCOM4_INSTANCE_
+
+/* ========== Register definition for SERCOM4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM4_I2CM_CTRLA     (0x42001800) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (0x42001804) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD      (0x4200180C) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (0x42001814) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (0x42001816) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (0x42001818) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (0x4200181A) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY  (0x4200181C) /**< \brief (SERCOM4) I2CM Syncbusy */
+#define REG_SERCOM4_I2CM_ADDR      (0x42001824) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (0x42001828) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL   (0x42001830) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA     (0x42001800) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (0x42001804) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR  (0x42001814) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (0x42001816) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (0x42001818) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (0x4200181A) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY  (0x4200181C) /**< \brief (SERCOM4) I2CS Syncbusy */
+#define REG_SERCOM4_I2CS_ADDR      (0x42001824) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (0x42001828) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (0x42001800) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (0x42001804) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD       (0x4200180C) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (0x42001814) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (0x42001816) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (0x42001818) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (0x4200181A) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY   (0x4200181C) /**< \brief (SERCOM4) SPI Syncbusy */
+#define REG_SERCOM4_SPI_ADDR       (0x42001824) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (0x42001828) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL    (0x42001830) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA    (0x42001800) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (0x42001804) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD     (0x4200180C) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL     (0x4200180E) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (0x42001814) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (0x42001816) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (0x42001818) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (0x4200181A) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) USART Syncbusy */
+#define REG_SERCOM4_USART_DATA     (0x42001828) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL  (0x42001830) /**< \brief (SERCOM4) USART Debug Control */
+#else
+#define REG_SERCOM4_I2CM_CTRLA     (*(RwReg  *)0x42001800UL) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (*(RwReg  *)0x42001804UL) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD      (*(RwReg  *)0x4200180CUL) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY  (*(RoReg  *)0x4200181CUL) /**< \brief (SERCOM4) I2CM Syncbusy */
+#define REG_SERCOM4_I2CM_ADDR      (*(RwReg  *)0x42001824UL) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL   (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA     (*(RwReg  *)0x42001800UL) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (*(RwReg  *)0x42001804UL) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR  (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY  (*(RoReg  *)0x4200181CUL) /**< \brief (SERCOM4) I2CS Syncbusy */
+#define REG_SERCOM4_I2CS_ADDR      (*(RwReg  *)0x42001824UL) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (*(RwReg  *)0x42001800UL) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (*(RwReg  *)0x42001804UL) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD       (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY   (*(RoReg  *)0x4200181CUL) /**< \brief (SERCOM4) SPI Syncbusy */
+#define REG_SERCOM4_SPI_ADDR       (*(RwReg  *)0x42001824UL) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (*(RwReg  *)0x42001828UL) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL    (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA    (*(RwReg  *)0x42001800UL) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (*(RwReg  *)0x42001804UL) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD     (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL     (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg  *)0x4200181CUL) /**< \brief (SERCOM4) USART Syncbusy */
+#define REG_SERCOM4_USART_DATA     (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL  (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM4 peripheral ========== */
+#define SERCOM4_DMAC_ID_RX          9        // Index of DMA RX trigger
+#define SERCOM4_DMAC_ID_TX          10       // Index of DMA TX trigger
+#define SERCOM4_GCLK_ID_CORE        24       // Index of Generic Clock for Core
+#define SERCOM4_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM4_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM4_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom5.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom5.h
new file mode 100644
index 00000000..70ffc3be
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/sercom5.h
@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM5
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM5_INSTANCE_
+#define _SAMD21_SERCOM5_INSTANCE_
+
+/* ========== Register definition for SERCOM5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM5_I2CM_CTRLA     (0x42001C00) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (0x42001C04) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD      (0x42001C0C) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (0x42001C14) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (0x42001C16) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (0x42001C18) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (0x42001C1A) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY  (0x42001C1C) /**< \brief (SERCOM5) I2CM Syncbusy */
+#define REG_SERCOM5_I2CM_ADDR      (0x42001C24) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (0x42001C28) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL   (0x42001C30) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA     (0x42001C00) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (0x42001C04) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR  (0x42001C14) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (0x42001C16) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (0x42001C18) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (0x42001C1A) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY  (0x42001C1C) /**< \brief (SERCOM5) I2CS Syncbusy */
+#define REG_SERCOM5_I2CS_ADDR      (0x42001C24) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (0x42001C28) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (0x42001C00) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (0x42001C04) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD       (0x42001C0C) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (0x42001C14) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (0x42001C16) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (0x42001C18) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (0x42001C1A) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY   (0x42001C1C) /**< \brief (SERCOM5) SPI Syncbusy */
+#define REG_SERCOM5_SPI_ADDR       (0x42001C24) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (0x42001C28) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL    (0x42001C30) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA    (0x42001C00) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (0x42001C04) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD     (0x42001C0C) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL     (0x42001C0E) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (0x42001C14) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (0x42001C16) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (0x42001C18) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (0x42001C1A) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) USART Syncbusy */
+#define REG_SERCOM5_USART_DATA     (0x42001C28) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL  (0x42001C30) /**< \brief (SERCOM5) USART Debug Control */
+#else
+#define REG_SERCOM5_I2CM_CTRLA     (*(RwReg  *)0x42001C00UL) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (*(RwReg  *)0x42001C04UL) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD      (*(RwReg  *)0x42001C0CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY  (*(RoReg  *)0x42001C1CUL) /**< \brief (SERCOM5) I2CM Syncbusy */
+#define REG_SERCOM5_I2CM_ADDR      (*(RwReg  *)0x42001C24UL) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL   (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA     (*(RwReg  *)0x42001C00UL) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (*(RwReg  *)0x42001C04UL) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR  (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY  (*(RoReg  *)0x42001C1CUL) /**< \brief (SERCOM5) I2CS Syncbusy */
+#define REG_SERCOM5_I2CS_ADDR      (*(RwReg  *)0x42001C24UL) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (*(RwReg  *)0x42001C00UL) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (*(RwReg  *)0x42001C04UL) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD       (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY   (*(RoReg  *)0x42001C1CUL) /**< \brief (SERCOM5) SPI Syncbusy */
+#define REG_SERCOM5_SPI_ADDR       (*(RwReg  *)0x42001C24UL) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (*(RwReg  *)0x42001C28UL) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL    (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA    (*(RwReg  *)0x42001C00UL) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (*(RwReg  *)0x42001C04UL) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD     (*(RwReg16*)0x42001C0CUL) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL     (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg  *)0x42001C1CUL) /**< \brief (SERCOM5) USART Syncbusy */
+#define REG_SERCOM5_USART_DATA     (*(RwReg16*)0x42001C28UL) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL  (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM5 peripheral ========== */
+#define SERCOM5_DMAC_ID_RX          11       // Index of DMA RX trigger
+#define SERCOM5_DMAC_ID_TX          12       // Index of DMA TX trigger
+#define SERCOM5_GCLK_ID_CORE        25       // Index of Generic Clock for Core
+#define SERCOM5_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
+#define SERCOM5_INT_MSB             6       
+
+#endif /* _SAMD21_SERCOM5_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/sysctrl.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/sysctrl.h
new file mode 100644
index 00000000..fe31e772
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/sysctrl.h
@@ -0,0 +1,106 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SYSCTRL
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_INSTANCE_
+#define _SAMD21_SYSCTRL_INSTANCE_
+
+/* ========== Register definition for SYSCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SYSCTRL_INTENCLR       (0x40000800) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET       (0x40000804) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG        (0x40000808) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR         (0x4000080C) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC           (0x40000810) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K        (0x40000814) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K         (0x40000818) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K      (0x4000081C) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M          (0x40000820) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL       (0x40000824) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL        (0x40000828) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL        (0x4000082C) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC       (0x40000830) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33          (0x40000834) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG           (0x4000083C) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF           (0x40000840) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA      (0x40000844) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO      (0x40000848) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB      (0x4000084C) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS     (0x40000850) /**< \brief (SYSCTRL) DPLL Status */
+#else
+#define REG_SYSCTRL_INTENCLR       (*(RwReg  *)0x40000800UL) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET       (*(RwReg  *)0x40000804UL) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG        (*(RwReg  *)0x40000808UL) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR         (*(RoReg  *)0x4000080CUL) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC           (*(RwReg16*)0x40000810UL) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K        (*(RwReg16*)0x40000814UL) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K         (*(RwReg  *)0x40000818UL) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K      (*(RwReg8 *)0x4000081CUL) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M          (*(RwReg  *)0x40000820UL) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL       (*(RwReg16*)0x40000824UL) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL        (*(RwReg  *)0x40000828UL) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL        (*(RwReg  *)0x4000082CUL) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC       (*(RwReg8 *)0x40000830UL) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33          (*(RwReg  *)0x40000834UL) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG           (*(RwReg16*)0x4000083CUL) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF           (*(RwReg  *)0x40000840UL) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA      (*(RwReg8 *)0x40000844UL) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO      (*(RwReg  *)0x40000848UL) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB      (*(RwReg  *)0x4000084CUL) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS     (*(RoReg8 *)0x40000850UL) /**< \brief (SYSCTRL) DPLL Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SYSCTRL peripheral ========== */
+#define SYSCTRL_BGAP_CALIB_MSB      11      
+#define SYSCTRL_BOD33_CALIB_MSB     5       
+#define SYSCTRL_DFLL48M_COARSE_MSB  5       
+#define SYSCTRL_DFLL48M_FINE_MSB    9       
+#define SYSCTRL_GCLK_ID_DFLL48      0        // Index of Generic Clock for DFLL48
+#define SYSCTRL_GCLK_ID_FDPLL       1        // Index of Generic Clock for DPLL
+#define SYSCTRL_GCLK_ID_FDPLL32K    2        // Index of Generic Clock for DPLL 32K
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6       
+#define SYSCTRL_POR33_ENTEST_MSB    1       
+#define SYSCTRL_SYSTEM_CLOCK        1000000  // Initial system clock frequency
+#define SYSCTRL_ULPVREF_DIVLEV_MSB  3       
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1       
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2       
+#define SYSCTRL_VREF_CONTROL_MSB    48      
+#define SYSCTRL_VREF_STATUS_MSB     7       
+#define SYSCTRL_VREG_LEVEL_MSB      2       
+#define SYSCTRL_BOD12_VERSION       0x111   
+#define SYSCTRL_BOD33_VERSION       0x111   
+#define SYSCTRL_DFLL48M_VERSION     0x301   
+#define SYSCTRL_FDPLL_VERSION       0x111   
+#define SYSCTRL_OSCULP32K_VERSION   0x111   
+#define SYSCTRL_OSC8M_VERSION       0x120   
+#define SYSCTRL_OSC32K_VERSION      0x1101  
+#define SYSCTRL_VREF_VERSION        0x200   
+#define SYSCTRL_VREG_VERSION        0x201   
+#define SYSCTRL_XOSC_VERSION        0x1111  
+#define SYSCTRL_XOSC32K_VERSION     0x1111  
+
+#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/tc3.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc3.h
new file mode 100644
index 00000000..b7acb689
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc3.h
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC3
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC3_INSTANCE_
+#define _SAMD21_TC3_INSTANCE_
+
+/* ========== Register definition for TC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC3_CTRLA              (0x42002C00) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ            (0x42002C02) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR           (0x42002C04) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (0x42002C05) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC              (0x42002C06) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (0x42002C08) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL             (0x42002C0A) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (0x42002C0C) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (0x42002C0D) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (0x42002C0E) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (0x42002C0F) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT      (0x42002C10) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0        (0x42002C18) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1        (0x42002C1A) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT      (0x42002C10) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0        (0x42002C18) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1        (0x42002C1C) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT       (0x42002C10) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER         (0x42002C14) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0         (0x42002C18) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1         (0x42002C19) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC3_CTRLA              (*(RwReg16*)0x42002C00UL) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ            (*(RwReg16*)0x42002C02UL) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR           (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC              (*(RwReg8 *)0x42002C06UL) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL             (*(RwReg16*)0x42002C0AUL) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (*(RwReg8 *)0x42002C0EUL) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (*(RoReg8 *)0x42002C0FUL) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT      (*(RwReg16*)0x42002C10UL) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0        (*(RwReg16*)0x42002C18UL) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1        (*(RwReg16*)0x42002C1AUL) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT      (*(RwReg  *)0x42002C10UL) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0        (*(RwReg  *)0x42002C18UL) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1        (*(RwReg  *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT       (*(RwReg8 *)0x42002C10UL) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER         (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0         (*(RwReg8 *)0x42002C18UL) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1         (*(RwReg8 *)0x42002C19UL) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC3 peripheral ========== */
+#define TC3_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC3_CC16_NUM                2        // Number of 16-bit Counters
+#define TC3_CC32_NUM                2        // Number of 32-bit Counters
+#define TC3_DITHERING_EXT           0        // Dithering feature implemented
+#define TC3_DMAC_ID_MC_0            25
+#define TC3_DMAC_ID_MC_1            26
+#define TC3_DMAC_ID_MC_LSB          25
+#define TC3_DMAC_ID_MC_MSB          26
+#define TC3_DMAC_ID_MC_SIZE         2
+#define TC3_DMAC_ID_OVF             24       // Indexes of DMA Overflow trigger
+#define TC3_GCLK_ID                 27       // Index of Generic Clock
+#define TC3_MASTER                  0       
+#define TC3_OW_NUM                  2        // Number of Output Waveforms
+#define TC3_PERIOD_EXT              0        // Period feature implemented
+#define TC3_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC3_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/tc4.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc4.h
new file mode 100644
index 00000000..83aeea40
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc4.h
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC4
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC4_INSTANCE_
+#define _SAMD21_TC4_INSTANCE_
+
+/* ========== Register definition for TC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC4_CTRLA              (0x42003000) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ            (0x42003002) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR           (0x42003004) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (0x42003005) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC              (0x42003006) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (0x42003008) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL             (0x4200300A) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (0x4200300C) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (0x4200300D) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (0x4200300E) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (0x4200300F) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT      (0x42003010) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0        (0x42003018) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1        (0x4200301A) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT      (0x42003010) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0        (0x42003018) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1        (0x4200301C) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT       (0x42003010) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER         (0x42003014) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0         (0x42003018) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1         (0x42003019) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC4_CTRLA              (*(RwReg16*)0x42003000UL) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ            (*(RwReg16*)0x42003002UL) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR           (*(RwReg8 *)0x42003004UL) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (*(RwReg8 *)0x42003005UL) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC              (*(RwReg8 *)0x42003006UL) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (*(RwReg8 *)0x42003008UL) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL             (*(RwReg16*)0x4200300AUL) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (*(RwReg8 *)0x4200300CUL) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (*(RwReg8 *)0x4200300DUL) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (*(RwReg8 *)0x4200300EUL) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (*(RoReg8 *)0x4200300FUL) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT      (*(RwReg16*)0x42003010UL) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0        (*(RwReg16*)0x42003018UL) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1        (*(RwReg16*)0x4200301AUL) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT      (*(RwReg  *)0x42003010UL) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0        (*(RwReg  *)0x42003018UL) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1        (*(RwReg  *)0x4200301CUL) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT       (*(RwReg8 *)0x42003010UL) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER         (*(RwReg8 *)0x42003014UL) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0         (*(RwReg8 *)0x42003018UL) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1         (*(RwReg8 *)0x42003019UL) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC4 peripheral ========== */
+#define TC4_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC4_CC16_NUM                2        // Number of 16-bit Counters
+#define TC4_CC32_NUM                2        // Number of 32-bit Counters
+#define TC4_DITHERING_EXT           0        // Dithering feature implemented
+#define TC4_DMAC_ID_MC_0            28
+#define TC4_DMAC_ID_MC_1            29
+#define TC4_DMAC_ID_MC_LSB          28
+#define TC4_DMAC_ID_MC_MSB          29
+#define TC4_DMAC_ID_MC_SIZE         2
+#define TC4_DMAC_ID_OVF             27       // Indexes of DMA Overflow trigger
+#define TC4_GCLK_ID                 28       // Index of Generic Clock
+#define TC4_MASTER                  1       
+#define TC4_OW_NUM                  2        // Number of Output Waveforms
+#define TC4_PERIOD_EXT              0        // Period feature implemented
+#define TC4_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC4_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/tc5.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc5.h
new file mode 100644
index 00000000..0a364f37
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc5.h
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC5
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC5_INSTANCE_
+#define _SAMD21_TC5_INSTANCE_
+
+/* ========== Register definition for TC5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC5_CTRLA              (0x42003400) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ            (0x42003402) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR           (0x42003404) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (0x42003405) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC              (0x42003406) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (0x42003408) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL             (0x4200340A) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (0x4200340C) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (0x4200340D) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (0x4200340E) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (0x4200340F) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT      (0x42003410) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0        (0x42003418) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1        (0x4200341A) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT      (0x42003410) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0        (0x42003418) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1        (0x4200341C) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT       (0x42003410) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER         (0x42003414) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0         (0x42003418) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1         (0x42003419) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC5_CTRLA              (*(RwReg16*)0x42003400UL) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ            (*(RwReg16*)0x42003402UL) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR           (*(RwReg8 *)0x42003404UL) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (*(RwReg8 *)0x42003405UL) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC              (*(RwReg8 *)0x42003406UL) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (*(RwReg8 *)0x42003408UL) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL             (*(RwReg16*)0x4200340AUL) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (*(RwReg8 *)0x4200340CUL) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (*(RwReg8 *)0x4200340DUL) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (*(RwReg8 *)0x4200340EUL) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (*(RoReg8 *)0x4200340FUL) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT      (*(RwReg16*)0x42003410UL) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0        (*(RwReg16*)0x42003418UL) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1        (*(RwReg16*)0x4200341AUL) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT      (*(RwReg  *)0x42003410UL) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0        (*(RwReg  *)0x42003418UL) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1        (*(RwReg  *)0x4200341CUL) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT       (*(RwReg8 *)0x42003410UL) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER         (*(RwReg8 *)0x42003414UL) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0         (*(RwReg8 *)0x42003418UL) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1         (*(RwReg8 *)0x42003419UL) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC5 peripheral ========== */
+#define TC5_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC5_CC16_NUM                2        // Number of 16-bit Counters
+#define TC5_CC32_NUM                2        // Number of 32-bit Counters
+#define TC5_DITHERING_EXT           0        // Dithering feature implemented
+#define TC5_DMAC_ID_MC_0            31
+#define TC5_DMAC_ID_MC_1            32
+#define TC5_DMAC_ID_MC_LSB          31
+#define TC5_DMAC_ID_MC_MSB          32
+#define TC5_DMAC_ID_MC_SIZE         2
+#define TC5_DMAC_ID_OVF             30       // Indexes of DMA Overflow trigger
+#define TC5_GCLK_ID                 28       // Index of Generic Clock
+#define TC5_MASTER                  0       
+#define TC5_OW_NUM                  2        // Number of Output Waveforms
+#define TC5_PERIOD_EXT              0        // Period feature implemented
+#define TC5_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC5_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/tc6.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc6.h
new file mode 100644
index 00000000..debdf847
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc6.h
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC6
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC6_INSTANCE_
+#define _SAMD21_TC6_INSTANCE_
+
+/* ========== Register definition for TC6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC6_CTRLA              (0x42003800) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ            (0x42003802) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR           (0x42003804) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (0x42003805) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC              (0x42003806) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (0x42003808) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL             (0x4200380A) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (0x4200380C) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (0x4200380D) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (0x4200380E) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (0x4200380F) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT      (0x42003810) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0        (0x42003818) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1        (0x4200381A) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT      (0x42003810) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0        (0x42003818) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1        (0x4200381C) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT       (0x42003810) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER         (0x42003814) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0         (0x42003818) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1         (0x42003819) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC6_CTRLA              (*(RwReg16*)0x42003800UL) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ            (*(RwReg16*)0x42003802UL) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR           (*(RwReg8 *)0x42003804UL) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (*(RwReg8 *)0x42003805UL) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC              (*(RwReg8 *)0x42003806UL) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (*(RwReg8 *)0x42003808UL) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL             (*(RwReg16*)0x4200380AUL) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (*(RwReg8 *)0x4200380CUL) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (*(RwReg8 *)0x4200380DUL) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (*(RwReg8 *)0x4200380EUL) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (*(RoReg8 *)0x4200380FUL) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT      (*(RwReg16*)0x42003810UL) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0        (*(RwReg16*)0x42003818UL) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1        (*(RwReg16*)0x4200381AUL) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT      (*(RwReg  *)0x42003810UL) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0        (*(RwReg  *)0x42003818UL) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1        (*(RwReg  *)0x4200381CUL) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT       (*(RwReg8 *)0x42003810UL) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER         (*(RwReg8 *)0x42003814UL) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0         (*(RwReg8 *)0x42003818UL) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1         (*(RwReg8 *)0x42003819UL) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC6 peripheral ========== */
+#define TC6_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC6_CC16_NUM                2        // Number of 16-bit Counters
+#define TC6_CC32_NUM                2        // Number of 32-bit Counters
+#define TC6_DITHERING_EXT           0        // Dithering feature implemented
+#define TC6_DMAC_ID_MC_0            34
+#define TC6_DMAC_ID_MC_1            35
+#define TC6_DMAC_ID_MC_LSB          34
+#define TC6_DMAC_ID_MC_MSB          35
+#define TC6_DMAC_ID_MC_SIZE         2
+#define TC6_DMAC_ID_OVF             33       // Indexes of DMA Overflow trigger
+#define TC6_GCLK_ID                 29       // Index of Generic Clock
+#define TC6_MASTER                  1       
+#define TC6_OW_NUM                  2        // Number of Output Waveforms
+#define TC6_PERIOD_EXT              0        // Period feature implemented
+#define TC6_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC6_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/tc7.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc7.h
new file mode 100644
index 00000000..299f6ab7
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/tc7.h
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC7
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC7_INSTANCE_
+#define _SAMD21_TC7_INSTANCE_
+
+/* ========== Register definition for TC7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC7_CTRLA              (0x42003C00) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ            (0x42003C02) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR           (0x42003C04) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (0x42003C05) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC              (0x42003C06) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (0x42003C08) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL             (0x42003C0A) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (0x42003C0C) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (0x42003C0D) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (0x42003C0E) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (0x42003C0F) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT      (0x42003C10) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0        (0x42003C18) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1        (0x42003C1A) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT      (0x42003C10) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0        (0x42003C18) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1        (0x42003C1C) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT       (0x42003C10) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER         (0x42003C14) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0         (0x42003C18) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1         (0x42003C19) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC7_CTRLA              (*(RwReg16*)0x42003C00UL) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ            (*(RwReg16*)0x42003C02UL) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR           (*(RwReg8 *)0x42003C04UL) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (*(RwReg8 *)0x42003C05UL) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC              (*(RwReg8 *)0x42003C06UL) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (*(RwReg8 *)0x42003C08UL) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL             (*(RwReg16*)0x42003C0AUL) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (*(RwReg8 *)0x42003C0CUL) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (*(RwReg8 *)0x42003C0DUL) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (*(RwReg8 *)0x42003C0EUL) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (*(RoReg8 *)0x42003C0FUL) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT      (*(RwReg16*)0x42003C10UL) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0        (*(RwReg16*)0x42003C18UL) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1        (*(RwReg16*)0x42003C1AUL) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT      (*(RwReg  *)0x42003C10UL) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0        (*(RwReg  *)0x42003C18UL) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1        (*(RwReg  *)0x42003C1CUL) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT       (*(RwReg8 *)0x42003C10UL) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER         (*(RwReg8 *)0x42003C14UL) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0         (*(RwReg8 *)0x42003C18UL) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1         (*(RwReg8 *)0x42003C19UL) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC7 peripheral ========== */
+#define TC7_CC8_NUM                 2        // Number of 8-bit Counters
+#define TC7_CC16_NUM                2        // Number of 16-bit Counters
+#define TC7_CC32_NUM                2        // Number of 32-bit Counters
+#define TC7_DITHERING_EXT           0        // Dithering feature implemented
+#define TC7_DMAC_ID_MC_0            37
+#define TC7_DMAC_ID_MC_1            38
+#define TC7_DMAC_ID_MC_LSB          37
+#define TC7_DMAC_ID_MC_MSB          38
+#define TC7_DMAC_ID_MC_SIZE         2
+#define TC7_DMAC_ID_OVF             36       // Indexes of DMA Overflow trigger
+#define TC7_GCLK_ID                 29       // Index of Generic Clock
+#define TC7_MASTER                  0       
+#define TC7_OW_NUM                  2        // Number of Output Waveforms
+#define TC7_PERIOD_EXT              0        // Period feature implemented
+#define TC7_SHADOW_EXT              0        // Shadow feature implemented
+
+#endif /* _SAMD21_TC7_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/tcc0.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/tcc0.h
new file mode 100644
index 00000000..451eaecf
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/tcc0.h
@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC0
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC0_INSTANCE_
+#define _SAMD21_TCC0_INSTANCE_
+
+/* ========== Register definition for TCC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC0_CTRLA             (0x42002000) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR          (0x42002004) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET          (0x42002005) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY          (0x42002008) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA            (0x4200200C) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB            (0x42002010) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL           (0x42002014) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL           (0x42002018) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL           (0x4200201E) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL            (0x42002020) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR          (0x42002024) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET          (0x42002028) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG           (0x4200202C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS            (0x42002030) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT             (0x42002034) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT              (0x42002038) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE              (0x4200203C) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER               (0x42002040) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0               (0x42002044) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1               (0x42002048) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2               (0x4200204C) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3               (0x42002050) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB             (0x42002064) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB             (0x42002068) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB              (0x4200206C) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0              (0x42002070) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1              (0x42002074) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2              (0x42002078) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3              (0x4200207C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#else
+#define REG_TCC0_CTRLA             (*(RwReg  *)0x42002000UL) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR          (*(RwReg8 *)0x42002004UL) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET          (*(RwReg8 *)0x42002005UL) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY          (*(RoReg  *)0x42002008UL) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA            (*(RwReg  *)0x4200200CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB            (*(RwReg  *)0x42002010UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL           (*(RwReg  *)0x42002014UL) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL           (*(RwReg  *)0x42002018UL) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL           (*(RwReg8 *)0x4200201EUL) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL            (*(RwReg  *)0x42002020UL) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR          (*(RwReg  *)0x42002024UL) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET          (*(RwReg  *)0x42002028UL) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG           (*(RwReg  *)0x4200202CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS            (*(RwReg  *)0x42002030UL) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT             (*(RwReg  *)0x42002034UL) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT              (*(RwReg16*)0x42002038UL) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE              (*(RwReg  *)0x4200203CUL) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER               (*(RwReg  *)0x42002040UL) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0               (*(RwReg  *)0x42002044UL) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1               (*(RwReg  *)0x42002048UL) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2               (*(RwReg  *)0x4200204CUL) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3               (*(RwReg  *)0x42002050UL) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB             (*(RwReg16*)0x42002064UL) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB             (*(RwReg  *)0x42002068UL) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB              (*(RwReg  *)0x4200206CUL) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0              (*(RwReg  *)0x42002070UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1              (*(RwReg  *)0x42002074UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2              (*(RwReg  *)0x42002078UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3              (*(RwReg  *)0x4200207CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC0 peripheral ========== */
+#define TCC0_CC_NUM                 4        // Number of Compare/Capture units
+#define TCC0_DITHERING              1        // Dithering feature implemented
+#define TCC0_DMAC_ID_MC_0           14
+#define TCC0_DMAC_ID_MC_1           15
+#define TCC0_DMAC_ID_MC_2           16
+#define TCC0_DMAC_ID_MC_3           17
+#define TCC0_DMAC_ID_MC_LSB         14
+#define TCC0_DMAC_ID_MC_MSB         17
+#define TCC0_DMAC_ID_MC_SIZE        4
+#define TCC0_DMAC_ID_OVF            13       // DMA overflow/underflow/retrigger trigger
+#define TCC0_DTI                    1        // Dead-Time-Insertion feature implemented
+#define TCC0_EXT                    31       // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
+#define TCC0_GCLK_ID                26       // Index of Generic Clock
+#define TCC0_OTMX                   1        // Output Matrix feature implemented
+#define TCC0_OW_NUM                 8        // Number of Output Waveforms
+#define TCC0_PG                     1        // Pattern Generation feature implemented
+#define TCC0_SIZE                   24      
+#define TCC0_SWAP                   1        // DTI outputs swap feature implemented
+#define TCC0_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC0_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/tcc1.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/tcc1.h
new file mode 100644
index 00000000..64dc3dbd
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/tcc1.h
@@ -0,0 +1,104 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC1
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC1_INSTANCE_
+#define _SAMD21_TCC1_INSTANCE_
+
+/* ========== Register definition for TCC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC1_CTRLA             (0x42002400) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR          (0x42002404) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET          (0x42002405) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY          (0x42002408) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA            (0x4200240C) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB            (0x42002410) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_DRVCTRL           (0x42002418) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL           (0x4200241E) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL            (0x42002420) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR          (0x42002424) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET          (0x42002428) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG           (0x4200242C) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS            (0x42002430) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT             (0x42002434) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT              (0x42002438) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE              (0x4200243C) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER               (0x42002440) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0               (0x42002444) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1               (0x42002448) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB             (0x42002464) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB             (0x42002468) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB              (0x4200246C) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0              (0x42002470) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1              (0x42002474) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC1_CTRLA             (*(RwReg  *)0x42002400UL) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR          (*(RwReg8 *)0x42002404UL) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET          (*(RwReg8 *)0x42002405UL) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY          (*(RoReg  *)0x42002408UL) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA            (*(RwReg  *)0x4200240CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB            (*(RwReg  *)0x42002410UL) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_DRVCTRL           (*(RwReg  *)0x42002418UL) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL           (*(RwReg8 *)0x4200241EUL) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL            (*(RwReg  *)0x42002420UL) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR          (*(RwReg  *)0x42002424UL) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET          (*(RwReg  *)0x42002428UL) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG           (*(RwReg  *)0x4200242CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS            (*(RwReg  *)0x42002430UL) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT             (*(RwReg  *)0x42002434UL) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT              (*(RwReg16*)0x42002438UL) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE              (*(RwReg  *)0x4200243CUL) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER               (*(RwReg  *)0x42002440UL) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0               (*(RwReg  *)0x42002444UL) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1               (*(RwReg  *)0x42002448UL) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB             (*(RwReg16*)0x42002464UL) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB             (*(RwReg  *)0x42002468UL) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB              (*(RwReg  *)0x4200246CUL) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0              (*(RwReg  *)0x42002470UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1              (*(RwReg  *)0x42002474UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC1 peripheral ========== */
+#define TCC1_CC_NUM                 2        // Number of Compare/Capture units
+#define TCC1_DITHERING              1        // Dithering feature implemented
+#define TCC1_DMAC_ID_MC_0           19
+#define TCC1_DMAC_ID_MC_1           20
+#define TCC1_DMAC_ID_MC_LSB         19
+#define TCC1_DMAC_ID_MC_MSB         20
+#define TCC1_DMAC_ID_MC_SIZE        2
+#define TCC1_DMAC_ID_OVF            18       // DMA overflow/underflow/retrigger trigger
+#define TCC1_DTI                    0        // Dead-Time-Insertion feature implemented
+#define TCC1_EXT                    24       // Coding of implemented extended features
+#define TCC1_GCLK_ID                26       // Index of Generic Clock
+#define TCC1_OTMX                   0        // Output Matrix feature implemented
+#define TCC1_OW_NUM                 4        // Number of Output Waveforms
+#define TCC1_PG                     1        // Pattern Generation feature implemented
+#define TCC1_SIZE                   24      
+#define TCC1_SWAP                   0        // DTI outputs swap feature implemented
+#define TCC1_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC1_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/tcc2.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/tcc2.h
new file mode 100644
index 00000000..2b394b35
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/tcc2.h
@@ -0,0 +1,100 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC2
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC2_INSTANCE_
+#define _SAMD21_TCC2_INSTANCE_
+
+/* ========== Register definition for TCC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC2_CTRLA             (0x42002800) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR          (0x42002804) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET          (0x42002805) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY          (0x42002808) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA            (0x4200280C) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB            (0x42002810) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_DRVCTRL           (0x42002818) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL           (0x4200281E) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL            (0x42002820) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR          (0x42002824) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET          (0x42002828) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG           (0x4200282C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS            (0x42002830) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT             (0x42002834) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE              (0x4200283C) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER               (0x42002840) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0               (0x42002844) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1               (0x42002848) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB             (0x42002868) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB              (0x4200286C) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0              (0x42002870) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1              (0x42002874) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC2_CTRLA             (*(RwReg  *)0x42002800UL) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR          (*(RwReg8 *)0x42002804UL) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET          (*(RwReg8 *)0x42002805UL) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY          (*(RoReg  *)0x42002808UL) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA            (*(RwReg  *)0x4200280CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB            (*(RwReg  *)0x42002810UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_DRVCTRL           (*(RwReg  *)0x42002818UL) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL           (*(RwReg8 *)0x4200281EUL) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL            (*(RwReg  *)0x42002820UL) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR          (*(RwReg  *)0x42002824UL) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET          (*(RwReg  *)0x42002828UL) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG           (*(RwReg  *)0x4200282CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS            (*(RwReg  *)0x42002830UL) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT             (*(RwReg  *)0x42002834UL) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE              (*(RwReg  *)0x4200283CUL) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER               (*(RwReg  *)0x42002840UL) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0               (*(RwReg  *)0x42002844UL) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1               (*(RwReg  *)0x42002848UL) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB             (*(RwReg  *)0x42002868UL) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB              (*(RwReg  *)0x4200286CUL) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0              (*(RwReg  *)0x42002870UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1              (*(RwReg  *)0x42002874UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC2 peripheral ========== */
+#define TCC2_CC_NUM                 2        // Number of Compare/Capture units
+#define TCC2_DITHERING              0        // Dithering feature implemented
+#define TCC2_DMAC_ID_MC_0           22
+#define TCC2_DMAC_ID_MC_1           23
+#define TCC2_DMAC_ID_MC_LSB         22
+#define TCC2_DMAC_ID_MC_MSB         23
+#define TCC2_DMAC_ID_MC_SIZE        2
+#define TCC2_DMAC_ID_OVF            21       // DMA overflow/underflow/retrigger trigger
+#define TCC2_DTI                    0        // Dead-Time-Insertion feature implemented
+#define TCC2_EXT                    0        // Coding of implemented extended features
+#define TCC2_GCLK_ID                27       // Index of Generic Clock
+#define TCC2_OTMX                   0        // Output Matrix feature implemented
+#define TCC2_OW_NUM                 2        // Number of Output Waveforms
+#define TCC2_PG                     0        // Pattern Generation feature implemented
+#define TCC2_SIZE                   16      
+#define TCC2_SWAP                   0        // DTI outputs swap feature implemented
+#define TCC2_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC2_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/usb.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/usb.h
new file mode 100644
index 00000000..357e8c9a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/usb.h
@@ -0,0 +1,329 @@
+/**
+ * \file
+ *
+ * \brief Instance description for USB
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_INSTANCE_
+#define _SAMD21_USB_INSTANCE_
+
+/* ========== Register definition for USB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USB_CTRLA              (0x41005000) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY           (0x41005002) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL            (0x41005003) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS          (0x4100500D) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD            (0x41005024) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL             (0x41005028) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB       (0x41005008) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD        (0x4100500A) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS      (0x4100500C) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM        (0x41005010) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR    (0x41005014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET    (0x41005018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG     (0x4100501C) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY   (0x41005020) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB         (0x41005008) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC         (0x4100500A) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS        (0x4100500C) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM          (0x41005010) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH      (0x41005012) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR      (0x41005014) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET      (0x41005018) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG       (0x4100501C) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY      (0x41005020) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0    (0x41005100) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1    (0x41005120) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2    (0x41005140) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3    (0x41005160) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4    (0x41005180) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5    (0x410051A0) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6    (0x410051C0) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7    (0x410051E0) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#else
+#define REG_USB_CTRLA              (*(RwReg8 *)0x41005000UL) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY           (*(RoReg8 *)0x41005002UL) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL            (*(RwReg8 *)0x41005003UL) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS          (*(RoReg8 *)0x4100500DUL) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD            (*(RwReg  *)0x41005024UL) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL             (*(RwReg16*)0x41005028UL) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB       (*(RwReg16*)0x41005008UL) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD        (*(RwReg8 *)0x4100500AUL) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS      (*(RoReg8 *)0x4100500CUL) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM        (*(RoReg16*)0x41005010UL) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR    (*(RwReg16*)0x41005014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET    (*(RwReg16*)0x41005018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG     (*(RwReg16*)0x4100501CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY   (*(RoReg16*)0x41005020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB         (*(RwReg16*)0x41005008UL) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC         (*(RwReg8 *)0x4100500AUL) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS        (*(RwReg8 *)0x4100500CUL) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM          (*(RwReg16*)0x41005010UL) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH      (*(RoReg8 *)0x41005012UL) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR      (*(RwReg16*)0x41005014UL) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET      (*(RwReg16*)0x41005018UL) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG       (*(RwReg16*)0x4100501CUL) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY      (*(RoReg16*)0x41005020UL) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0    (*(RwReg8 *)0x41005100UL) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1    (*(RwReg8 *)0x41005120UL) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2    (*(RwReg8 *)0x41005140UL) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3    (*(RwReg8 *)0x41005160UL) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4    (*(RwReg8 *)0x41005180UL) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5    (*(RwReg8 *)0x410051A0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6    (*(RwReg8 *)0x410051C0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7    (*(RwReg8 *)0x410051E0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for USB peripheral ========== */
+#define USB_EPT_NBR                 8        // Number of USB end points (obsolete)
+#define USB_EPT_NUM                 8        // Number of USB end points
+#define USB_GCLK_ID                 6        // Index of Generic Clock
+#define USB_PIPE_NUM                8        // Number of USB pipes
+
+#endif /* _SAMD21_USB_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/instance/wdt.h b/uf2-samdx1/lib/samd21/samd21a/include/instance/wdt.h
new file mode 100644
index 00000000..33110ef6
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/instance/wdt.h
@@ -0,0 +1,56 @@
+/**
+ * \file
+ *
+ * \brief Instance description for WDT
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_INSTANCE_
+#define _SAMD21_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CTRL               (0x40001000) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (0x40001001) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (0x40001002) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (0x40001004) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (0x40001005) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (0x40001006) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS             (0x40001007) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR              (0x40001008) /**< \brief (WDT) Clear */
+#else
+#define REG_WDT_CTRL               (*(RwReg8 *)0x40001000UL) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (*(RwReg8 *)0x40001001UL) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (*(RwReg8 *)0x40001002UL) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (*(RwReg8 *)0x40001004UL) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (*(RwReg8 *)0x40001006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS             (*(RoReg8 *)0x40001007UL) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR              (*(WoReg8 *)0x40001008UL) /**< \brief (WDT) Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for WDT peripheral ========== */
+#define WDT_GCLK_ID                 3        // Index of Generic Clock
+
+#endif /* _SAMD21_WDT_INSTANCE_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e15a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e15a.h
new file mode 100644
index 00000000..1f65cd9e
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e15a.h
@@ -0,0 +1,651 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15A_PIO_
+#define _SAMD21E15A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21E15A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e16a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e16a.h
new file mode 100644
index 00000000..fa57fe61
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e16a.h
@@ -0,0 +1,651 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16A_PIO_
+#define _SAMD21E16A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21E16A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e17a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e17a.h
new file mode 100644
index 00000000..6eb9655a
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e17a.h
@@ -0,0 +1,651 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E17A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17A_PIO_
+#define _SAMD21E17A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21E17A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e18a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e18a.h
new file mode 100644
index 00000000..60b7ca7d
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21e18a.h
@@ -0,0 +1,651 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E18A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E18A_PIO_
+#define _SAMD21E18A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21E18A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g15a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g15a.h
new file mode 100644
index 00000000..8103761b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g15a.h
@@ -0,0 +1,937 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G15A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15A_PIO_
+#define _SAMD21G15A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL(1) << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0             _L(54) /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0              _L(7)
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0    (_UL(1) << 22)
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PB23H_GCLK_IO1             _L(55) /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1              _L(7)
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1    (_UL(1) << 23)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PB10H_GCLK_IO4             _L(42) /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4              _L(7)
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PB11H_GCLK_IO5             _L(43) /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5              _L(7)
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL(1) << 10)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+#define PIN_PB11D_SERCOM4_PAD3         _L(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PB22D_SERCOM5_PAD2         _L(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PB23D_SERCOM5_PAD3         _L(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PB10F_TCC0_WO4             _L(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL(1) << 10)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PB11F_TCC0_WO5             _L(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL(1) << 11)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL(1) << 10)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL(1) << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PB10G_I2S_MCK1             _L(42) /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1              _L(6)
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1    (_UL(1) << 10)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PB11G_I2S_SCK1             _L(43) /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1              _L(6)
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1    (_UL(1) << 11)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21G15A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g16a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g16a.h
new file mode 100644
index 00000000..cfd0b3e7
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g16a.h
@@ -0,0 +1,937 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G16A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16A_PIO_
+#define _SAMD21G16A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL(1) << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0             _L(54) /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0              _L(7)
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0    (_UL(1) << 22)
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PB23H_GCLK_IO1             _L(55) /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1              _L(7)
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1    (_UL(1) << 23)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PB10H_GCLK_IO4             _L(42) /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4              _L(7)
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PB11H_GCLK_IO5             _L(43) /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5              _L(7)
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL(1) << 10)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+#define PIN_PB11D_SERCOM4_PAD3         _L(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PB22D_SERCOM5_PAD2         _L(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PB23D_SERCOM5_PAD3         _L(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PB10F_TCC0_WO4             _L(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL(1) << 10)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PB11F_TCC0_WO5             _L(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL(1) << 11)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL(1) << 10)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL(1) << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PB10G_I2S_MCK1             _L(42) /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1              _L(6)
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1    (_UL(1) << 10)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PB11G_I2S_SCK1             _L(43) /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1              _L(6)
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1    (_UL(1) << 11)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21G16A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g17a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g17a.h
new file mode 100644
index 00000000..0b81cbf1
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g17a.h
@@ -0,0 +1,937 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17A_PIO_
+#define _SAMD21G17A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL(1) << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0             _L(54) /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0              _L(7)
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0    (_UL(1) << 22)
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PB23H_GCLK_IO1             _L(55) /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1              _L(7)
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1    (_UL(1) << 23)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PB10H_GCLK_IO4             _L(42) /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4              _L(7)
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PB11H_GCLK_IO5             _L(43) /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5              _L(7)
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL(1) << 10)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+#define PIN_PB11D_SERCOM4_PAD3         _L(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PB22D_SERCOM5_PAD2         _L(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PB23D_SERCOM5_PAD3         _L(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PB10F_TCC0_WO4             _L(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL(1) << 10)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PB11F_TCC0_WO5             _L(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL(1) << 11)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL(1) << 10)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL(1) << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PB10G_I2S_MCK1             _L(42) /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1              _L(6)
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1    (_UL(1) << 10)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PB11G_I2S_SCK1             _L(43) /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1              _L(6)
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1    (_UL(1) << 11)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21G17A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g17au.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g17au.h
new file mode 100644
index 00000000..97600dc5
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g17au.h
@@ -0,0 +1,882 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17AU
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17AU_PIO_
+#define _SAMD21G17AU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0              _L(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0               _L(4)
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0     (_UL(1) <<  2)
+#define PIN_PB03E_TC6_WO1              _L(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1               _L(4)
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1     (_UL(1) <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0              _L(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0               _L(4)
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0     (_UL(1) << 20)
+#define PIN_PA21E_TC7_WO1              _L(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1               _L(4)
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1     (_UL(1) << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PB04B_ADC_AIN12            _L(36) /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12             _L(1)
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12   (_UL(1) <<  4)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21G17AU_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g18a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g18a.h
new file mode 100644
index 00000000..cc30819d
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g18a.h
@@ -0,0 +1,937 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G18A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18A_PIO_
+#define _SAMD21G18A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL(1) << 23) /**< \brief PORT Mask  for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0             _L(54) /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0              _L(7)
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0    (_UL(1) << 22)
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PB23H_GCLK_IO1             _L(55) /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1              _L(7)
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1    (_UL(1) << 23)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PB10H_GCLK_IO4             _L(42) /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4              _L(7)
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PB11H_GCLK_IO5             _L(43) /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5              _L(7)
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL(1) << 10)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+#define PIN_PB11D_SERCOM4_PAD3         _L(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PB22D_SERCOM5_PAD2         _L(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PB23D_SERCOM5_PAD3         _L(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PB10F_TCC0_WO4             _L(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL(1) << 10)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PB11F_TCC0_WO5             _L(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL(1) << 11)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL(1) << 10)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL(1) << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PB10G_I2S_MCK1             _L(42) /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1              _L(6)
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1    (_UL(1) << 10)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PB11G_I2S_SCK1             _L(43) /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1              _L(6)
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1    (_UL(1) << 11)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21G18A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g18au.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g18au.h
new file mode 100644
index 00000000..6f35efad
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21g18au.h
@@ -0,0 +1,882 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G18AU
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18AU_PIO_
+#define _SAMD21G18AU_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0              _L(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0               _L(4)
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0     (_UL(1) <<  2)
+#define PIN_PB03E_TC6_WO1              _L(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1               _L(4)
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1     (_UL(1) <<  3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0              _L(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0               _L(4)
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0     (_UL(1) << 20)
+#define PIN_PA21E_TC7_WO1              _L(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1               _L(4)
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1     (_UL(1) << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PB04B_ADC_AIN12            _L(36) /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12             _L(1)
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12   (_UL(1) <<  4)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+
+#endif /* _SAMD21G18AU_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j15a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j15a.h
new file mode 100644
index 00000000..5e19c9b5
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j15a.h
@@ -0,0 +1,1225 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J15A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15A_PIO_
+#define _SAMD21J15A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00              (_UL(1) <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01              (_UL(1) <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05              (_UL(1) <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06              (_UL(1) <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07              (_UL(1) <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12              (_UL(1) << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13              (_UL(1) << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14              (_UL(1) << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15              (_UL(1) << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16              (_UL(1) << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17              (_UL(1) << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL(1) << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30              (_UL(1) << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31              (_UL(1) << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0             _L(46) /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0              _L(7)
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PB22H_GCLK_IO0             _L(54) /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0              _L(7)
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0    (_UL(1) << 22)
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PB15H_GCLK_IO1             _L(47) /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1              _L(7)
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PB23H_GCLK_IO1             _L(55) /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1              _L(7)
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1    (_UL(1) << 23)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PB16H_GCLK_IO2             _L(48) /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2              _L(7)
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PB17H_GCLK_IO3             _L(49) /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3              _L(7)
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PB10H_GCLK_IO4             _L(42) /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4              _L(7)
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PB11H_GCLK_IO5             _L(43) /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5              _L(7)
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PB12H_GCLK_IO6             _L(44) /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6              _L(7)
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6    (_UL(1) << 12)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+#define PIN_PB13H_GCLK_IO7             _L(45) /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7              _L(7)
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7    (_UL(1) << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0          _L(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0          _L(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1          _L(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1          _L(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5          _L(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6          _L(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7          _L(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12         _L(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13         _L(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14         _L(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14         _L(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14          _L(0)
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14  (_UL(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15         _L(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15         _L(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15          _L(0)
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15  (_UL(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PB12C_SERCOM4_PAD0         _L(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0          _L(2)
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PB13C_SERCOM4_PAD1         _L(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1          _L(2)
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2         _L(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2          _L(2)
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+#define PIN_PB11D_SERCOM4_PAD3         _L(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL(1) << 11)
+#define PIN_PB15C_SERCOM4_PAD3         _L(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3          _L(2)
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0         _L(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0          _L(2)
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0  (_UL(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PB30D_SERCOM5_PAD0         _L(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0  (_UL(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1         _L(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1          _L(2)
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1  (_UL(1) << 17)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PB31D_SERCOM5_PAD1         _L(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1  (_UL(1) << 31)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2         _L(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2  (_UL(1) <<  0)
+#define PIN_PB22D_SERCOM5_PAD2         _L(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3         _L(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3  (_UL(1) <<  1)
+#define PIN_PB23D_SERCOM5_PAD3         _L(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PB30E_TCC0_WO0             _L(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0              _L(4)
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0    (_UL(1) << 30)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PB31E_TCC0_WO1             _L(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1              _L(4)
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1    (_UL(1) << 31)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PB10F_TCC0_WO4             _L(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL(1) << 10)
+#define PIN_PB16F_TCC0_WO4             _L(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4              _L(5)
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4    (_UL(1) << 16)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PB11F_TCC0_WO5             _L(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL(1) << 11)
+#define PIN_PB17F_TCC0_WO5             _L(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5              _L(5)
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5    (_UL(1) << 17)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PB12F_TCC0_WO6             _L(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6              _L(5)
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PB13F_TCC0_WO7             _L(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7              _L(5)
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PB30F_TCC1_WO2             _L(62) /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2              _L(5)
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2    (_UL(1) << 30)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+#define PIN_PB31F_TCC1_WO3             _L(63) /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3              _L(5)
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3    (_UL(1) << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PB12E_TC4_WO0              _L(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0               _L(4)
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0     (_UL(1) << 12)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+#define PIN_PB13E_TC4_WO1              _L(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1               _L(4)
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1     (_UL(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL(1) << 10)
+#define PIN_PB14E_TC5_WO0              _L(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0               _L(4)
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0     (_UL(1) << 14)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL(1) << 11)
+#define PIN_PB15E_TC5_WO1              _L(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1               _L(4)
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0              _L(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0               _L(4)
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0     (_UL(1) <<  2)
+#define PIN_PB16E_TC6_WO0              _L(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0               _L(4)
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0     (_UL(1) << 16)
+#define PIN_PB03E_TC6_WO1              _L(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1               _L(4)
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1     (_UL(1) <<  3)
+#define PIN_PB17E_TC6_WO1              _L(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1               _L(4)
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1     (_UL(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0              _L(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0               _L(4)
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0     (_UL(1) << 20)
+#define PIN_PB00E_TC7_WO0              _L(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0               _L(4)
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0     (_UL(1) <<  0)
+#define PIN_PB22E_TC7_WO0              _L(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0               _L(4)
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0     (_UL(1) << 22)
+#define PIN_PA21E_TC7_WO1              _L(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1               _L(4)
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1     (_UL(1) << 21)
+#define PIN_PB01E_TC7_WO1              _L(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1               _L(4)
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1     (_UL(1) <<  1)
+#define PIN_PB23E_TC7_WO1              _L(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1               _L(4)
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1     (_UL(1) << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB00B_ADC_AIN8             _L(32) /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8              _L(1)
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8    (_UL(1) <<  0)
+#define PIN_PB01B_ADC_AIN9             _L(33) /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9              _L(1)
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9    (_UL(1) <<  1)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PB04B_ADC_AIN12            _L(36) /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12             _L(1)
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12   (_UL(1) <<  4)
+#define PIN_PB05B_ADC_AIN13            _L(37) /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13             _L(1)
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13   (_UL(1) <<  5)
+#define PIN_PB06B_ADC_AIN14            _L(38) /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14             _L(1)
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14   (_UL(1) <<  6)
+#define PIN_PB07B_ADC_AIN15            _L(39) /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15             _L(1)
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15   (_UL(1) <<  7)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PB12G_I2S_FS1              _L(44) /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1               _L(6)
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1     (_UL(1) << 12)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PB17G_I2S_MCK0             _L(49) /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0              _L(6)
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0    (_UL(1) << 17)
+#define PIN_PB10G_I2S_MCK1             _L(42) /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1              _L(6)
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1    (_UL(1) << 10)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PB11G_I2S_SCK1             _L(43) /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1              _L(6)
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1    (_UL(1) << 11)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+#define PIN_PB16G_I2S_SD1              _L(48) /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1               _L(6)
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1     (_UL(1) << 16)
+
+#endif /* _SAMD21J15A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j16a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j16a.h
new file mode 100644
index 00000000..a5977a4e
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j16a.h
@@ -0,0 +1,1225 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J16A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16A_PIO_
+#define _SAMD21J16A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00              (_UL(1) <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01              (_UL(1) <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05              (_UL(1) <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06              (_UL(1) <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07              (_UL(1) <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12              (_UL(1) << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13              (_UL(1) << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14              (_UL(1) << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15              (_UL(1) << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16              (_UL(1) << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17              (_UL(1) << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL(1) << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30              (_UL(1) << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31              (_UL(1) << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0             _L(46) /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0              _L(7)
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PB22H_GCLK_IO0             _L(54) /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0              _L(7)
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0    (_UL(1) << 22)
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PB15H_GCLK_IO1             _L(47) /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1              _L(7)
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PB23H_GCLK_IO1             _L(55) /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1              _L(7)
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1    (_UL(1) << 23)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PB16H_GCLK_IO2             _L(48) /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2              _L(7)
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PB17H_GCLK_IO3             _L(49) /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3              _L(7)
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PB10H_GCLK_IO4             _L(42) /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4              _L(7)
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PB11H_GCLK_IO5             _L(43) /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5              _L(7)
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PB12H_GCLK_IO6             _L(44) /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6              _L(7)
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6    (_UL(1) << 12)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+#define PIN_PB13H_GCLK_IO7             _L(45) /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7              _L(7)
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7    (_UL(1) << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0          _L(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0          _L(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1          _L(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1          _L(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5          _L(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6          _L(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7          _L(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12         _L(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13         _L(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14         _L(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14         _L(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14          _L(0)
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14  (_UL(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15         _L(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15         _L(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15          _L(0)
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15  (_UL(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PB12C_SERCOM4_PAD0         _L(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0          _L(2)
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PB13C_SERCOM4_PAD1         _L(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1          _L(2)
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2         _L(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2          _L(2)
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+#define PIN_PB11D_SERCOM4_PAD3         _L(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL(1) << 11)
+#define PIN_PB15C_SERCOM4_PAD3         _L(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3          _L(2)
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0         _L(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0          _L(2)
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0  (_UL(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PB30D_SERCOM5_PAD0         _L(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0  (_UL(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1         _L(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1          _L(2)
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1  (_UL(1) << 17)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PB31D_SERCOM5_PAD1         _L(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1  (_UL(1) << 31)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2         _L(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2  (_UL(1) <<  0)
+#define PIN_PB22D_SERCOM5_PAD2         _L(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3         _L(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3  (_UL(1) <<  1)
+#define PIN_PB23D_SERCOM5_PAD3         _L(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PB30E_TCC0_WO0             _L(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0              _L(4)
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0    (_UL(1) << 30)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PB31E_TCC0_WO1             _L(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1              _L(4)
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1    (_UL(1) << 31)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PB10F_TCC0_WO4             _L(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL(1) << 10)
+#define PIN_PB16F_TCC0_WO4             _L(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4              _L(5)
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4    (_UL(1) << 16)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PB11F_TCC0_WO5             _L(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL(1) << 11)
+#define PIN_PB17F_TCC0_WO5             _L(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5              _L(5)
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5    (_UL(1) << 17)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PB12F_TCC0_WO6             _L(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6              _L(5)
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PB13F_TCC0_WO7             _L(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7              _L(5)
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PB30F_TCC1_WO2             _L(62) /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2              _L(5)
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2    (_UL(1) << 30)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+#define PIN_PB31F_TCC1_WO3             _L(63) /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3              _L(5)
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3    (_UL(1) << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PB12E_TC4_WO0              _L(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0               _L(4)
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0     (_UL(1) << 12)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+#define PIN_PB13E_TC4_WO1              _L(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1               _L(4)
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1     (_UL(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL(1) << 10)
+#define PIN_PB14E_TC5_WO0              _L(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0               _L(4)
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0     (_UL(1) << 14)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL(1) << 11)
+#define PIN_PB15E_TC5_WO1              _L(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1               _L(4)
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0              _L(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0               _L(4)
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0     (_UL(1) <<  2)
+#define PIN_PB16E_TC6_WO0              _L(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0               _L(4)
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0     (_UL(1) << 16)
+#define PIN_PB03E_TC6_WO1              _L(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1               _L(4)
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1     (_UL(1) <<  3)
+#define PIN_PB17E_TC6_WO1              _L(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1               _L(4)
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1     (_UL(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0              _L(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0               _L(4)
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0     (_UL(1) << 20)
+#define PIN_PB00E_TC7_WO0              _L(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0               _L(4)
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0     (_UL(1) <<  0)
+#define PIN_PB22E_TC7_WO0              _L(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0               _L(4)
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0     (_UL(1) << 22)
+#define PIN_PA21E_TC7_WO1              _L(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1               _L(4)
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1     (_UL(1) << 21)
+#define PIN_PB01E_TC7_WO1              _L(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1               _L(4)
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1     (_UL(1) <<  1)
+#define PIN_PB23E_TC7_WO1              _L(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1               _L(4)
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1     (_UL(1) << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB00B_ADC_AIN8             _L(32) /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8              _L(1)
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8    (_UL(1) <<  0)
+#define PIN_PB01B_ADC_AIN9             _L(33) /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9              _L(1)
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9    (_UL(1) <<  1)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PB04B_ADC_AIN12            _L(36) /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12             _L(1)
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12   (_UL(1) <<  4)
+#define PIN_PB05B_ADC_AIN13            _L(37) /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13             _L(1)
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13   (_UL(1) <<  5)
+#define PIN_PB06B_ADC_AIN14            _L(38) /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14             _L(1)
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14   (_UL(1) <<  6)
+#define PIN_PB07B_ADC_AIN15            _L(39) /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15             _L(1)
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15   (_UL(1) <<  7)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PB12G_I2S_FS1              _L(44) /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1               _L(6)
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1     (_UL(1) << 12)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PB17G_I2S_MCK0             _L(49) /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0              _L(6)
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0    (_UL(1) << 17)
+#define PIN_PB10G_I2S_MCK1             _L(42) /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1              _L(6)
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1    (_UL(1) << 10)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PB11G_I2S_SCK1             _L(43) /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1              _L(6)
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1    (_UL(1) << 11)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+#define PIN_PB16G_I2S_SD1              _L(48) /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1               _L(6)
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1     (_UL(1) << 16)
+
+#endif /* _SAMD21J16A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j17a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j17a.h
new file mode 100644
index 00000000..9e4954d8
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j17a.h
@@ -0,0 +1,1225 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J17A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17A_PIO_
+#define _SAMD21J17A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00              (_UL(1) <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01              (_UL(1) <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05              (_UL(1) <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06              (_UL(1) <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07              (_UL(1) <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12              (_UL(1) << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13              (_UL(1) << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14              (_UL(1) << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15              (_UL(1) << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16              (_UL(1) << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17              (_UL(1) << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL(1) << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30              (_UL(1) << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31              (_UL(1) << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0             _L(46) /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0              _L(7)
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PB22H_GCLK_IO0             _L(54) /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0              _L(7)
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0    (_UL(1) << 22)
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PB15H_GCLK_IO1             _L(47) /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1              _L(7)
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PB23H_GCLK_IO1             _L(55) /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1              _L(7)
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1    (_UL(1) << 23)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PB16H_GCLK_IO2             _L(48) /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2              _L(7)
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PB17H_GCLK_IO3             _L(49) /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3              _L(7)
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PB10H_GCLK_IO4             _L(42) /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4              _L(7)
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PB11H_GCLK_IO5             _L(43) /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5              _L(7)
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PB12H_GCLK_IO6             _L(44) /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6              _L(7)
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6    (_UL(1) << 12)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+#define PIN_PB13H_GCLK_IO7             _L(45) /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7              _L(7)
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7    (_UL(1) << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0          _L(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0          _L(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1          _L(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1          _L(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5          _L(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6          _L(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7          _L(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12         _L(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13         _L(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14         _L(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14         _L(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14          _L(0)
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14  (_UL(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15         _L(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15         _L(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15          _L(0)
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15  (_UL(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PB12C_SERCOM4_PAD0         _L(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0          _L(2)
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PB13C_SERCOM4_PAD1         _L(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1          _L(2)
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2         _L(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2          _L(2)
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+#define PIN_PB11D_SERCOM4_PAD3         _L(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL(1) << 11)
+#define PIN_PB15C_SERCOM4_PAD3         _L(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3          _L(2)
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0         _L(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0          _L(2)
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0  (_UL(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PB30D_SERCOM5_PAD0         _L(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0  (_UL(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1         _L(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1          _L(2)
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1  (_UL(1) << 17)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PB31D_SERCOM5_PAD1         _L(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1  (_UL(1) << 31)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2         _L(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2  (_UL(1) <<  0)
+#define PIN_PB22D_SERCOM5_PAD2         _L(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3         _L(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3  (_UL(1) <<  1)
+#define PIN_PB23D_SERCOM5_PAD3         _L(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PB30E_TCC0_WO0             _L(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0              _L(4)
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0    (_UL(1) << 30)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PB31E_TCC0_WO1             _L(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1              _L(4)
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1    (_UL(1) << 31)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PB10F_TCC0_WO4             _L(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL(1) << 10)
+#define PIN_PB16F_TCC0_WO4             _L(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4              _L(5)
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4    (_UL(1) << 16)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PB11F_TCC0_WO5             _L(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL(1) << 11)
+#define PIN_PB17F_TCC0_WO5             _L(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5              _L(5)
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5    (_UL(1) << 17)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PB12F_TCC0_WO6             _L(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6              _L(5)
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PB13F_TCC0_WO7             _L(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7              _L(5)
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PB30F_TCC1_WO2             _L(62) /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2              _L(5)
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2    (_UL(1) << 30)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+#define PIN_PB31F_TCC1_WO3             _L(63) /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3              _L(5)
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3    (_UL(1) << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PB12E_TC4_WO0              _L(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0               _L(4)
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0     (_UL(1) << 12)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+#define PIN_PB13E_TC4_WO1              _L(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1               _L(4)
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1     (_UL(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL(1) << 10)
+#define PIN_PB14E_TC5_WO0              _L(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0               _L(4)
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0     (_UL(1) << 14)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL(1) << 11)
+#define PIN_PB15E_TC5_WO1              _L(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1               _L(4)
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0              _L(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0               _L(4)
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0     (_UL(1) <<  2)
+#define PIN_PB16E_TC6_WO0              _L(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0               _L(4)
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0     (_UL(1) << 16)
+#define PIN_PB03E_TC6_WO1              _L(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1               _L(4)
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1     (_UL(1) <<  3)
+#define PIN_PB17E_TC6_WO1              _L(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1               _L(4)
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1     (_UL(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0              _L(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0               _L(4)
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0     (_UL(1) << 20)
+#define PIN_PB00E_TC7_WO0              _L(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0               _L(4)
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0     (_UL(1) <<  0)
+#define PIN_PB22E_TC7_WO0              _L(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0               _L(4)
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0     (_UL(1) << 22)
+#define PIN_PA21E_TC7_WO1              _L(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1               _L(4)
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1     (_UL(1) << 21)
+#define PIN_PB01E_TC7_WO1              _L(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1               _L(4)
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1     (_UL(1) <<  1)
+#define PIN_PB23E_TC7_WO1              _L(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1               _L(4)
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1     (_UL(1) << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB00B_ADC_AIN8             _L(32) /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8              _L(1)
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8    (_UL(1) <<  0)
+#define PIN_PB01B_ADC_AIN9             _L(33) /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9              _L(1)
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9    (_UL(1) <<  1)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PB04B_ADC_AIN12            _L(36) /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12             _L(1)
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12   (_UL(1) <<  4)
+#define PIN_PB05B_ADC_AIN13            _L(37) /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13             _L(1)
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13   (_UL(1) <<  5)
+#define PIN_PB06B_ADC_AIN14            _L(38) /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14             _L(1)
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14   (_UL(1) <<  6)
+#define PIN_PB07B_ADC_AIN15            _L(39) /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15             _L(1)
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15   (_UL(1) <<  7)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PB12G_I2S_FS1              _L(44) /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1               _L(6)
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1     (_UL(1) << 12)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PB17G_I2S_MCK0             _L(49) /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0              _L(6)
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0    (_UL(1) << 17)
+#define PIN_PB10G_I2S_MCK1             _L(42) /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1              _L(6)
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1    (_UL(1) << 10)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PB11G_I2S_SCK1             _L(43) /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1              _L(6)
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1    (_UL(1) << 11)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+#define PIN_PB16G_I2S_SD1              _L(48) /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1               _L(6)
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1     (_UL(1) << 16)
+
+#endif /* _SAMD21J17A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j18a.h b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j18a.h
new file mode 100644
index 00000000..89f49959
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/pio/samd21j18a.h
@@ -0,0 +1,1225 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J18A
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J18A_PIO_
+#define _SAMD21J18A_PIO_
+
+#define PIN_PA00                           0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                           1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                           2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                           3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                           4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                           5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                           6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                           7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                           8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                           9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                          10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                          11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                          12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                          13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                          14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                          15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                          16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                          17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                          18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                          19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                          20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                          21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                          22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                          23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                          24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                          25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                          27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA28                          28  /**< \brief Pin Number for PA28 */
+#define PORT_PA28              (_UL(1) << 28) /**< \brief PORT Mask  for PA28 */
+#define PIN_PA30                          30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                          31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                          32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00              (_UL(1) <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                          33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01              (_UL(1) <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                          34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                          35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                          36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                          37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05              (_UL(1) <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                          38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06              (_UL(1) <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                          39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07              (_UL(1) <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                          40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                          41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                          42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                          43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                          44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12              (_UL(1) << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                          45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13              (_UL(1) << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                          46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14              (_UL(1) << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                          47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15              (_UL(1) << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                          48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16              (_UL(1) << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                          49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17              (_UL(1) << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                          54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                          55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL(1) << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                          62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30              (_UL(1) << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                          63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31              (_UL(1) << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0             _L(46) /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0              _L(7)
+#define PINMUX_PB14H_GCLK_IO0      ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PB22H_GCLK_IO0             _L(54) /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0              _L(7)
+#define PINMUX_PB22H_GCLK_IO0      ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0    (_UL(1) << 22)
+#define PIN_PA14H_GCLK_IO0             _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0              _L(7)
+#define PINMUX_PA14H_GCLK_IO0      ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0    (_UL(1) << 14)
+#define PIN_PA27H_GCLK_IO0             _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0              _L(7)
+#define PINMUX_PA27H_GCLK_IO0      ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0    (_UL(1) << 27)
+#define PIN_PA28H_GCLK_IO0             _L(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0              _L(7)
+#define PINMUX_PA28H_GCLK_IO0      ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0    (_UL(1) << 28)
+#define PIN_PA30H_GCLK_IO0             _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0              _L(7)
+#define PINMUX_PA30H_GCLK_IO0      ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0    (_UL(1) << 30)
+#define PIN_PB15H_GCLK_IO1             _L(47) /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1              _L(7)
+#define PINMUX_PB15H_GCLK_IO1      ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PB23H_GCLK_IO1             _L(55) /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1              _L(7)
+#define PINMUX_PB23H_GCLK_IO1      ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1    (_UL(1) << 23)
+#define PIN_PA15H_GCLK_IO1             _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1              _L(7)
+#define PINMUX_PA15H_GCLK_IO1      ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1    (_UL(1) << 15)
+#define PIN_PB16H_GCLK_IO2             _L(48) /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2              _L(7)
+#define PINMUX_PB16H_GCLK_IO2      ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA16H_GCLK_IO2             _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2              _L(7)
+#define PINMUX_PA16H_GCLK_IO2      ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2    (_UL(1) << 16)
+#define PIN_PA17H_GCLK_IO3             _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3              _L(7)
+#define PINMUX_PA17H_GCLK_IO3      ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PB17H_GCLK_IO3             _L(49) /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3              _L(7)
+#define PINMUX_PB17H_GCLK_IO3      ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3    (_UL(1) << 17)
+#define PIN_PA10H_GCLK_IO4             _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4              _L(7)
+#define PINMUX_PA10H_GCLK_IO4      ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA20H_GCLK_IO4             _L(20) /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4              _L(7)
+#define PINMUX_PA20H_GCLK_IO4      ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4    (_UL(1) << 20)
+#define PIN_PB10H_GCLK_IO4             _L(42) /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4              _L(7)
+#define PINMUX_PB10H_GCLK_IO4      ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4    (_UL(1) << 10)
+#define PIN_PA11H_GCLK_IO5             _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5              _L(7)
+#define PINMUX_PA11H_GCLK_IO5      ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA21H_GCLK_IO5             _L(21) /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5              _L(7)
+#define PINMUX_PA21H_GCLK_IO5      ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5    (_UL(1) << 21)
+#define PIN_PB11H_GCLK_IO5             _L(43) /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5              _L(7)
+#define PINMUX_PB11H_GCLK_IO5      ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5    (_UL(1) << 11)
+#define PIN_PA22H_GCLK_IO6             _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6              _L(7)
+#define PINMUX_PA22H_GCLK_IO6      ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6    (_UL(1) << 22)
+#define PIN_PB12H_GCLK_IO6             _L(44) /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6              _L(7)
+#define PINMUX_PB12H_GCLK_IO6      ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6    (_UL(1) << 12)
+#define PIN_PA23H_GCLK_IO7             _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7              _L(7)
+#define PINMUX_PA23H_GCLK_IO7      ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7    (_UL(1) << 23)
+#define PIN_PB13H_GCLK_IO7             _L(45) /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7              _L(7)
+#define PINMUX_PB13H_GCLK_IO7      ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7    (_UL(1) << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0          _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0          _L(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0          _L(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0           _L(0)
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0  (_UL(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PA00A_EIC_EXTINT0           _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1          _L(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1          _L(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1           _L(0)
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1  (_UL(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5          _L(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5           _L(0)
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5  (_UL(1) <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM        _L(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6          _L(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6  (_UL(1) <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7          _L(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7  (_UL(1) <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA28A_EIC_EXTINT8          _L(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8           _L(0)
+#define PINMUX_PA28A_EIC_EXTINT8   ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8  (_UL(1) << 28)
+#define PIN_PA28A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT10         _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10          _L(0)
+#define PINMUX_PA30A_EIC_EXTINT10  ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10  (_UL(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT11         _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11          _L(0)
+#define PINMUX_PA31A_EIC_EXTINT11  ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11  (_UL(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT12         _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12          _L(0)
+#define PINMUX_PA24A_EIC_EXTINT12  ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12  (_UL(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12         _L(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12          _L(0)
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12  (_UL(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM       _L(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT13         _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13          _L(0)
+#define PINMUX_PA25A_EIC_EXTINT13  ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13  (_UL(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13         _L(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13          _L(0)
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13  (_UL(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM       _L(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14         _L(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14         _L(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14          _L(0)
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14  (_UL(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT15         _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15          _L(0)
+#define PINMUX_PA27A_EIC_EXTINT15  ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15  (_UL(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15         _L(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15          _L(0)
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15  (_UL(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15         _L(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15          _L(0)
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15  (_UL(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM       _L(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL(1) <<  8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM               _L(24) /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM                _L(6)
+#define PINMUX_PA24G_USB_DM        ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM      (_UL(1) << 24)
+#define PIN_PA25G_USB_DP               _L(25) /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP                _L(6)
+#define PINMUX_PA25G_USB_DP        ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP      (_UL(1) << 25)
+#define PIN_PA23G_USB_SOF_1KHZ         _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ          _L(6)
+#define PINMUX_PA23G_USB_SOF_1KHZ  ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ  (_UL(1) << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0         _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL(1) << 16)
+#define PIN_PA00D_SERCOM1_PAD0          _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL(1) <<  0)
+#define PIN_PA17C_SERCOM1_PAD1         _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL(1) << 17)
+#define PIN_PA01D_SERCOM1_PAD1          _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL(1) <<  1)
+#define PIN_PA30D_SERCOM1_PAD2         _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL(1) << 18)
+#define PIN_PA31D_SERCOM1_PAD3         _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL(1) << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0          _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0          _L(3)
+#define PINMUX_PA08D_SERCOM2_PAD0  ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0  (_UL(1) <<  8)
+#define PIN_PA12C_SERCOM2_PAD0         _L(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL(1) << 12)
+#define PIN_PA09D_SERCOM2_PAD1          _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1          _L(3)
+#define PINMUX_PA09D_SERCOM2_PAD1  ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1  (_UL(1) <<  9)
+#define PIN_PA13C_SERCOM2_PAD1         _L(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0         _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0          _L(3)
+#define PINMUX_PA16D_SERCOM3_PAD0  ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0  (_UL(1) << 16)
+#define PIN_PA22C_SERCOM3_PAD0         _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL(1) << 22)
+#define PIN_PA17D_SERCOM3_PAD1         _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1          _L(3)
+#define PINMUX_PA17D_SERCOM3_PAD1  ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1  (_UL(1) << 17)
+#define PIN_PA23C_SERCOM3_PAD1         _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL(1) << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0         _L(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PA12D_SERCOM4_PAD0  ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PB08D_SERCOM4_PAD0         _L(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL(1) <<  8)
+#define PIN_PB12C_SERCOM4_PAD0         _L(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0          _L(2)
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0  (_UL(1) << 12)
+#define PIN_PA13D_SERCOM4_PAD1         _L(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PA13D_SERCOM4_PAD1  ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PB09D_SERCOM4_PAD1         _L(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL(1) <<  9)
+#define PIN_PB13C_SERCOM4_PAD1         _L(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1          _L(2)
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1  (_UL(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2         _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2         _L(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2          _L(2)
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2  (_UL(1) << 14)
+#define PIN_PA15D_SERCOM4_PAD3         _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL(1) << 15)
+#define PIN_PB11D_SERCOM4_PAD3         _L(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL(1) << 11)
+#define PIN_PB15C_SERCOM4_PAD3         _L(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3          _L(2)
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3  (_UL(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0         _L(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0          _L(2)
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0  (_UL(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD0         _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PA22D_SERCOM5_PAD0  ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0  (_UL(1) << 22)
+#define PIN_PB02D_SERCOM5_PAD0         _L(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL(1) <<  2)
+#define PIN_PB30D_SERCOM5_PAD0         _L(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0          _L(3)
+#define PINMUX_PB30D_SERCOM5_PAD0  ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0  (_UL(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1         _L(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1          _L(2)
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1  (_UL(1) << 17)
+#define PIN_PA23D_SERCOM5_PAD1         _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PA23D_SERCOM5_PAD1  ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1  (_UL(1) << 23)
+#define PIN_PB03D_SERCOM5_PAD1         _L(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL(1) <<  3)
+#define PIN_PB31D_SERCOM5_PAD1         _L(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1          _L(3)
+#define PINMUX_PB31D_SERCOM5_PAD1  ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1  (_UL(1) << 31)
+#define PIN_PA24D_SERCOM5_PAD2         _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2         _L(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2  (_UL(1) <<  0)
+#define PIN_PB22D_SERCOM5_PAD2         _L(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3         _L(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3  (_UL(1) <<  1)
+#define PIN_PB23D_SERCOM5_PAD3         _L(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL(1) << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0              _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0              _L(4)
+#define PINMUX_PA04E_TCC0_WO0      ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0    (_UL(1) <<  4)
+#define PIN_PA08E_TCC0_WO0              _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0              _L(4)
+#define PINMUX_PA08E_TCC0_WO0      ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0    (_UL(1) <<  8)
+#define PIN_PB30E_TCC0_WO0             _L(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0              _L(4)
+#define PINMUX_PB30E_TCC0_WO0      ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0    (_UL(1) << 30)
+#define PIN_PA05E_TCC0_WO1              _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1              _L(4)
+#define PINMUX_PA05E_TCC0_WO1      ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1    (_UL(1) <<  5)
+#define PIN_PA09E_TCC0_WO1              _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1              _L(4)
+#define PINMUX_PA09E_TCC0_WO1      ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1    (_UL(1) <<  9)
+#define PIN_PB31E_TCC0_WO1             _L(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1              _L(4)
+#define PINMUX_PB31E_TCC0_WO1      ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1    (_UL(1) << 31)
+#define PIN_PA10F_TCC0_WO2             _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL(1) << 10)
+#define PIN_PA18F_TCC0_WO2             _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2              _L(5)
+#define PINMUX_PA18F_TCC0_WO2      ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2    (_UL(1) << 18)
+#define PIN_PA11F_TCC0_WO3             _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL(1) << 11)
+#define PIN_PA19F_TCC0_WO3             _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3              _L(5)
+#define PINMUX_PA19F_TCC0_WO3      ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3    (_UL(1) << 19)
+#define PIN_PA14F_TCC0_WO4             _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4              _L(5)
+#define PINMUX_PA14F_TCC0_WO4      ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4    (_UL(1) << 14)
+#define PIN_PA22F_TCC0_WO4             _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4              _L(5)
+#define PINMUX_PA22F_TCC0_WO4      ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4    (_UL(1) << 22)
+#define PIN_PB10F_TCC0_WO4             _L(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL(1) << 10)
+#define PIN_PB16F_TCC0_WO4             _L(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4              _L(5)
+#define PINMUX_PB16F_TCC0_WO4      ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4    (_UL(1) << 16)
+#define PIN_PA15F_TCC0_WO5             _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5              _L(5)
+#define PINMUX_PA15F_TCC0_WO5      ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5    (_UL(1) << 15)
+#define PIN_PA23F_TCC0_WO5             _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5              _L(5)
+#define PINMUX_PA23F_TCC0_WO5      ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5    (_UL(1) << 23)
+#define PIN_PB11F_TCC0_WO5             _L(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL(1) << 11)
+#define PIN_PB17F_TCC0_WO5             _L(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5              _L(5)
+#define PINMUX_PB17F_TCC0_WO5      ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5    (_UL(1) << 17)
+#define PIN_PA12F_TCC0_WO6             _L(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA20F_TCC0_WO6             _L(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6              _L(5)
+#define PINMUX_PA20F_TCC0_WO6      ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6    (_UL(1) << 20)
+#define PIN_PB12F_TCC0_WO6             _L(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6              _L(5)
+#define PINMUX_PB12F_TCC0_WO6      ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6    (_UL(1) << 12)
+#define PIN_PA16F_TCC0_WO6             _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6              _L(5)
+#define PINMUX_PA16F_TCC0_WO6      ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6    (_UL(1) << 16)
+#define PIN_PA13F_TCC0_WO7             _L(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA21F_TCC0_WO7             _L(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7              _L(5)
+#define PINMUX_PA21F_TCC0_WO7      ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7    (_UL(1) << 21)
+#define PIN_PB13F_TCC0_WO7             _L(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7              _L(5)
+#define PINMUX_PB13F_TCC0_WO7      ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7    (_UL(1) << 13)
+#define PIN_PA17F_TCC0_WO7             _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7              _L(5)
+#define PINMUX_PA17F_TCC0_WO7      ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7    (_UL(1) << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0              _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0              _L(4)
+#define PINMUX_PA06E_TCC1_WO0      ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0    (_UL(1) <<  6)
+#define PIN_PA10E_TCC1_WO0             _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0              _L(4)
+#define PINMUX_PA10E_TCC1_WO0      ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0    (_UL(1) << 10)
+#define PIN_PA30E_TCC1_WO0             _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0              _L(4)
+#define PINMUX_PA30E_TCC1_WO0      ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0    (_UL(1) << 30)
+#define PIN_PA07E_TCC1_WO1              _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1              _L(4)
+#define PINMUX_PA07E_TCC1_WO1      ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1    (_UL(1) <<  7)
+#define PIN_PA11E_TCC1_WO1             _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1              _L(4)
+#define PINMUX_PA11E_TCC1_WO1      ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1    (_UL(1) << 11)
+#define PIN_PA31E_TCC1_WO1             _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1              _L(4)
+#define PINMUX_PA31E_TCC1_WO1      ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1    (_UL(1) << 31)
+#define PIN_PA08F_TCC1_WO2              _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2              _L(5)
+#define PINMUX_PA08F_TCC1_WO2      ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2    (_UL(1) <<  8)
+#define PIN_PA24F_TCC1_WO2             _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2              _L(5)
+#define PINMUX_PA24F_TCC1_WO2      ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2    (_UL(1) << 24)
+#define PIN_PB30F_TCC1_WO2             _L(62) /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2              _L(5)
+#define PINMUX_PB30F_TCC1_WO2      ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2    (_UL(1) << 30)
+#define PIN_PA09F_TCC1_WO3              _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3              _L(5)
+#define PINMUX_PA09F_TCC1_WO3      ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3    (_UL(1) <<  9)
+#define PIN_PA25F_TCC1_WO3             _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3              _L(5)
+#define PINMUX_PA25F_TCC1_WO3      ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3    (_UL(1) << 25)
+#define PIN_PB31F_TCC1_WO3             _L(63) /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3              _L(5)
+#define PINMUX_PB31F_TCC1_WO3      ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3    (_UL(1) << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0             _L(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0              _L(4)
+#define PINMUX_PA12E_TCC2_WO0      ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0    (_UL(1) << 12)
+#define PIN_PA16E_TCC2_WO0             _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0              _L(4)
+#define PINMUX_PA16E_TCC2_WO0      ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0    (_UL(1) << 16)
+#define PIN_PA00E_TCC2_WO0              _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0              _L(4)
+#define PINMUX_PA00E_TCC2_WO0      ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0    (_UL(1) <<  0)
+#define PIN_PA13E_TCC2_WO1             _L(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1              _L(4)
+#define PINMUX_PA13E_TCC2_WO1      ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1    (_UL(1) << 13)
+#define PIN_PA17E_TCC2_WO1             _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1              _L(4)
+#define PINMUX_PA17E_TCC2_WO1      ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1    (_UL(1) << 17)
+#define PIN_PA01E_TCC2_WO1              _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1              _L(4)
+#define PINMUX_PA01E_TCC2_WO1      ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1    (_UL(1) <<  1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL(1) << 14)
+#define PIN_PA19E_TC3_WO1              _L(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL(1) << 19)
+#define PIN_PA15E_TC3_WO1              _L(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL(1) <<  8)
+#define PIN_PB12E_TC4_WO0              _L(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0               _L(4)
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0     (_UL(1) << 12)
+#define PIN_PA23E_TC4_WO1              _L(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL(1) <<  9)
+#define PIN_PB13E_TC4_WO1              _L(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1               _L(4)
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1     (_UL(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL(1) << 10)
+#define PIN_PB14E_TC5_WO0              _L(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0               _L(4)
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0     (_UL(1) << 14)
+#define PIN_PA25E_TC5_WO1              _L(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL(1) << 11)
+#define PIN_PB15E_TC5_WO1              _L(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1               _L(4)
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1     (_UL(1) << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0              _L(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0               _L(4)
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0     (_UL(1) <<  2)
+#define PIN_PB16E_TC6_WO0              _L(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0               _L(4)
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0     (_UL(1) << 16)
+#define PIN_PB03E_TC6_WO1              _L(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1               _L(4)
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1     (_UL(1) <<  3)
+#define PIN_PB17E_TC6_WO1              _L(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1               _L(4)
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1     (_UL(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0              _L(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0               _L(4)
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0     (_UL(1) << 20)
+#define PIN_PB00E_TC7_WO0              _L(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0               _L(4)
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0     (_UL(1) <<  0)
+#define PIN_PB22E_TC7_WO0              _L(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0               _L(4)
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0     (_UL(1) << 22)
+#define PIN_PA21E_TC7_WO1              _L(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1               _L(4)
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1     (_UL(1) << 21)
+#define PIN_PB01E_TC7_WO1              _L(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1               _L(4)
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1     (_UL(1) <<  1)
+#define PIN_PB23E_TC7_WO1              _L(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1               _L(4)
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1     (_UL(1) << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0              _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0              _L(1)
+#define PINMUX_PA02B_ADC_AIN0      ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0    (_UL(1) <<  2)
+#define PIN_PA03B_ADC_AIN1              _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1              _L(1)
+#define PINMUX_PA03B_ADC_AIN1      ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1    (_UL(1) <<  3)
+#define PIN_PB08B_ADC_AIN2             _L(40) /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2              _L(1)
+#define PINMUX_PB08B_ADC_AIN2      ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2    (_UL(1) <<  8)
+#define PIN_PB09B_ADC_AIN3             _L(41) /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3              _L(1)
+#define PINMUX_PB09B_ADC_AIN3      ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3    (_UL(1) <<  9)
+#define PIN_PA04B_ADC_AIN4              _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4              _L(1)
+#define PINMUX_PA04B_ADC_AIN4      ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4    (_UL(1) <<  4)
+#define PIN_PA05B_ADC_AIN5              _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5              _L(1)
+#define PINMUX_PA05B_ADC_AIN5      ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5    (_UL(1) <<  5)
+#define PIN_PA06B_ADC_AIN6              _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6              _L(1)
+#define PINMUX_PA06B_ADC_AIN6      ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6    (_UL(1) <<  6)
+#define PIN_PA07B_ADC_AIN7              _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7              _L(1)
+#define PINMUX_PA07B_ADC_AIN7      ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7    (_UL(1) <<  7)
+#define PIN_PB00B_ADC_AIN8             _L(32) /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8              _L(1)
+#define PINMUX_PB00B_ADC_AIN8      ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8    (_UL(1) <<  0)
+#define PIN_PB01B_ADC_AIN9             _L(33) /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9              _L(1)
+#define PINMUX_PB01B_ADC_AIN9      ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9    (_UL(1) <<  1)
+#define PIN_PB02B_ADC_AIN10            _L(34) /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10             _L(1)
+#define PINMUX_PB02B_ADC_AIN10     ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10   (_UL(1) <<  2)
+#define PIN_PB03B_ADC_AIN11            _L(35) /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11             _L(1)
+#define PINMUX_PB03B_ADC_AIN11     ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11   (_UL(1) <<  3)
+#define PIN_PB04B_ADC_AIN12            _L(36) /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12             _L(1)
+#define PINMUX_PB04B_ADC_AIN12     ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12   (_UL(1) <<  4)
+#define PIN_PB05B_ADC_AIN13            _L(37) /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13             _L(1)
+#define PINMUX_PB05B_ADC_AIN13     ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13   (_UL(1) <<  5)
+#define PIN_PB06B_ADC_AIN14            _L(38) /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14             _L(1)
+#define PINMUX_PB06B_ADC_AIN14     ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14   (_UL(1) <<  6)
+#define PIN_PB07B_ADC_AIN15            _L(39) /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15             _L(1)
+#define PINMUX_PB07B_ADC_AIN15     ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15   (_UL(1) <<  7)
+#define PIN_PA08B_ADC_AIN16             _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16             _L(1)
+#define PINMUX_PA08B_ADC_AIN16     ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16   (_UL(1) <<  8)
+#define PIN_PA09B_ADC_AIN17             _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17             _L(1)
+#define PINMUX_PA09B_ADC_AIN17     ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17   (_UL(1) <<  9)
+#define PIN_PA10B_ADC_AIN18            _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18             _L(1)
+#define PINMUX_PA10B_ADC_AIN18     ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18   (_UL(1) << 10)
+#define PIN_PA11B_ADC_AIN19            _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19             _L(1)
+#define PINMUX_PA11B_ADC_AIN19     ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19   (_UL(1) << 11)
+#define PIN_PA04B_ADC_VREFP             _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP             _L(1)
+#define PINMUX_PA04B_ADC_VREFP     ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP   (_UL(1) <<  4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL(1) <<  7)
+#define PIN_PA12H_AC_CMP0              _L(12) /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0               _L(7)
+#define PINMUX_PA12H_AC_CMP0       ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0     (_UL(1) << 12)
+#define PIN_PA18H_AC_CMP0              _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0               _L(7)
+#define PINMUX_PA18H_AC_CMP0       ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0     (_UL(1) << 18)
+#define PIN_PA13H_AC_CMP1              _L(13) /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1               _L(7)
+#define PINMUX_PA13H_AC_CMP1       ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1     (_UL(1) << 13)
+#define PIN_PA19H_AC_CMP1              _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1               _L(7)
+#define PINMUX_PA19H_AC_CMP1       ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1     (_UL(1) << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT              _L(2) /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT              _L(1)
+#define PINMUX_PA02B_DAC_VOUT      ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT    (_UL(1) <<  2)
+#define PIN_PA03B_DAC_VREFP             _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP             _L(1)
+#define PINMUX_PA03B_DAC_VREFP     ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP   (_UL(1) <<  3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0              _L(11) /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0               _L(6)
+#define PINMUX_PA11G_I2S_FS0       ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0     (_UL(1) << 11)
+#define PIN_PA21G_I2S_FS0              _L(21) /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0               _L(6)
+#define PINMUX_PA21G_I2S_FS0       ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0     (_UL(1) << 21)
+#define PIN_PB12G_I2S_FS1              _L(44) /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1               _L(6)
+#define PINMUX_PB12G_I2S_FS1       ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1     (_UL(1) << 12)
+#define PIN_PA09G_I2S_MCK0              _L(9) /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0              _L(6)
+#define PINMUX_PA09G_I2S_MCK0      ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0    (_UL(1) <<  9)
+#define PIN_PB17G_I2S_MCK0             _L(49) /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0              _L(6)
+#define PINMUX_PB17G_I2S_MCK0      ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0    (_UL(1) << 17)
+#define PIN_PB10G_I2S_MCK1             _L(42) /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1              _L(6)
+#define PINMUX_PB10G_I2S_MCK1      ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1    (_UL(1) << 10)
+#define PIN_PA10G_I2S_SCK0             _L(10) /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0              _L(6)
+#define PINMUX_PA10G_I2S_SCK0      ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0    (_UL(1) << 10)
+#define PIN_PA20G_I2S_SCK0             _L(20) /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0              _L(6)
+#define PINMUX_PA20G_I2S_SCK0      ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0    (_UL(1) << 20)
+#define PIN_PB11G_I2S_SCK1             _L(43) /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1              _L(6)
+#define PINMUX_PB11G_I2S_SCK1      ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1    (_UL(1) << 11)
+#define PIN_PA07G_I2S_SD0               _L(7) /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0               _L(6)
+#define PINMUX_PA07G_I2S_SD0       ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0     (_UL(1) <<  7)
+#define PIN_PA19G_I2S_SD0              _L(19) /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0               _L(6)
+#define PINMUX_PA19G_I2S_SD0       ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0     (_UL(1) << 19)
+#define PIN_PA08G_I2S_SD1               _L(8) /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1               _L(6)
+#define PINMUX_PA08G_I2S_SD1       ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1     (_UL(1) <<  8)
+#define PIN_PB16G_I2S_SD1              _L(48) /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1               _L(6)
+#define PINMUX_PB16G_I2S_SD1       ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1     (_UL(1) << 16)
+
+#endif /* _SAMD21J18A_PIO_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/sam.h b/uf2-samdx1/lib/samd21/samd21a/include/sam.h
new file mode 100644
index 00000000..684510b9
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/sam.h
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Top level header file
+ *
+ * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \license_stop
+ *
+ */
+
+#ifndef _SAM_
+#define _SAM_
+
+#if   defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
+  #include "samd21e15a.h"
+#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
+  #include "samd21e16a.h"
+#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
+  #include "samd21e17a.h"
+#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
+  #include "samd21e18a.h"
+#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
+  #include "samd21g15a.h"
+#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
+  #include "samd21g16a.h"
+#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
+  #include "samd21g17a.h"
+#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
+  #include "samd21g17au.h"
+#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
+  #include "samd21g18a.h"
+#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
+  #include "samd21g18au.h"
+#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
+  #include "samd21j15a.h"
+#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
+  #include "samd21j16a.h"
+#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
+  #include "samd21j17a.h"
+#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
+  #include "samd21j18a.h"
+#else
+  #error Library does not support the specified device
+#endif
+
+#endif /* _SAM_ */
+
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21.h
new file mode 100644
index 00000000..afe84d4f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21.h
@@ -0,0 +1,69 @@
+/**
+ * \file
+ *
+ * \brief Top header file for SAMD21
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_
+#define _SAMD21_
+
+/**
+ * \defgroup SAMD21_definitions SAMD21 Device Definitions
+ * \brief SAMD21 CMSIS Definitions.
+ */
+
+#if   defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
+  #include "samd21e15a.h"
+#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
+  #include "samd21e16a.h"
+#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
+  #include "samd21e17a.h"
+#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
+  #include "samd21e18a.h"
+#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
+  #include "samd21g15a.h"
+#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
+  #include "samd21g16a.h"
+#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
+  #include "samd21g17a.h"
+#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
+  #include "samd21g17au.h"
+#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
+  #include "samd21g18a.h"
+#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
+  #include "samd21g18au.h"
+#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
+  #include "samd21j15a.h"
+#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
+  #include "samd21j16a.h"
+#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
+  #include "samd21j17a.h"
+#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
+  #include "samd21j18a.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAMD21_ */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21e15a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21e15a.h
new file mode 100644
index 00000000..3a3d5d52
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21e15a.h
@@ -0,0 +1,552 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15A_
+#define _SAMD21E15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15A_definitions SAMD21E15A definitions
+ * This file defines all structures and symbols for SAMD21E15A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E15A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E15A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E15A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E15A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E15A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E15A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E15A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E15A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E15A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00008000) /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00001000) /* 4 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x1001030D)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21e16a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21e16a.h
new file mode 100644
index 00000000..7bb07c66
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21e16a.h
@@ -0,0 +1,552 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16A_
+#define _SAMD21E16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions
+ * This file defines all structures and symbols for SAMD21E16A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E16A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E16A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E16A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E16A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E16A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E16A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E16A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E16A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E16A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00010000) /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00002000) /* 8 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x1001030C)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21e17a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21e17a.h
new file mode 100644
index 00000000..df037351
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21e17a.h
@@ -0,0 +1,552 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17A_
+#define _SAMD21E17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions
+ * This file defines all structures and symbols for SAMD21E17A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E17A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E17A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E17A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E17A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E17A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E17A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E17A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E17A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E17A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x1001030B)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E17A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21e18a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21e18a.h
new file mode 100644
index 00000000..8e7bcb7f
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21e18a.h
@@ -0,0 +1,552 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E18A_
+#define _SAMD21E18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions
+ * This file defines all structures and symbols for SAMD21E18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21E18A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21E18A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21E18A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21E18A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21E18A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21E18A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21E18A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21E18A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21E18A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM   4                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00040000) /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00008000) /* 32 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x1001030A)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           1
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E18A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21g15a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21g15a.h
new file mode 100644
index 00000000..5131ac4c
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21g15a.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15A_
+#define _SAMD21G15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions
+ * This file defines all structures and symbols for SAMD21G15A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G15A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G15A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G15A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G15A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G15A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G15A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G15A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G15A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G15A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00008000) /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00001000) /* 4 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x10010308)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21g16a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21g16a.h
new file mode 100644
index 00000000..10212802
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21g16a.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16A_
+#define _SAMD21G16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions
+ * This file defines all structures and symbols for SAMD21G16A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G16A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G16A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G16A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G16A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G16A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G16A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G16A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G16A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G16A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00010000) /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00002000) /* 8 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x10010307)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21g17a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21g17a.h
new file mode 100644
index 00000000..dc3b1612
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21g17a.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17A_
+#define _SAMD21G17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions
+ * This file defines all structures and symbols for SAMD21G17A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G17A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G17A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G17A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G17A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G17A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G17A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G17A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G17A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x10010306)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21g17au.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21g17au.h
new file mode 100644
index 00000000..46225b3b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21g17au.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17AU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17AU_
+#define _SAMD21G17AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions
+ * This file defines all structures and symbols for SAMD21G17AU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G17AU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G17AU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G17AU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G17AU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G17AU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G17AU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G17AU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G17AU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x10010310)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17AU_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21g18a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21g18a.h
new file mode 100644
index 00000000..2840b6e1
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21g18a.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18A_
+#define _SAMD21G18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions
+ * This file defines all structures and symbols for SAMD21G18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G18A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G18A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G18A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G18A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G18A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G18A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G18A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G18A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G18A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pvReserved21;
+  void* pvReserved22;
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       3                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5 }          /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00040000) /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00008000) /* 32 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x10010305)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21g18au.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21g18au.h
new file mode 100644
index 00000000..82c2532b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21g18au.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18AU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18AU_
+#define _SAMD21G18AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions
+ * This file defines all structures and symbols for SAMD21G18AU:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21G18AU-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21G18AU Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21G18AU System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21G18AU Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21G18AU Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21G18AU External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21G18AU Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21G18AU Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00040000) /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00008000) /* 32 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x1001030F)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18AU_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21j15a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21j15a.h
new file mode 100644
index 00000000..80aba23e
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21j15a.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15A_
+#define _SAMD21J15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions
+ * This file defines all structures and symbols for SAMD21J15A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J15A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J15A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J15A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J15A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J15A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J15A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J15A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J15A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J15A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00008000) /* 32 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00001000) /* 4 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x10010303)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J15A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21j16a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21j16a.h
new file mode 100644
index 00000000..b054d7ed
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21j16a.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16A_
+#define _SAMD21J16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions
+ * This file defines all structures and symbols for SAMD21J16A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J16A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J16A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J16A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J16A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J16A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J16A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J16A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J16A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J16A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00010000) /* 64 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00002000) /* 8 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x10010302)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J16A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21j17a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21j17a.h
new file mode 100644
index 00000000..bc85d930
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21j17a.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17A_
+#define _SAMD21J17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions
+ * This file defines all structures and symbols for SAMD21J17A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J17A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J17A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J17A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J17A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J17A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J17A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J17A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J17A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J17A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x10010301)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J17A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/samd21j18a.h b/uf2-samdx1/lib/samd21/samd21a/include/samd21j18a.h
new file mode 100644
index 00000000..ee9a8fa1
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/samd21j18a.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J18A_
+#define _SAMD21J18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions
+ * This file defines all structures and symbols for SAMD21J18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x)          x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L(x)          x ## L            /**< C code: Long integer literal constant value */
+#define _UL(x)         x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x)          x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L(x)          x                 /**< Assembler: Long integer literal constant value */
+#define _UL(x)         x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M0+ Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                 */
+  HardFault_IRQn           = -13,/**<  3 Cortex-M0+ Hard Fault Interrupt        */
+  SVCall_IRQn              = -5, /**< 11 Cortex-M0+ SV Call Interrupt           */
+  PendSV_IRQn              = -2, /**< 14 Cortex-M0+ Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 Cortex-M0+ System Tick Interrupt       */
+  /******  SAMD21J18A-specific Interrupt Numbers ***********************/
+  PM_IRQn                  =  0, /**<  0 SAMD21J18A Power Manager (PM) */
+  SYSCTRL_IRQn             =  1, /**<  1 SAMD21J18A System Control (SYSCTRL) */
+  WDT_IRQn                 =  2, /**<  2 SAMD21J18A Watchdog Timer (WDT) */
+  RTC_IRQn                 =  3, /**<  3 SAMD21J18A Real-Time Counter (RTC) */
+  EIC_IRQn                 =  4, /**<  4 SAMD21J18A External Interrupt Controller (EIC) */
+  NVMCTRL_IRQn             =  5, /**<  5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_IRQn                =  6, /**<  6 SAMD21J18A Direct Memory Access Controller (DMAC) */
+  USB_IRQn                 =  7, /**<  7 SAMD21J18A Universal Serial Bus (USB) */
+  EVSYS_IRQn               =  8, /**<  8 SAMD21J18A Event System Interface (EVSYS) */
+  SERCOM0_IRQn             =  9, /**<  9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
+  SERCOM1_IRQn             = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
+  SERCOM2_IRQn             = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
+  SERCOM3_IRQn             = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
+  SERCOM4_IRQn             = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
+  SERCOM5_IRQn             = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
+  TCC0_IRQn                = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
+  TCC1_IRQn                = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
+  TCC2_IRQn                = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
+  TC3_IRQn                 = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
+  ADC_IRQn                 = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
+  AC_IRQn                  = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
+  DAC_IRQn                 = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
+  PTC_IRQn                 = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
+  I2S_IRQn                 = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
+
+  PERIPH_COUNT_IRQn        = 28  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pvReservedM12;
+  void* pvReservedM11;
+  void* pvReservedM10;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVC_Handler;
+  void* pvReservedM4;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnSYSCTRL_Handler;               /*  1 System Control */
+  void* pfnWDT_Handler;                   /*  2 Watchdog Timer */
+  void* pfnRTC_Handler;                   /*  3 Real-Time Counter */
+  void* pfnEIC_Handler;                   /*  4 External Interrupt Controller */
+  void* pfnNVMCTRL_Handler;               /*  5 Non-Volatile Memory Controller */
+  void* pfnDMAC_Handler;                  /*  6 Direct Memory Access Controller */
+  void* pfnUSB_Handler;                   /*  7 Universal Serial Bus */
+  void* pfnEVSYS_Handler;                 /*  8 Event System Interface */
+  void* pfnSERCOM0_Handler;               /*  9 Serial Communication Interface 0 */
+  void* pfnSERCOM1_Handler;               /* 10 Serial Communication Interface 1 */
+  void* pfnSERCOM2_Handler;               /* 11 Serial Communication Interface 2 */
+  void* pfnSERCOM3_Handler;               /* 12 Serial Communication Interface 3 */
+  void* pfnSERCOM4_Handler;               /* 13 Serial Communication Interface 4 */
+  void* pfnSERCOM5_Handler;               /* 14 Serial Communication Interface 5 */
+  void* pfnTCC0_Handler;                  /* 15 Timer Counter Control 0 */
+  void* pfnTCC1_Handler;                  /* 16 Timer Counter Control 1 */
+  void* pfnTCC2_Handler;                  /* 17 Timer Counter Control 2 */
+  void* pfnTC3_Handler;                   /* 18 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 19 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 20 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 21 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 22 Basic Timer Counter 7 */
+  void* pfnADC_Handler;                   /* 23 Analog Digital Converter */
+  void* pfnAC_Handler;                    /* 24 Analog Comparators */
+  void* pfnDAC_Handler;                   /* 25 Digital Analog Converter */
+  void* pfnPTC_Handler;                   /* 26 Peripheral Touch Controller */
+  void* pfnI2S_Handler;                   /* 27 Inter-IC Sound Interface */
+  void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler               ( void );
+void NMI_Handler                 ( void );
+void HardFault_Handler           ( void );
+void SVC_Handler                 ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void SYSCTRL_Handler             ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_Handler                 ( void );
+void NVMCTRL_Handler             ( void );
+void DMAC_Handler                ( void );
+void USB_Handler                 ( void );
+void EVSYS_Handler               ( void );
+void SERCOM0_Handler             ( void );
+void SERCOM1_Handler             ( void );
+void SERCOM2_Handler             ( void );
+void SERCOM3_Handler             ( void );
+void SERCOM4_Handler             ( void );
+void SERCOM5_Handler             ( void );
+void TCC0_Handler                ( void );
+void TCC1_Handler                ( void );
+void TCC2_Handler                ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void ADC_Handler                 ( void );
+void AC_Handler                  ( void );
+void DAC_Handler                 ( void );
+void PTC_Handler                 ( void );
+void I2S_Handler                 ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN          1        
+#define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
+#define __MPU_PRESENT          0         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK           3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT          35 /**< \brief Port Module (PORT) */
+#define ID_DMAC          36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB           37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2       68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4       70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0          72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2          74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3           75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4           76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6           78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7           79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC           80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC            81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC           82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC           83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S           84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT  85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC                           (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC                           (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK                          (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX                      (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S                           (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB                           (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0                          (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1                          (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2                          (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS                    (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC                           (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC                           (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0                       (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL                       (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3                           (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB                           (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC               ((Adc      *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM      1                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC }                    /**< \brief (ADC) Instances List */
+
+#define DAC               ((Dac      *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define GCLK              ((Gclk     *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX          ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { SBMATRIX }               /**< \brief (HMATRIXB) Instances List */
+
+#define I2S               ((I2s      *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MTB               ((Mtb      *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM      1                          /**< \brief (MTB) Number of instances */
+#define MTB_INSTS         { MTB }                    /**< \brief (MTB) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL                   (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT               (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1                  (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2                  (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4                  (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0              ((Pac      *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1              ((Pac      *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2              ((Pac      *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM      3                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC0, PAC1, PAC2 }       /**< \brief (PAC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS        ((Port     *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1                          /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS  { PORT_IOBUS }             /**< \brief (PORT) Instances List */
+
+#define PTC               ((void     *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID       34
+#define PTC_INST_NUM      1                          /**< \brief (PTC) Number of instances */
+#define PTC_INSTS         { PTC }                    /**< \brief (PTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL           ((Sysctrl  *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM  1                          /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS     { SYSCTRL }                /**< \brief (SYSCTRL) Instances List */
+
+#define TC3               ((Tc       *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       5                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM      3                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2 }       /**< \brief (TCC) Instances List */
+
+#define USB               ((Usb      *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE            _UL(0x00040000) /* 256 kB */
+#define FLASH_PAGE_SIZE       64
+#define FLASH_NB_OF_PAGES     4096
+#define FLASH_USER_PAGE_SIZE  64
+#define HMCRAMC0_SIZE         _UL(0x00008000) /* 32 kB */
+
+#define FLASH_ADDR            _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR  _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR         _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR             _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR              _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL(0x10010300)
+#define EIC_EXTINT_NUM        16
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J18A_H */
diff --git a/uf2-samdx1/lib/samd21/samd21a/include/system_samd21.h b/uf2-samdx1/lib/samd21/samd21a/include/system_samd21.h
new file mode 100644
index 00000000..223911ce
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/include/system_samd21.h
@@ -0,0 +1,47 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SYSTEM_SAMD21_H_INCLUDED_
+#define _SYSTEM_SAMD21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;   /*!< System Clock Frequency (Core Clock)  */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAMD21_H_INCLUDED */
diff --git a/uf2-samdx1/lib/samd21/samd21a/keil/Flash/ATSAMD21_128.FLM b/uf2-samdx1/lib/samd21/samd21a/keil/Flash/ATSAMD21_128.FLM
new file mode 100644
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diff --git a/uf2-samdx1/lib/samd21/samd21a/keil/Flash/ATSAMD21_64.FLM b/uf2-samdx1/lib/samd21/samd21a/keil/Flash/ATSAMD21_64.FLM
new file mode 100644
index 0000000000000000000000000000000000000000..fe35451372260216ed86b6dd0660ba6ad75ba286
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HcmV?d00001

diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E15A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E15A.svd
new file mode 100644
index 00000000..a3517545
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E15A.svd
@@ -0,0 +1,19401 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21E15A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21E15A device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 32-pin package (refer to http://www.atmel.com/devices/SAMD21E15A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x1001030D</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E16A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E16A.svd
new file mode 100644
index 00000000..cf4d7479
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E16A.svd
@@ -0,0 +1,19401 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21E16A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21E16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 32-pin package (refer to http://www.atmel.com/devices/SAMD21E16A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x1001030C</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E17A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E17A.svd
new file mode 100644
index 00000000..68f6dd92
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E17A.svd
@@ -0,0 +1,19401 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21E17A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21E17A device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 32-pin package (refer to http://www.atmel.com/devices/SAMD21E17A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x1001030B</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E18A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E18A.svd
new file mode 100644
index 00000000..dba06dd9
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21E18A.svd
@@ -0,0 +1,19401 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21E18A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21E18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 32-pin package (refer to http://www.atmel.com/devices/SAMD21E18A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x1001030A</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G15A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G15A.svd
new file mode 100644
index 00000000..d358fc3e
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G15A.svd
@@ -0,0 +1,19445 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21G15A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21G15A device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 48-pin package (refer to http://www.atmel.com/devices/SAMD21G15A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10010308</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G16A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G16A.svd
new file mode 100644
index 00000000..28463744
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G16A.svd
@@ -0,0 +1,19445 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21G16A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21G16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 48-pin package (refer to http://www.atmel.com/devices/SAMD21G16A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10010307</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G17A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G17A.svd
new file mode 100644
index 00000000..b8d912db
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G17A.svd
@@ -0,0 +1,19445 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21G17A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21G17A device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 48-pin package (refer to http://www.atmel.com/devices/SAMD21G17A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10010306</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G17AU.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G17AU.svd
new file mode 100644
index 00000000..b3bb1d8b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G17AU.svd
@@ -0,0 +1,19475 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21G17AU</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21G17AU device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 45-pin package (refer to http://www.atmel.com/devices/SAMD21G17AU.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10010310</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC6_</name>
+              <description>TC6 APB Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC7_</name>
+              <description>TC7 APB Clock Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC6</name>
+      <description>Basic Timer Counter 6</description>
+      <baseAddress>0x42003800</baseAddress>
+      <interrupt>
+        <name>TC6_INTREQ</name>
+        <value>21</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC7</name>
+      <description>Basic Timer Counter 7</description>
+      <baseAddress>0x42003C00</baseAddress>
+      <interrupt>
+        <name>TC7_INTREQ</name>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G18A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G18A.svd
new file mode 100644
index 00000000..08177614
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G18A.svd
@@ -0,0 +1,19445 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21G18A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21G18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 48-pin package (refer to http://www.atmel.com/devices/SAMD21G18A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10010305</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G18AU.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G18AU.svd
new file mode 100644
index 00000000..5a6b31a0
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21G18AU.svd
@@ -0,0 +1,19475 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21G18AU</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21G18AU device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 45-pin package (refer to http://www.atmel.com/devices/SAMD21G18AU.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x1001030F</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC6_</name>
+              <description>TC6 APB Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC7_</name>
+              <description>TC7 APB Clock Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC6</name>
+      <description>Basic Timer Counter 6</description>
+      <baseAddress>0x42003800</baseAddress>
+      <interrupt>
+        <name>TC6_INTREQ</name>
+        <value>21</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC7</name>
+      <description>Basic Timer Counter 7</description>
+      <baseAddress>0x42003C00</baseAddress>
+      <interrupt>
+        <name>TC7_INTREQ</name>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J15A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J15A.svd
new file mode 100644
index 00000000..f06661f3
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J15A.svd
@@ -0,0 +1,19475 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21J15A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21J15A device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 64-pin package (refer to http://www.atmel.com/devices/SAMD21J15A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10010303</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC6_</name>
+              <description>TC6 APB Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC7_</name>
+              <description>TC7 APB Clock Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC6</name>
+      <description>Basic Timer Counter 6</description>
+      <baseAddress>0x42003800</baseAddress>
+      <interrupt>
+        <name>TC6_INTREQ</name>
+        <value>21</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC7</name>
+      <description>Basic Timer Counter 7</description>
+      <baseAddress>0x42003C00</baseAddress>
+      <interrupt>
+        <name>TC7_INTREQ</name>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J16A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J16A.svd
new file mode 100644
index 00000000..d596484b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J16A.svd
@@ -0,0 +1,19475 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21J16A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21J16A device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 64-pin package (refer to http://www.atmel.com/devices/SAMD21J16A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10010302</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC6_</name>
+              <description>TC6 APB Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC7_</name>
+              <description>TC7 APB Clock Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC6</name>
+      <description>Basic Timer Counter 6</description>
+      <baseAddress>0x42003800</baseAddress>
+      <interrupt>
+        <name>TC6_INTREQ</name>
+        <value>21</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC7</name>
+      <description>Basic Timer Counter 7</description>
+      <baseAddress>0x42003C00</baseAddress>
+      <interrupt>
+        <name>TC7_INTREQ</name>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J17A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J17A.svd
new file mode 100644
index 00000000..ef7abd1b
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J17A.svd
@@ -0,0 +1,19475 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21J17A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21J17A device: Cortex-M0+ Microcontroller with 128KB Flash, 16KB SRAM, 64-pin package (refer to http://www.atmel.com/devices/SAMD21J17A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10010301</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC6_</name>
+              <description>TC6 APB Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC7_</name>
+              <description>TC7 APB Clock Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC6</name>
+      <description>Basic Timer Counter 6</description>
+      <baseAddress>0x42003800</baseAddress>
+      <interrupt>
+        <name>TC6_INTREQ</name>
+        <value>21</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC7</name>
+      <description>Basic Timer Counter 7</description>
+      <baseAddress>0x42003C00</baseAddress>
+      <interrupt>
+        <name>TC7_INTREQ</name>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J18A.svd b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J18A.svd
new file mode 100644
index 00000000..c175fb18
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/svd/ATSAMD21J18A.svd
@@ -0,0 +1,19475 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <vendor>Atmel Corporation</vendor>
+  <vendorID>ATMEL</vendorID>
+  <name>ATSAMD21J18A</name>
+  <series>SAMD21</series>
+  <version>D</version>
+  <description>Atmel ATSAMD21J18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 64-pin package (refer to http://www.atmel.com/devices/SAMD21J18A.aspx for more)</description>
+  <licenseText>
+  ============================================================================\n
+                   Atmel Microcontroller Software Support\n
+  ============================================================================\n
+  Copyright (c) 2016 Atmel Corporation,\n
+                     a wholly owned subsidiary of Microchip Technology Inc.\n
+\n
+  Licensed under the Apache License, Version 2.0 (the "License");\n
+  you may not use this file except in compliance with the License.\n
+  You may obtain a copy of the Licence at\n
+\n
+      http://www.apache.org/licenses/LICENSE-2.0\n
+\n
+  Unless required by applicable law or agreed to in writing, software\n
+  distributed under the License is distributed on an "AS IS" BASIS,\n
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
+  See the License for the specific language governing permissions and\n
+  limitations under the License.\n
+  ============================================================================
+  </licenseText>
+  <cpu>
+    <name>CM0+</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <vtorPresent>true</vtorPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <headerSystemFilename>system_samd21</headerSystemFilename>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AC</name>
+      <version>1.1.1</version>
+      <description>Analog Comparators</description>
+      <groupName>AC</groupName>
+      <prependToName>AC_</prependToName>
+      <baseAddress>0x42004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AC_INTREQ</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMUX</name>
+              <description>Low-Power Mux</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>START0</name>
+              <description>Comparator 0 Start Comparison</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START1</name>
+              <description>Comparator 1 Start Comparison</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMPEO0</name>
+              <description>Comparator 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEO1</name>
+              <description>Comparator 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINEO0</name>
+              <description>Window 0 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI0</name>
+              <description>Comparator 0 Event Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMPEI1</name>
+              <description>Comparator 1 Event Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COMP0</name>
+              <description>Comparator 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COMP1</name>
+              <description>Comparator 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WIN0</name>
+              <description>Window 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>READY0</name>
+              <description>Comparator 0 Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>READY1</name>
+              <description>Comparator 1 Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSC</name>
+          <description>Status C</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <description>Comparator 0 Current State</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATE1</name>
+              <description>Comparator 1 Current State</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WSTATE0</name>
+              <description>Window 0 Current State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WSTATE0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Signal is above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Signal is inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Signal is below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Control</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WEN0</name>
+              <description>Window 0 Mode Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINTSEL0</name>
+              <description>Window 0 Interrupt Selection</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WINTSEL0Select</name>
+                <enumeratedValue>
+                  <name>ABOVE</name>
+                  <description>Interrupt on signal above window</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INSIDE</name>
+                  <description>Interrupt on signal inside window</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BELOW</name>
+                  <description>Interrupt on signal below window</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OUTSIDE</name>
+                  <description>Interrupt on signal outside window</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMPCTRL%s</name>
+          <description>Comparator Control n</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SINGLE</name>
+              <description>Single-Shot Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTSEL</name>
+              <description>Interrupt Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>INTSELSelect</name>
+                <enumeratedValue>
+                  <name>TOGGLE</name>
+                  <description>Interrupt on comparator output toggle</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Interrupt on comparator output rising</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Interrupt on comparator output falling</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EOC</name>
+                  <description>Interrupt on end of comparison (single-shot mode only)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Input Mux Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Ground</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VSCALE</name>
+                  <description>VDD scaler</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Internal bandgap voltage</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Input Mux Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>I/O pin 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>I/O pin 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>I/O pin 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>I/O pin 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SWAP</name>
+              <description>Swap Inputs and Invert</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OUT</name>
+              <description>Output</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>OUTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>The output of COMPn is not routed to the COMPn I/O port</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNC</name>
+                  <description>The asynchronous output of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SYNC</name>
+                  <description>The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FLEN</name>
+              <description>Filter Length</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>FLENSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>No filtering</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ3</name>
+                  <description>3-bit majority function (2 of 3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MAJ5</name>
+                  <description>5-bit majority function (3 of 5)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>SCALER%s</name>
+          <description>Scaler n</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Scaler Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ADC</name>
+      <version>1.2.0</version>
+      <description>Analog Digital Converter</description>
+      <groupName>ADC</groupName>
+      <prependToName>ADC_</prependToName>
+      <baseAddress>0x42004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ADC_INTREQ</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REFCTRL</name>
+          <description>Reference Control</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>1.0V voltage reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC0</name>
+                  <description>1/1.48 VDDANA</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTVCC1</name>
+                  <description>1/2 VDDANA (only for VDDANA &gt; 2.0V)</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFA</name>
+                  <description>External reference</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AREFB</name>
+                  <description>External reference</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>REFCOMP</name>
+              <description>Reference Buffer Offset Compensation Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AVGCTRL</name>
+          <description>Average Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLENUM</name>
+              <description>Number of Samples to be Collected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>SAMPLENUMSelect</name>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>1 sample</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>2 samples</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>4 samples</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 samples</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 samples</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 samples</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 samples</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 samples</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 samples</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 samples</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 samples</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ADJRES</name>
+              <description>Adjusting Result / Division Coefficient</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPCTRL</name>
+          <description>Sampling Time Control</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SAMPLEN</name>
+              <description>Sampling Time Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DIFFMODE</name>
+              <description>Differential Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left-Adjusted Result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FREERUN</name>
+              <description>Free Running Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CORREN</name>
+              <description>Digital Correction Logic Enabled</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESSEL</name>
+              <description>Conversion Result Resolution</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESSELSelect</name>
+                <enumeratedValue>
+                  <name>12BIT</name>
+                  <description>12-bit result</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16BIT</name>
+                  <description>For averaging mode output</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10BIT</name>
+                  <description>10-bit result</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8BIT</name>
+                  <description>8-bit result</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Peripheral clock divided by 4</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Peripheral clock divided by 8</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Peripheral clock divided by 16</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Peripheral clock divided by 32</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Peripheral clock divided by 64</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Peripheral clock divided by 128</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Peripheral clock divided by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Peripheral clock divided by 512</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINCTRL</name>
+          <description>Window Monitor Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>WINMODE</name>
+              <description>Window Monitor Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WINMODESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No window mode (default)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE1</name>
+                  <description>Mode 1: RESULT &gt; WINLT</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE2</name>
+                  <description>Mode 2: RESULT &lt; WINUT</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE3</name>
+                  <description>Mode 3: WINLT &lt; RESULT &lt; WINUT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MODE4</name>
+                  <description>Mode 4: !(WINLT &lt; RESULT &lt; WINUT)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIG</name>
+          <description>Software Trigger</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLUSH</name>
+              <description>ADC Conversion Flush</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>START</name>
+              <description>ADC Start Conversion</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INPUTCTRL</name>
+          <description>Input Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUXPOS</name>
+              <description>Positive Mux Input Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXPOSSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN8</name>
+                  <description>ADC AIN8 Pin</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN9</name>
+                  <description>ADC AIN9 Pin</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN10</name>
+                  <description>ADC AIN10 Pin</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN11</name>
+                  <description>ADC AIN11 Pin</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN12</name>
+                  <description>ADC AIN12 Pin</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN13</name>
+                  <description>ADC AIN13 Pin</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN14</name>
+                  <description>ADC AIN14 Pin</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN15</name>
+                  <description>ADC AIN15 Pin</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN16</name>
+                  <description>ADC AIN16 Pin</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN17</name>
+                  <description>ADC AIN17 Pin</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN18</name>
+                  <description>ADC AIN18 Pin</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN19</name>
+                  <description>ADC AIN19 Pin</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TEMP</name>
+                  <description>Temperature Reference</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BANDGAP</name>
+                  <description>Bandgap Voltage</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDCOREVCC</name>
+                  <description>1/4  Scaled Core Supply</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCALEDIOVCC</name>
+                  <description>1/4  Scaled I/O Supply</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC Output</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MUXNEG</name>
+              <description>Negative Mux Input Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>MUXNEGSelect</name>
+                <enumeratedValue>
+                  <name>PIN0</name>
+                  <description>ADC AIN0 Pin</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN1</name>
+                  <description>ADC AIN1 Pin</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN2</name>
+                  <description>ADC AIN2 Pin</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN3</name>
+                  <description>ADC AIN3 Pin</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN4</name>
+                  <description>ADC AIN4 Pin</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN5</name>
+                  <description>ADC AIN5 Pin</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN6</name>
+                  <description>ADC AIN6 Pin</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PIN7</name>
+                  <description>ADC AIN7 Pin</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GND</name>
+                  <description>Internal Ground</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IOGND</name>
+                  <description>I/O Ground</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INPUTSCAN</name>
+              <description>Number of Input Channels Included in Scan</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>INPUTOFFSET</name>
+              <description>Positive Mux Setting Offset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Gain Factor Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>1X</name>
+                  <description>1x</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2X</name>
+                  <description>2x</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4X</name>
+                  <description>4x</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8X</name>
+                  <description>8x</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16X</name>
+                  <description>16x</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>1/2x</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event In</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCEI</name>
+              <description>Synchronization Event In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESRDYEO</name>
+              <description>Result Ready Event Out</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMONEO</name>
+              <description>Window Monitor Event Out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x17</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RESRDY</name>
+              <description>Result Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WINMON</name>
+              <description>Window Monitor</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x19</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESULT</name>
+          <description>Result</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>RESULT</name>
+              <description>Result Conversion Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINLT</name>
+          <description>Window Monitor Lower Threshold</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINLT</name>
+              <description>Window Lower Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WINUT</name>
+          <description>Window Monitor Upper Threshold</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>WINUT</name>
+              <description>Window Upper Threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAINCORR</name>
+          <description>Gain Correction</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>GAINCORR</name>
+              <description>Gain Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OFFSETCORR</name>
+          <description>Offset Correction</description>
+          <addressOffset>0x26</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>OFFSETCORR</name>
+              <description>Offset Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALIB</name>
+          <description>Calibration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LINEARITY_CAL</name>
+              <description>Linearity Calibration Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BIAS_CAL</name>
+              <description>Bias Calibration Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x2A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DAC</name>
+      <version>1.1.0</version>
+      <description>Digital Analog Converter</description>
+      <groupName>DAC</groupName>
+      <prependToName>DAC_</prependToName>
+      <baseAddress>0x42004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DAC_INTREQ</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EOEN</name>
+              <description>External Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IOEN</name>
+              <description>Internal Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEFTADJ</name>
+              <description>Left Adjusted Data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VPD</name>
+              <description>Voltage Pump Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BDWP</name>
+              <description>Bypass DATABUF Write Protection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFSEL</name>
+              <description>Reference Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFSELSelect</name>
+                <enumeratedValue>
+                  <name>INT1V</name>
+                  <description>Internal 1.0V reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AVCC</name>
+                  <description>AVCC</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>VREFP</name>
+                  <description>External reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>STARTEI</name>
+              <description>Start Conversion Event Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTYEO</name>
+              <description>Data Buffer Empty Event Output</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>UNDERRUN</name>
+              <description>Underrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EMPTY</name>
+              <description>Data Buffer Empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data value to be converted</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATABUF</name>
+          <description>Data Buffer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATABUF</name>
+              <description>Data Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMAC</name>
+      <version>1.0.0</version>
+      <description>Direct Memory Access Controller</description>
+      <groupName>DMAC</groupName>
+      <prependToName>DMAC_</prependToName>
+      <baseAddress>0x41004800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMAC_INTREQ</name>
+        <value>6</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAENABLE</name>
+              <description>DMA Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCENABLE</name>
+              <description>CRC Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN0</name>
+              <description>Priority Level 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN1</name>
+              <description>Priority Level 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN2</name>
+              <description>Priority Level 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLEN3</name>
+              <description>Priority Level 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCTRL</name>
+          <description>CRC Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CRCBEATSIZE</name>
+              <description>CRC Beat Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCBEATSIZESelect</name>
+                <enumeratedValue>
+                  <name>BYTE</name>
+                  <description>8-bit bus transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HWORD</name>
+                  <description>16-bit bus transfer</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WORD</name>
+                  <description>32-bit bus transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCPOLY</name>
+              <description>CRC Polynomial Type</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CRCPOLYSelect</name>
+                <enumeratedValue>
+                  <name>CRC16</name>
+                  <description>CRC-16 (CRC-CCITT)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CRC32</name>
+                  <description>CRC32 (IEEE 802.3)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CRCSRC</name>
+              <description>CRC Input Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>CRCSRCSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>IO</name>
+                  <description>I/O interface</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCDATAIN</name>
+          <description>CRC Data Input</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCDATAIN</name>
+              <description>CRC Data Input</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCCHKSUM</name>
+          <description>CRC Checksum</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CRCCHKSUM</name>
+              <description>CRC Checksum</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CRCSTATUS</name>
+          <description>CRC Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CRCBUSY</name>
+              <description>CRC Module Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRCZERO</name>
+              <description>CRC Zero</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>QOS Control</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <resetValue>0x15</resetValue>
+          <fields>
+            <field>
+              <name>WRBQOS</name>
+              <description>Write-Back Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WRBQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FQOS</name>
+              <description>Fetch Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Transfer Quality of Service</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWTRIGCTRL</name>
+          <description>Software Trigger Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWTRIG0</name>
+              <description>Channel 0 Software Trigger</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG1</name>
+              <description>Channel 1 Software Trigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG2</name>
+              <description>Channel 2 Software Trigger</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG3</name>
+              <description>Channel 3 Software Trigger</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG4</name>
+              <description>Channel 4 Software Trigger</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG5</name>
+              <description>Channel 5 Software Trigger</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG6</name>
+              <description>Channel 6 Software Trigger</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG7</name>
+              <description>Channel 7 Software Trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG8</name>
+              <description>Channel 8 Software Trigger</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG9</name>
+              <description>Channel 9 Software Trigger</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG10</name>
+              <description>Channel 10 Software Trigger</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWTRIG11</name>
+              <description>Channel 11 Software Trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRICTRL0</name>
+          <description>Priority Control 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LVLPRI0</name>
+              <description>Level 0 Channel Priority Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN0</name>
+              <description>Level 0 Round-Robin Scheduling Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI1</name>
+              <description>Level 1 Channel Priority Number</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN1</name>
+              <description>Level 1 Round-Robin Scheduling Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI2</name>
+              <description>Level 2 Channel Priority Number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN2</name>
+              <description>Level 2 Round-Robin Scheduling Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVLPRI3</name>
+              <description>Level 3 Channel Priority Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>RRLVLEN3</name>
+              <description>Level 3 Round-Robin Scheduling Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTPEND</name>
+          <description>Interrupt Pending</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TERR</name>
+              <description>Transfer Error</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Transfer Complete</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Fetch Error</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PEND</name>
+              <description>Pending</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTSTATUS</name>
+          <description>Interrupt Status</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CHINT0</name>
+              <description>Channel 0 Pending Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT1</name>
+              <description>Channel 1 Pending Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT2</name>
+              <description>Channel 2 Pending Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT3</name>
+              <description>Channel 3 Pending Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT4</name>
+              <description>Channel 4 Pending Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT5</name>
+              <description>Channel 5 Pending Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT6</name>
+              <description>Channel 6 Pending Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT7</name>
+              <description>Channel 7 Pending Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT8</name>
+              <description>Channel 8 Pending Interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT9</name>
+              <description>Channel 9 Pending Interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT10</name>
+              <description>Channel 10 Pending Interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHINT11</name>
+              <description>Channel 11 Pending Interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSYCH</name>
+          <description>Busy Channels</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>BUSYCH0</name>
+              <description>Busy Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH1</name>
+              <description>Busy Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH2</name>
+              <description>Busy Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH3</name>
+              <description>Busy Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH4</name>
+              <description>Busy Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH5</name>
+              <description>Busy Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH6</name>
+              <description>Busy Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH7</name>
+              <description>Busy Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH8</name>
+              <description>Busy Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH9</name>
+              <description>Busy Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH10</name>
+              <description>Busy Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSYCH11</name>
+              <description>Busy Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PENDCH</name>
+          <description>Pending Channels</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PENDCH0</name>
+              <description>Pending Channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH1</name>
+              <description>Pending Channel 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH2</name>
+              <description>Pending Channel 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH3</name>
+              <description>Pending Channel 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH4</name>
+              <description>Pending Channel 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH5</name>
+              <description>Pending Channel 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH6</name>
+              <description>Pending Channel 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH7</name>
+              <description>Pending Channel 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH8</name>
+              <description>Pending Channel 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH9</name>
+              <description>Pending Channel 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH10</name>
+              <description>Pending Channel 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PENDCH11</name>
+              <description>Pending Channel 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACTIVE</name>
+          <description>Active Channel and Levels</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LVLEX0</name>
+              <description>Level 0 Channel Trigger Request Executing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX1</name>
+              <description>Level 1 Channel Trigger Request Executing</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX2</name>
+              <description>Level 2 Channel Trigger Request Executing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LVLEX3</name>
+              <description>Level 3 Channel Trigger Request Executing</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ID</name>
+              <description>Active Channel ID</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ABUSY</name>
+              <description>Active Channel Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTCNT</name>
+              <description>Active Channel Block Transfer Count</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASEADDR</name>
+          <description>Descriptor Memory Section Base Address</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BASEADDR</name>
+              <description>Descriptor Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRBADDR</name>
+          <description>Write-Back Memory Section Base Address</description>
+          <addressOffset>0x38</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRBADDR</name>
+              <description>Write-Back Memory Base Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHID</name>
+          <description>Channel ID</description>
+          <addressOffset>0x3F</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Channel ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLA</name>
+          <description>Channel Control A</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Channel Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Channel Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHCTRLB</name>
+          <description>Channel Control B</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Input Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRIG</name>
+                  <description>Transfer and periodic transfer trigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CTRIG</name>
+                  <description>Conditional transfer trigger</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CBLOCK</name>
+                  <description>Conditional block transfer</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSKIP</name>
+                  <description>Skip next block suspend action</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVIE</name>
+              <description>Channel Event Input Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVOE</name>
+              <description>Channel Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LVL</name>
+              <description>Channel Arbitration Level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LVLSelect</name>
+                <enumeratedValue>
+                  <name>LVL0</name>
+                  <description>Channel Priority Level 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL1</name>
+                  <description>Channel Priority Level 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL2</name>
+                  <description>Channel Priority Level 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LVL3</name>
+                  <description>Channel Priority Level 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGSRC</name>
+              <description>Trigger Source</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>TRIGSRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Only software/event triggers</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TRIGACT</name>
+              <description>Trigger Action</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TRIGACTSelect</name>
+                <enumeratedValue>
+                  <name>BLOCK</name>
+                  <description>One trigger required for each block transfer</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BEAT</name>
+                  <description>One trigger required for each beat transfer</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TRANSACTION</name>
+                  <description>One trigger required for each transaction</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Software Command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NOACT</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>Channel suspend operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESUME</name>
+                  <description>Channel resume operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENCLR</name>
+          <description>Channel Interrupt Enable Clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTENSET</name>
+          <description>Channel Interrupt Enable Set</description>
+          <addressOffset>0x4D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHINTFLAG</name>
+          <description>Channel Interrupt Flag Status and Clear</description>
+          <addressOffset>0x4E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TERR</name>
+              <description>Channel Transfer Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCMPL</name>
+              <description>Channel Transfer Complete</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SUSP</name>
+              <description>Channel Suspend</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x4F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>PEND</name>
+              <description>Channel Pending</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSY</name>
+              <description>Channel Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Channel Fetch Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DSU</name>
+      <version>2.0.0</version>
+      <description>Device Service Unit</description>
+      <groupName>DSU</groupName>
+      <prependToName>DSU_</prependToName>
+      <baseAddress>0x41002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x2000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0000</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC</name>
+              <description>32-bit Cyclic Redundancy Check</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MBIST</name>
+              <description>Memory Built-In Self-Test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CE</name>
+              <description>Chip Erase</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSA</name>
+          <description>Status A</description>
+          <addressOffset>0x0001</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DONE</name>
+              <description>Done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CRSTEXT</name>
+              <description>CPU Reset Phase Extension</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BERR</name>
+              <description>Bus Error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAIL</name>
+              <description>Failure</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Protection Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUSB</name>
+          <description>Status B</description>
+          <addressOffset>0x0002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x10</resetValue>
+          <fields>
+            <field>
+              <name>PROT</name>
+              <description>Protected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DBGPRES</name>
+              <description>Debugger Present</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD0</name>
+              <description>Debug Communication Channel 0 Dirty</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCCD1</name>
+              <description>Debug Communication Channel 1 Dirty</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPE</name>
+              <description>Hot-Plugging Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x0004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LENGTH</name>
+          <description>Length</description>
+          <addressOffset>0x0008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LENGTH</name>
+              <description>Length</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>30</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Data</description>
+          <addressOffset>0x000C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DCC%s</name>
+          <description>Debug Communication Channel n</description>
+          <addressOffset>0x0010</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DID</name>
+          <description>Device Identification</description>
+          <addressOffset>0x0018</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10010300</resetValue>
+          <fields>
+            <field>
+              <name>DEVSEL</name>
+              <description>Device Select</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIE</name>
+              <description>Die Identification</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIES</name>
+              <description>Product Series</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAMILY</name>
+              <description>Product Family</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PROCESSOR</name>
+              <description>Processor</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ENTRY%s</name>
+          <description>Coresight ROM Table Entry n</description>
+          <addressOffset>0x1000</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EPRES</name>
+              <description>Entry Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FMT</name>
+              <description>Format</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDOFF</name>
+              <description>Address Offset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>END</name>
+          <description>Coresight ROM Table End</description>
+          <addressOffset>0x1008</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>END</name>
+              <description>End Marker</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEMTYPE</name>
+          <description>Coresight ROM Table Memory Type</description>
+          <addressOffset>0x1FCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SMEMP</name>
+              <description>System Memory Present</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>Peripheral Identification 4</description>
+          <addressOffset>0x1FD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>JEPCC</name>
+              <description>JEP-106 Continuation Code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FKBC</name>
+              <description>4KB Count</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>Peripheral Identification 0</description>
+          <addressOffset>0x1FE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000D0</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBL</name>
+              <description>Part Number Low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>Peripheral Identification 1</description>
+          <addressOffset>0x1FE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000FC</resetValue>
+          <fields>
+            <field>
+              <name>PARTNBH</name>
+              <description>Part Number High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>JEPIDCL</name>
+              <description>Low part of the JEP-106 Identity Code</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>Peripheral Identification 2</description>
+          <addressOffset>0x1FE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>JEPIDCH</name>
+              <description>JEP-106 Identity Code High</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>JEPU</name>
+              <description>JEP-106 Identity Code is used</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REVISION</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>Peripheral Identification 3</description>
+          <addressOffset>0x1FEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>CUSMOD</name>
+              <description>ARM CUSMOD</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>REVAND</name>
+              <description>Revision Number</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>Component Identification 0</description>
+          <addressOffset>0x1FF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB0</name>
+              <description>Preamble Byte 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>Component Identification 1</description>
+          <addressOffset>0x1FF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLE</name>
+              <description>Preamble</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CCLASS</name>
+              <description>Component Class</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>Component Identification 2</description>
+          <addressOffset>0x1FF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB2</name>
+              <description>Preamble Byte 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>Component Identification 3</description>
+          <addressOffset>0x1FFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000000B1</resetValue>
+          <fields>
+            <field>
+              <name>PREAMBLEB3</name>
+              <description>Preamble Byte 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EIC</name>
+      <version>1.0.1</version>
+      <description>External Interrupt Controller</description>
+      <groupName>EIC</groupName>
+      <prependToName>EIC_</prependToName>
+      <baseAddress>0x40001800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EIC_INTREQ</name>
+        <value>4</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMICTRL</name>
+          <description>Non-Maskable Interrupt Control</description>
+          <addressOffset>0x02</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMISENSE</name>
+              <description>Non-Maskable Interrupt Sense</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>NMISENSESelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NMIFILTEN</name>
+              <description>Non-Maskable Interrupt Filter Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NMIFLAG</name>
+          <description>Non-Maskable Interrupt Flag Status and Clear</description>
+          <addressOffset>0x03</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>NMI</name>
+              <description>Non-Maskable Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINTEO0</name>
+              <description>External Interrupt 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO1</name>
+              <description>External Interrupt 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO2</name>
+              <description>External Interrupt 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO3</name>
+              <description>External Interrupt 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO4</name>
+              <description>External Interrupt 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO5</name>
+              <description>External Interrupt 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO6</name>
+              <description>External Interrupt 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO7</name>
+              <description>External Interrupt 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO8</name>
+              <description>External Interrupt 8 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO9</name>
+              <description>External Interrupt 9 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO10</name>
+              <description>External Interrupt 10 Event Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO11</name>
+              <description>External Interrupt 11 Event Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO12</name>
+              <description>External Interrupt 12 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO13</name>
+              <description>External Interrupt 13 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO14</name>
+              <description>External Interrupt 14 Event Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINTEO15</name>
+              <description>External Interrupt 15 Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0 Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1 Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6 Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12 Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13 Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14 Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EXTINT0</name>
+              <description>External Interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT1</name>
+              <description>External Interrupt 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT2</name>
+              <description>External Interrupt 2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT3</name>
+              <description>External Interrupt 3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT4</name>
+              <description>External Interrupt 4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT5</name>
+              <description>External Interrupt 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT6</name>
+              <description>External Interrupt 6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT7</name>
+              <description>External Interrupt 7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT8</name>
+              <description>External Interrupt 8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT9</name>
+              <description>External Interrupt 9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT10</name>
+              <description>External Interrupt 10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT11</name>
+              <description>External Interrupt 11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT12</name>
+              <description>External Interrupt 12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT13</name>
+              <description>External Interrupt 13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT14</name>
+              <description>External Interrupt 14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXTINT15</name>
+              <description>External Interrupt 15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP</name>
+          <description>Wake-Up Enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAKEUPEN0</name>
+              <description>External Interrupt 0 Wake-up Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN1</name>
+              <description>External Interrupt 1 Wake-up Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN2</name>
+              <description>External Interrupt 2 Wake-up Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN3</name>
+              <description>External Interrupt 3 Wake-up Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN4</name>
+              <description>External Interrupt 4 Wake-up Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN5</name>
+              <description>External Interrupt 5 Wake-up Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN6</name>
+              <description>External Interrupt 6 Wake-up Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN7</name>
+              <description>External Interrupt 7 Wake-up Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN8</name>
+              <description>External Interrupt 8 Wake-up Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN9</name>
+              <description>External Interrupt 9 Wake-up Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN10</name>
+              <description>External Interrupt 10 Wake-up Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN11</name>
+              <description>External Interrupt 11 Wake-up Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN12</name>
+              <description>External Interrupt 12 Wake-up Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN13</name>
+              <description>External Interrupt 13 Wake-up Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN14</name>
+              <description>External Interrupt 14 Wake-up Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUPEN15</name>
+              <description>External Interrupt 15 Wake-up Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CONFIG%s</name>
+          <description>Configuration n</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SENSE0</name>
+              <description>Input Sense 0 Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE0Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising-edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling-edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both-edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High-level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low-level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN0</name>
+              <description>Filter 0 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE1</name>
+              <description>Input Sense 1 Configuration</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE1Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN1</name>
+              <description>Filter 1 Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE2</name>
+              <description>Input Sense 2 Configuration</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE2Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN2</name>
+              <description>Filter 2 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE3</name>
+              <description>Input Sense 3 Configuration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE3Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN3</name>
+              <description>Filter 3 Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE4</name>
+              <description>Input Sense 4 Configuration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE4Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN4</name>
+              <description>Filter 4 Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE5</name>
+              <description>Input Sense 5 Configuration</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE5Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN5</name>
+              <description>Filter 5 Enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE6</name>
+              <description>Input Sense 6 Configuration</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE6Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN6</name>
+              <description>Filter 6 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SENSE7</name>
+              <description>Input Sense 7 Configuration</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SENSE7Select</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No detection</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Rising edge detection</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Falling edge detection</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Both edges detection</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>High level detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Low level detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FILTEN7</name>
+              <description>Filter 7 Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EVSYS</name>
+      <version>1.0.1</version>
+      <description>Event System Interface</description>
+      <groupName>EVSYS</groupName>
+      <prependToName>EVSYS_</prependToName>
+      <baseAddress>0x42000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EVSYS_INTREQ</name>
+        <value>8</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GCLKREQ</name>
+              <description>Generic Clock Requests</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHANNEL</name>
+          <description>Channel</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SWEVT</name>
+              <description>Software Event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVGEN</name>
+              <description>Event Generator Selection</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>PATH</name>
+              <description>Path Selection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PATHSelect</name>
+                <enumeratedValue>
+                  <name>SYNCHRONOUS</name>
+                  <description>Synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNCHRONIZED</name>
+                  <description>Resynchronized path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ASYNCHRONOUS</name>
+                  <description>Asynchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EDGSEL</name>
+              <description>Edge Detection Selection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EDGSELSelect</name>
+                <enumeratedValue>
+                  <name>NO_EVT_OUTPUT</name>
+                  <description>No event output when using the resynchronized or synchronous path</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISING_EDGE</name>
+                  <description>Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING_EDGE</name>
+                  <description>Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH_EDGES</name>
+                  <description>Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>User Multiplexer</description>
+          <addressOffset>0x08</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>USER</name>
+              <description>User Multiplexer Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CHANNEL</name>
+              <description>Channel Event Selection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>CHANNELSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>No Channel Output Selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHSTATUS</name>
+          <description>Channel Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x000F00FF</resetValue>
+          <fields>
+            <field>
+              <name>USRRDY0</name>
+              <description>Channel 0 User Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY1</name>
+              <description>Channel 1 User Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY2</name>
+              <description>Channel 2 User Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY3</name>
+              <description>Channel 3 User Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY4</name>
+              <description>Channel 4 User Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY5</name>
+              <description>Channel 5 User Ready</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY6</name>
+              <description>Channel 6 User Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY7</name>
+              <description>Channel 7 User Ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY0</name>
+              <description>Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY1</name>
+              <description>Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY2</name>
+              <description>Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY3</name>
+              <description>Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY4</name>
+              <description>Channel 4 Busy</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY5</name>
+              <description>Channel 5 Busy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY6</name>
+              <description>Channel 6 Busy</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY7</name>
+              <description>Channel 7 Busy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY8</name>
+              <description>Channel 8 User Ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY9</name>
+              <description>Channel 9 User Ready</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY10</name>
+              <description>Channel 10 User Ready</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USRRDY11</name>
+              <description>Channel 11 User Ready</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY8</name>
+              <description>Channel 8 Busy</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY9</name>
+              <description>Channel 9 Busy</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY10</name>
+              <description>Channel 10 Busy</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHBUSY11</name>
+              <description>Channel 11 Busy</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection Interrupt Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection Interrupt Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection Interrupt Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection Interrupt Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVR0</name>
+              <description>Channel 0 Overrun</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR1</name>
+              <description>Channel 1 Overrun</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR2</name>
+              <description>Channel 2 Overrun</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR3</name>
+              <description>Channel 3 Overrun</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR4</name>
+              <description>Channel 4 Overrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR5</name>
+              <description>Channel 5 Overrun</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR6</name>
+              <description>Channel 6 Overrun</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR7</name>
+              <description>Channel 7 Overrun</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD0</name>
+              <description>Channel 0 Event Detection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD1</name>
+              <description>Channel 1 Event Detection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD2</name>
+              <description>Channel 2 Event Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD3</name>
+              <description>Channel 3 Event Detection</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD4</name>
+              <description>Channel 4 Event Detection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD5</name>
+              <description>Channel 5 Event Detection</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD6</name>
+              <description>Channel 6 Event Detection</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD7</name>
+              <description>Channel 7 Event Detection</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR8</name>
+              <description>Channel 8 Overrun</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR9</name>
+              <description>Channel 9 Overrun</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR10</name>
+              <description>Channel 10 Overrun</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVR11</name>
+              <description>Channel 11 Overrun</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD8</name>
+              <description>Channel 8 Event Detection</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD9</name>
+              <description>Channel 9 Event Detection</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD10</name>
+              <description>Channel 10 Event Detection</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVD11</name>
+              <description>Channel 11 Event Detection</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GCLK</name>
+      <version>2.1.0</version>
+      <description>Generic Clock Generator</description>
+      <groupName>GCLK</groupName>
+      <prependToName>GCLK_</prependToName>
+      <baseAddress>0x40000C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy Status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKCTRL</name>
+          <description>Generic Clock Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Selection ID</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <enumeratedValues>
+                <name>IDSelect</name>
+                <enumeratedValue>
+                  <name>DFLL48</name>
+                  <description>DFLL48</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL32K</name>
+                  <description>FDPLL32K</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WDT</name>
+                  <description>WDT</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RTC</name>
+                  <description>RTC</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EIC</name>
+                  <description>EIC</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USB</name>
+                  <description>USB</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_0</name>
+                  <description>EVSYS_0</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_1</name>
+                  <description>EVSYS_1</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_2</name>
+                  <description>EVSYS_2</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_3</name>
+                  <description>EVSYS_3</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_4</name>
+                  <description>EVSYS_4</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_5</name>
+                  <description>EVSYS_5</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_6</name>
+                  <description>EVSYS_6</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_7</name>
+                  <description>EVSYS_7</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_8</name>
+                  <description>EVSYS_8</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_9</name>
+                  <description>EVSYS_9</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_10</name>
+                  <description>EVSYS_10</description>
+                  <value>0x11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EVSYS_11</name>
+                  <description>EVSYS_11</description>
+                  <value>0x12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOMX_SLOW</name>
+                  <description>SERCOMX_SLOW</description>
+                  <value>0x13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM0_CORE</name>
+                  <description>SERCOM0_CORE</description>
+                  <value>0x14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM1_CORE</name>
+                  <description>SERCOM1_CORE</description>
+                  <value>0x15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM2_CORE</name>
+                  <description>SERCOM2_CORE</description>
+                  <value>0x16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM3_CORE</name>
+                  <description>SERCOM3_CORE</description>
+                  <value>0x17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM4_CORE</name>
+                  <description>SERCOM4_CORE</description>
+                  <value>0x18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SERCOM5_CORE</name>
+                  <description>SERCOM5_CORE</description>
+                  <value>0x19</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC0_TCC1</name>
+                  <description>TCC0_TCC1</description>
+                  <value>0x1a</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TCC2_TC3</name>
+                  <description>TCC2_TC3</description>
+                  <value>0x1b</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC4_TC5</name>
+                  <description>TC4_TC5</description>
+                  <value>0x1c</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TC6_TC7</name>
+                  <description>TC6_TC7</description>
+                  <value>0x1d</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ADC</name>
+                  <description>ADC</description>
+                  <value>0x1e</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_DIG</name>
+                  <description>AC_DIG</description>
+                  <value>0x1f</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AC_ANA</name>
+                  <description>AC_ANA</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DAC</name>
+                  <description>DAC</description>
+                  <value>0x21</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_0</name>
+                  <description>I2S_0</description>
+                  <value>0x23</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S_1</name>
+                  <description>I2S_1</description>
+                  <value>0x24</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GEN</name>
+              <description>Generic Clock Generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>GENSelect</name>
+                <enumeratedValue>
+                  <name>GCLK0</name>
+                  <description>Generic clock generator 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK1</name>
+                  <description>Generic clock generator 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK2</name>
+                  <description>Generic clock generator 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK3</name>
+                  <description>Generic clock generator 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK4</name>
+                  <description>Generic clock generator 4</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK5</name>
+                  <description>Generic clock generator 5</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK6</name>
+                  <description>Generic clock generator 6</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK7</name>
+                  <description>Generic clock generator 7</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENCTRL</name>
+          <description>Generic Clock Generator Control</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>SRC</name>
+              <description>Source Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>XOSC</name>
+                  <description>XOSC oscillator output</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKIN</name>
+                  <description>Generator input pad</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLKGEN1</name>
+                  <description>Generic clock generator 1 output</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSCULP32K</name>
+                  <description>OSCULP32K oscillator output</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC32K</name>
+                  <description>OSC32K oscillator output</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>XOSC32K</name>
+                  <description>XOSC32K oscillator output</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>OSC8M</name>
+                  <description>OSC8M oscillator output</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DFLL48M</name>
+                  <description>DFLL48M output</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FDPLL</name>
+                  <description>FDPLL output</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>GENEN</name>
+              <description>Generic Clock Generator Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDC</name>
+              <description>Improve Duty Cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OOV</name>
+              <description>Output Off Value</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OE</name>
+              <description>Output Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIVSEL</name>
+              <description>Divide Selection</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GENDIV</name>
+          <description>Generic Clock Generator Division</description>
+          <addressOffset>0x8</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>Generic Clock Generator Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Division Factor</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMATRIX</name>
+      <version>2.1.2</version>
+      <description>HSB Matrix</description>
+      <groupName>HMATRIXB</groupName>
+      <prependToName>HMATRIXB_</prependToName>
+      <baseAddress>0x41007000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRAS%s</name>
+          <description>Priority A for Slave</description>
+          <addressOffset>0x080</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>PRBS%s</name>
+          <description>Priority B for Slave</description>
+          <addressOffset>0x084</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SFR%s</name>
+          <description>Special Function</description>
+          <addressOffset>0x110</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SFR</name>
+              <description>Special Function Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <version>1.0.2</version>
+      <description>Inter-IC Sound Interface</description>
+      <groupName>I2S</groupName>
+      <prependToName>I2S_</prependToName>
+      <baseAddress>0x42005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S_INTREQ</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CLKCTRL%s</name>
+          <description>Clock Unit n Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SLOTSIZE</name>
+              <description>Slot Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLOTSIZESelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8-bit Slot for Clock Unit n</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16-bit Slot for Clock Unit n</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24-bit Slot for Clock Unit n</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32-bit Slot for Clock Unit n</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NBSLOTS</name>
+              <description>Number of Slots in Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FSWIDTH</name>
+              <description>Frame Sync Width</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FSWIDTHSelect</name>
+                <enumeratedValue>
+                  <name>SLOT</name>
+                  <description>Frame Sync Pulse is 1 Slot wide (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Frame Sync Pulse is half a Frame wide</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BIT</name>
+                  <description>Frame Sync Pulse is 1 Bit wide</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BURST</name>
+                  <description>Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITDELAY</name>
+              <description>Data Delay from Frame Sync</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITDELAYSelect</name>
+                <enumeratedValue>
+                  <name>LJ</name>
+                  <description>Left Justified (0 Bit Delay)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2S</name>
+                  <description>I2S (1 Bit Delay)</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSSEL</name>
+              <description>Frame Sync Select</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>FSSELSelect</name>
+                <enumeratedValue>
+                  <name>SCKDIV</name>
+                  <description>Divided Serial Clock n is used as Frame Sync n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FSPIN</name>
+                  <description>FSn input pin is used as Frame Sync n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FSINV</name>
+              <description>Frame Sync Invert</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKSEL</name>
+              <description>Serial Clock Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SCKSELSelect</name>
+                <enumeratedValue>
+                  <name>MCKDIV</name>
+                  <description>Divided Master Clock n is used as Serial Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SCKPIN</name>
+                  <description>SCKn input pin is used as Serial Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKSEL</name>
+              <description>Master Clock Select</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MCKSELSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_I2S_n is used as Master Clock n source</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MCKPIN</name>
+                  <description>MCKn input pin is used as Master Clock n source</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MCKEN</name>
+              <description>Master Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKDIV</name>
+              <description>Master Clock Division Factor</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTDIV</name>
+              <description>Master Clock Output Division Factor</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>FSOUTINV</name>
+              <description>Frame Sync Output Invert</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SCKOUTINV</name>
+              <description>Serial Clock Output Invert</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCKOUTINV</name>
+              <description>Master Clock Output Invert</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0 Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1 Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0 Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1 Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RXRDY0</name>
+              <description>Receive Ready 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXRDY1</name>
+              <description>Receive Ready 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR0</name>
+              <description>Receive Overrun 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXOR1</name>
+              <description>Receive Overrun 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY0</name>
+              <description>Transmit Ready 0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXRDY1</name>
+              <description>Transmit Ready 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR0</name>
+              <description>Transmit Underrun 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXUR1</name>
+              <description>Transmit Underrun 1</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN0</name>
+              <description>Clock Unit 0 Enable Synchronization Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CKEN1</name>
+              <description>Clock Unit 1 Enable Synchronization Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN0</name>
+              <description>Serializer 0 Enable Synchronization Status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEREN1</name>
+              <description>Serializer 1 Enable Synchronization Status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA0</name>
+              <description>Data 0 Synchronization Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DATA1</name>
+              <description>Data 1 Synchronization Status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SERCTRL%s</name>
+          <description>Serializer n Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SERMODE</name>
+              <description>Serializer Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SERMODESelect</name>
+                <enumeratedValue>
+                  <name>RX</name>
+                  <description>Receive</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TX</name>
+                  <description>Transmit</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PDM2</name>
+                  <description>Receive one PDM data on each serial clock edge</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXDEFAULT</name>
+              <description>Line Default Line when Slot Disabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>TXDEFAULTSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Output Default Value is 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Output Default Value is 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIZ</name>
+                  <description>Output Default Value is high impedance</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TXSAME</name>
+              <description>Transmit Data when Underrun</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>TXSAMESelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Zero data transmitted in case of underrun</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SAME</name>
+                  <description>Last data transmitted in case of underrun</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKSEL</name>
+              <description>Clock Unit Selection</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>CLKSELSelect</name>
+                <enumeratedValue>
+                  <name>CLK0</name>
+                  <description>Use Clock Unit 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLK1</name>
+                  <description>Use Clock Unit 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTADJ</name>
+              <description>Data Slot Formatting Adjust</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>SLOTADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in slot</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in slot</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DATASIZE</name>
+              <description>Data Word Size</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>DATASIZESelect</name>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bits</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>24</name>
+                  <description>24 bits</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>20</name>
+                  <description>20 bits</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>18</name>
+                  <description>18 bits</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bits</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16C</name>
+                  <description>16 bits compact stereo</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bits</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8C</name>
+                  <description>8 bits compact stereo</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WORDADJ</name>
+              <description>Data Word Formatting Adjust</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>WORDADJSelect</name>
+                <enumeratedValue>
+                  <name>RIGHT</name>
+                  <description>Data is right adjusted in word</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LEFT</name>
+                  <description>Data is left adjusted in word</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EXTEND</name>
+              <description>Data Formatting Bit Extension</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>EXTENDSelect</name>
+                <enumeratedValue>
+                  <name>ZERO</name>
+                  <description>Extend with zeroes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ONE</name>
+                  <description>Extend with ones</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Extend with Most Significant Bit</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Extend with Least Significant Bit</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BITREV</name>
+              <description>Data Formatting Bit Reverse</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>BITREVSelect</name>
+                <enumeratedValue>
+                  <name>MSBIT</name>
+                  <description>Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LSBIT</name>
+                  <description>Transfer Data Least Significant Bit (LSB) first</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>SLOTDIS0</name>
+              <description>Slot 0 Disabled for this Serializer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS1</name>
+              <description>Slot 1 Disabled for this Serializer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS2</name>
+              <description>Slot 2 Disabled for this Serializer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS3</name>
+              <description>Slot 3 Disabled for this Serializer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS4</name>
+              <description>Slot 4 Disabled for this Serializer</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS5</name>
+              <description>Slot 5 Disabled for this Serializer</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS6</name>
+              <description>Slot 6 Disabled for this Serializer</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLOTDIS7</name>
+              <description>Slot 7 Disabled for this Serializer</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MONO</name>
+              <description>Mono Mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MONOSelect</name>
+                <enumeratedValue>
+                  <name>STEREO</name>
+                  <description>Normal mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MONO</name>
+                  <description>Left channel data is duplicated to right channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DMA</name>
+              <description>Single or Multiple DMA Channels</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>DMASelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single DMA channel</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MULTIPLE</name>
+                  <description>One DMA channel per data channel</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RXLOOP</name>
+              <description>Loop-back Test Mode</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>DATA%s</name>
+          <description>Data n</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Sample Data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MTB</name>
+      <version>1.0.0</version>
+      <description>Cortex-M0+ Micro-Trace Buffer</description>
+      <groupName>MTB</groupName>
+      <prependToName>MTB_</prependToName>
+      <baseAddress>0x41006000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>POSITION</name>
+          <description>MTB Position</description>
+          <addressOffset>0x000</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WRAP</name>
+              <description>Pointer Value Wraps</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POINTER</name>
+              <description>Trace Packet Location Pointer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MASTER</name>
+          <description>MTB Master</description>
+          <addressOffset>0x004</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MASK</name>
+              <description>Maximum Value of the Trace Buffer in SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TSTARTEN</name>
+              <description>Trace Start Input Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTOPEN</name>
+              <description>Trace Stop Input Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFRWPRIV</name>
+              <description>Special Function Register Write Privilege</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMPRIV</name>
+              <description>SRAM Privilege</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALTREQ</name>
+              <description>Halt Request</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Main Trace Enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW</name>
+          <description>MTB Flow</description>
+          <addressOffset>0x008</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>AUTOSTOP</name>
+              <description>Auto Stop Tracing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AUTOHALT</name>
+              <description>Auto Halt Request</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WATERMARK</name>
+              <description>Watermark value</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>29</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BASE</name>
+          <description>MTB Base</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>ITCTRL</name>
+          <description>MTB Integration Mode Control</description>
+          <addressOffset>0xF00</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMSET</name>
+          <description>MTB Claim Set</description>
+          <addressOffset>0xFA0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>CLAIMCLR</name>
+          <description>MTB Claim Clear</description>
+          <addressOffset>0xFA4</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKACCESS</name>
+          <description>MTB Lock Access</description>
+          <addressOffset>0xFB0</addressOffset>
+          <size>32</size>
+        </register>
+        <register>
+          <name>LOCKSTATUS</name>
+          <description>MTB Lock Status</description>
+          <addressOffset>0xFB4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>AUTHSTATUS</name>
+          <description>MTB Authentication Status</description>
+          <addressOffset>0xFB8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVARCH</name>
+          <description>MTB Device Architecture</description>
+          <addressOffset>0xFBC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVID</name>
+          <description>MTB Device Configuration</description>
+          <addressOffset>0xFC8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>DEVTYPE</name>
+          <description>MTB Device Type</description>
+          <addressOffset>0xFCC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID4</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID5</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID6</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFD8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID7</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFDC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFE8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>PID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFEC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID0</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID1</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID2</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+        <register>
+          <name>CID3</name>
+          <description>CoreSight</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>NVMCTRL</name>
+      <version>1.0.6</version>
+      <description>Non-Volatile Memory Controller</description>
+      <groupName>NVMCTRL</groupName>
+      <prependToName>NVMCTRL_</prependToName>
+      <baseAddress>0x41004000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>NVMCTRL_INTREQ</name>
+        <value>5</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>ER</name>
+                  <description>Erase Row - Erases the row addressed by the ADDR register.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WP</name>
+                  <description>Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>EAR</name>
+                  <description>Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAP</name>
+                  <description>Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SF</name>
+                  <description>Security Flow Command</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WL</name>
+                  <description>Write lockbits</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LR</name>
+                  <description>Lock Region - Locks the region containing the address location in the ADDR register.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UR</name>
+                  <description>Unlock Region - Unlocks the region containing the address location in the ADDR register.</description>
+                  <value>0x41</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPRM</name>
+                  <description>Sets the power reduction mode.</description>
+                  <value>0x42</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CPRM</name>
+                  <description>Clears the power reduction mode.</description>
+                  <value>0x43</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PBC</name>
+                  <description>Page Buffer Clear - Clears the page buffer.</description>
+                  <value>0x44</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SSB</name>
+                  <description>Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.</description>
+                  <value>0x45</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVALL</name>
+                  <description>Invalidates all cache lines.</description>
+                  <value>0x46</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMDEX</name>
+              <description>Command Execution</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <enumeratedValues>
+                <name>CMDEXSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Execution Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>RWS</name>
+              <description>NVM Read Wait States</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>RWSSelect</name>
+                <enumeratedValue>
+                  <name>SINGLE</name>
+                  <description>Single Auto Wait State</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HALF</name>
+                  <description>Half Auto Wait State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DUAL</name>
+                  <description>Dual Auto Wait State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MANW</name>
+              <description>Manual Write</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLEEPPRM</name>
+              <description>Power Reduction Mode during Sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SLEEPPRMSelect</name>
+                <enumeratedValue>
+                  <name>WAKEONACCESS</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>WAKEUPINSTANT</name>
+                  <description>NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Auto power reduction disabled.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>READMODE</name>
+              <description>NVMCTRL Read Mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>READMODESelect</name>
+                <enumeratedValue>
+                  <name>NO_MISS_PENALTY</name>
+                  <description>The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW_POWER</name>
+                  <description>Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DETERMINISTIC</name>
+                  <description>The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CACHEDIS</name>
+              <description>Cache Disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARAM</name>
+          <description>NVM Parameter</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NVMP</name>
+              <description>NVM Pages</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PSZ</name>
+              <description>Page Size</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>PSZSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 bytes</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 bytes</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 bytes</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 bytes</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 bytes</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 bytes</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 bytes</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <description>1024 bytes</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READY</name>
+              <description>NVM Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PRM</name>
+              <description>Power Reduction Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>NVM Page Buffer Active Loading</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PROGE</name>
+              <description>Programming Error Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOCKE</name>
+              <description>Lock Error Status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVME</name>
+              <description>NVM Error</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Security Bit Status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>NVM Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK</name>
+          <description>Lock Section</description>
+          <addressOffset>0x20</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>Region Lock Bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAC0</name>
+      <version>1.0.1</version>
+      <description>Peripheral Access Controller 0</description>
+      <groupName>PAC</groupName>
+      <prependToName>PAC_</prependToName>
+      <baseAddress>0x40000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x08</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WPCLR</name>
+          <description>Write Protection Clear</description>
+          <addressOffset>0x0</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPSET</name>
+          <description>Write Protection Set</description>
+          <addressOffset>0x4</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WP</name>
+              <description>Write Protection Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC1</name>
+      <description>Peripheral Access Controller 1</description>
+      <baseAddress>0x41000000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="PAC0">
+      <name>PAC2</name>
+      <description>Peripheral Access Controller 2</description>
+      <baseAddress>0x42000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>PM</name>
+      <version>2.0.1</version>
+      <description>Power Manager</description>
+      <groupName>PM</groupName>
+      <prependToName>PM_</prependToName>
+      <baseAddress>0x40000400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PM_INTREQ</name>
+        <value>0</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>8</size>
+        </register>
+        <register>
+          <name>SLEEP</name>
+          <description>Sleep Mode</description>
+          <addressOffset>0x01</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>Idle Mode Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDLESelect</name>
+                <enumeratedValue>
+                  <name>CPU</name>
+                  <description>The CPU clock domain is stopped</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>AHB</name>
+                  <description>The CPU and AHB clock domains are stopped</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APB</name>
+                  <description>The CPU, AHB and APB clock domains are stopped</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSEL</name>
+          <description>CPU Clock Select</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CPUDIV</name>
+              <description>CPU Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CPUDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBASEL</name>
+          <description>APBA Clock Select</description>
+          <addressOffset>0x09</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBADIV</name>
+              <description>APBA Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBADIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBSEL</name>
+          <description>APBB Clock Select</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBBDIV</name>
+              <description>APBB Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBBDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCSEL</name>
+          <description>APBC Clock Select</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>APBCDIV</name>
+              <description>APBC Prescaler Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>APBCDIVSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Divide by 1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide by 32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide by 128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBMASK</name>
+          <description>AHB Mask</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>HPB0_</name>
+              <description>HPB0 AHB Clock Mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB1_</name>
+              <description>HPB1 AHB Clock Mask</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HPB2_</name>
+              <description>HPB2 AHB Clock Mask</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU AHB Clock Mask</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL AHB Clock Mask</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC AHB Clock Mask</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB AHB Clock Mask</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBAMASK</name>
+          <description>APBA Mask</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC0_</name>
+              <description>PAC0 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PM_</name>
+              <description>PM APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYSCTRL_</name>
+              <description>SYSCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCLK_</name>
+              <description>GCLK APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_</name>
+              <description>WDT APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RTC_</name>
+              <description>RTC APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EIC_</name>
+              <description>EIC APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBBMASK</name>
+          <description>APBB Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PAC1_</name>
+              <description>PAC1 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DSU_</name>
+              <description>DSU APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NVMCTRL_</name>
+              <description>NVMCTRL APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PORT_</name>
+              <description>PORT APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DMAC_</name>
+              <description>DMAC APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USB_</name>
+              <description>USB APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HMATRIX_</name>
+              <description>HMATRIX APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APBCMASK</name>
+          <description>APBC Mask</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>PAC2_</name>
+              <description>PAC2 APB Clock Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EVSYS_</name>
+              <description>EVSYS APB Clock Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM0_</name>
+              <description>SERCOM0 APB Clock Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM1_</name>
+              <description>SERCOM1 APB Clock Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM2_</name>
+              <description>SERCOM2 APB Clock Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM3_</name>
+              <description>SERCOM3 APB Clock Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM4_</name>
+              <description>SERCOM4 APB Clock Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SERCOM5_</name>
+              <description>SERCOM5 APB Clock Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC0_</name>
+              <description>TCC0 APB Clock Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC1_</name>
+              <description>TCC1 APB Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCC2_</name>
+              <description>TCC2 APB Clock Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC3_</name>
+              <description>TC3 APB Clock Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC4_</name>
+              <description>TC4 APB Clock Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC5_</name>
+              <description>TC5 APB Clock Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC6_</name>
+              <description>TC6 APB Clock Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TC7_</name>
+              <description>TC7 APB Clock Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADC_</name>
+              <description>ADC APB Clock Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AC_</name>
+              <description>AC APB Clock Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DAC_</name>
+              <description>DAC APB Clock Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTC_</name>
+              <description>PTC APB Clock Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>I2S_</name>
+              <description>I2S APB Clock Enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x34</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x35</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x36</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CKRDY</name>
+              <description>Clock Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RCAUSE</name>
+          <description>Reset Cause</description>
+          <addressOffset>0x38</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>POR</name>
+              <description>Power On Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD12</name>
+              <description>Brown Out 12 Detector Reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33</name>
+              <description>Brown Out 33 Detector Reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EXT</name>
+              <description>External Reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT</name>
+              <description>Watchdog Reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYST</name>
+              <description>System Reset Request</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PORT</name>
+      <version>1.0.0</version>
+      <description>Port Module</description>
+      <groupName>PORT</groupName>
+      <prependToName>PORT_</prependToName>
+      <baseAddress>0x41004400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIR%s</name>
+          <description>Data Direction</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Port Data Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRCLR%s</name>
+          <description>Data Direction Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRCLR</name>
+              <description>Port Data Direction Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRSET%s</name>
+          <description>Data Direction Set</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRSET</name>
+              <description>Port Data Direction Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>DIRTGL%s</name>
+          <description>Data Direction Toggle</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DIRTGL</name>
+              <description>Port Data Direction Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUT%s</name>
+          <description>Data Output Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUT</name>
+              <description>Port Data Output Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTCLR%s</name>
+          <description>Data Output Value Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTCLR</name>
+              <description>Port Data Output Value Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTSET%s</name>
+          <description>Data Output Value Set</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTSET</name>
+              <description>Port Data Output Value Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>OUTTGL%s</name>
+          <description>Data Output Value Toggle</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OUTTGL</name>
+              <description>Port Data Output Value Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>IN%s</name>
+          <description>Data Input Value</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>IN</name>
+              <description>Port Data Input Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>CTRL%s</name>
+          <description>Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SAMPLING</name>
+              <description>Input Sampling Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x80</dimIncrement>
+          <name>WRCONFIG%s</name>
+          <description>Write Configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>PINMASK</name>
+              <description>Pin Mask for Multiple Pin Configuration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMUX</name>
+              <description>Peripheral Multiplexing</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>WRPMUX</name>
+              <description>Write PMUX</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WRPINCFG</name>
+              <description>Write PINCFG</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HWSEL</name>
+              <description>Half-Word Select</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX0_%s</name>
+          <description>Peripheral Multiplexing n - Group 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXE</name>
+              <description>Peripheral Multiplexing Even</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXESelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PMUXO</name>
+              <description>Peripheral Multiplexing Odd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PMUXOSelect</name>
+                <enumeratedValue>
+                  <name>A</name>
+                  <description>Peripheral function A selected</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>B</name>
+                  <description>Peripheral function B selected</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>C</name>
+                  <description>Peripheral function C selected</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>D</name>
+                  <description>Peripheral function D selected</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>E</name>
+                  <description>Peripheral function E selected</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>F</name>
+                  <description>Peripheral function F selected</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>G</name>
+                  <description>Peripheral function G selected</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>H</name>
+                  <description>Peripheral function H selected</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PMUX0_%s">
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PMUX1_%s</name>
+          <description>Peripheral Multiplexing n - Group 1</description>
+          <addressOffset>0xb0</addressOffset>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG0_%s</name>
+          <description>Pin Configuration n - Group 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PMUXEN</name>
+              <description>Peripheral Multiplexer Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INEN</name>
+              <description>Input Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PULLEN</name>
+              <description>Pull Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRVSTR</name>
+              <description>Output Driver Strength Selection</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register derivedFrom="PINCFG0_%s">
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PINCFG1_%s</name>
+          <description>Pin Configuration n - Group 1</description>
+          <addressOffset>0xc0</addressOffset>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PORT">
+      <name>PORT_IOBUS</name>
+      <description>Port Module (IOBUS)</description>
+      <groupName>PORT_IOBUS</groupName>
+      <prependToName>PORT_IOBUS_</prependToName>
+      <baseAddress>0x60000000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <version>1.0.1</version>
+      <description>Real-Time Counter</description>
+      <groupName>RTC</groupName>
+      <prependToName>RTC_</prependToName>
+      <baseAddress>0x40001400</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_INTREQ</name>
+        <value>3</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>MODE0</name>
+        <description>32-bit Counter with Single 32-bit Compare</description>
+        <headerStructName>RtcMode0</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE0 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE0 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE0 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE0 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE0 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE0 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE0 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode0 -->
+       <cluster>
+        <name>MODE1</name>
+        <description>16-bit Counter with Two 16-bit Compares</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode1</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE1 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE1 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO0</name>
+              <description>Compare 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMPEO1</name>
+              <description>Compare 1 Event Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE1 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE1 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE1 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CMP0</name>
+              <description>Compare 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>MODE1 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>MODE1 Counter Period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Counter Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>COMP%s</name>
+          <description>MODE1 Compare n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COMP</name>
+              <description>Compare Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode1 -->
+       <cluster>
+        <name>MODE2</name>
+        <description>Clock/Calendar with Alarm</description>
+        <alternateCluster>MODE0</alternateCluster>
+        <headerStructName>RtcMode2</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRL</name>
+          <description>MODE2 Control</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Mode 0: 32-bit Counter</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Mode 1: 16-bit Counter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLOCK</name>
+                  <description>Mode 2: Clock/Calendar</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CLKREP</name>
+              <description>Clock Representation</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MATCHCLR</name>
+              <description>Clear on Match</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/32</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/64</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/128</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/256</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/512</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>CLK_RTC_CNT = GCLK_RTC/1024</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <resetValue>0x0010</resetValue>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>MODE2 Event Control</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PEREO0</name>
+              <description>Periodic Interval 0 Event Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO1</name>
+              <description>Periodic Interval 1 Event Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO2</name>
+              <description>Periodic Interval 2 Event Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO3</name>
+              <description>Periodic Interval 3 Event Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO4</name>
+              <description>Periodic Interval 4 Event Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO5</name>
+              <description>Periodic Interval 5 Event Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO6</name>
+              <description>Periodic Interval 6 Event Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PEREO7</name>
+              <description>Periodic Interval 7 Event Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALARMEO0</name>
+              <description>Alarm 0 Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow Event Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>MODE2 Interrupt Enable Clear</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>MODE2 Interrupt Enable Set</description>
+          <addressOffset>0x07</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>MODE2 Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ALARM0</name>
+              <description>Alarm 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x0B</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Run During Debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FREQCORR</name>
+          <description>Frequency Correction</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <description>Correction Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>SIGN</name>
+              <description>Correction Sign</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>MODE2 Clock Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>AM when CLKREP in 12-hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>PM when CLKREP in 12-hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>ALARM%s</name>
+          <description>MODE2 Alarm n Value</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SECOND</name>
+              <description>Second</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>MINUTE</name>
+              <description>Minute</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>HOUR</name>
+              <description>Hour</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <enumeratedValues>
+                <name>HOURSelect</name>
+                <enumeratedValue>
+                  <name>AM</name>
+                  <description>Morning hour</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PM</name>
+                  <description>Afternoon hour</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DAY</name>
+              <description>Day</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>MONTH</name>
+              <description>Month</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>YEAR</name>
+              <description>Year</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>1</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>MASK%s</name>
+          <description>MODE2 Alarm n Mask</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Alarm Mask Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>SELSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Alarm Disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SS</name>
+                  <description>Match seconds only</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMSS</name>
+                  <description>Match seconds and minutes only</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HHMMSS</name>
+                  <description>Match seconds, minutes, and hours only</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, and days only</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, and months only</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>YYMMDDHHMMSS</name>
+                  <description>Match seconds, minutes, hours, days, months, and years</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- RtcMode2 -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SERCOM0</name>
+      <version>2.0.0</version>
+      <description>Serial Communication Interface 0</description>
+      <groupName>SERCOM</groupName>
+      <prependToName>SERCOM_</prependToName>
+      <baseAddress>0x42000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SERCOM0_INTREQ</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>I2CM</name>
+        <description>I2C Master Mode</description>
+        <headerStructName>SercomI2cm</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CM Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>MEXTTOEN</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INACTOUT</name>
+              <description>Inactive Time-Out</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CM Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QCEN</name>
+              <description>Quick Command Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>I2CM Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>BAUDLOW</name>
+              <description>Baud Rate Value Low</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUD</name>
+              <description>High Speed Baud Rate Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>HSBAUDLOW</name>
+              <description>High Speed Baud Rate Value Low</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CM Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CM Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CM Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>MB</name>
+              <description>Master On Bus Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SB</name>
+              <description>Slave On Bus Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CM Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ARBLOST</name>
+              <description>Arbitration Lost</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUSSTATE</name>
+              <description>Bus State</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEXTTOUT</name>
+              <description>Master SCL Low Extend Timeout</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LENERR</name>
+              <description>Length Error</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CM Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYSOP</name>
+              <description>System Operation Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CM Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+            <field>
+              <name>LENEN</name>
+              <description>Length Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LEN</name>
+              <description>Length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CM Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>I2CM Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cm -->
+       <cluster>
+        <name>I2CS</name>
+        <description>I2C Slave Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomI2cs</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>I2CS Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PINOUT</name>
+              <description>Pin Usage</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SDAHOLD</name>
+              <description>SDA Hold Time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SEXTTOEN</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPEED</name>
+              <description>Transfer Speed</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SCLSM</name>
+              <description>SCL Clock Stretch Mode</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LOWTOUTEN</name>
+              <description>SCL Low Timeout Enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>I2CS Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SMEN</name>
+              <description>Smart Mode Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GCMD</name>
+              <description>PMBus Group Command</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AACKEN</name>
+              <description>Automatic Address Acknowledge</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACKACT</name>
+              <description>Acknowledge Action</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>I2CS Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>I2CS Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>I2CS Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PREC</name>
+              <description>Stop Received Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMATCH</name>
+              <description>Address Match Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DRDY</name>
+              <description>Data Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>I2CS Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUSERR</name>
+              <description>Bus Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Transmit Collision</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXNACK</name>
+              <description>Received Not Acknowledge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIR</name>
+              <description>Read/Write Direction</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SR</name>
+              <description>Repeated Start</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LOWTOUT</name>
+              <description>SCL Low Timeout</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CLKHOLD</name>
+              <description>Clock Hold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEXTTOUT</name>
+              <description>Slave SCL Low Extend Timeout</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HS</name>
+              <description>High Speed</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>I2CS Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>I2CS Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>GENCEN</name>
+              <description>General Call Address Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>TENBITEN</name>
+              <description>Ten Bit Addressing Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2CS Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomI2cs -->
+       <cluster>
+        <name>SPI</name>
+        <description>SPI Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomSpi</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>SPI Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DOPO</name>
+              <description>Data Out Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DIPO</name>
+              <description>Data In Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CPHA</name>
+              <description>Clock Phase</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>SPI Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>PLOADEN</name>
+              <description>Data Preload Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSDE</name>
+              <description>Slave Select Low Detect Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSSEN</name>
+              <description>Master Slave Select Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AMODE</name>
+              <description>Address Mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>SPI Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>SPI Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>SPI Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>SPI Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SSL</name>
+              <description>Slave Select Low Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SPI Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>SPI Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI Address</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>ADDRMASK</name>
+              <description>Address Mask</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>SPI Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>SPI Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomSpi -->
+       <cluster>
+        <name>USART</name>
+        <description>USART Mode</description>
+        <alternateCluster>I2CM</alternateCluster>
+        <headerStructName>SercomUsart</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>USART Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>USART_EXT_CLK</name>
+                  <description>USART mode with external clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>USART_INT_CLK</name>
+                  <description>USART mode with internal clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_SLAVE</name>
+                  <description>SPI mode with external clock</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SPI_MASTER</name>
+                  <description>SPI mode with internal clock</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_SLAVE</name>
+                  <description>I2C mode with external clock</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>I2C_MASTER</name>
+                  <description>I2C mode with internal clock</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run during Standby</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IBON</name>
+              <description>Immediate Buffer Overflow Notification</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SAMPR</name>
+              <description>Sample</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TXPO</name>
+              <description>Transmit Data Pinout</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>RXPO</name>
+              <description>Receive Data Pinout</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>SAMPA</name>
+              <description>Sample Adjustment</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>FORM</name>
+              <description>Frame Format</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CMODE</name>
+              <description>Communication Mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPOL</name>
+              <description>Clock Polarity</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DORD</name>
+              <description>Data Order</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>USART Control B</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CHSIZE</name>
+              <description>Character Size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>SBMODE</name>
+              <description>Stop Bit Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLDEN</name>
+              <description>Collision Detection Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SFDE</name>
+              <description>Start of Frame Detection Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENC</name>
+              <description>Encoding Format</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PMODE</name>
+              <description>Parity Mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXEN</name>
+              <description>Transmitter Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXEN</name>
+              <description>Receiver Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD</name>
+          <description>USART Baud Rate</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRAC_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_FRACFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+            </field>
+            <field>
+              <name>FP</name>
+              <description>Fractional Part</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BAUD_USARTFP_MODE</name>
+          <description>USART Baud Rate</description>
+          <alternateRegister>BAUD</alternateRegister>
+          <addressOffset>0x0C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>BAUD</name>
+              <description>Baud Rate Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXPL</name>
+          <description>USART Receive Pulse Length</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>RXPL</name>
+              <description>Receive Pulse Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>USART Interrupt Enable Clear</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>USART Interrupt Enable Set</description>
+          <addressOffset>0x16</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>USART Interrupt Flag Status and Clear</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DRE</name>
+              <description>Data Register Empty Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXC</name>
+              <description>Transmit Complete Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXC</name>
+              <description>Receive Complete Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXS</name>
+              <description>Receive Start Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTSIC</name>
+              <description>Clear To Send Input Change Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXBRK</name>
+              <description>Break Received Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERROR</name>
+              <description>Combined Error Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>USART Status</description>
+          <addressOffset>0x1A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PERR</name>
+              <description>Parity Error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FERR</name>
+              <description>Frame Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUFOVF</name>
+              <description>Buffer Overflow</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTS</name>
+              <description>Clear To Send</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ISF</name>
+              <description>Inconsistent Sync Field</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COLL</name>
+              <description>Collision Detected</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>USART Syncbusy</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>SERCOM Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>CTRLB Synchronization Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>USART Data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Data Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>USART Debug Control</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGSTOP</name>
+              <description>Debug Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- SercomUsart -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM1</name>
+      <description>Serial Communication Interface 1</description>
+      <baseAddress>0x42000C00</baseAddress>
+      <interrupt>
+        <name>SERCOM1_INTREQ</name>
+        <value>10</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM2</name>
+      <description>Serial Communication Interface 2</description>
+      <baseAddress>0x42001000</baseAddress>
+      <interrupt>
+        <name>SERCOM2_INTREQ</name>
+        <value>11</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM3</name>
+      <description>Serial Communication Interface 3</description>
+      <baseAddress>0x42001400</baseAddress>
+      <interrupt>
+        <name>SERCOM3_INTREQ</name>
+        <value>12</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM4</name>
+      <description>Serial Communication Interface 4</description>
+      <baseAddress>0x42001800</baseAddress>
+      <interrupt>
+        <name>SERCOM4_INTREQ</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SERCOM0">
+      <name>SERCOM5</name>
+      <description>Serial Communication Interface 5</description>
+      <baseAddress>0x42001C00</baseAddress>
+      <interrupt>
+        <name>SERCOM5_INTREQ</name>
+        <value>14</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSCTRL</name>
+      <version>2.0.1</version>
+      <description>System Control</description>
+      <groupName>SYSCTRL</groupName>
+      <prependToName>SYSCTRL_</prependToName>
+      <baseAddress>0x40000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSCTRL_INTREQ</name>
+        <value>1</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x04</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection Interrupt Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCLKSR</name>
+          <description>Power and Clocks Status</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>XOSCRDY</name>
+              <description>XOSC Ready</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XOSC32KRDY</name>
+              <description>XOSC32K Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC32KRDY</name>
+              <description>OSC32K Ready</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OSC8MRDY</name>
+              <description>OSC8M Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRDY</name>
+              <description>DFLL Ready</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLOOB</name>
+              <description>DFLL Out Of Bounds</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKF</name>
+              <description>DFLL Lock Fine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLLCKC</name>
+              <description>DFLL Lock Coarse</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFLLRCS</name>
+              <description>DFLL Reference Clock Stopped</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33RDY</name>
+              <description>BOD33 Ready</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BOD33DET</name>
+              <description>BOD33 Detection</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>B33SRDY</name>
+              <description>BOD33 Synchronization Ready</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKR</name>
+              <description>DPLL Lock Rise</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLCKF</name>
+              <description>DPLL Lock Fall</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPLLLTO</name>
+              <description>DPLL Lock Timeout</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC</name>
+          <description>External Multipurpose Crystal Oscillator (XOSC) Control</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GAIN</name>
+              <description>Oscillator Gain</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>GAINSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>2MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>4MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>16MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4</name>
+                  <description>30MHz</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>AMPGC</name>
+              <description>Automatic Amplitude Gain Control</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Start-Up Time</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XOSC32K</name>
+          <description>32kHz External Crystal Oscillator (XOSC32K) Control</description>
+          <addressOffset>0x14</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>XTALEN</name>
+              <description>Crystal Oscillator Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>AAMPEN</name>
+              <description>Automatic Amplitude Control Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC32K</name>
+          <description>32kHz Internal Oscillator (OSC32K) Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <resetValue>0x003F0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN32K</name>
+              <description>32kHz Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EN1K</name>
+              <description>1kHz Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STARTUP</name>
+              <description>Oscillator Start-Up Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSCULP32K</name>
+          <description>32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>8</size>
+          <resetValue>0x1F</resetValue>
+          <fields>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>WRTLOCK</name>
+              <description>Write Lock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OSC8M</name>
+          <description>8MHz Internal Oscillator (OSC8M) Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <resetValue>0x87070382</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Oscillator Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESC</name>
+              <description>Oscillator Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>1</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Oscillator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>FRANGE</name>
+              <description>Oscillator Frequency Range</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FRANGESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>4 to 6MHz</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>6 to 8MHz</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>8 to 11MHz</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>3</name>
+                  <description>11 to 15MHz</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLCTRL</name>
+          <description>DFLL48M Control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>16</size>
+          <resetValue>0x0080</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DFLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode Selection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STABLE</name>
+              <description>Stable DFLL Frequency</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LLAW</name>
+              <description>Lose Lock After Wake</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>USBCRM</name>
+              <description>USB Clock Recovery Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Control</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCDIS</name>
+              <description>Chill Cycle Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QLDIS</name>
+              <description>Quick Lock Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BPLCKC</name>
+              <description>Bypass Coarse Lock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAITLOCK</name>
+              <description>Wait Lock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLVAL</name>
+          <description>DFLL48M Value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FINE</name>
+              <description>Fine Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>COARSE</name>
+              <description>Coarse Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>DIFF</name>
+              <description>Multiplication Ratio Difference</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLMUL</name>
+          <description>DFLL48M Multiplier</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>MUL</name>
+              <description>DFLL Multiply Factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+            <field>
+              <name>FSTEP</name>
+              <description>Fine Maximum Step</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>CSTEP</name>
+              <description>Coarse Maximum Step</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DFLLSYNC</name>
+          <description>DFLL48M Synchronization</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>READREQ</name>
+              <description>Read Request</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD33</name>
+          <description>3.3V Brown-Out Detector (BOD33) Control</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HYST</name>
+              <description>Hysteresis</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ACTION</name>
+              <description>BOD33 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>ACTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>The BOD33 generates a reset</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>The BOD33 generates an interrupt</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CEN</name>
+              <description>Clock Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PSEL</name>
+              <description>Prescaler Select</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PSELSelect</name>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide clock by 2</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide clock by 4</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide clock by 8</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide clock by 16</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32</name>
+                  <description>Divide clock by 32</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide clock by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>Divide clock by 128</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide clock by 256</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>Divide clock by 512</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1K</name>
+                  <description>Divide clock by 1024</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2K</name>
+                  <description>Divide clock by 2048</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4K</name>
+                  <description>Divide clock by 4096</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8K</name>
+                  <description>Divide clock by 8192</description>
+                  <value>0xc</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16K</name>
+                  <description>Divide clock by 16384</description>
+                  <value>0xd</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV32K</name>
+                  <description>Divide clock by 32768</description>
+                  <value>0xe</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64K</name>
+                  <description>Divide clock by 65536</description>
+                  <value>0xf</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LEVEL</name>
+              <description>BOD33 Threshold Level</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREG</name>
+          <description>Voltage Regulator System (VREG) Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FORCELDO</name>
+              <description>Force LDO Voltage Regulator</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VREF</name>
+          <description>Voltage References System (VREF) Control</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>TSEN</name>
+              <description>Temperature Sensor Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BGOUTEN</name>
+              <description>Bandgap Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CALIB</name>
+              <description>Bandgap Voltage Generator Calibration</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLA</name>
+          <description>DPLL Control A</description>
+          <addressOffset>0x44</addressOffset>
+          <size>8</size>
+          <resetValue>0x80</resetValue>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONDEMAND</name>
+              <description>On Demand Clock Activation</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLRATIO</name>
+          <description>DPLL Ratio Control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>LDR</name>
+              <description>Loop Divider Ratio</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+            </field>
+            <field>
+              <name>LDRFRAC</name>
+              <description>Loop Divider Ratio Fractional Part</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLCTRLB</name>
+          <description>DPLL Control B</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>FILTER</name>
+              <description>Proportional Integral Filter Selection</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>FILTERSelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>Default filter mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LBFILT</name>
+                  <description>Low bandwidth filter</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HBFILT</name>
+                  <description>High bandwidth filter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HDFILT</name>
+                  <description>High damping filter</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LPEN</name>
+              <description>Low-Power Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WUF</name>
+              <description>Wake Up Fast</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>REFCLK</name>
+              <description>Reference Clock Selection</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>REFCLKSelect</name>
+                <enumeratedValue>
+                  <name>REF0</name>
+                  <description>CLK_DPLL_REF0 clock reference</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>REF1</name>
+                  <description>CLK_DPLL_REF1 clock reference</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>GCLK_DPLL clock reference</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LTIME</name>
+              <description>Lock Time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>LTIMESelect</name>
+                <enumeratedValue>
+                  <name>DEFAULT</name>
+                  <description>No time-out</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8MS</name>
+                  <description>Time-out if no lock within 8 ms</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>9MS</name>
+                  <description>Time-out if no lock within 9 ms</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>10MS</name>
+                  <description>Time-out if no lock within 10 ms</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>11MS</name>
+                  <description>Time-out if no lock within 11 ms</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LBYPASS</name>
+              <description>Lock Bypass</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Clock Divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPLLSTATUS</name>
+          <description>DPLL Status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>DPLL Lock Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLKRDY</name>
+              <description>Output Clock Ready</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>DPLL Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIV</name>
+              <description>Divider Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TC3</name>
+      <version>1.2.1</version>
+      <description>Basic Timer Counter 3</description>
+      <groupName>TC</groupName>
+      <prependToName>TC_</prependToName>
+      <baseAddress>0x42002C00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TC3_INTREQ</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>COUNT8</name>
+        <description>8-bit Counter Mode</description>
+        <headerStructName>TcCount8</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT8 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>COUNT8 Period Value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>8</size>
+          <resetValue>0xFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT8 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount8 -->
+       <cluster>
+        <name>COUNT16</name>
+        <description>16-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount16</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT16 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x2</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT16 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount16 -->
+       <cluster>
+        <name>COUNT32</name>
+        <description>32-bit Counter Mode</description>
+        <alternateCluster>COUNT8</alternateCluster>
+        <headerStructName>TcCount32</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>TC Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>COUNT16</name>
+                  <description>Counter in 16-bit mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT8</name>
+                  <description>Counter in 8-bit mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT32</name>
+                  <description>Counter in 32-bit mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation Operation</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPWM</name>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>Prescaler: GCLK_TC</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Prescaler: GCLK_TC/2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Prescaler: GCLK_TC/4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Prescaler: GCLK_TC/8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Prescaler: GCLK_TC/16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Prescaler: GCLK_TC/64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Prescaler: GCLK_TC/256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Prescaler: GCLK_TC/1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset the counter on next generic clock</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset the counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset the counter on next generic clock. Reset the prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>READREQ</name>
+          <description>Read Request</description>
+          <addressOffset>0x02</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>ADDR</name>
+              <description>Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>RCONT</name>
+              <description>Read Continuously</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RREQ</name>
+              <description>Read Request</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <resetValue>0x02</resetValue>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>Command</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Force a start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force a stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLC</name>
+          <description>Control C</description>
+          <addressOffset>0x06</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Invert Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Invert Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x08</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Run Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x0A</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>EVACT</name>
+              <description>Event Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACTSelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or retrigger TC on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start TC on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period captured in CC0, pulse width in CC1</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period captured in CC1, pulse width in CC0</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TCINV</name>
+              <description>TC Inverted Event Input</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI</name>
+              <description>TC Event Input</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Event Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x0D</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x0E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SYNCRDY</name>
+              <description>Synchronization Ready</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x0F</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x08</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>COUNT32 Counter Value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Count Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>COUNT32 Compare/Capture</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- TcCount32 -->
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC4</name>
+      <description>Basic Timer Counter 4</description>
+      <baseAddress>0x42003000</baseAddress>
+      <interrupt>
+        <name>TC4_INTREQ</name>
+        <value>19</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC5</name>
+      <description>Basic Timer Counter 5</description>
+      <baseAddress>0x42003400</baseAddress>
+      <interrupt>
+        <name>TC5_INTREQ</name>
+        <value>20</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC6</name>
+      <description>Basic Timer Counter 6</description>
+      <baseAddress>0x42003800</baseAddress>
+      <interrupt>
+        <name>TC6_INTREQ</name>
+        <value>21</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TC3">
+      <name>TC7</name>
+      <description>Basic Timer Counter 7</description>
+      <baseAddress>0x42003C00</baseAddress>
+      <interrupt>
+        <name>TC7_INTREQ</name>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TCC0</name>
+      <version>1.0.1</version>
+      <description>Timer Counter Control 0</description>
+      <groupName>TCC</groupName>
+      <prependToName>TCC_</prependToName>
+      <baseAddress>0x42002000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x090</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TCC0_INTREQ</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RESOLUTION</name>
+              <description>Enhanced Resolution</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RESOLUTIONSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>Dithering is disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH4</name>
+                  <description>Dithering is done every 16 PWM frames</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH5</name>
+                  <description>Dithering is done every 32 PWM frames</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DITH6</name>
+                  <description>Dithering is done every 64 PWM frames</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>PRESCALER</name>
+              <description>Prescaler</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>PRESCALERSelect</name>
+                <enumeratedValue>
+                  <name>DIV1</name>
+                  <description>No division</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV2</name>
+                  <description>Divide by 2</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV4</name>
+                  <description>Divide by 4</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV8</name>
+                  <description>Divide by 8</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV16</name>
+                  <description>Divide by 16</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV64</name>
+                  <description>Divide by 64</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>Divide by 256</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>Divide by 1024</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PRESCSYNC</name>
+              <description>Prescaler and Counter Synchronization Selection</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>PRESCSYNCSelect</name>
+                <enumeratedValue>
+                  <name>GCLK</name>
+                  <description>Reload or reset counter on next GCLK</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PRESC</name>
+                  <description>Reload or reset counter on next prescaler clock</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESYNC</name>
+                  <description>Reload or reset counter on next GCLK and reset prescaler counter</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ALOCK</name>
+              <description>Auto Lock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN0</name>
+              <description>Capture Channel 0 Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN1</name>
+              <description>Capture Channel 1 Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN2</name>
+              <description>Capture Channel 2 Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CPTEN3</name>
+              <description>Capture Channel 3 Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBCLR</name>
+          <description>Control B Clear</description>
+          <addressOffset>0x04</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLBSET</name>
+          <description>Control B Set</description>
+          <addressOffset>0x05</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DIR</name>
+              <description>Counter Direction</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LUPD</name>
+              <description>Lock Update</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ONESHOT</name>
+              <description>One-Shot</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>IDXCMD</name>
+              <description>Ramp Index Command</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>IDXCMDSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Command disabled: Index toggles between cycles A and B</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SET</name>
+                  <description>Set index: cycle B will be forced in the next cycle</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CLEAR</name>
+                  <description>Clear index: cycle A will be forced in the next cycle</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOLD</name>
+                  <description>Hold index: the next cycle will be the same as the current cycle</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CMD</name>
+              <description>TCC Command</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CMDSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No action</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Clear start, restart or retrigger</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Force stop</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPDATE</name>
+                  <description>Force update of double buffered registers</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>READSYNC</name>
+                  <description>Force COUNT read synchronization</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x08</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Swrst Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CTRLB</name>
+              <description>Ctrlb Busy</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STATUS</name>
+              <description>Status Busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>COUNT</name>
+              <description>Count Busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATT</name>
+              <description>Pattern Busy</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVE</name>
+              <description>Wave Busy</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC0</name>
+              <description>Compare Channel 0 Busy</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC1</name>
+              <description>Compare Channel 1 Busy</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC2</name>
+              <description>Compare Channel 2 Busy</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CC3</name>
+              <description>Compare Channel 3 Busy</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PATTB</name>
+              <description>Pattern Buffer Busy</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEB</name>
+              <description>Wave Buffer Busy</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Busy</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB0</name>
+              <description>Compare Channel Buffer 0 Busy</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB1</name>
+              <description>Compare Channel Buffer 1 Busy</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB2</name>
+              <description>Compare Channel Buffer 2 Busy</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCB3</name>
+              <description>Compare Channel Buffer 3 Busy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLA</name>
+          <description>Recoverable Fault A Configuration</description>
+          <addressOffset>0x0C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault A Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault A Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault A Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault A Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault A Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault A Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault A Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault A Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault A Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault A Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FCTRLB</name>
+          <description>Recoverable Fault B Configuration</description>
+          <addressOffset>0x10</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>SRC</name>
+              <description>Fault B Source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SRCSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Fault input disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <description>MCEx (x=0,1) event input</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INVERT</name>
+                  <description>Inverted MCEx (x=0,1) event input</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ALTFAULT</name>
+                  <description>Alternate fault (A or B) state at the end of the previous period</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>KEEP</name>
+              <description>Fault B Keeper</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>QUAL</name>
+              <description>Fault B Qualification</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BLANK</name>
+              <description>Fault B Blanking Mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>BLANKSelect</name>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No blanking applied</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RISE</name>
+                  <description>Blanking applied from rising edge of the output waveform</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALL</name>
+                  <description>Blanking applied from falling edge of the output waveform</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Blanking applied from each toggle of the output waveform</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RESTART</name>
+              <description>Fault B Restart</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>HALT</name>
+              <description>Fault B Halt Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>HALTSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Halt action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HW</name>
+                  <description>Hardware halt action</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SW</name>
+                  <description>Software halt action</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NR</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CHSEL</name>
+              <description>Fault B Capture Channel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CHSELSelect</name>
+                <enumeratedValue>
+                  <name>CC0</name>
+                  <description>Capture value stored in channel 0</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC1</name>
+                  <description>Capture value stored in channel 1</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC2</name>
+                  <description>Capture value stored in channel 2</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CC3</name>
+                  <description>Capture value stored in channel 3</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CAPTURE</name>
+              <description>Fault B Capture Action</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>CAPTURESelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>No capture</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPT</name>
+                  <description>Capture on fault</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMIN</name>
+                  <description>Minimum capture</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAPTMAX</name>
+                  <description>Maximum capture</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMIN</name>
+                  <description>Minimum local detection</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOCMAX</name>
+                  <description>Maximum local detection</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DERIV0</name>
+                  <description>Minimum and maximum local detection</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>BLANKVAL</name>
+              <description>Fault B Blanking Time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL</name>
+              <description>Fault B Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WEXCTRL</name>
+          <description>Waveform Extension Configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OTMX</name>
+              <description>Output Matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN0</name>
+              <description>Dead-time Insertion Generator 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN1</name>
+              <description>Dead-time Insertion Generator 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN2</name>
+              <description>Dead-time Insertion Generator 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTIEN3</name>
+              <description>Dead-time Insertion Generator 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DTLS</name>
+              <description>Dead-time Low Side Outputs Value</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+            <field>
+              <name>DTHS</name>
+              <description>Dead-time High Side Outputs Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DRVCTRL</name>
+          <description>Driver Control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>NRE0</name>
+              <description>Non-Recoverable State 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE1</name>
+              <description>Non-Recoverable State 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE2</name>
+              <description>Non-Recoverable State 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE3</name>
+              <description>Non-Recoverable State 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE4</name>
+              <description>Non-Recoverable State 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE5</name>
+              <description>Non-Recoverable State 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE6</name>
+              <description>Non-Recoverable State 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRE7</name>
+              <description>Non-Recoverable State 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV0</name>
+              <description>Non-Recoverable State 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV1</name>
+              <description>Non-Recoverable State 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV2</name>
+              <description>Non-Recoverable State 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV3</name>
+              <description>Non-Recoverable State 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV4</name>
+              <description>Non-Recoverable State 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV5</name>
+              <description>Non-Recoverable State 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV6</name>
+              <description>Non-Recoverable State 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>NRV7</name>
+              <description>Non-Recoverable State 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN0</name>
+              <description>Output Waveform 0 Inversion</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN1</name>
+              <description>Output Waveform 1 Inversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN2</name>
+              <description>Output Waveform 2 Inversion</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN3</name>
+              <description>Output Waveform 3 Inversion</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN4</name>
+              <description>Output Waveform 4 Inversion</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN5</name>
+              <description>Output Waveform 5 Inversion</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN6</name>
+              <description>Output Waveform 6 Inversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>INVEN7</name>
+              <description>Output Waveform 7 Inversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL0</name>
+              <description>Non-Recoverable Fault Input 0 Filter Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FILTERVAL1</name>
+              <description>Non-Recoverable Fault Input 1 Filter Value</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBGCTRL</name>
+          <description>Debug Control</description>
+          <addressOffset>0x1E</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DBGRUN</name>
+              <description>Debug Running Mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FDDBD</name>
+              <description>Fault Detection on Debug Break Detection</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVCTRL</name>
+          <description>Event Control</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>EVACT0</name>
+              <description>Timer/counter Input Event0 Action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT0Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Start, restart or re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNTEV</name>
+                  <description>Count on event</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Start counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INC</name>
+                  <description>Increment counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>COUNT</name>
+                  <description>Count on active state of asynchronous event</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>EVACT1</name>
+              <description>Timer/counter Input Event1 Action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>EVACT1Select</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Event action disabled</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RETRIGGER</name>
+                  <description>Re-trigger counter on event</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIR</name>
+                  <description>Direction control</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Stop counter on event</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DEC</name>
+                  <description>Decrement counter on event</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PPW</name>
+                  <description>Period capture value in CC0 register, pulse width capture value in CC1 register</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PWP</name>
+                  <description>Period capture value in CC1 register, pulse width capture value in CC0 register</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FAULT</name>
+                  <description>Non-recoverable fault</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CNTSEL</name>
+              <description>Timer/counter Output Event Mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CNTSELSelect</name>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>END</name>
+                  <description>An interrupt/event is generated when a counter cycle ends</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BETWEEN</name>
+                  <description>An interrupt/event is generated when a counter cycle ends, except for the first and last cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOUNDARY</name>
+                  <description>An interrupt/event is generated when a new counter cycle starts or a counter cycle ends</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>OVFEO</name>
+              <description>Overflow/Underflow Output Event Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRGEO</name>
+              <description>Retrigger Output Event Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNTEO</name>
+              <description>Timer/counter Output Event Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV0</name>
+              <description>Inverted Event 0 Input Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCINV1</name>
+              <description>Inverted Event 1 Input Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI0</name>
+              <description>Timer/counter Event 0 Input Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TCEI1</name>
+              <description>Timer/counter Event 1 Input Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI0</name>
+              <description>Match or Capture Channel 0 Event Input Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI1</name>
+              <description>Match or Capture Channel 1 Event Input Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI2</name>
+              <description>Match or Capture Channel 2 Event Input Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEI3</name>
+              <description>Match or Capture Channel 3 Event Input Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO0</name>
+              <description>Match or Capture Channel 0 Event Output Enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO1</name>
+              <description>Match or Capture Channel 1 Event Output Enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO2</name>
+              <description>Match or Capture Channel 2 Event Output Enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MCEO3</name>
+              <description>Match or Capture Channel 3 Event Output Enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault Interrupt Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A Interrupt Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B Interrupt Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 Interrupt Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 Interrupt Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture Channel 0 Interrupt Enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture Channel 1 Interrupt Enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture Channel 2 Interrupt Enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture Channel 3 Interrupt Enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>OVF</name>
+              <description>Overflow</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRG</name>
+              <description>Retrigger</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CNT</name>
+              <description>Counter</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>Error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC0</name>
+              <description>Match or Capture 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC1</name>
+              <description>Match or Capture 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC2</name>
+              <description>Match or Capture 2</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MC3</name>
+              <description>Match or Capture 3</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>32</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STOP</name>
+              <description>Stop</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDX</name>
+              <description>Ramp</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFS</name>
+              <description>Non-Recoverable Debug Fault State</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLAVE</name>
+              <description>Slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PATTBV</name>
+              <description>Pattern Buffer Valid</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAVEBV</name>
+              <description>Wave Buffer Valid</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERBV</name>
+              <description>Period Buffer Valid</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTAIN</name>
+              <description>Recoverable Fault A Input</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTBIN</name>
+              <description>Recoverable Fault B Input</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0IN</name>
+              <description>Non-Recoverable Fault0 Input</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1IN</name>
+              <description>Non-Recoverable Fault1 Input</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULTA</name>
+              <description>Recoverable Fault A State</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULTB</name>
+              <description>Recoverable Fault B State</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT0</name>
+              <description>Non-Recoverable Fault 0 State</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>FAULT1</name>
+              <description>Non-Recoverable Fault 1 State</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV0</name>
+              <description>Compare Channel 0 Buffer Valid</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV1</name>
+              <description>Compare Channel 1 Buffer Valid</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV2</name>
+              <description>Compare Channel 2 Buffer Valid</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CCBV3</name>
+              <description>Compare Channel 3 Buffer Valid</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CMP0</name>
+              <description>Compare Channel 0 Value</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP1</name>
+              <description>Compare Channel 1 Value</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP2</name>
+              <description>Compare Channel 2 Value</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMP3</name>
+              <description>Compare Channel 3 Value</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT</name>
+          <description>Count</description>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH4</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH5</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNT_DITH6</name>
+          <description>Count</description>
+          <alternateRegister>COUNT</alternateRegister>
+          <addressOffset>0x34</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>COUNT</name>
+              <description>Counter Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATT</name>
+          <description>Pattern</description>
+          <addressOffset>0x38</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGE0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGE7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV0</name>
+              <description>Pattern Generator 0 Output Value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV1</name>
+              <description>Pattern Generator 1 Output Value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV2</name>
+              <description>Pattern Generator 2 Output Value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV3</name>
+              <description>Pattern Generator 3 Output Value</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV4</name>
+              <description>Pattern Generator 4 Output Value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV5</name>
+              <description>Pattern Generator 5 Output Value</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV6</name>
+              <description>Pattern Generator 6 Output Value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGV7</name>
+              <description>Pattern Generator 7 Output Value</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVE</name>
+          <description>Waveform Control</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGEN</name>
+              <description>Waveform Generation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMP</name>
+              <description>Ramp Mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPEREN</name>
+              <description>Circular period Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN0</name>
+              <description>Circular Channel 0 Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN1</name>
+              <description>Circular Channel 1 Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN2</name>
+              <description>Circular Channel 2 Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCEN3</name>
+              <description>Circular Channel 3 Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL0</name>
+              <description>Channel 0 Polarity</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL1</name>
+              <description>Channel 1 Polarity</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL2</name>
+              <description>Channel 2 Polarity</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POL3</name>
+              <description>Channel 3 Polarity</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP0</name>
+              <description>Swap DTI Output Pair 0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP1</name>
+              <description>Swap DTI Output Pair 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP2</name>
+              <description>Swap DTI Output Pair 2</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAP3</name>
+              <description>Swap DTI Output Pair 3</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER</name>
+          <description>Period</description>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH4</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH5</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PER_DITH6</name>
+          <description>Period</description>
+          <alternateRegister>PER</alternateRegister>
+          <addressOffset>0x40</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PER</name>
+              <description>Period Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s</name>
+          <description>Compare and Capture</description>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH4</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH5</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CC%s_DITH6</name>
+          <description>Compare and Capture</description>
+          <alternateRegister>CC%s</alternateRegister>
+          <addressOffset>0x44</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCY</name>
+              <description>Dithering Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CC</name>
+              <description>Channel Compare/Capture Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PATTB</name>
+          <description>Pattern Buffer</description>
+          <addressOffset>0x64</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>PGEB0</name>
+              <description>Pattern Generator 0 Output Enable Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB1</name>
+              <description>Pattern Generator 1 Output Enable Buffer</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB2</name>
+              <description>Pattern Generator 2 Output Enable Buffer</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB3</name>
+              <description>Pattern Generator 3 Output Enable Buffer</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB4</name>
+              <description>Pattern Generator 4 Output Enable Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB5</name>
+              <description>Pattern Generator 5 Output Enable Buffer</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB6</name>
+              <description>Pattern Generator 6 Output Enable Buffer</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGEB7</name>
+              <description>Pattern Generator 7 Output Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB0</name>
+              <description>Pattern Generator 0 Output Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB1</name>
+              <description>Pattern Generator 1 Output Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB2</name>
+              <description>Pattern Generator 2 Output Enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB3</name>
+              <description>Pattern Generator 3 Output Enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB4</name>
+              <description>Pattern Generator 4 Output Enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB5</name>
+              <description>Pattern Generator 5 Output Enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB6</name>
+              <description>Pattern Generator 6 Output Enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PGVB7</name>
+              <description>Pattern Generator 7 Output Enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAVEB</name>
+          <description>Waveform Control Buffer</description>
+          <addressOffset>0x68</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>WAVEGENB</name>
+              <description>Waveform Generation Buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <enumeratedValues>
+                <name>WAVEGENBSelect</name>
+                <enumeratedValue>
+                  <name>NFRQ</name>
+                  <description>Normal frequency</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MFRQ</name>
+                  <description>Match frequency</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NPWM</name>
+                  <description>Normal PWM</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSCRITICAL</name>
+                  <description>Dual-slope critical</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTTOM</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSBOTH</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DSTOP</name>
+                  <description>Dual-slope with interrupt/event condition when COUNT reaches TOP</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>RAMPB</name>
+              <description>Ramp Mode Buffer</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>RAMPBSelect</name>
+                <enumeratedValue>
+                  <name>RAMP1</name>
+                  <description>RAMP1 operation</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2A</name>
+                  <description>Alternative RAMP2 operation</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RAMP2</name>
+                  <description>RAMP2 operation</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>CIPERENB</name>
+              <description>Circular Period Enable Buffer</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB0</name>
+              <description>Circular Channel 0 Enable Buffer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB1</name>
+              <description>Circular Channel 1 Enable Buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB2</name>
+              <description>Circular Channel 2 Enable Buffer</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>CICCENB3</name>
+              <description>Circular Channel 3 Enable Buffer</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB0</name>
+              <description>Channel 0 Polarity Buffer</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB1</name>
+              <description>Channel 1 Polarity Buffer</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB2</name>
+              <description>Channel 2 Polarity Buffer</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>POLB3</name>
+              <description>Channel 3 Polarity Buffer</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB0</name>
+              <description>Swap DTI Output Pair 0 Buffer</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB1</name>
+              <description>Swap DTI Output Pair 1 Buffer</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB2</name>
+              <description>Swap DTI Output Pair 2 Buffer</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWAPB3</name>
+              <description>Swap DTI Output Pair 3 Buffer</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB</name>
+          <description>Period Buffer</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH4</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH5</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERB_DITH6</name>
+          <description>Period Buffer</description>
+          <alternateRegister>PERB</alternateRegister>
+          <addressOffset>0x6C</addressOffset>
+          <size>32</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>PERB</name>
+              <description>Period Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s</name>
+          <description>Compare and Capture Buffer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH4</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>20</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH5</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>19</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CCB%s_DITH6</name>
+          <description>Compare and Capture Buffer</description>
+          <alternateRegister>CCB%s</alternateRegister>
+          <addressOffset>0x70</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DITHERCYB</name>
+              <description>Dithering Buffer Cycle Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+            </field>
+            <field>
+              <name>CCB</name>
+              <description>Channel Compare/Capture Buffer Value</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>18</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC1</name>
+      <description>Timer Counter Control 1</description>
+      <baseAddress>0x42002400</baseAddress>
+      <interrupt>
+        <name>TCC1_INTREQ</name>
+        <value>16</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="TCC0">
+      <name>TCC2</name>
+      <description>Timer Counter Control 2</description>
+      <baseAddress>0x42002800</baseAddress>
+      <interrupt>
+        <name>TCC2_INTREQ</name>
+        <value>17</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>USB</name>
+      <version>1.0.1</version>
+      <description>Universal Serial Bus</description>
+      <groupName>USB</groupName>
+      <prependToName>USB_</prependToName>
+      <baseAddress>0x41005000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_INTREQ</name>
+        <value>7</value>
+      </interrupt>
+      <registers>
+       <cluster>
+        <name>DEVICE</name>
+        <description>USB is Device</description>
+        <headerStructName>UsbDevice</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>DEVICE Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <resetValue>0x0001</resetValue>
+          <fields>
+            <field>
+              <name>DETACH</name>
+              <description>Detach</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>FS : Full Speed</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>LS : Low Speed</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>HS : High Speed capable</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HSTM</name>
+                  <description>HSTM: High Speed Test Mode (force high-speed mode for test mode)</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>NREPLY</name>
+              <description>No Reply</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTPCKT</name>
+              <description>Test packet mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>OPMODE2</name>
+              <description>Specific Operational Mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>GNAK</name>
+              <description>Global NAK</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMHDSK</name>
+              <description>Link Power Management Handshake</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>LPMHDSKSelect</name>
+                <enumeratedValue>
+                  <name>NO</name>
+                  <description>No handshake. LPM is not supported</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ACK</name>
+                  <description>ACK</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NYET</name>
+                  <description>NYET</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>STALL</name>
+                  <description>STALL</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DADD</name>
+          <description>DEVICE Device Address</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>DADD</name>
+              <description>Device Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+            </field>
+            <field>
+              <name>ADDEN</name>
+              <description>Device Address Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>DEVICE Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x40</resetValue>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>SPEEDSelect</name>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HS</name>
+                  <description>High-speed mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LS</name>
+                  <description>Low-speed mode</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>LINESTATESelect</name>
+                <enumeratedValue>
+                  <name>0</name>
+                  <description>SE0/RESET</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1</name>
+                  <description>FS-J or LS-K State</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2</name>
+                  <description>FS-K or LS-J State</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>DEVICE Device Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FNCERR</name>
+              <description>Frame Number CRC Error</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>DEVICE Device Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>DEVICE Device Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame Interrupt Enable in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>DEVICE Device Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>SUSPEND</name>
+              <description>Suspend</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MSOF</name>
+              <description>Micro Start of Frame in High Speed Mode</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOF</name>
+              <description>Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORST</name>
+              <description>End of Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>EORSM</name>
+              <description>End Of Resume</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMNYET</name>
+              <description>Link Power Management Not Yet</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>LPMSUSP</name>
+              <description>Link Power Management Suspend</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EPINTSMRY</name>
+          <description>DEVICE End Point Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>End Point 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>End Point 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>End Point 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>End Point 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>End Point 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>End Point 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>End Point 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>End Point 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPCFG%s</name>
+          <description>DEVICE End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EPTYPE0</name>
+              <description>End Point Type0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <description>End Point Type1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>NYETDIS</name>
+              <description>NYET Token Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSCLR%s</name>
+          <description>DEVICE End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank Clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUSSET%s</name>
+          <description>DEVICE End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle OUT Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle IN Set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request Set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPSTATUS%s</name>
+          <description>DEVICE End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGLOUT</name>
+              <description>Data Toggle Out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTGLIN</name>
+              <description>Data Toggle In</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ0</name>
+              <description>Stall 0 Request</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STALLRQ1</name>
+              <description>Stall 1 Request</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTFLAG%s</name>
+          <description>DEVICE End Point Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENCLR%s</name>
+          <description>DEVICE End Point Interrupt Clear Flag</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/Out Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/Out Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>EPINTENSET%s</name>
+          <description>DEVICE End Point Interrupt Set Flag</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL0</name>
+              <description>Error Flow 0 Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL1</name>
+              <description>Error Flow 1 Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RXSTP</name>
+              <description>Received Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <description>Stall 0 In/out Interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <description>Stall 1 In/out Interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbDevice -->
+       <cluster>
+        <name>HOST</name>
+        <description>USB is Host</description>
+        <alternateCluster>DEVICE</alternateCluster>
+        <headerStructName>UsbHost</headerStructName>
+        <addressOffset>0x0</addressOffset>
+        <register>
+          <name>CTRLA</name>
+          <description>Control A</description>
+          <addressOffset>0x000</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RUNSTDBY</name>
+              <description>Run in Standby Mode</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Operating Mode</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <enumeratedValues>
+                <name>MODESelect</name>
+                <enumeratedValue>
+                  <name>DEVICE</name>
+                  <description>Device Mode</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HOST</name>
+                  <description>Host Mode</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYNCBUSY</name>
+          <description>Synchronization Busy</description>
+          <addressOffset>0x002</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SWRST</name>
+              <description>Software Reset Synchronization Busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable Synchronization Busy</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QOSCTRL</name>
+          <description>USB Quality Of Service</description>
+          <addressOffset>0x003</addressOffset>
+          <size>8</size>
+          <resetValue>0x05</resetValue>
+          <fields>
+            <field>
+              <name>CQOS</name>
+              <description>Configuration Quality of Service</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>CQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DQOS</name>
+              <description>Data Quality of Service</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>DQOSSelect</name>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <description>Background (no sensitive operation)</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <description>Sensitive Bandwidth</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <description>Sensitive Latency</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <description>Critical Latency</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRLB</name>
+          <description>HOST Control B</description>
+          <addressOffset>0x008</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>RESUME</name>
+              <description>Send USB Resume</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SPDCONF</name>
+              <description>Speed Configuration for Host</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <enumeratedValues>
+                <name>SPDCONFSelect</name>
+                <enumeratedValue>
+                  <name>NORMAL</name>
+                  <description>Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FS</name>
+                  <description>Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TSTJ</name>
+              <description>Test mode J</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TSTK</name>
+              <description>Test mode K</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SOFE</name>
+              <description>Start of Frame Generation Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BUSRESET</name>
+              <description>Send USB Reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>VBUSOK</name>
+              <description>VBUS is OK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>L1RESUME</name>
+              <description>Send L1 Resume</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HSOFC</name>
+          <description>HOST Host Start Of Frame Control</description>
+          <addressOffset>0x00A</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>FLENC</name>
+              <description>Frame Length Control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>FLENCE</name>
+              <description>Frame Length Control Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>HOST Status</description>
+          <addressOffset>0x00C</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>SPEED</name>
+              <description>Speed Status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>LINESTATE</name>
+              <description>USB Line State Status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSMSTATUS</name>
+          <description>Finite State Machine Status</description>
+          <addressOffset>0x00D</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <resetValue>0x01</resetValue>
+          <fields>
+            <field>
+              <name>FSMSTATE</name>
+              <description>Fine State Machine Status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <name>FSMSTATESelect</name>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>OFF (L3). It corresponds to the powered-off, disconnected, and disabled state</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ON</name>
+                  <description>ON (L0). It corresponds to the Idle and Active states</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SUSPEND</name>
+                  <description>SUSPEND (L2)</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SLEEP</name>
+                  <description>SLEEP (L1)</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DNRESUME</name>
+                  <description>DNRESUME. Down Stream Resume.</description>
+                  <value>0x10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UPRESUME</name>
+                  <description>UPRESUME. Up Stream Resume.</description>
+                  <value>0x20</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>RESET. USB lines Reset.</description>
+                  <value>0x40</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FNUM</name>
+          <description>HOST Host Frame Number</description>
+          <addressOffset>0x010</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>MFNUM</name>
+              <description>Micro Frame Number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>FNUM</name>
+              <description>Frame Number</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLENHIGH</name>
+          <description>HOST Host Frame Length</description>
+          <addressOffset>0x012</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>FLENHIGH</name>
+              <description>Frame Length</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>HOST Host Interrupt Enable Clear</description>
+          <addressOffset>0x014</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>BUS Reset Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to Device Interrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from Device Interrupt Disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection Interrupt Disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>HOST Host Interrupt Enable Set</description>
+          <addressOffset>0x018</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>DownStream to the Device Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume fromthe device Interrupt Enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access Interrupt Enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Link Power Management Interrupt Enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection Interrupt Enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>HOST Host Interrupt Flag</description>
+          <addressOffset>0x01C</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>HSOF</name>
+              <description>Host Start Of Frame</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>Bus Reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WAKEUP</name>
+              <description>Wake Up</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DNRSM</name>
+              <description>Downstream</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>UPRSM</name>
+              <description>Upstream Resume from the Device</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>RAMACER</name>
+              <description>Ram Access</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DCONN</name>
+              <description>Device Connection</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>DDISC</name>
+              <description>Device Disconnection</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PINTSMRY</name>
+          <description>HOST Pipe Interrupt Summary</description>
+          <addressOffset>0x020</addressOffset>
+          <size>16</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>EPINT0</name>
+              <description>Pipe 0 Interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT1</name>
+              <description>Pipe 1 Interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT2</name>
+              <description>Pipe 2 Interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT3</name>
+              <description>Pipe 3 Interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT4</name>
+              <description>Pipe 4 Interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT5</name>
+              <description>Pipe 5 Interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT6</name>
+              <description>Pipe 6 Interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPINT7</name>
+              <description>Pipe 7 Interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESCADD</name>
+          <description>Descriptor Address</description>
+          <addressOffset>0x024</addressOffset>
+          <size>32</size>
+          <fields>
+            <field>
+              <name>DESCADD</name>
+              <description>Descriptor Address Value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PADCAL</name>
+          <description>USB PAD Calibration</description>
+          <addressOffset>0x028</addressOffset>
+          <size>16</size>
+          <fields>
+            <field>
+              <name>TRANSP</name>
+              <description>USB Pad Transp calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRANSN</name>
+              <description>USB Pad Transn calibration</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+            </field>
+            <field>
+              <name>TRIM</name>
+              <description>USB Pad Trim calibration</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PCFG%s</name>
+          <description>HOST End Point Configuration</description>
+          <addressOffset>0x100</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>PTOKEN</name>
+              <description>Pipe Token</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+            <field>
+              <name>BK</name>
+              <description>Pipe Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PTYPE</name>
+              <description>Pipe Type</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>BINTERVAL%s</name>
+          <description>HOST Bus Access Period of Pipe</description>
+          <addressOffset>0x103</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>BITINTERVAL</name>
+              <description>Bit Interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSCLR%s</name>
+          <description>HOST End Point Pipe Status Clear</description>
+          <addressOffset>0x104</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Curren Bank clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUSSET%s</name>
+          <description>HOST End Point Pipe Status Set</description>
+          <addressOffset>0x105</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle Set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank Set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze Set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 Ready Set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 Ready Set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PSTATUS%s</name>
+          <description>HOST End Point Pipe Status</description>
+          <addressOffset>0x106</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>DTGL</name>
+              <description>Data Toggle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CURBK</name>
+              <description>Current Bank</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PFREEZE</name>
+              <description>Pipe Freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK0RDY</name>
+              <description>Bank 0 ready</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BK1RDY</name>
+              <description>Bank 1 ready</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTFLAG%s</name>
+          <description>HOST Pipe Interrupt Flag</description>
+          <addressOffset>0x107</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Flag</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Flag</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Flag</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Flag</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENCLR%s</name>
+          <description>HOST Pipe Interrupt Flag Clear</description>
+          <addressOffset>0x108</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Inetrrupt Disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x20</dimIncrement>
+          <name>PINTENSET%s</name>
+          <description>HOST Pipe Interrupt Flag Set</description>
+          <addressOffset>0x109</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>TRCPT0</name>
+              <description>Transfer Complete 0 Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRCPT1</name>
+              <description>Transfer Complete 1 Interrupt Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TRFAIL</name>
+              <description>Error Flow Interrupt Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>PERR</name>
+              <description>Pipe Error Interrupt Enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>TXSTP</name>
+              <description>Transmit  Setup Interrupt Enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>STALL</name>
+              <description>Stall Interrupt Enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+       </cluster> <!-- UsbHost -->
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <version>2.0.0</version>
+      <description>Watchdog Timer</description>
+      <groupName>WDT</groupName>
+      <prependToName>WDT_</prependToName>
+      <baseAddress>0x40001000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WDT_INTREQ</name>
+        <value>2</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WEN</name>
+              <description>Watchdog Timer Window Mode Enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>ALWAYSON</name>
+              <description>Always-On</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG</name>
+          <description>Configuration</description>
+          <addressOffset>0x1</addressOffset>
+          <size>8</size>
+          <resetValue>0xBB</resetValue>
+          <fields>
+            <field>
+              <name>PER</name>
+              <description>Time-Out Period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>PERSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WINDOW</name>
+              <description>Window Mode Time-Out Period</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>WINDOWSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EWCTRL</name>
+          <description>Early Warning Interrupt Control</description>
+          <addressOffset>0x2</addressOffset>
+          <size>8</size>
+          <resetValue>0x0B</resetValue>
+          <fields>
+            <field>
+              <name>EWOFFSET</name>
+              <description>Early Warning Interrupt Time Offset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <enumeratedValues>
+                <name>EWOFFSETSelect</name>
+                <enumeratedValue>
+                  <name>8</name>
+                  <description>8 clock cycles</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16</name>
+                  <description>16 clock cycles</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>32</name>
+                  <description>32 clock cycles</description>
+                  <value>0x2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>64</name>
+                  <description>64 clock cycles</description>
+                  <value>0x3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>128</name>
+                  <description>128 clock cycles</description>
+                  <value>0x4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <description>256 clock cycles</description>
+                  <value>0x5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <description>512 clock cycles</description>
+                  <value>0x6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1K</name>
+                  <description>1024 clock cycles</description>
+                  <value>0x7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>2K</name>
+                  <description>2048 clock cycles</description>
+                  <value>0x8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4K</name>
+                  <description>4096 clock cycles</description>
+                  <value>0x9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8K</name>
+                  <description>8192 clock cycles</description>
+                  <value>0xa</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>16K</name>
+                  <description>16384 clock cycles</description>
+                  <value>0xb</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENCLR</name>
+          <description>Interrupt Enable Clear</description>
+          <addressOffset>0x4</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTENSET</name>
+          <description>Interrupt Enable Set</description>
+          <addressOffset>0x5</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning Interrupt Enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTFLAG</name>
+          <description>Interrupt Flag Status and Clear</description>
+          <addressOffset>0x6</addressOffset>
+          <size>8</size>
+          <fields>
+            <field>
+              <name>EW</name>
+              <description>Early Warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status</description>
+          <addressOffset>0x7</addressOffset>
+          <size>8</size>
+          <access>read-only</access>
+          <fields>
+            <field>
+              <name>SYNCBUSY</name>
+              <description>Synchronization Busy</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR</name>
+          <description>Clear</description>
+          <addressOffset>0x8</addressOffset>
+          <size>8</size>
+          <access>write-only</access>
+          <fields>
+            <field>
+              <name>CLEAR</name>
+              <description>Watchdog Clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+              <enumeratedValues>
+                <name>CLEARSelect</name>
+                <enumeratedValue>
+                  <name>KEY</name>
+                  <description>Clear Key</description>
+                  <value>0xa5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/uf2-samdx1/lib/samd21/samd21a/templates/library.c b/uf2-samdx1/lib/samd21/samd21a/templates/library.c
new file mode 100644
index 00000000..e9780854
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/templates/library.c
@@ -0,0 +1,15 @@
+/*
+ * $projectname$.c
+ *
+ * Created: $date$
+ * Author : $user$
+ */ 
+
+#include "sam.h"
+
+
+/* Replace with your library code */
+int myfunc(void)
+{
+	return 0;
+}
diff --git a/uf2-samdx1/lib/samd21/samd21a/templates/library.cpp b/uf2-samdx1/lib/samd21/samd21a/templates/library.cpp
new file mode 100644
index 00000000..ea4a55a2
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/templates/library.cpp
@@ -0,0 +1,15 @@
+/*
+ * $projectname$.cpp
+ *
+ * Created: $date$
+ * Author : $user$
+ */ 
+
+#include "sam.h"
+
+
+/* Replace with your library code */
+int myfunc(void)
+{
+	return 0;
+}
diff --git a/uf2-samdx1/lib/samd21/samd21a/templates/main.c b/uf2-samdx1/lib/samd21/samd21a/templates/main.c
new file mode 100644
index 00000000..f718b447
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/templates/main.c
@@ -0,0 +1,21 @@
+/*
+ * $projectname$.c
+ *
+ * Created: $date$
+ * Author : $user$
+ */ 
+
+
+#include "sam.h"
+
+
+int main(void)
+{
+    /* Initialize the SAM system */
+    SystemInit();
+
+    /* Replace with your application code */
+    while (1) 
+    {
+    }
+}
diff --git a/uf2-samdx1/lib/samd21/samd21a/templates/main.cpp b/uf2-samdx1/lib/samd21/samd21a/templates/main.cpp
new file mode 100644
index 00000000..ce48c3c3
--- /dev/null
+++ b/uf2-samdx1/lib/samd21/samd21a/templates/main.cpp
@@ -0,0 +1,21 @@
+/*
+ * $projectname$.cpp
+ *
+ * Created: $date$
+ * Author : $user$
+ */ 
+
+
+#include "sam.h"
+
+
+int main(void)
+{
+    /* Initialize the SAM system */
+    SystemInit();
+
+    /* Replace with your application code */
+    while (1) 
+    {
+    }
+}
diff --git a/uf2-samdx1/lib/uf2/.clang-format b/uf2-samdx1/lib/uf2/.clang-format
new file mode 100644
index 00000000..08abf793
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/.clang-format
@@ -0,0 +1,4 @@
+BasedOnStyle: LLVM
+IndentWidth: 4
+UseTab: Never
+ColumnLimit: 100
diff --git a/uf2-samdx1/lib/uf2/.gitignore b/uf2-samdx1/lib/uf2/.gitignore
new file mode 100644
index 00000000..d41b5102
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/.gitignore
@@ -0,0 +1,7 @@
+tmp
+*.sw?
+flash.uf2
+flash.bin
+
+built/
+uf2tool/uf2hid.h
diff --git a/uf2-samdx1/lib/uf2/.gitmodules b/uf2-samdx1/lib/uf2/.gitmodules
new file mode 100644
index 00000000..2c6b3070
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "hidapi"]
+	path = hidapi
+	url = ../../signal11/hidapi
diff --git a/uf2-samdx1/lib/uf2/LICENSE.txt b/uf2-samdx1/lib/uf2/LICENSE.txt
new file mode 100644
index 00000000..d3e3605f
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/LICENSE.txt
@@ -0,0 +1,25 @@
+Microsoft UF2
+
+The MIT License (MIT)
+
+Copyright (c) Microsoft Corporation
+
+All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/uf2-samdx1/lib/uf2/README.md b/uf2-samdx1/lib/uf2/README.md
new file mode 100644
index 00000000..7a60bf58
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/README.md
@@ -0,0 +1,342 @@
+# USB Flashing Format (UF2)
+
+UF2 is a file format, developed by Microsoft for [PXT](https://github.com/Microsoft/pxt) 
+(also known as [Microsoft MakeCode](https://makecode.com)), that is particularly suitable for 
+flashing microcontrollers over MSC (Mass Storage Class; aka removable flash drive).
+
+For a more friendly explanation, check out [this blog post](https://makecode.com/blog/one-chip-to-flash-them-all).
+Also, take a look at the list of [implementations](#implementations) at the bottom of this document.
+
+## Overview
+
+The UF2 file consists of 512 byte blocks, each of which is self-contained and independent of others. 
+Each 512 byte block consists of (see below for details):
+* magic numbers at the beginning and at the end
+* address where the data should be flashed
+* up to 476 bytes of data
+
+The data transfers over MSC always arrive in multiples of 512 bytes.
+Together with the FAT file system structure, this means that blocks of the
+UF2 file are always aligned with the MSC writes - the microcontroller 
+never gets a partial file.
+
+The magic numbers let the microcontroller distinguish an UF2 file block from
+other data (eg., FAT table entry, or various book-keeping files stored by some
+operating systems).  When a UF2 block is recognized, it can be flashed
+immediately (unless flash page size is more than 256 bytes; in that case a buffer
+is needed). The actual handling of file format during writing is very simple
+(~10 lines of C code in simplest version).
+
+## File format
+
+A UF2 file consists of 512 byte blocks. Each block starts with a 32 byte
+header, followed by data, and a final magic number.
+All fields, except for data, are 32 bit unsigned little endian integers.
+
+| Offset | Size | Value                                             |
+|--------|------|---------------------------------------------------|
+| 0      | 4    | First magic number, `0x0A324655` (`"UF2\n"`)      |
+| 4      | 4    | Second magic number, `0x9E5D5157`                 |
+| 8      | 4    | Flags                                             |
+| 12     | 4    | Address in flash where the data should be written |
+| 16     | 4    | Number of bytes used in data (often 256)          |
+| 20     | 4    | Sequential block number; starts at 0              |
+| 24     | 4    | Total number of blocks in file                    |
+| 28     | 4    | File size or board family ID or zero              |
+| 32     | 476  | Data, padded with zeros                           |
+| 508    | 4    | Final magic number, `0x0AB16F30`                  |
+
+The following C struct can be used:
+
+```C
+struct UF2_Block {
+    // 32 byte header
+    uint32_t magicStart0;
+    uint32_t magicStart1;
+    uint32_t flags;
+    uint32_t targetAddr;
+    uint32_t payloadSize;
+    uint32_t blockNo;
+    uint32_t numBlocks;
+    uint32_t fileSize; // or familyID;
+    uint8_t data[476];
+    uint32_t magicEnd;
+} UF2_Block;
+```
+
+### Flags
+
+Currently, there are five flags defined:
+
+* `0x00000001` - **not main flash** - this block should be skipped when writing the
+  device flash; it can be used to store "comments" in the file, typically
+  embedded source code or debug info that does not fit on the device flash
+* `0x00001000` - **file container** - see below
+* `0x00002000` - **familyID present** - when set, the `fileSize/familyID` holds a value
+  identifying the board family (usually corresponds to an MCU)
+* `0x00004000` - **MD5 checksum present** - see below
+* `0x00008000` - **extension tags present** - see below
+
+### Family ID
+
+This field is optional, and should be set only when the corresponding
+flag is set. It is recommended that new bootloaders require the field to
+be set appropriately, and refuse to flash UF2 files without it.
+If you're developing your own bootloader, and your
+board family isn't listed here, pick a new family ID at random. It's good
+to also send a PR here, so your family can be listed.
+
+If the `familyID` doesn't match, the bootloader should disregard the
+entire block, including `blockNo` and `numBlocks` fields.
+In particular, writing a full UF2 file with non-matching `familyID`
+should not reset the board.
+This also allows for several files with different `familyID` to be
+simply concatenated together, and the whole resulting file to be copied
+to the device with only one actually being written to flash.
+
+#### Picking numbers at random
+
+The reason to pick numbers at random is to minimize risk of collisions
+in the wild. Do not pick random numbers by banging on keyboard, or by using
+`0xdeadf00d`, `0x42424242` etc. A good way is to use the following
+shell command: `printf "0x%04x%04x\n" $RANDOM $RANDOM`
+Another good way is the link at the bottom of https://microsoft.github.io/uf2/patcher/
+This procedure was unfortunately not used for the SAMD51 and NRF52840 below.
+
+#### Family list
+
+The current master list of family IDs is maintained in a [JSON file](utils/uf2families.json).
+
+### Rationale
+
+The magic number at the end is meant to mitigate partial block writes.
+
+Second and final magic numbers were randomly selected, except for the last byte
+of final magic number, which was forced to be `'\n'` (`0xA`). Together with the
+first magic number being `"UF2\n"` this makes it easy to identify UF2 blocks in
+a text editor.
+
+The header is padded to 32 bytes, as hex editors commonly use 16 or 32 bytes
+as line length.  This way, the data payload is aligned to line start.
+
+32 bit integers are used for all fields so that large flash sizes can be
+supported in future, as well as for simplicity. Little endian is used, as most
+microcontrollers are little endian. 8 bit microcontrollers can choose to just
+use the first 16 bits of various header fields.
+
+The total number of blocks in the file and the sequential block number make it
+easy for the bootloader to detect that all blocks have been transferred. It
+requires one bit of memory per block (eg., on SAMD21G18A it's 128 bytes).
+Alternatively, the bootloader might ignore that and just implement a reset
+after say 1 second break in incoming UF2 blocks.
+
+### Payload sizes
+
+The number of data bytes is configurable and depends on the size of
+the flash page (that is the smallest size that can be erased) on the
+microcontroller.
+
+* if the page size is more than `476` bytes, the bootloader should support
+  any payload size, as it needs to buffer the entire page in memory anyway
+* if the page size is less than `476` bytes, the payload should be a multiple
+  of page size, so it can be written without buffering; the target address
+  should also be a multiple of page size
+
+In any event, payload size and target address should always be 4-byte aligned.
+
+Note that payload size of `256` is always correct, and makes it easy to convert
+between flash addresses and UF2 file offsets.
+
+For example, on Atmel's SAMD21 chips the page size is `256` bytes, and this 
+also is the payload size. If the page size was `128` bytes, one could use
+payload of `128*3`. Nordic nRF51 has page size of `1024` bytes, and thus 
+any payload size should be allowed.
+
+### Embedding sources
+
+Some IDEs will embed program sources in the UF2 file. This allows a UF2 files to be
+loaded by the IDE and serve as a natural backup and transfer format.
+This can be done in two ways:
+
+* using the "not main flash" flag
+* using normal blocks that are flashed to the device
+
+If the bootloader can expose `CURRENT.UF2` file (see below) and there is enough
+flash available, than the second option is more desirable, as it allows sharing
+programs directly from the board.
+
+See https://makecode.com/source-embedding for more info.
+
+### Robustness
+
+The file format is designed specifically to deal with the following problems:
+
+* operating system (OS) writing blocks in different order than occurs in a file
+* OS writing blocks multiple times
+* OS writing data that is not UF2 blocks
+* OS writing first/final part of a block, possibly for metadata detection or search indexing
+
+The only file system assumption we make is that blocks of file are aligned with
+blocks on the hard drive. It's likely true of many file systems besides FAT.
+
+We also assume that USB MSC device reports its block size to be a multiple of `512`
+bytes. In the wild these devices always almost report exactly `512`, and some
+operating systems do not support other values.
+
+## Files exposed by bootloaders
+
+Bootloaders may expose virtual files in their MSC devices.  These are
+standardized here, so that flashing tools can automatically detect the
+bootloaders.
+
+* `INFO_UF2.TXT` - contains information about the bootloader build and the board on which it is running
+* `INDEX.HTM` - redirects to a page that contains an IDE or other information
+* `CURRENT.UF2` - the contents of the entire flash of the device, starting at `0x00000000`, with `256` payload size;
+  thus, the size of this file will report as twice the size of flash
+
+Flashing tools can use the presence of `INFO_UF2.TXT` (in upper or lower case,
+as FAT is case-insensitive) file as an indication that a given directory is
+actually a connected UF2 board. The other files should not be used for
+detection.
+
+Typical `INFO_UF2.TXT` file looks like this:
+```
+UF2 Bootloader v1.1.3 SFA
+Model: Arduino Zero
+Board-ID: SAMD21G18A-Zero-v0
+```
+
+The `Board-ID` field is machine-readable and consists of a number of dash-separated tokens.
+The first token is the CPU type, second is the board type, and third is the board revision.
+More tokens can be also added.
+
+The bootloader should contain its info file as a static string somewhere in its code.
+If possible, the last word of the bootloader code should point to this string.
+This way, the info file can be found in the initial section of the `CURRENT.UF2`
+file as well. Thus, a board type can be determined from the contents of `CURRENT.UF2`.
+This is particularly useful with the source embedding (see above).
+
+## File containers
+
+It is also possible to use the UF2 format as a container for one or more
+regular files (akin to a TAR file, or ZIP archive without compression).  This
+is useful when the embedded device being flashed sports a file system.
+
+The program to run may reside in one of the files, or in the main flash memory.
+
+In such a usage the `file container` flag is set on blocks, the field `fileSize`
+holds the file size of the current file, and the field `targetAddr` holds the
+offset in current file.
+
+The `not main flash` flag on blocks should be ignored when the `file container` is set.
+
+The file name is stored at `&data[payloadSize]` (ie., right after the actual payload) and
+terminated with a `0x00` byte.  The format of filename is dependent on the
+bootloader (usually implemented as some sort of file system daemon). 
+
+The bootloader will usually allow any size of the payload.
+
+The current files on device might be exposed as multiple UF2 files, instead of
+a single `CURRENT.UF2`. They may reside in directories, however, due to UF2 general
+design, it doesn't matter which directory the UF2 file is written to.
+
+Typical writing procedure is as follows:
+* validate UF2 magic numbers
+* make sure that `targetAddr < fileSize` and that `fileSize` isn't out of reasonable range
+* write `0x00` at `data[475]` to ensure NUL termination of file name
+* read file name from `&data[payloadSize]`; perform any mapping on the file name
+* create a directory where the file is to be written if it doesn't exist
+* open the file for writing
+* truncate the file to `fileSize`
+* seek `targetAddr`
+* write the payload (ie., `data[0 ... payloadSize - 1]`)
+* close the file
+
+The fields `blockNo` and `numBlocks` refer to the entire UF2 file, not the current
+file.
+
+## MD5 checksum
+
+When the `0x4000` flag is set, the last 24 bytes of `data[]` hold the following structure:
+
+| Offset | Size | Value                                             |
+|--------|------|---------------------------------------------------|
+| 0      | 4    | Start address of region                           |
+| 4      | 4    | Length of region in bytes                         |
+| 8      | 16   | MD5 checksum in binary format                     |
+
+The flashing program should compute the MD5 sum of the specified region.
+If the region checksum matches, flashing of the current block can be skipped.
+Typically, many blocks in sequence will have the same region specified,
+and can all be skipped, if the matching succeeded.
+The position of the current block will typically be inside of the region.
+The position and size of the region should be multiple of page erase size
+(4k or 64k on typical SPI flash).
+
+This is currently only used on ESP32, which is also why MD5 checksum is used.
+
+## Extension tags
+
+When the `0x8000` flag is set, additional information can be appended right after
+payload data (i.e., it starts at `32 + payloadSize`).
+Every tag starts at 4 byte boundary.
+The first byte of tag contains its total size in bytes (including the size byte
+and type designation).
+The next three bytes designate the type of tag (if you want to define custom
+tags, pick them at random).
+The last tag has size of `0` and type of `0`.
+
+Standard tag designations follow:
+* `0x9fc7bc` - version of firmware file - UTF8 semver string
+* `0x650d9d` - description of device for which the firmware file is destined (UTF8)
+* `0x0be9f7` - page size of target device (32 bit unsigned number)
+* `0xb46db0` - SHA-2 checksum of firmware (can be of various size)
+* `0xc8a729` - device type identifier - a refinement of `familyID` meant to identify a kind of device
+  (eg., a toaster with specific pinout and heating unit), not only MCU; 32 or 64 bit number; can be hash of `0x650d9d`
+
+For example, the following bytes encode firmware version `0.1.2` for device
+named `ACME Toaster mk3` (line breaks added for clarity):
+
+```
+09 bc c7 9f 30 2e 31 2e 32 00 00 00
+14 9d 0d 65 41 43 4d 45 20 54 6f 61 73 74 65 72 20 6d 6b 33
+00 00 00 00
+```
+
+Extension tags can, but don't have to, be repeated in all blocks.
+
+## Implementations
+
+### Bootloaders
+
+* [Microchip ATSAMD21 and ATSAMD51](https://github.com/Microsoft/uf2-samdx1)
+* [Arduino UNO](https://github.com/mmoskal/uf2-uno)
+* [STM32F103](https://github.com/mmoskal/uf2-stm32)
+* [STM32F4](https://github.com/mmoskal/uf2-stm32f)
+* [Nordic NRF52840](https://github.com/adafruit/Adafruit_nRF52840_Bootloader)
+* [Linux (RPi Zero)](https://github.com/microsoft/uf2-linux)
+* [Cypress FX2](https://github.com/whitequark/libfx2/tree/master/firmware/boot-uf2)
+* [Tiny UF2](https://github.com/adafruit/tinyuf2) - Support ESP32-S2, iMXRT10xx, STM32F4
+* [RP2040 chip](https://www.raspberrypi.org/products/raspberry-pi-pico/) - native support in silicon
+* [UF2-ChibiOS](https://github.com/striso/uf2-ChibiOS) - Supports STM32H7
+
+There's an ongoing effort to implement UF2 in [Codal](https://github.com/lancaster-university/codal-core).
+
+### Editors
+
+* https://arcade.makecode.com
+* https://makecode.adafruit.com
+* https://makecode.seeedstudio.com
+* https://maker.makecode.com
+
+### Libraries
+
+* https://www.npmjs.com/package/uf2
+
+## License
+
+MIT
+
+## Code of Conduct
+
+This project has adopted the [Microsoft Open Source Code of Conduct](https://opensource.microsoft.com/codeofconduct/). For more information see the [Code of Conduct FAQ](https://opensource.microsoft.com/codeofconduct/faq/) or contact [opencode@microsoft.com](mailto:opencode@microsoft.com) with any additional questions or comments.
diff --git a/uf2-samdx1/lib/uf2/SECURITY.md b/uf2-samdx1/lib/uf2/SECURITY.md
new file mode 100644
index 00000000..869fdfe2
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/SECURITY.md
@@ -0,0 +1,41 @@
+<!-- BEGIN MICROSOFT SECURITY.MD V0.0.7 BLOCK -->
+
+## Security
+
+Microsoft takes the security of our software products and services seriously, which includes all source code repositories managed through our GitHub organizations, which include [Microsoft](https://github.com/Microsoft), [Azure](https://github.com/Azure), [DotNet](https://github.com/dotnet), [AspNet](https://github.com/aspnet), [Xamarin](https://github.com/xamarin), and [our GitHub organizations](https://opensource.microsoft.com/).
+
+If you believe you have found a security vulnerability in any Microsoft-owned repository that meets [Microsoft's definition of a security vulnerability](https://aka.ms/opensource/security/definition), please report it to us as described below.
+
+## Reporting Security Issues
+
+**Please do not report security vulnerabilities through public GitHub issues.**
+
+Instead, please report them to the Microsoft Security Response Center (MSRC) at [https://msrc.microsoft.com/create-report](https://aka.ms/opensource/security/create-report).
+
+If you prefer to submit without logging in, send email to [secure@microsoft.com](mailto:secure@microsoft.com).  If possible, encrypt your message with our PGP key; please download it from the [Microsoft Security Response Center PGP Key page](https://aka.ms/opensource/security/pgpkey).
+
+You should receive a response within 24 hours. If for some reason you do not, please follow up via email to ensure we received your original message. Additional information can be found at [microsoft.com/msrc](https://aka.ms/opensource/security/msrc). 
+
+Please include the requested information listed below (as much as you can provide) to help us better understand the nature and scope of the possible issue:
+
+  * Type of issue (e.g. buffer overflow, SQL injection, cross-site scripting, etc.)
+  * Full paths of source file(s) related to the manifestation of the issue
+  * The location of the affected source code (tag/branch/commit or direct URL)
+  * Any special configuration required to reproduce the issue
+  * Step-by-step instructions to reproduce the issue
+  * Proof-of-concept or exploit code (if possible)
+  * Impact of the issue, including how an attacker might exploit the issue
+
+This information will help us triage your report more quickly.
+
+If you are reporting for a bug bounty, more complete reports can contribute to a higher bounty award. Please visit our [Microsoft Bug Bounty Program](https://aka.ms/opensource/security/bounty) page for more details about our active programs.
+
+## Preferred Languages
+
+We prefer all communications to be in English.
+
+## Policy
+
+Microsoft follows the principle of [Coordinated Vulnerability Disclosure](https://aka.ms/opensource/security/cvd).
+
+<!-- END MICROSOFT SECURITY.MD BLOCK -->
diff --git a/uf2-samdx1/lib/uf2/_config.yml b/uf2-samdx1/lib/uf2/_config.yml
new file mode 100644
index 00000000..c4192631
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/_config.yml
@@ -0,0 +1 @@
+theme: jekyll-theme-cayman
\ No newline at end of file
diff --git a/uf2-samdx1/lib/uf2/cf2.md b/uf2-samdx1/lib/uf2/cf2.md
new file mode 100644
index 00000000..a71a0b89
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/cf2.md
@@ -0,0 +1,126 @@
+# Binary Bootloader-embedded Config (CF2)
+
+## Motivation
+
+The goal of CF2 is to run the same binary on a number of devices with different
+peripheral configuration, but the same MCU.
+Typically, this has been achieved by embedding identification components in hardware
+(eg. connecting certain MCU pins to GND or 3V) and having the firmware dynamically
+detect these.
+While simple, this only allows a few bits of configuration data to be stored on device.
+
+Instead, we use the bootloader area for storing device specific configuration data.
+Such data is not altered when the device is programmed with new firmware,
+and the said firmware can refer to the configuration data in the bootloader area to
+alter its behavior.
+
+For example, MakeCode Arcade requires a device with 7 buttons (directions, A, B, and MENU),
+a screen from a specific family, and one of the few supported accelerometers.
+The exact configuration depends on the manufacturer, but the binary produced by MakeCode
+will work on any device with the right MCU, provided it has the right configuration
+data in the bootloader area.
+
+Thus, the user only needs to select the type of MCU (which is color coded, 
+and is assigned a simple user-facing name), and the resulting binary will work
+on their device.
+Moreover, they can drag the UF2 file between devices, provided they run the same MCU.
+Once bootloaders are updated with networking support (wired or wireless), one device with 
+a given MCU will be able to flash another.
+
+## Configuration data format
+
+Data comes as pairs of 32 bit unsigned integers (in machine byte order).
+* first pair is `0x1e9e10f1, 0x20227a79`
+* second pair consists of the number of configuration entries, and a zero (reserved)
+* then configuration entries follow, where the first element is the configuration
+  entry key number, and the second is the value (these entries are sorted by key number)
+* finally, a number of zeroes follows (typically at least a few hundred), 
+  to store any additional configuration data in future
+
+The file `configkeys.h` with definitions of key names can be downloaded from the 
+patcher website (see below).
+
+If you require your own key names, please use 
+[random large key names](https://github.com/Microsoft/uf2#picking-numbers-at-random).
+
+## The Patcher
+
+At https://microsoft.github.io/uf2/patcher/ we provide a tool, which given a UF2 or BIN file
+and a configuration definition, binary-patches the UF2/BIN file and lets the user download it.
+The tool also parses existing configuration information from the UF2/BIN file to show it.
+
+Such tool is to be used by makers of devices.
+For example, for MakeCode Arcade, this includes both factories and users who take an existing
+multi-purpose board and connect keys and screen.
+Such user would then download generic MakeCode Arcade bootloader (either a UF2 file,
+which upgrades the bootloader, or a .BIN file with the bootloader) for the given MCU,
+and binary patch it with their configuration.
+Then, they would update the bootloader, and have a Arcade-compatible device.
+
+## Configuration file syntax
+
+Example:
+
+```bash
+# This is comment, which is ignored
+// this is also a comment
+
+# Configuration values for display registers and size
+DISPLAY_CFG0 = 0x80
+DISPLAY_CFG1 = 0x603
+DISPLAY_CFG2 = 0x16
+DISPLAY_HEIGHT = 128
+DISPLAY_WIDTH = 160
+
+PINS_PORT_SIZE = PA_32 # see below
+
+# pin headers (if any)
+PIN_A0 = PA02
+PIN_A1 = PA05
+PIN_A2 = PB08
+PIN_D2 = PA07
+PIN_D3 = PB22
+PIN_SCK = PA01
+PIN_MISO = PB23
+PIN_MOSI = PA00
+
+# pin functions
+PIN_BTN_LEFT = PIN_D2        # use pin header name
+PIN_BTN_UP = PB13            # use pin directly
+PIN_DISPLAY_CS = 18          # can even just use a number for the pin
+PIN_DISPLAY_SCK = PIN_SCK
+PIN_DISPLAY_MOSI = PIN_MOSI
+
+# custom configuration keys
+_679732427 = 123
+_815320287 = 0x80192
+
+# remove an existing config entry
+PIN_BTN_MENU2 = null
+```
+
+The keys are either key names, or underscore followed by a decimal number.
+The values are numbers in either decimal or hexadecimal,
+references to other keys, or pin numbers.
+The way pin numbers are parsed depends on the `PINS_PORT_SIZE`:
+* `PA_16` - pins are `PA00`-`PA15`, `PB00-PB15`, ..., used on STM32
+* `PA_32` - pins are `PA00`-`PA31`, ... - used on Microchip ATSAMD
+* `P0_16` - pins are `P0_0`-`P0_15`, `P1_0-P1_15`, ... - not used?
+* `P0_32` - pins are `P0_0-P0_31`, ... - used on Nordic NRF
+* `0` or missing - pins are `P_0`, `P_1`, ..., `P_1000`
+
+Certain keys (like `PINS_PORT_SIZE`) have a number of pre-defined values,
+which can be used instead of integers.
+
+Because you're usually use this syntax to patch an existing configuration,
+you sometimes may want to remove an entry that's already there.
+To do that, use `null` as the value of the key.
+
+For list of keys and predefined values, see `configkeys.h` which can be downloaded
+from the patcher website.
+
+## Running from node.js
+
+The patcher tool can be also run from command line.
+Download [patcher.js](https://raw.githubusercontent.com/Microsoft/uf2/master/patcher/patcher.js)
+and run it with node. It will print out help.
diff --git a/uf2-samdx1/lib/uf2/hf2.md b/uf2-samdx1/lib/uf2/hf2.md
new file mode 100644
index 00000000..ade63442
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hf2.md
@@ -0,0 +1,287 @@
+# HID Flashing Format
+
+HF2 (HID Flashing Format) is a protocol and message format intended for
+communication with embedded devices. Basic functions supported include:
+
+* serial communication for `printf()` debugging etc.
+* flashing (updating device firmware)
+* debugger interfaces
+
+It is optimized for packet formats, where packets are around 64 bytes long.
+It will work for smaller packets, of at least a few bytes, or bigger
+ones, but be less efficient.
+
+In particular, it is suitable for running over USB HID (Human Interface Device),
+which is widely supported in various operating systems without the need for kernel-space
+drivers. It is also possible to run the protocol over a WebUSB link with either a single
+interrupt endpoint or two bulk endpoints, as well as using just the control pipe,
+allowing direct access from supported browsers. 
+
+## Raw message format
+
+HF2 messages are composed of packets. Packets are up to 64 bytes long.
+Messages sent from host to device and vice versa have the same basic format.
+
+The first byte of each packet indicates:
+* length of the remaining data (payload) in the packet, in the lower 6 bits, i.e., between 0 and 63 inclusive
+* the type of the packet, in the two high bits.
+
+| Bit 7 | Bit 6 | Hex  | Meaning
+|-------|-------|------|----------------------------------------------
+| 0     | 0     | 0x00 | Inner packet of a command message
+| 0     | 1     | 0x40 | Final packet of a command message
+| 1     | 0     | 0x80 | Serial `stdout`
+| 1     | 1     | 0xC0 | Serial `stderr`
+
+Serial messages are thus between 0 and 63 bytes in length.
+
+Command messages can have any length (though devices will typically limit
+it to the native flash page size + 64 bytes). They consist of a zero or more
+inner packets, followed by a single final packet. Any of these packets
+can carry between 0 and 63 bytes of payload.
+
+For example:
+
+```
+Packet 0: 83 01 02 03 AB FF FF FF
+Packet 1: 85 04 05 06 07 08
+Packet 2: 80 DE 42 42 42 42 FF FF
+Packet 3: D0 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 FF FF FF
+--->
+Decoded: 01 02 03 04 05 06 07 08 D0 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17
+```
+
+Note that packets can be longer than the first byte requires (packets 0, 2, and 3 are).
+The additional data should be discarded.
+This is due to various HID implementations imposing an exact 64 byte packet size.
+
+Different command messages cannot be interleaved.
+
+Serial messages should not be interleaved with command messages (though it would be
+technically possible).
+
+## Higher-level message format
+
+### Serial messages
+
+Serial messages are meant for `printf()` style debugging
+and general simple data output from the device.
+If the device supports only one serial channel, it should support
+the `stdout` channel. Otherwise, `stdout` is meant
+for data output (eg., logging measurements), and `stderr`
+is meant for `printf()` debugging.
+
+The logging application on the host may choose to send these
+two channels into a single output stream.
+
+Serial messages contain between `0` and `63` bytes of payload data. 
+Size of `0` can be used as a keep-alive packet if needed.
+
+### Command messages
+
+Command structure:
+
+```c
+struct Command {
+    uint32_t command_id;
+    uint16_t tag;
+    uint8_t reserved0;
+    uint8_t reserved1;
+    uint8_t data[...];
+};
+
+struct Response {
+    uint16_t tag;
+    uint8_t status;
+    uint8_t status_info;
+    uint8_t data[...];
+};
+```
+
+All words in HF2 are little endian.
+
+The `tag` is an arbitrary number set by the host, for example as sequence 
+number. The response should repeat the `tag`.
+
+The two reserved bytes in the command should be sent as zero and ignored by the device.
+
+The response status is one of the following:
+* `0x00` - command understood and executed correctly
+* `0x01` - command not understood
+* `0x02` - command execution error
+
+Note, that embedded devices might crash on invalid arguments, instead
+of returning errors. OTOH, the devices should always handle invalid commands with
+`0x01` status.
+
+In case of non-zero status, the `status_info` field can contain additional information.
+
+The host shall not send a new command, until the previous one was responded to.
+TODO does this make sense? maybe just let USB flow control handle this?
+
+## Standard commands
+
+Below we list standard commands. Not all commands have to be supported by all
+devices.
+
+When the C fragment states `no results`, it means just a response
+with zero status and no additional data should be expected.
+
+### BININFO (0x0001)
+
+This command states the current mode of the device:
+* ``mode == 0x01`` - bootloader, and thus flashing of user-space programs is allowed
+* ``mode == 0x02`` - user-space mode.
+It also returns the size of flash page size (flashing needs to be done on page-by-page basis),
+and the maximum size of message. It is always the case that 
+``max_message_size >= flash_page_size + 64``.
+
+```c
+struct HF2_BININFO_Result {
+    uint32_t mode;
+    uint32_t flash_page_size;
+    uint32_t flash_num_pages;
+    uint32_t max_message_size;
+    uint32_t family_id; // optional
+};
+```
+
+### INFO (0x0002)
+
+Various device information. 
+The result is a character array. See `INFO_UF2.TXT` in UF2 format for details.
+
+```c
+// no arguments
+struct HF2_INFO_Result {
+    uint8_t info[...];
+};
+```
+
+
+### RESET INTO APP (0x0003)
+
+Reset the device into user-space app. Usually, no response at all will arrive for this command.
+
+```c
+// no arguments, no result
+```
+
+
+### RESET INTO BOOTLOADER (0x0004)
+
+Reset the device into bootloader, usually for flashing. Usually, no response at all will arrive for this command.
+
+```c
+// no arguments, no result
+```
+
+### START FLASH (0x0005)
+
+When issued in bootloader mode, it has no effect.
+In user-space mode it causes handover to bootloader.
+A `BININFO` command can be issued to verify that.
+
+```c
+// no arguments, no result
+```
+
+### WRITE FLASH PAGE (0x0006)
+
+Write a single page of flash memory.
+
+```c
+struct HF2_WRITE_FLASH_PAGE_Command {
+    uint32_t target_addr;
+    uint8_t data[flash_page_size];
+};
+// no result
+```
+
+### CHKSUM PAGES (0x0007)
+
+Compute checksum of a number of pages.
+Maximum value for ``num_pages`` is ``max_message_size / 2 - 2``.
+The checksum algorithm used is CRC-16-CCITT.
+
+```c
+struct HF2_CHKSUM_PAGES_Command {
+    uint32_t target_addr;
+    uint32_t num_pages;
+};
+struct HF2_CHKSUM_PAGES_Result {
+    uint16_t chksums[0 /* num_pages */];
+};
+```
+
+### READ WORDS (0x0008)
+
+Read a number of words from memory. 
+Memory is read word by word (and not byte by byte), and ``target_addr`` must
+be suitably aligned. This is to support reading of special IO regions.
+
+```c
+struct HF2_READ_WORDS_Command {
+    uint32_t target_addr;
+    uint32_t num_words;
+};
+struct HF2_READ_WORDS_Result {
+    uint32_t words[num_words];
+};
+```
+
+### WRITE WORDS (0x0009)
+
+Dual of READ WORDS, with the same constraints.
+
+```c
+struct HF2_WRITE_WORDS_Command {
+    uint32_t target_addr;
+    uint32_t num_words;
+    uint32_t words[num_words];
+};
+// no result
+```
+
+### DMESG (0x0010)
+
+Return internal log buffer if any.
+The result is a character array.
+
+```c
+// no arguments
+struct HF2_DMESG_Result {
+    uint8_t logs[...];
+};
+```
+
+
+## Extensibility
+
+The HF2 protocol is easy to extend with new command messages.  The command ids
+you introduce should be chosen at random.  This ensures very low probability of
+conflict between different extensions.
+
+While numbers like `0x42420123`, `0x10001`, or `0xdeaff00d` may look random,
+others are likely to use them as well and a conflict might occur.
+Please also do not use numbers below `0xffff`, as these are standardized here.
+Ideally, use one of the following commands (or similar) to generate a random number:
+
+```bash
+node -p "require('crypto').randomBytes(4).toString('hex')"
+# or slightly worse:
+printf "%04x%04x\n" $RANDOM $RANDOM
+```
+
+If you change the behavior of a command, even just extend what it can do, and
+there is even a remote possibility of devices or interface applications using
+it in the wild, it's best to introduce a new command, and possibly have the
+device handle both (fall-through `switch` cases are useful here).
+
+## Detection of HF2 devices
+
+## Notes
+
+If the device exposes both HID and WebUSB, it has to use two separate
+interfaces. 
+
diff --git a/uf2-samdx1/lib/uf2/hidapi/.gitattributes b/uf2-samdx1/lib/uf2/hidapi/.gitattributes
new file mode 100644
index 00000000..edb79feb
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/.gitattributes
@@ -0,0 +1,7 @@
+* text=auto
+
+*.sln text eol=crlf
+*.vcproj text eol=crlf
+
+bootstrap text eol=lf
+configure.ac text eol=lf
diff --git a/uf2-samdx1/lib/uf2/hidapi/.gitignore b/uf2-samdx1/lib/uf2/hidapi/.gitignore
new file mode 100644
index 00000000..b43ca58c
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/.gitignore
@@ -0,0 +1,20 @@
+
+# Autotools-added generated files
+Makefile.in
+aclocal.m4
+autom4te.cache/
+config.*
+configure
+depcomp
+install-sh
+libusb/Makefile.in
+linux/Makefile.in
+ltmain.sh
+mac/Makefile.in
+missing
+testgui/Makefile.in
+windows/Makefile.in
+
+Makefile
+stamp-h1
+libtool
diff --git a/uf2-samdx1/lib/uf2/hidapi/AUTHORS.txt b/uf2-samdx1/lib/uf2/hidapi/AUTHORS.txt
new file mode 100644
index 00000000..7acafd78
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/AUTHORS.txt
@@ -0,0 +1,16 @@
+
+HIDAPI Authors:
+
+Alan Ott <alan@signal11.us>:
+	Original Author and Maintainer
+	Linux, Windows, and Mac implementations
+
+Ludovic Rousseau <rousseau@debian.org>:
+	Formatting for Doxygen documentation
+	Bug fixes
+	Correctness fixes
+
+
+For a comprehensive list of contributions, see the commit list at github:
+	http://github.com/signal11/hidapi/commits/master
+
diff --git a/uf2-samdx1/lib/uf2/hidapi/HACKING.txt b/uf2-samdx1/lib/uf2/hidapi/HACKING.txt
new file mode 100644
index 00000000..761d4b65
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/HACKING.txt
@@ -0,0 +1,15 @@
+This file is mostly for the maintainer.
+
+1. Build hidapi.dll
+2. Build hidtest.exe in DEBUG and RELEASE
+3. Commit all
+
+4. Run the Following
+	export VERSION=0.1.0
+	export TAG_NAME=hidapi-$VERSION
+	git tag $TAG_NAME
+	git archive --format zip --prefix $TAG_NAME/ $TAG_NAME >../$TAG_NAME.zip
+5. Test the zip file.
+6. Run the following:
+	git push origin $TAG_NAME
+
diff --git a/uf2-samdx1/lib/uf2/hidapi/LICENSE-bsd.txt b/uf2-samdx1/lib/uf2/hidapi/LICENSE-bsd.txt
new file mode 100644
index 00000000..538cdf95
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/LICENSE-bsd.txt
@@ -0,0 +1,26 @@
+Copyright (c) 2010, Alan Ott, Signal 11 Software
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of Signal 11 Software nor the names of its
+      contributors may be used to endorse or promote products derived from
+      this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/uf2-samdx1/lib/uf2/hidapi/LICENSE-gpl3.txt b/uf2-samdx1/lib/uf2/hidapi/LICENSE-gpl3.txt
new file mode 100644
index 00000000..94a9ed02
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/LICENSE-gpl3.txt
@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+  The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works.  By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users.  We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors.  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
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+free programs, and that you know you can do these things.
+
+  To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights.  Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+  For example, if you distribute copies of such a program, whether
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+  Developers that use the GNU GPL protect your rights with two steps:
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+  For the developers' and authors' protection, the GPL clearly explains
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+  Some devices are designed to deny users access to install or run
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+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+                       TERMS AND CONDITIONS
+
+  0. Definitions.
+
+  "This License" refers to version 3 of the GNU General Public License.
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+  "Copyright" also means copyright-like laws that apply to other kinds of
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+
+  Nothing in this License shall be construed as excluding or limiting
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+
+  12. No Surrender of Others' Freedom.
+
+  If conditions are imposed on you (whether by court order, agreement or
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+
+  13. Use with the GNU Affero General Public License.
+
+  Notwithstanding any other provision of this License, you have
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+
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+be similar in spirit to the present version, but may differ in detail to
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+
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+  If the Program specifies that a proxy can decide which future
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+  15. Disclaimer of Warranty.
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+Program, unless a warranty or assumption of liability accompanies a
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+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
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+
+    <one line to give the program's name and a brief idea of what it does.>
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+    This program is free software: you can redistribute it and/or modify
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+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
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+
+    You should have received a copy of the GNU General Public License
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+
+Also add information on how to contact you by electronic and paper mail.
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+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
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+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.
diff --git a/uf2-samdx1/lib/uf2/hidapi/LICENSE-orig.txt b/uf2-samdx1/lib/uf2/hidapi/LICENSE-orig.txt
new file mode 100644
index 00000000..e3f33808
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/LICENSE-orig.txt
@@ -0,0 +1,9 @@
+ HIDAPI - Multi-Platform library for
+ communication with HID devices.
+
+ Copyright 2009, Alan Ott, Signal 11 Software.
+ All Rights Reserved.
+ 
+ This software may be used by anyone for any reason so
+ long as the copyright notice in the source files
+ remains intact.
diff --git a/uf2-samdx1/lib/uf2/hidapi/LICENSE.txt b/uf2-samdx1/lib/uf2/hidapi/LICENSE.txt
new file mode 100644
index 00000000..e1676d4c
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/LICENSE.txt
@@ -0,0 +1,13 @@
+HIDAPI can be used under one of three licenses.
+
+1. The GNU General Public License, version 3.0, in LICENSE-gpl3.txt
+2. A BSD-Style License, in LICENSE-bsd.txt.
+3. The more liberal original HIDAPI license. LICENSE-orig.txt
+
+The license chosen is at the discretion of the user of HIDAPI. For example:
+1. An author of GPL software would likely use HIDAPI under the terms of the
+GPL.
+
+2. An author of commercial closed-source software would likely use HIDAPI
+under the terms of the BSD-style license or the original HIDAPI license.
+
diff --git a/uf2-samdx1/lib/uf2/hidapi/Makefile.am b/uf2-samdx1/lib/uf2/hidapi/Makefile.am
new file mode 100644
index 00000000..196c991b
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/Makefile.am
@@ -0,0 +1,81 @@
+
+ACLOCAL_AMFLAGS = -I m4
+
+if OS_FREEBSD
+pkgconfigdir=$(prefix)/libdata/pkgconfig
+else
+pkgconfigdir=$(libdir)/pkgconfig
+endif
+
+if OS_LINUX
+pkgconfig_DATA=pc/hidapi-hidraw.pc pc/hidapi-libusb.pc
+else
+pkgconfig_DATA=pc/hidapi.pc
+endif
+
+SUBDIRS=
+
+if OS_LINUX
+SUBDIRS += linux libusb
+endif
+
+if OS_DARWIN
+SUBDIRS += mac
+endif
+
+if OS_FREEBSD
+SUBDIRS += libusb
+endif
+
+if OS_KFREEBSD
+SUBDIRS += libusb
+endif
+
+if OS_WINDOWS
+SUBDIRS += windows
+endif
+
+SUBDIRS += hidtest
+
+if BUILD_TESTGUI
+SUBDIRS += testgui
+endif
+
+EXTRA_DIST = udev doxygen
+
+dist_doc_DATA = \
+ README.txt \
+ AUTHORS.txt \
+ LICENSE-bsd.txt \
+ LICENSE-gpl3.txt \
+ LICENSE-orig.txt \
+ LICENSE.txt
+
+SCMCLEAN_TARGETS= \
+ aclocal.m4 \
+ config.guess \
+ config.sub \
+ configure \
+ config.h.in \
+ depcomp \
+ install-sh \
+ ltmain.sh \
+ missing \
+ mac/Makefile.in \
+ testgui/Makefile.in \
+ libusb/Makefile.in \
+ Makefile.in \
+ linux/Makefile.in \
+ windows/Makefile.in \
+ m4/libtool.m4 \
+ m4/lt~obsolete.m4 \
+ m4/ltoptions.m4 \
+ m4/ltsugar.m4 \
+ m4/ltversion.m4
+
+SCMCLEAN_DIR_TARGETS = \
+ autom4te.cache
+
+scm-clean: distclean
+	rm -f $(SCMCLEAN_TARGETS)
+	rm -Rf $(SCMCLEAN_DIR_TARGETS)
diff --git a/uf2-samdx1/lib/uf2/hidapi/README.txt b/uf2-samdx1/lib/uf2/hidapi/README.txt
new file mode 100644
index 00000000..f19dae4a
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/README.txt
@@ -0,0 +1,339 @@
+         HIDAPI library for Windows, Linux, FreeBSD and Mac OS X
+        =========================================================
+
+About
+======
+
+HIDAPI is a multi-platform library which allows an application to interface
+with USB and Bluetooth HID-Class devices on Windows, Linux, FreeBSD, and Mac
+OS X.  HIDAPI can be either built as a shared library (.so or .dll) or
+can be embedded directly into a target application by adding a single source
+file (per platform) and a single header.
+
+HIDAPI has four back-ends:
+	* Windows (using hid.dll)
+	* Linux/hidraw (using the Kernel's hidraw driver)
+	* Linux/libusb (using libusb-1.0)
+	* FreeBSD (using libusb-1.0)
+	* Mac (using IOHidManager)
+
+On Linux, either the hidraw or the libusb back-end can be used. There are
+tradeoffs, and the functionality supported is slightly different.
+
+Linux/hidraw (linux/hid.c):
+This back-end uses the hidraw interface in the Linux kernel.  While this
+back-end will support both USB and Bluetooth, it has some limitations on
+kernels prior to 2.6.39, including the inability to send or receive feature
+reports.  In addition, it will only communicate with devices which have
+hidraw nodes associated with them.  Keyboards, mice, and some other devices
+which are blacklisted from having hidraw nodes will not work. Fortunately,
+for nearly all the uses of hidraw, this is not a problem.
+
+Linux/FreeBSD/libusb (libusb/hid.c):
+This back-end uses libusb-1.0 to communicate directly to a USB device. This
+back-end will of course not work with Bluetooth devices.
+
+HIDAPI also comes with a Test GUI. The Test GUI is cross-platform and uses
+Fox Toolkit (http://www.fox-toolkit.org).  It will build on every platform
+which HIDAPI supports.  Since it relies on a 3rd party library, building it
+is optional but recommended because it is so useful when debugging hardware.
+
+What Does the API Look Like?
+=============================
+The API provides the the most commonly used HID functions including sending
+and receiving of input, output, and feature reports.  The sample program,
+which communicates with a heavily hacked up version of the Microchip USB
+Generic HID sample looks like this (with error checking removed for
+simplicity):
+
+#ifdef WIN32
+#include <windows.h>
+#endif
+#include <stdio.h>
+#include <stdlib.h>
+#include "hidapi.h"
+
+#define MAX_STR 255
+
+int main(int argc, char* argv[])
+{
+	int res;
+	unsigned char buf[65];
+	wchar_t wstr[MAX_STR];
+	hid_device *handle;
+	int i;
+
+	// Initialize the hidapi library
+	res = hid_init();
+
+	// Open the device using the VID, PID,
+	// and optionally the Serial number.
+	handle = hid_open(0x4d8, 0x3f, NULL);
+
+	// Read the Manufacturer String
+	res = hid_get_manufacturer_string(handle, wstr, MAX_STR);
+	wprintf(L"Manufacturer String: %s\n", wstr);
+
+	// Read the Product String
+	res = hid_get_product_string(handle, wstr, MAX_STR);
+	wprintf(L"Product String: %s\n", wstr);
+
+	// Read the Serial Number String
+	res = hid_get_serial_number_string(handle, wstr, MAX_STR);
+	wprintf(L"Serial Number String: (%d) %s\n", wstr[0], wstr);
+
+	// Read Indexed String 1
+	res = hid_get_indexed_string(handle, 1, wstr, MAX_STR);
+	wprintf(L"Indexed String 1: %s\n", wstr);
+
+	// Toggle LED (cmd 0x80). The first byte is the report number (0x0).
+	buf[0] = 0x0;
+	buf[1] = 0x80;
+	res = hid_write(handle, buf, 65);
+
+	// Request state (cmd 0x81). The first byte is the report number (0x0).
+	buf[0] = 0x0;
+	buf[1] = 0x81;
+	res = hid_write(handle, buf, 65);
+
+	// Read requested state
+	res = hid_read(handle, buf, 65);
+
+	// Print out the returned buffer.
+	for (i = 0; i < 4; i++)
+		printf("buf[%d]: %d\n", i, buf[i]);
+
+	// Finalize the hidapi library
+	res = hid_exit();
+
+	return 0;
+}
+
+If you have your own simple test programs which communicate with standard
+hardware development boards (such as those from Microchip, TI, Atmel,
+FreeScale and others), please consider sending me something like the above
+for inclusion into the HIDAPI source.  This will help others who have the
+same hardware as you do.
+
+License
+========
+HIDAPI may be used by one of three licenses as outlined in LICENSE.txt.
+
+Download
+=========
+HIDAPI can be downloaded from github
+	git clone git://github.com/signal11/hidapi.git
+
+Build Instructions
+===================
+
+This section is long. Don't be put off by this. It's not long because it's
+complicated to build HIDAPI; it's quite the opposite.  This section is long
+because of the flexibility of HIDAPI and the large number of ways in which
+it can be built and used.  You will likely pick a single build method.
+
+HIDAPI can be built in several different ways. If you elect to build a
+shared library, you will need to build it from the HIDAPI source
+distribution.  If you choose instead to embed HIDAPI directly into your
+application, you can skip the building and look at the provided platform
+Makefiles for guidance.  These platform Makefiles are located in linux/
+libusb/ mac/ and windows/ and are called Makefile-manual.  In addition,
+Visual Studio projects are provided.  Even if you're going to embed HIDAPI
+into your project, it is still beneficial to build the example programs.
+
+
+Prerequisites:
+---------------
+
+	Linux:
+	-------
+	On Linux, you will need to install development packages for libudev,
+	libusb and optionally Fox-toolkit (for the test GUI). On
+	Debian/Ubuntu systems these can be installed by running:
+	    sudo apt-get install libudev-dev libusb-1.0-0-dev libfox-1.6-dev
+
+	If you downloaded the source directly from the git repository (using
+	git clone), you'll need Autotools:
+	    sudo apt-get install autotools-dev autoconf automake libtool
+
+	FreeBSD:
+	---------
+	On FreeBSD you will need to install GNU make, libiconv, and
+	optionally Fox-Toolkit (for the test GUI). This is done by running
+	the following:
+	    pkg_add -r gmake libiconv fox16
+
+	If you downloaded the source directly from the git repository (using
+	git clone), you'll need Autotools:
+	    pkg_add -r autotools
+
+	Mac:
+	-----
+	On Mac, you will need to install Fox-Toolkit if you wish to build
+	the Test GUI. There are two ways to do this, and each has a slight
+	complication. Which method you use depends on your use case.
+
+	If you wish to build the Test GUI just for your own testing on your
+	own computer, then the easiest method is to install Fox-Toolkit
+	using ports:
+		sudo port install fox
+
+	If you wish to build the TestGUI app bundle to redistribute to
+	others, you will need to install Fox-toolkit from source.  This is
+	because the version of fox that gets installed using ports uses the
+	ports X11 libraries which are not compatible with the Apple X11
+	libraries.  If you install Fox with ports and then try to distribute
+	your built app bundle, it will simply fail to run on other systems.
+	To install Fox-Toolkit manually, download the source package from
+	http://www.fox-toolkit.org, extract it, and run the following from
+	within the extracted source:
+		./configure && make && make install
+
+	Windows:
+	---------
+	On Windows, if you want to build the test GUI, you will need to get
+	the hidapi-externals.zip package from the download site.  This
+	contains pre-built binaries for Fox-toolkit.  Extract
+	hidapi-externals.zip just outside of hidapi, so that
+	hidapi-externals and hidapi are on the same level, as shown:
+
+	     Parent_Folder
+	       |
+	       +hidapi
+	       +hidapi-externals
+
+	Again, this step is not required if you do not wish to build the
+	test GUI.
+
+
+Building HIDAPI into a shared library on Unix Platforms:
+---------------------------------------------------------
+
+On Unix-like systems such as Linux, FreeBSD, Mac, and even Windows, using
+Mingw or Cygwin, the easiest way to build a standard system-installed shared
+library is to use the GNU Autotools build system.  If you checked out the
+source from the git repository, run the following:
+
+	./bootstrap
+	./configure
+	make
+	make install     <----- as root, or using sudo
+
+If you downloaded a source package (ie: if you did not run git clone), you
+can skip the ./bootstrap step.
+
+./configure can take several arguments which control the build. The two most
+likely to be used are:
+	--enable-testgui
+		Enable build of the Test GUI. This requires Fox toolkit to
+		be installed.  Instructions for installing Fox-Toolkit on
+		each platform are in the Prerequisites section above.
+
+	--prefix=/usr
+		Specify where you want the output headers and libraries to
+		be installed. The example above will put the headers in
+		/usr/include and the binaries in /usr/lib. The default is to
+		install into /usr/local which is fine on most systems.
+
+Building the manual way on Unix platforms:
+-------------------------------------------
+
+Manual Makefiles are provided mostly to give the user and idea what it takes
+to build a program which embeds HIDAPI directly inside of it. These should
+really be used as examples only. If you want to build a system-wide shared
+library, use the Autotools method described above.
+
+	To build HIDAPI using the manual makefiles, change to the directory
+	of your platform and run make. For example, on Linux run:
+		cd linux/
+		make -f Makefile-manual
+
+	To build the Test GUI using the manual makefiles:
+		cd testgui/
+		make -f Makefile-manual
+
+Building on Windows:
+---------------------
+
+To build the HIDAPI DLL on Windows using Visual Studio, build the .sln file
+in the windows/ directory.
+
+To build the Test GUI on windows using Visual Studio, build the .sln file in
+the testgui/ directory.
+
+To build HIDAPI using MinGW or Cygwin using Autotools, use the instructions
+in the section titled "Building HIDAPI into a shared library on Unix
+Platforms" above.  Note that building the Test GUI with MinGW or Cygwin will
+require the Windows procedure in the Prerequisites section above (ie:
+hidapi-externals.zip).
+
+To build HIDAPI using MinGW using the Manual Makefiles, see the section
+"Building the manual way on Unix platforms" above.
+
+HIDAPI can also be built using the Windows DDK (now also called the Windows
+Driver Kit or WDK). This method was originally required for the HIDAPI build
+but not anymore. However, some users still prefer this method. It is not as
+well supported anymore but should still work. Patches are welcome if it does
+not. To build using the DDK:
+
+   1. Install the Windows Driver Kit (WDK) from Microsoft.
+   2. From the Start menu, in the Windows Driver Kits folder, select Build
+      Environments, then your operating system, then the x86 Free Build
+      Environment (or one that is appropriate for your system).
+   3. From the console, change directory to the windows/ddk_build/ directory,
+      which is part of the HIDAPI distribution.
+   4. Type build.
+   5. You can find the output files (DLL and LIB) in a subdirectory created
+      by the build system which is appropriate for your environment. On
+      Windows XP, this directory is objfre_wxp_x86/i386.
+
+Cross Compiling
+================
+
+This section talks about cross compiling HIDAPI for Linux using autotools.
+This is useful for using HIDAPI on embedded Linux targets.  These
+instructions assume the most raw kind of embedded Linux build, where all
+prerequisites will need to be built first.  This process will of course vary
+based on your embedded Linux build system if you are using one, such as
+OpenEmbedded or Buildroot.
+
+For the purpose of this section, it will be assumed that the following
+environment variables are exported.
+
+	$ export STAGING=$HOME/out
+	$ export HOST=arm-linux
+
+STAGING and HOST can be modified to suit your setup.
+
+Prerequisites
+--------------
+
+Note that the build of libudev is the very basic configuration.
+
+Build Libusb. From the libusb source directory, run:
+	./configure --host=$HOST --prefix=$STAGING
+	make
+	make install
+
+Build libudev. From the libudev source directory, run:
+	./configure --disable-gudev --disable-introspection --disable-hwdb \
+		 --host=$HOST --prefix=$STAGING
+	make
+	make install
+
+Building HIDAPI
+----------------
+
+Build HIDAPI:
+
+	PKG_CONFIG_DIR= \
+	PKG_CONFIG_LIBDIR=$STAGING/lib/pkgconfig:$STAGING/share/pkgconfig \
+	PKG_CONFIG_SYSROOT_DIR=$STAGING \
+	./configure --host=$HOST --prefix=$STAGING
+
+
+Signal 11 Software - 2010-04-11
+                     2010-07-28
+                     2011-09-10
+                     2012-05-01
+                     2012-07-03
diff --git a/uf2-samdx1/lib/uf2/hidapi/android/jni/Android.mk b/uf2-samdx1/lib/uf2/hidapi/android/jni/Android.mk
new file mode 100644
index 00000000..527b43fd
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/android/jni/Android.mk
@@ -0,0 +1,19 @@
+LOCAL_PATH:= $(call my-dir)
+
+HIDAPI_ROOT_REL:= ../..
+HIDAPI_ROOT_ABS:= $(LOCAL_PATH)/../..
+
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := \
+  $(HIDAPI_ROOT_REL)/libusb/hid.c
+
+LOCAL_C_INCLUDES += \
+  $(HIDAPI_ROOT_ABS)/hidapi \
+  $(HIDAPI_ROOT_ABS)/android
+
+LOCAL_SHARED_LIBRARIES := libusb1.0
+
+LOCAL_MODULE := libhidapi
+
+include $(BUILD_SHARED_LIBRARY)
diff --git a/uf2-samdx1/lib/uf2/hidapi/bootstrap b/uf2-samdx1/lib/uf2/hidapi/bootstrap
new file mode 100644
index 00000000..81e9b74b
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/bootstrap
@@ -0,0 +1,2 @@
+#!/bin/sh -x
+autoreconf --install --verbose --force
diff --git a/uf2-samdx1/lib/uf2/hidapi/configure.ac b/uf2-samdx1/lib/uf2/hidapi/configure.ac
new file mode 100644
index 00000000..c6747f90
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/configure.ac
@@ -0,0 +1,236 @@
+AC_PREREQ(2.63)
+
+# Version number. This is currently the only place.
+m4_define([HIDAPI_MAJOR],   0)
+m4_define([HIDAPI_MINOR],   8)
+m4_define([HIDAPI_RELEASE], 0)
+m4_define([HIDAPI_RC],      -rc1)
+m4_define([VERSION_STRING], HIDAPI_MAJOR[.]HIDAPI_MINOR[.]HIDAPI_RELEASE[]HIDAPI_RC)
+
+AC_INIT([hidapi],[VERSION_STRING],[alan@signal11.us])
+
+# Library soname version
+# Follow the following rules (particularly the ones in the second link):
+#  http://www.gnu.org/software/libtool/manual/html_node/Updating-version-info.html
+#  http://sourceware.org/autobook/autobook/autobook_91.html
+lt_current="0"
+lt_revision="0"
+lt_age="0"
+LTLDFLAGS="-version-info ${lt_current}:${lt_revision}:${lt_age}"
+
+AC_CONFIG_MACRO_DIR([m4])
+AM_INIT_AUTOMAKE([foreign -Wall -Werror])
+AC_CONFIG_MACRO_DIR([m4])
+
+m4_ifdef([AM_PROG_AR], [AM_PROG_AR])
+LT_INIT
+
+AC_PROG_CC
+AC_PROG_CXX
+AC_PROG_OBJC
+PKG_PROG_PKG_CONFIG
+
+
+m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
+
+hidapi_lib_error() {
+	echo ""
+	echo "  Library $1 was not found on this system."
+	echo "  Please install it and re-run ./configure"
+	echo ""
+	exit 1
+}
+
+hidapi_prog_error() {
+	echo ""
+	echo "  Program $1 was not found on this system."
+	echo "  This program is part of $2."
+	echo "  Please install it and re-run ./configure"
+	echo ""
+	exit 1
+}
+
+AC_MSG_CHECKING([operating system])
+AC_MSG_RESULT($host)
+case $host in
+*-linux*)
+	AC_MSG_RESULT([ (Linux back-end)])
+	AC_DEFINE(OS_LINUX, 1, [Linux implementations])
+	AC_SUBST(OS_LINUX)
+	backend="linux"
+	os="linux"
+	threads="pthreads"
+
+	# HIDAPI/hidraw libs
+	PKG_CHECK_MODULES([libudev], [libudev], true, [hidapi_lib_error libudev])
+	LIBS_HIDRAW_PR+=" $libudev_LIBS"
+	CFLAGS_HIDRAW+=" $libudev_CFLAGS"
+
+	# HIDAPI/libusb libs
+	AC_CHECK_LIB([rt], [clock_gettime], [LIBS_LIBUSB_PRIVATE+=" -lrt"], [hidapi_lib_error librt])
+	PKG_CHECK_MODULES([libusb], [libusb-1.0 >= 1.0.9], true, [hidapi_lib_error libusb-1.0])
+	LIBS_LIBUSB_PRIVATE+=" $libusb_LIBS"
+	CFLAGS_LIBUSB+=" $libusb_CFLAGS"
+	;;
+*-darwin*)
+	AC_MSG_RESULT([ (Mac OS X back-end)])
+	AC_DEFINE(OS_DARWIN, 1, [Mac implementation])
+	AC_SUBST(OS_DARWIN)
+	backend="mac"
+	os="darwin"
+	threads="pthreads"
+	LIBS="${LIBS} -framework IOKit -framework CoreFoundation"
+	;;
+*-freebsd*)
+	AC_MSG_RESULT([ (FreeBSD back-end)])
+	AC_DEFINE(OS_FREEBSD, 1, [FreeBSD implementation])
+	AC_SUBST(OS_FREEBSD)
+	backend="libusb"
+	os="freebsd"
+	threads="pthreads"
+
+	CFLAGS="$CFLAGS -I/usr/local/include"
+	LDFLAGS="$LDFLAGS -L/usr/local/lib"
+	LIBS="${LIBS}"
+	AC_CHECK_LIB([usb], [libusb_init], [LIBS_LIBUSB_PRIVATE="${LIBS_LIBUSB_PRIVATE} -lusb"], [hidapi_lib_error libusb])
+	AC_CHECK_LIB([iconv], [iconv_open], [LIBS_LIBUSB_PRIVATE="${LIBS_LIBUSB_PRIVATE} -liconv"], [hidapi_lib_error libiconv])
+	echo libs_priv: $LIBS_LIBUSB_PRIVATE
+	;;
+*-kfreebsd*)
+	AC_MSG_RESULT([ (kFreeBSD back-end)])
+	AC_DEFINE(OS_KFREEBSD, 1, [kFreeBSD implementation])
+	AC_SUBST(OS_KFREEBSD)
+	backend="libusb"
+	os="kfreebsd"
+	threads="pthreads"
+
+	AC_CHECK_LIB([usb], [libusb_init], [LIBS_LIBUSB_PRIVATE="${LIBS_LIBUSB_PRIVATE} -lusb"], [hidapi_lib_error libusb])
+	echo libs_priv: $LIBS_LIBUSB_PRIVATE
+	;;
+*-mingw*)
+	AC_MSG_RESULT([ (Windows back-end, using MinGW)])
+	backend="windows"
+	os="windows"
+	threads="windows"
+	win_implementation="mingw"
+	;;
+*-cygwin*)
+	AC_MSG_RESULT([ (Windows back-end, using Cygwin)])
+	backend="windows"
+	os="windows"
+	threads="windows"
+	win_implementation="cygwin"
+	;;
+*)
+	AC_MSG_ERROR([HIDAPI is not supported on your operating system yet])
+esac
+
+LIBS_HIDRAW="${LIBS} ${LIBS_HIDRAW_PR}"
+LIBS_LIBUSB="${LIBS} ${LIBS_LIBUSB_PRIVATE}"
+AC_SUBST([LIBS_HIDRAW])
+AC_SUBST([LIBS_LIBUSB])
+AC_SUBST([CFLAGS_LIBUSB])
+AC_SUBST([CFLAGS_HIDRAW])
+
+if test "x$os" = xwindows; then
+	AC_DEFINE(OS_WINDOWS, 1, [Windows implementations])
+	AC_SUBST(OS_WINDOWS)
+	LDFLAGS="${LDFLAGS} -no-undefined"
+	LIBS="${LIBS} -lsetupapi"
+fi
+
+if test "x$threads" = xpthreads; then
+	AX_PTHREAD([found_pthreads=yes], [found_pthreads=no])
+
+	if test "x$found_pthreads" = xyes; then
+		if test "x$os" = xlinux; then
+			# Only use pthreads for libusb implementation on Linux.
+			LIBS_LIBUSB="$PTHREAD_LIBS $LIBS_LIBUSB"
+			CFLAGS_LIBUSB="$CFLAGS_LIBUSB $PTHREAD_CFLAGS"
+			# There's no separate CC on Linux for threading,
+			# so it's ok that both implementations use $PTHREAD_CC
+			CC="$PTHREAD_CC"
+		else
+			LIBS="$PTHREAD_LIBS $LIBS"
+			CFLAGS="$CFLAGS $PTHREAD_CFLAGS"
+			CC="$PTHREAD_CC"
+		fi
+	fi
+fi
+
+# Test GUI
+AC_ARG_ENABLE([testgui],
+	[AS_HELP_STRING([--enable-testgui],
+		[enable building of test GUI (default n)])],
+	[testgui_enabled=$enableval],
+	[testgui_enabled='no'])
+AM_CONDITIONAL([BUILD_TESTGUI], [test "x$testgui_enabled" != "xno"])
+
+# Configure the MacOS TestGUI app bundle
+rm -Rf testgui/TestGUI.app
+mkdir -p testgui/TestGUI.app
+cp -R ${srcdir}/testgui/TestGUI.app.in/* testgui/TestGUI.app
+chmod -R u+w testgui/TestGUI.app
+mkdir testgui/TestGUI.app/Contents/MacOS/
+
+if test "x$testgui_enabled" != "xno"; then
+	if test "x$os" = xdarwin; then
+		# On Mac OS, don't use pkg-config.
+		AC_CHECK_PROG([foxconfig], [fox-config], [fox-config], false)
+		if test "x$foxconfig" = "xfalse"; then
+			hidapi_prog_error fox-config "FOX Toolkit"
+		fi
+		LIBS_TESTGUI+=`$foxconfig --libs`
+		LIBS_TESTGUI+=" -framework Cocoa -L/usr/X11R6/lib"
+		CFLAGS_TESTGUI+=`$foxconfig --cflags`
+		OBJCFLAGS+=" -x objective-c++"
+	elif test "x$os" = xwindows; then
+		# On Windows, just set the paths for Fox toolkit
+		if test "x$win_implementation" = xmingw; then
+			CFLAGS_TESTGUI="-I\$(srcdir)/../../hidapi-externals/fox/include -g -c"
+			LIBS_TESTGUI=" -mwindows \$(srcdir)/../../hidapi-externals/fox/lib/libFOX-1.6.a -lgdi32 -Wl,--enable-auto-import -static-libgcc -static-libstdc++ -lkernel32"
+		else
+			# Cygwin
+			CFLAGS_TESTGUI="-DWIN32 -I\$(srcdir)/../../hidapi-externals/fox/include -g -c"
+			LIBS_TESTGUI="\$(srcdir)/../../hidapi-externals/fox/lib/libFOX-cygwin-1.6.a -lgdi32 -Wl,--enable-auto-import -static-libgcc -static-libstdc++ -lkernel32"
+		fi
+	else
+		# On Linux and FreeBSD platforms, use pkg-config to find fox.
+		PKG_CHECK_MODULES([fox], [fox17], [], [PKG_CHECK_MODULES([fox], [fox])])
+		LIBS_TESTGUI="${LIBS_TESTGUI} $fox_LIBS"
+		if test "x$os" = xfreebsd; then
+			LIBS_TESTGUI="${LIBS_TESTGUI} -L/usr/local/lib"
+		fi
+		CFLAGS_TESTGUI="${CFLAGS_TESTGUI} $fox_CFLAGS"
+	fi
+fi
+AC_SUBST([LIBS_TESTGUI])
+AC_SUBST([CFLAGS_TESTGUI])
+AC_SUBST([backend])
+
+# OS info for Automake
+AM_CONDITIONAL(OS_LINUX, test "x$os" = xlinux)
+AM_CONDITIONAL(OS_DARWIN, test "x$os" = xdarwin)
+AM_CONDITIONAL(OS_FREEBSD, test "x$os" = xfreebsd)
+AM_CONDITIONAL(OS_KFREEBSD, test "x$os" = xkfreebsd)
+AM_CONDITIONAL(OS_WINDOWS, test "x$os" = xwindows)
+
+AC_CONFIG_HEADERS([config.h])
+
+if test "x$os" = "xlinux"; then
+	AC_CONFIG_FILES([pc/hidapi-hidraw.pc])
+	AC_CONFIG_FILES([pc/hidapi-libusb.pc])
+else
+	AC_CONFIG_FILES([pc/hidapi.pc])
+fi
+
+AC_SUBST(LTLDFLAGS)
+
+AC_CONFIG_FILES([Makefile \
+	hidtest/Makefile \
+	libusb/Makefile \
+	linux/Makefile \
+	mac/Makefile \
+	testgui/Makefile \
+	windows/Makefile])
+AC_OUTPUT
diff --git a/uf2-samdx1/lib/uf2/hidapi/doxygen/Doxyfile b/uf2-samdx1/lib/uf2/hidapi/doxygen/Doxyfile
new file mode 100644
index 00000000..9d983e9f
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/doxygen/Doxyfile
@@ -0,0 +1,1630 @@
+# Doxyfile 1.7.1
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project
+#
+# All text after a hash (#) is considered a comment and will be ignored
+# The format is:
+#       TAG = value [value, ...]
+# For lists items can also be appended using:
+#       TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ")
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# http://www.gnu.org/software/libiconv for the list of possible encodings.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
+# by quotes) that should identify the project.
+
+PROJECT_NAME           = hidapi
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number.
+# This could be handy for archiving the generated documentation or
+# if some version control system is used.
+
+PROJECT_NUMBER         =
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
+# base path where the generated documentation will be put.
+# If a relative path is entered, it will be relative to the location
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY       =
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
+# 4096 sub-directories (in 2 levels) under the output directory of each output
+# format and will distribute the generated files over these directories.
+# Enabling this option can be useful when feeding doxygen a huge amount of
+# source files, where putting all generated files in the same directory would
+# otherwise cause performance problems for the file system.
+
+CREATE_SUBDIRS         = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# The default language is English, other supported languages are:
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+
+OUTPUT_LANGUAGE        = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
+# include brief member descriptions after the members that are listed in
+# the file and class documentation (similar to JavaDoc).
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC      = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
+# the brief description of a member or function before the detailed description.
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF           = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator
+# that is used to form the text in various listings. Each string
+# in this list, if found as the leading text of the brief description, will be
+# stripped from the text and the result after processing the whole list, is
+# used as the annotated text. Otherwise, the brief description is used as-is.
+# If left blank, the following values are used ("$name" is automatically
+# replaced with the name of the entity): "The $name class" "The $name widget"
+# "The $name file" "is" "provides" "specifies" "contains"
+# "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF       =
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# Doxygen will generate a detailed section even if there is only a brief
+# description.
+
+ALWAYS_DETAILED_SEC    = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+
+INLINE_INHERITED_MEMB  = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
+# path before files name in the file list and in the header files. If set
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES        = YES
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
+# can be used to strip a user-defined part of the path. Stripping is
+# only done if one of the specified strings matches the left-hand part of
+# the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the
+# path to strip.
+
+STRIP_FROM_PATH        =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
+# the path mentioned in the documentation of a class, which tells
+# the reader which header file to include in order to use a class.
+# If left blank only the name of the header file containing the class
+# definition is used. Otherwise one should specify the include paths that
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH    =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
+# (but less readable) file names. This can be useful is your file systems
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES            = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
+# will interpret the first line (until the first dot) of a JavaDoc-style
+# comment as the brief description. If set to NO, the JavaDoc
+# comments will behave just like regular Qt-style comments
+# (thus requiring an explicit @brief command for a brief description.)
+
+JAVADOC_AUTOBRIEF      = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
+# interpret the first line (until the first dot) of a Qt-style
+# comment as the brief description. If set to NO, the comments
+# will behave just like regular Qt-style comments (thus requiring
+# an explicit \brief command for a brief description.)
+
+QT_AUTOBRIEF           = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
+# treat a multi-line C++ special comment block (i.e. a block of //! or ///
+# comments) as a brief description. This used to be the default behaviour.
+# The new default is to treat a multi-line C++ comment block as a detailed
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
+# member inherits the documentation from any documented member that it
+# re-implements.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
+# a new page for each member. If set to NO, the documentation of a member will
+# be part of the file/class/namespace that contains it.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab.
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE               = 8
+
+# This tag can be used to specify a number of aliases that acts
+# as commands in the documentation. An alias has the form "name=value".
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to
+# put the command \sideeffect (or @sideeffect) in the documentation, which
+# will result in a user-defined paragraph with heading "Side Effects:".
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES                =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
+# sources only. Doxygen will then generate output that is more tailored for C.
+# For instance, some of the names that are used will be different. The list
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C  = YES
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
+# sources only. Doxygen will then generate output that is more tailored for
+# Java. For instance, namespaces will be presented as packages, qualified
+# scopes will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources only. Doxygen will then generate output that is more tailored for
+# Fortran.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for
+# VHDL.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given extension.
+# Doxygen has a built-in mapping, but you can override or extend it using this
+# tag. The format is ext=language, where ext is a file extension, and language
+# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C,
+# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make
+# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C
+# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions
+# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.
+
+EXTENSION_MAPPING      =
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should
+# set this tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
+# func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
+# Doxygen will parse them like normal C++ but will assume all classes use public
+# instead of private inheritance when no explicit protection keyword is present.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate getter
+# and setter methods for a property. Setting this option to YES (the default)
+# will make doxygen to replace the get and set methods by a property in the
+# documentation. This will only work if the methods are indeed getting or
+# setting a simple type. If this is not the case, or you want to show the
+# methods anyway, you should set this option to NO.
+
+IDL_PROPERTY_SUPPORT   = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES, then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
+# the same type (for instance a group of public functions) to be put as a
+# subgroup of that type (e.g. under the Public Functions section). Set it to
+# NO to prevent subgrouping. Alternatively, this can be done per class using
+# the \nosubgrouping command.
+
+SUBGROUPING            = YES
+
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
+# is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically
+# be useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+
+TYPEDEF_HIDES_STRUCT   = NO
+
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
+# determine which symbols to keep in memory and which to flush to disk.
+# When the cache is full, less often used symbols will be written to disk.
+# For small to medium size projects (<1000 input files) the default value is
+# probably good enough. For larger projects a too small cache size can cause
+# doxygen to be busy swapping symbols to and from disk most of the time
+# causing a significant performance penality.
+# If the system has enough physical memory increasing the cache will improve the
+# performance by keeping more symbols in memory. Note that the value works on
+# a logarithmic scale so increasing the size by one will rougly double the
+# memory usage. The cache size is given by this formula:
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
+# corresponding to a cache size of 2^16 = 65536 symbols
+
+SYMBOL_CACHE_SIZE      = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
+# documentation are documented, even if no documentation was available.
+# Private class members and static file members will be hidden unless
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+
+EXTRACT_ALL            = NO
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
+# will be included in the documentation.
+
+EXTRACT_PRIVATE        = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file
+# will be included in the documentation.
+
+EXTRACT_STATIC         = NO
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
+# defined locally in source files will be included in the documentation.
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES  = YES
+
+# This flag is only useful for Objective-C code. When set to YES local
+# methods, which are defined in the implementation section but not in
+# the interface are included in the documentation.
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS  = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base
+# name of the file that contains the anonymous namespace. By default
+# anonymous namespace are hidden.
+
+EXTRACT_ANON_NSPACES   = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
+# undocumented members of documented classes, files or namespaces.
+# If set to NO (the default) these members will be included in the
+# various overviews, but no documentation section is generated.
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy.
+# If set to NO (the default) these classes will be included in the various
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
+# friend (class|struct|union) declarations.
+# If set to NO (the default) these declarations will be included in the
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS  = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
+# documentation blocks found inside the body of a function.
+# If set to NO (the default) these blocks will be appended to the
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation
+# that is typed after a \internal command is included. If the tag is set
+# to NO (the default) then the documentation will be excluded.
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS          = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
+# file names in lower-case letters. If set to YES upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+
+CASE_SENSE_NAMES       = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
+# will show members with their full class and namespace scopes in the
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES       = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
+# will put a list of the files that are included by a file in the documentation
+# of that file.
+
+SHOW_INCLUDE_FILES     = YES
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
+# will list include files with double quotes in the documentation
+# rather than with sharp brackets.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
+# is inserted in the documentation for inline members.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
+# will sort the (detailed) documentation of file and class members
+# alphabetically by member name. If set to NO the members will appear in
+# declaration order.
+
+SORT_MEMBER_DOCS       = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
+# brief documentation of file, namespace and class members alphabetically
+# by member name. If set to NO (the default) the members will appear in
+# declaration order.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen
+# will sort the (brief and detailed) documentation of class members so that
+# constructors and destructors are listed first. If set to NO (the default)
+# the constructors will appear in the respective orders defined by
+# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.
+# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO
+# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
+# hierarchy of group names into alphabetical order. If set to NO (the default)
+# the group names will appear in their defined order.
+
+SORT_GROUP_NAMES       = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
+# sorted by fully-qualified names, including namespaces. If set to
+# NO (the default), the class list will be sorted only by class name,
+# not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or
+# disable (NO) the todo list. This list is created by putting \todo
+# commands in the documentation.
+
+GENERATE_TODOLIST      = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or
+# disable (NO) the test list. This list is created by putting \test
+# commands in the documentation.
+
+GENERATE_TESTLIST      = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or
+# disable (NO) the bug list. This list is created by putting \bug
+# commands in the documentation.
+
+GENERATE_BUGLIST       = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
+# disable (NO) the deprecated list. This list is created by putting
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional
+# documentation sections, marked by \if sectionname ... \endif.
+
+ENABLED_SECTIONS       =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
+# the initial value of a variable or define consists of for it to appear in
+# the documentation. If the initializer consists of more lines than specified
+# here it will be hidden. Use a value of 0 to hide initializers completely.
+# The appearance of the initializer of individual variables and defines in the
+# documentation can be controlled using \showinitializer or \hideinitializer
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES  = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
+# at the bottom of the documentation of classes and structs. If set to YES the
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES        = YES
+
+# If the sources in your project are distributed over multiple directories
+# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
+# in the documentation. The default is NO.
+
+SHOW_DIRECTORIES       = NO
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
+# This will remove the Files entry from the Quick Index and from the
+# Folder Tree View (if specified). The default is YES.
+
+SHOW_FILES             = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
+# Namespaces page.
+# This will remove the Namespaces entry from the Quick Index
+# and from the Folder Tree View (if specified). The default is YES.
+
+SHOW_NAMESPACES        = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command <command> <input-file>, where <command> is the value of
+# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file
+# provided by doxygen. Whatever the program writes to standard output
+# is used as the file version. See the manual for examples.
+
+FILE_VERSION_FILTER    =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. The create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option.
+# You can optionally specify a file name after the option, if omitted
+# DoxygenLayout.xml will be used as the name of the layout file.
+
+LAYOUT_FILE            =
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated by doxygen. Possible values are YES and NO. If left blank
+# NO is used.
+
+WARNINGS               = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED   = YES
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some
+# parameters in a documented function, or documenting parameters that
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR      = YES
+
+# This WARN_NO_PARAMDOC option can be abled to get warnings for
+# functions that are documented, but have no documentation for their parameters
+# or return value. If set to NO (the default) doxygen will only warn about
+# wrong or incomplete parameter documentation, but not about the absence of
+# documentation.
+
+WARN_NO_PARAMDOC       = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that
+# doxygen can produce. The string should contain the $file, $line, and $text
+# tags, which will be replaced by the file and line number from which the
+# warning originated and the warning text. Optionally the format may contain
+# $version, which will be replaced by the version of the file (if it could
+# be obtained via FILE_VERSION_FILTER)
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning
+# and error messages should be written. If left blank the output is written
+# to stderr.
+
+WARN_LOGFILE           =
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain
+# documented source files. You may enter file names like "myfile.cpp" or
+# directories like "/usr/src/myproject". Separate the files or directories
+# with spaces.
+
+INPUT                  = ../hidapi
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
+# also the default input encoding. Doxygen uses libiconv (or the iconv built
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
+# the list of possible encodings.
+
+INPUT_ENCODING         = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank the following patterns are tested:
+# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx
+# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90
+
+FILE_PATTERNS          =
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories
+# should be searched for input files as well. Possible values are YES and NO.
+# If left blank NO is used.
+
+RECURSIVE              = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+
+EXCLUDE                =
+
+# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
+# directories that are symbolic links (a Unix filesystem feature) are excluded
+# from the input.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories. Note that the wildcards are matched
+# against the file with absolute path, so to exclude all test directories
+# for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+
+EXCLUDE_SYMBOLS        =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or
+# directories that contain example code fragments that are included (see
+# the \include command).
+
+EXAMPLE_PATH           =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank all files are included.
+
+EXAMPLE_PATTERNS       =
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude
+# commands irrespective of the value of the RECURSIVE tag.
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE      = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or
+# directories that contain image that are included in the documentation (see
+# the \image command).
+
+IMAGE_PATH             =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command <filter> <input-file>, where <filter>
+# is the value of the INPUT_FILTER tag, and <input-file> is the name of an
+# input file. Doxygen will then use the output that the filter program writes
+# to standard output.
+# If FILTER_PATTERNS is specified, this tag will be
+# ignored.
+
+INPUT_FILTER           =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis.
+# Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match.
+# The filters are a list of the form:
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
+# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER
+# is applied to all files.
+
+FILTER_PATTERNS        =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will be used to filter the input files when producing source
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES    = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will
+# be generated. Documented entities will be cross-referenced with these sources.
+# Note: To get rid of all source code in the generated output, make sure also
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER         = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
+# doxygen to hide any special comment blocks from generated source code
+# fragments. Normal C and C++ comments will always remain visible.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES
+# then for each documented function all documented
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES
+# then for each documented function all documented entities
+# called/used by that function will be listed.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
+# link to the source code.
+# Otherwise they will link to the documentation.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code
+# will point to the HTML generated by the htags(1) tool instead of doxygen
+# built-in source browser. The htags tool is part of GNU's global source
+# tagging system (see http://www.gnu.org/software/global/global.html). You
+# will need version 4.8.6 or higher.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
+# will generate a verbatim copy of the header file for each class for
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS       = YES
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
+# of all compounds will be generated. Enable this if the project
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX     = YES
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX    = 5
+
+# In case all classes in a project start with a common prefix, all
+# classes will be put under the same header in the alphabetical index.
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX          =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
+# generate HTML output.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT            = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard header.
+
+HTML_HEADER            =
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard footer.
+
+HTML_FOOTER            =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
+# style sheet that is used by each HTML page. It can be used to
+# fine-tune the look of the HTML output. If the tag is left blank doxygen
+# will generate a default style sheet. Note that doxygen will try to copy
+# the style sheet file to the HTML output directory, so don't put your own
+# stylesheet in the HTML output directory as well, or it will be erased!
+
+HTML_STYLESHEET        =
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
+# Doxygen will adjust the colors in the stylesheet and background images
+# according to this color. Hue is specified as an angle on a colorwheel,
+# see http://en.wikipedia.org/wiki/Hue for more information.
+# For instance the value 0 represents red, 60 is yellow, 120 is green,
+# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
+# The allowed range is 0 to 359.
+
+HTML_COLORSTYLE_HUE    = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
+# the colors in the HTML output. For a value of 0 the output will use
+# grayscales only. A value of 255 will produce the most vivid colors.
+
+HTML_COLORSTYLE_SAT    = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
+# the luminance component of the colors in the HTML output. Values below
+# 100 gradually make the output lighter, whereas values above 100 make
+# the output darker. The value divided by 100 is the actual gamma applied,
+# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
+# and 100 does not change the gamma.
+
+HTML_COLORSTYLE_GAMMA  = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting
+# this to NO can help when comparing the output of multiple runs.
+
+HTML_TIMESTAMP         = YES
+
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
+# files or namespaces will be aligned in HTML using tables. If set to
+# NO a bullet list will be used.
+
+HTML_ALIGN_MEMBERS     = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded. For this to work a browser that supports
+# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
+# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
+
+HTML_DYNAMIC_SECTIONS  = NO
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files
+# will be generated that can be used as input for Apple's Xcode 3
+# integrated development environment, introduced with OSX 10.5 (Leopard).
+# To create a documentation set, doxygen will generate a Makefile in the
+# HTML output directory. Running make will produce the docset in that
+# directory and running "make install" will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
+# it at startup.
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+
+GENERATE_DOCSET        = NO
+
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
+# feed. A documentation feed provides an umbrella under which multiple
+# documentation sets from a single provider (such as a company or product suite)
+# can be grouped.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
+# should uniquely identify the documentation set bundle. This should be a
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
+# will append .docset to the name.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+
+# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
+
+DOCSET_PUBLISHER_NAME  = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files
+# will be generated that can be used as input for tools like the
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP      = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
+# be used to specify the file name of the resulting .chm file. You
+# can add a path in front of the file if the result should not be
+# written to the html output directory.
+
+CHM_FILE               =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
+# be used to specify the location (absolute path including file name) of
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION           =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
+# controls if a separate .chi index file is generated (YES) or that
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI           = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file
+# content.
+
+CHM_INDEX_ENCODING     =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
+# controls whether a binary table of contents is generated (YES) or a
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND             = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
+# that can be used as input for Qt's qhelpgenerator to generate a
+# Qt Compressed Help (.qch) of the generated HTML documentation.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
+# be used to specify the file name of the resulting .qch file.
+# The path specified is relative to the HTML output folder.
+
+QCH_FILE               =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#namespace
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
+# add. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#custom-filters
+
+QHP_CUST_FILTER_NAME   =
+
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see
+# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters">
+# Qt Help Project / Custom Filters</a>.
+
+QHP_CUST_FILTER_ATTRS  =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's
+# filter section matches.
+# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes">
+# Qt Help Project / Filter Attributes</a>.
+
+QHP_SECT_FILTER_ATTRS  =
+
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
+# be used to specify the location of Qt's qhelpgenerator.
+# If non-empty doxygen will try to run qhelpgenerator on the generated
+# .qhp file.
+
+QHG_LOCATION           =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
+#  will be generated, which together with the HTML files, form an Eclipse help
+# plugin. To install this plugin and make it available under the help contents
+# menu in Eclipse, the contents of the directory containing the HTML and XML
+# files needs to be copied into the plugins directory of eclipse. The name of
+# the directory within the plugins directory should be the same as
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
+# the help appears.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have
+# this name.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
+# top of each HTML page. The value NO (the default) enables the index and
+# the value YES disables it.
+
+DISABLE_INDEX          = NO
+
+# This tag can be used to set the number of enum values (range [1..20])
+# that doxygen will group on one line in the generated HTML documentation.
+
+ENUM_VALUES_PER_LINE   = 4
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information.
+# If the tag value is set to YES, a side panel will be generated
+# containing a tree-like index structure (just like the one that
+# is generated for HTML Help). For this to work a browser that supports
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
+# Windows users are probably better off using the HTML help feature.
+
+GENERATE_TREEVIEW      = NO
+
+# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
+# and Class Hierarchy pages using a tree view instead of an ordered list.
+
+USE_INLINE_TREES       = NO
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
+# used to set the initial width (in pixels) of the frame in which the tree
+# is shown.
+
+TREEVIEW_WIDTH         = 250
+
+# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
+# links to external symbols imported via tag files in a separate window.
+
+EXT_LINKS_IN_WINDOW    = NO
+
+# Use this tag to change the font size of Latex formulas included
+# as images in the HTML documentation. The default is 10. Note that
+# when you change the font size after a successful doxygen run you need
+# to manually remove any form_*.png images from the HTML output directory
+# to force them to be regenerated.
+
+FORMULA_FONTSIZE       = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are
+# not supported properly for IE 6.0, but are supported on all modern browsers.
+# Note that when changing this option you need to delete any form_*.png files
+# in the HTML output before the changes have effect.
+
+FORMULA_TRANSPARENT    = YES
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box
+# for the HTML output. The underlying search engine uses javascript
+# and DHTML and should work on any modern browser. Note that when using
+# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
+# (GENERATE_DOCSET) there is already a search function so this one should
+# typically be disabled. For large projects the javascript based search engine
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+
+SEARCHENGINE           = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a PHP enabled web server instead of at the web client
+# using Javascript. Doxygen will generate the search PHP script and index
+# file to put on the web server. The advantage of the server
+# based approach is that it scales better to large projects and allows
+# full text search. The disadvances is that it is more difficult to setup
+# and does not have live searching capabilities.
+
+SERVER_BASED_SEARCH    = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
+# generate Latex output.
+
+GENERATE_LATEX         = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT           = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked. If left blank `latex' will be used as the default command name.
+# Note that when enabling USE_PDFLATEX this option is only used for
+# generating bitmaps for formulas in the HTML output, but not in the
+# Makefile that is written to the output directory.
+
+LATEX_CMD_NAME         = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
+# generate index for LaTeX. If left blank `makeindex' will be used as the
+# default command name.
+
+MAKEINDEX_CMD_NAME     = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
+# LaTeX documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_LATEX          = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used
+# by the printer. Possible values are: a4, a4wide, letter, legal and
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE             = a4wide
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES         =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
+# the generated latex document. The header should contain everything until
+# the first chapter. If it is left blank doxygen will generate a
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER           =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will
+# contain links (just like the HTML output) instead of page references
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS         = YES
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
+# plain latex in the generated Makefile. Set this option to YES to get a
+# higher quality PDF documentation.
+
+USE_PDFLATEX           = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
+# command to the generated LaTeX files. This will instruct LaTeX to keep
+# running if errors occur, instead of asking the user for help.
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE        = NO
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not
+# include the index chapters (such as File Index, Compound Index, etc.)
+# in the output.
+
+LATEX_HIDE_INDICES     = NO
+
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include
+# source code with syntax highlighting in the LaTeX output.
+# Note that which sources are shown also depends on other settings
+# such as SOURCE_BROWSER.
+
+LATEX_SOURCE_CODE      = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
+# The RTF output is optimized for Word 97 and may not look very pretty with
+# other RTF readers or editors.
+
+GENERATE_RTF           = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT             = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
+# RTF documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_RTF            = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
+# will contain hyperlink fields. The RTF file will
+# contain links (just like the HTML output) instead of page references.
+# This makes the output suitable for online browsing using WORD or other
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+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS         = NO
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+# Load stylesheet definitions from file. Syntax is similar to doxygen's
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+
+RTF_STYLESHEET_FILE    =
+
+# Set optional variables used in the generation of an rtf document.
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE    =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
+# generate man pages
+
+GENERATE_MAN           = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT             = man
+
+# The MAN_EXTENSION tag determines the extension that is added to
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION          = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
+# then it will generate one additional man file for each entity
+# documented in the real man page(s). These additional files
+# only source the real man page, but without them the man command
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS              = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will
+# generate an XML file that captures the structure of
+# the code including all documentation.
+
+GENERATE_XML           = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT             = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema,
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+# syntax of the XML files.
+
+XML_SCHEMA             =
+
+# The XML_DTD tag can be used to specify an XML DTD,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_DTD                =
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
+# dump the program listings (including syntax highlighting
+# and cross-referencing information) to the XML output. Note that
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING     = YES
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
+# generate an AutoGen Definitions (see autogen.sf.net) file
+# that captures the structure of the code including all
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+# and incomplete at the moment.
+
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+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will
+# generate a Perl module file that captures the structure of
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+# feature is still experimental and incomplete at the
+# moment.
+
+GENERATE_PERLMOD       = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX          = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
+# nicely formatted so it can be parsed by a human reader.
+# This is useful
+# if you want to understand what is going on.
+# On the other hand, if this
+# tag is set to NO the size of the Perl module output will be much smaller
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY         = YES
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+# The names of the make variables in the generated doxyrules.make file
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
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+
+PERLMOD_MAKEVAR_PREFIX =
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+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
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+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
+# evaluate all C-preprocessor directives found in the sources and include
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+ENABLE_PREPROCESSING   = YES
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+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
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+
+MACRO_EXPANSION        = NO
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+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
+# then the macro expansion is limited to the macros specified with the
+# PREDEFINED and EXPAND_AS_DEFINED tags.
+
+EXPAND_ONLY_PREDEF     = NO
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
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+SEARCH_INCLUDES        = YES
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+# The INCLUDE_PATH tag can be used to specify one or more directories that
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+
+INCLUDE_PATH           =
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+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
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+# The PREDEFINED tag can be used to specify one or more macro names that
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+
+PREDEFINED             =
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
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+
+EXPAND_AS_DEFINED      =
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+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
+# doxygen's preprocessor will remove all function-like macros that are alone
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+# function macros are typically used for boiler-plate code, and will confuse
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+
+SKIP_FUNCTION_MACROS   = YES
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+#---------------------------------------------------------------------------
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+# If a tag file is not located in the directory in which doxygen
+# is run, you must also specify the path to the tagfile here.
+
+TAGFILES               =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create
+# a tag file that is based on the input files it reads.
+
+GENERATE_TAGFILE       =
+
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed
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+# will be listed.
+
+ALLEXTERNALS           = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will
+# be listed.
+
+EXTERNAL_GROUPS        = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of `which perl').
+
+PERL_PATH              = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
+# or super classes. Setting the tag to NO turns the diagrams off. Note that
+# this option is superseded by the HAVE_DOT option below. This is only a
+# fallback. It is recommended to install and use dot, since it yields more
+# powerful graphs.
+
+CLASS_DIAGRAMS         = YES
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see
+# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
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+# default search path.
+
+MSCGEN_PATH            =
+
+# If set to YES, the inheritance and collaboration graphs will hide
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+
+HIDE_UNDOC_RELATIONS   = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz, a graph visualization
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section
+# have no effect if this option is set to NO (the default)
+
+HAVE_DOT               = NO
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
+# allowed to run in parallel. When set to 0 (the default) doxygen will
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+# explicitly to a value larger than 0 to get control over the balance
+# between CPU load and processing speed.
+
+DOT_NUM_THREADS        = 0
+
+# By default doxygen will write a font called FreeSans.ttf to the output
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+# using DOT_FONTNAME. You need need to make sure dot is able to find the font,
+# which can be done by putting it in a standard location or by setting the
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+
+DOT_FONTNAME           = FreeSans.ttf
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+
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+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
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+# indirect inheritance relations. Setting this tag to YES will force the
+# the CLASS_DIAGRAMS tag to NO.
+
+CLASS_GRAPH            = YES
+
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect implementation dependencies (inheritance, containment, and
+# class references variables) of the class with other documented classes.
+
+COLLABORATION_GRAPH    = YES
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+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for groups, showing the direct groups dependencies
+
+GROUP_GRAPHS           = YES
+
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+
+UML_LOOK               = NO
+
+# If set to YES, the inheritance and collaboration graphs will show the
+# relations between templates and their instances.
+
+TEMPLATE_RELATIONS     = NO
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
+# tags are set to YES then doxygen will generate a graph for each documented
+# file showing the direct and indirect include dependencies of the file with
+# other documented files.
+
+INCLUDE_GRAPH          = YES
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
+# documented header file showing the documented files that directly or
+# indirectly include this file.
+
+INCLUDED_BY_GRAPH      = YES
+
+# If the CALL_GRAPH and HAVE_DOT options are set to YES then
+# doxygen will generate a call dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable call graphs
+# for selected functions only using the \callgraph command.
+
+CALL_GRAPH             = NO
+
+# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
+# doxygen will generate a caller dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable caller
+# graphs for selected functions only using the \callergraph command.
+
+CALLER_GRAPH           = NO
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+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
+# will graphical hierarchy of all classes instead of a textual one.
+
+GRAPHICAL_HIERARCHY    = YES
+
+# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
+# then doxygen will show the dependencies a directory has on other directories
+# in a graphical way. The dependency relations are determined by the #include
+# relations between the files in the directories.
+
+DIRECTORY_GRAPH        = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. Possible values are png, jpg, or gif
+# If left blank png will be used.
+
+DOT_IMAGE_FORMAT       = png
+
+# The tag DOT_PATH can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+
+DOT_PATH               =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the
+# \dotfile command).
+
+DOTFILE_DIRS           =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
+# nodes that will be shown in the graph. If the number of nodes in a graph
+# becomes larger than this value, doxygen will truncate the graph, which is
+# visualized by representing a node as a red box. Note that doxygen if the
+# number of direct children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
+# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+
+DOT_GRAPH_MAX_NODES    = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
+# graphs generated by dot. A depth value of 3 means that only nodes reachable
+# from the root by following a path via at most 3 edges will be shown. Nodes
+# that lay further from the root node will be omitted. Note that setting this
+# option to 1 or 2 may greatly reduce the computation time needed for large
+# code bases. Also note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+
+MAX_DOT_GRAPH_DEPTH    = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not
+# seem to support this out of the box. Warning: Depending on the platform used,
+# enabling this option may lead to badly anti-aliased labels on the edges of
+# a graph (i.e. they become hard to read).
+
+DOT_TRANSPARENT        = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10)
+# support this, this feature is disabled by default.
+
+DOT_MULTI_TARGETS      = YES
+
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
+# generate a legend page explaining the meaning of the various boxes and
+# arrows in the dot generated graphs.
+
+GENERATE_LEGEND        = YES
+
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
+# remove the intermediate dot files that are used to generate
+# the various graphs.
+
+DOT_CLEANUP            = YES
diff --git a/uf2-samdx1/lib/uf2/hidapi/hidapi/hidapi.h b/uf2-samdx1/lib/uf2/hidapi/hidapi/hidapi.h
new file mode 100644
index 00000000..e5bc2dc4
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/hidapi/hidapi.h
@@ -0,0 +1,391 @@
+/*******************************************************
+ HIDAPI - Multi-Platform library for
+ communication with HID devices.
+
+ Alan Ott
+ Signal 11 Software
+
+ 8/22/2009
+
+ Copyright 2009, All Rights Reserved.
+
+ At the discretion of the user of this library,
+ this software may be licensed under the terms of the
+ GNU General Public License v3, a BSD-Style license, or the
+ original HIDAPI license as outlined in the LICENSE.txt,
+ LICENSE-gpl3.txt, LICENSE-bsd.txt, and LICENSE-orig.txt
+ files located at the root of the source distribution.
+ These files may also be found in the public source
+ code repository located at:
+        http://github.com/signal11/hidapi .
+********************************************************/
+
+/** @file
+ * @defgroup API hidapi API
+ */
+
+#ifndef HIDAPI_H__
+#define HIDAPI_H__
+
+#include <wchar.h>
+
+#ifdef _WIN32
+      #define HID_API_EXPORT __declspec(dllexport)
+      #define HID_API_CALL
+#else
+      #define HID_API_EXPORT /**< API export macro */
+      #define HID_API_CALL /**< API call macro */
+#endif
+
+#define HID_API_EXPORT_CALL HID_API_EXPORT HID_API_CALL /**< API export and call macro*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+		struct hid_device_;
+		typedef struct hid_device_ hid_device; /**< opaque hidapi structure */
+
+		/** hidapi info structure */
+		struct hid_device_info {
+			/** Platform-specific device path */
+			char *path;
+			/** Device Vendor ID */
+			unsigned short vendor_id;
+			/** Device Product ID */
+			unsigned short product_id;
+			/** Serial Number */
+			wchar_t *serial_number;
+			/** Device Release Number in binary-coded decimal,
+			    also known as Device Version Number */
+			unsigned short release_number;
+			/** Manufacturer String */
+			wchar_t *manufacturer_string;
+			/** Product string */
+			wchar_t *product_string;
+			/** Usage Page for this Device/Interface
+			    (Windows/Mac only). */
+			unsigned short usage_page;
+			/** Usage for this Device/Interface
+			    (Windows/Mac only).*/
+			unsigned short usage;
+			/** The USB interface which this logical device
+			    represents. Valid on both Linux implementations
+			    in all cases, and valid on the Windows implementation
+			    only if the device contains more than one interface. */
+			int interface_number;
+
+			/** Pointer to the next device */
+			struct hid_device_info *next;
+		};
+
+
+		/** @brief Initialize the HIDAPI library.
+
+			This function initializes the HIDAPI library. Calling it is not
+			strictly necessary, as it will be called automatically by
+			hid_enumerate() and any of the hid_open_*() functions if it is
+			needed.  This function should be called at the beginning of
+			execution however, if there is a chance of HIDAPI handles
+			being opened by different threads simultaneously.
+			
+			@ingroup API
+
+			@returns
+				This function returns 0 on success and -1 on error.
+		*/
+		int HID_API_EXPORT HID_API_CALL hid_init(void);
+
+		/** @brief Finalize the HIDAPI library.
+
+			This function frees all of the static data associated with
+			HIDAPI. It should be called at the end of execution to avoid
+			memory leaks.
+
+			@ingroup API
+
+		    @returns
+				This function returns 0 on success and -1 on error.
+		*/
+		int HID_API_EXPORT HID_API_CALL hid_exit(void);
+
+		/** @brief Enumerate the HID Devices.
+
+			This function returns a linked list of all the HID devices
+			attached to the system which match vendor_id and product_id.
+			If @p vendor_id is set to 0 then any vendor matches.
+			If @p product_id is set to 0 then any product matches.
+			If @p vendor_id and @p product_id are both set to 0, then
+			all HID devices will be returned.
+
+			@ingroup API
+			@param vendor_id The Vendor ID (VID) of the types of device
+				to open.
+			@param product_id The Product ID (PID) of the types of
+				device to open.
+
+		    @returns
+		    	This function returns a pointer to a linked list of type
+		    	struct #hid_device, containing information about the HID devices
+		    	attached to the system, or NULL in the case of failure. Free
+		    	this linked list by calling hid_free_enumeration().
+		*/
+		struct hid_device_info HID_API_EXPORT * HID_API_CALL hid_enumerate(unsigned short vendor_id, unsigned short product_id);
+
+		/** @brief Free an enumeration Linked List
+
+		    This function frees a linked list created by hid_enumerate().
+
+			@ingroup API
+		    @param devs Pointer to a list of struct_device returned from
+		    	      hid_enumerate().
+		*/
+		void  HID_API_EXPORT HID_API_CALL hid_free_enumeration(struct hid_device_info *devs);
+
+		/** @brief Open a HID device using a Vendor ID (VID), Product ID
+			(PID) and optionally a serial number.
+
+			If @p serial_number is NULL, the first device with the
+			specified VID and PID is opened.
+
+			@ingroup API
+			@param vendor_id The Vendor ID (VID) of the device to open.
+			@param product_id The Product ID (PID) of the device to open.
+			@param serial_number The Serial Number of the device to open
+				               (Optionally NULL).
+
+			@returns
+				This function returns a pointer to a #hid_device object on
+				success or NULL on failure.
+		*/
+		HID_API_EXPORT hid_device * HID_API_CALL hid_open(unsigned short vendor_id, unsigned short product_id, const wchar_t *serial_number);
+
+		/** @brief Open a HID device by its path name.
+
+			The path name be determined by calling hid_enumerate(), or a
+			platform-specific path name can be used (eg: /dev/hidraw0 on
+			Linux).
+
+			@ingroup API
+		    @param path The path name of the device to open
+
+			@returns
+				This function returns a pointer to a #hid_device object on
+				success or NULL on failure.
+		*/
+		HID_API_EXPORT hid_device * HID_API_CALL hid_open_path(const char *path);
+
+		/** @brief Write an Output report to a HID device.
+
+			The first byte of @p data[] must contain the Report ID. For
+			devices which only support a single report, this must be set
+			to 0x0. The remaining bytes contain the report data. Since
+			the Report ID is mandatory, calls to hid_write() will always
+			contain one more byte than the report contains. For example,
+			if a hid report is 16 bytes long, 17 bytes must be passed to
+			hid_write(), the Report ID (or 0x0, for devices with a
+			single report), followed by the report data (16 bytes). In
+			this example, the length passed in would be 17.
+
+			hid_write() will send the data on the first OUT endpoint, if
+			one exists. If it does not, it will send the data through
+			the Control Endpoint (Endpoint 0).
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param data The data to send, including the report number as
+				the first byte.
+			@param length The length in bytes of the data to send.
+
+			@returns
+				This function returns the actual number of bytes written and
+				-1 on error.
+		*/
+		int  HID_API_EXPORT HID_API_CALL hid_write(hid_device *device, const unsigned char *data, size_t length);
+
+		/** @brief Read an Input report from a HID device with timeout.
+
+			Input reports are returned
+			to the host through the INTERRUPT IN endpoint. The first byte will
+			contain the Report number if the device uses numbered reports.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param data A buffer to put the read data into.
+			@param length The number of bytes to read. For devices with
+				multiple reports, make sure to read an extra byte for
+				the report number.
+			@param milliseconds timeout in milliseconds or -1 for blocking wait.
+
+			@returns
+				This function returns the actual number of bytes read and
+				-1 on error. If no packet was available to be read within
+				the timeout period, this function returns 0.
+		*/
+		int HID_API_EXPORT HID_API_CALL hid_read_timeout(hid_device *dev, unsigned char *data, size_t length, int milliseconds);
+
+		/** @brief Read an Input report from a HID device.
+
+			Input reports are returned
+		    to the host through the INTERRUPT IN endpoint. The first byte will
+			contain the Report number if the device uses numbered reports.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param data A buffer to put the read data into.
+			@param length The number of bytes to read. For devices with
+				multiple reports, make sure to read an extra byte for
+				the report number.
+
+			@returns
+				This function returns the actual number of bytes read and
+				-1 on error. If no packet was available to be read and
+				the handle is in non-blocking mode, this function returns 0.
+		*/
+		int  HID_API_EXPORT HID_API_CALL hid_read(hid_device *device, unsigned char *data, size_t length);
+
+		/** @brief Set the device handle to be non-blocking.
+
+			In non-blocking mode calls to hid_read() will return
+			immediately with a value of 0 if there is no data to be
+			read. In blocking mode, hid_read() will wait (block) until
+			there is data to read before returning.
+
+			Nonblocking can be turned on and off at any time.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param nonblock enable or not the nonblocking reads
+			 - 1 to enable nonblocking
+			 - 0 to disable nonblocking.
+
+			@returns
+				This function returns 0 on success and -1 on error.
+		*/
+		int  HID_API_EXPORT HID_API_CALL hid_set_nonblocking(hid_device *device, int nonblock);
+
+		/** @brief Send a Feature report to the device.
+
+			Feature reports are sent over the Control endpoint as a
+			Set_Report transfer.  The first byte of @p data[] must
+			contain the Report ID. For devices which only support a
+			single report, this must be set to 0x0. The remaining bytes
+			contain the report data. Since the Report ID is mandatory,
+			calls to hid_send_feature_report() will always contain one
+			more byte than the report contains. For example, if a hid
+			report is 16 bytes long, 17 bytes must be passed to
+			hid_send_feature_report(): the Report ID (or 0x0, for
+			devices which do not use numbered reports), followed by the
+			report data (16 bytes). In this example, the length passed
+			in would be 17.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param data The data to send, including the report number as
+				the first byte.
+			@param length The length in bytes of the data to send, including
+				the report number.
+
+			@returns
+				This function returns the actual number of bytes written and
+				-1 on error.
+		*/
+		int HID_API_EXPORT HID_API_CALL hid_send_feature_report(hid_device *device, const unsigned char *data, size_t length);
+
+		/** @brief Get a feature report from a HID device.
+
+			Set the first byte of @p data[] to the Report ID of the
+			report to be read.  Make sure to allow space for this
+			extra byte in @p data[]. Upon return, the first byte will
+			still contain the Report ID, and the report data will
+			start in data[1].
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param data A buffer to put the read data into, including
+				the Report ID. Set the first byte of @p data[] to the
+				Report ID of the report to be read, or set it to zero
+				if your device does not use numbered reports.
+			@param length The number of bytes to read, including an
+				extra byte for the report ID. The buffer can be longer
+				than the actual report.
+
+			@returns
+				This function returns the number of bytes read plus
+				one for the report ID (which is still in the first
+				byte), or -1 on error.
+		*/
+		int HID_API_EXPORT HID_API_CALL hid_get_feature_report(hid_device *device, unsigned char *data, size_t length);
+
+		/** @brief Close a HID device.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+		*/
+		void HID_API_EXPORT HID_API_CALL hid_close(hid_device *device);
+
+		/** @brief Get The Manufacturer String from a HID device.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param string A wide string buffer to put the data into.
+			@param maxlen The length of the buffer in multiples of wchar_t.
+
+			@returns
+				This function returns 0 on success and -1 on error.
+		*/
+		int HID_API_EXPORT_CALL hid_get_manufacturer_string(hid_device *device, wchar_t *string, size_t maxlen);
+
+		/** @brief Get The Product String from a HID device.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param string A wide string buffer to put the data into.
+			@param maxlen The length of the buffer in multiples of wchar_t.
+
+			@returns
+				This function returns 0 on success and -1 on error.
+		*/
+		int HID_API_EXPORT_CALL hid_get_product_string(hid_device *device, wchar_t *string, size_t maxlen);
+
+		/** @brief Get The Serial Number String from a HID device.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param string A wide string buffer to put the data into.
+			@param maxlen The length of the buffer in multiples of wchar_t.
+
+			@returns
+				This function returns 0 on success and -1 on error.
+		*/
+		int HID_API_EXPORT_CALL hid_get_serial_number_string(hid_device *device, wchar_t *string, size_t maxlen);
+
+		/** @brief Get a string from a HID device, based on its string index.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+			@param string_index The index of the string to get.
+			@param string A wide string buffer to put the data into.
+			@param maxlen The length of the buffer in multiples of wchar_t.
+
+			@returns
+				This function returns 0 on success and -1 on error.
+		*/
+		int HID_API_EXPORT_CALL hid_get_indexed_string(hid_device *device, int string_index, wchar_t *string, size_t maxlen);
+
+		/** @brief Get a string describing the last error which occurred.
+
+			@ingroup API
+			@param device A device handle returned from hid_open().
+
+			@returns
+				This function returns a string containing the last error
+				which occurred or NULL if none has occurred.
+		*/
+		HID_API_EXPORT const wchar_t* HID_API_CALL hid_error(hid_device *device);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/uf2-samdx1/lib/uf2/hidapi/hidtest/.gitignore b/uf2-samdx1/lib/uf2/hidapi/hidtest/.gitignore
new file mode 100644
index 00000000..a9ce7a23
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/hidtest/.gitignore
@@ -0,0 +1,17 @@
+Debug
+Release
+*.exp
+*.ilk
+*.lib
+*.suo
+*.vcproj.*
+*.ncb
+*.suo
+*.dll
+*.pdb
+*.o
+.deps/
+.libs/
+hidtest-hidraw
+hidtest-libusb
+hidtest
diff --git a/uf2-samdx1/lib/uf2/hidapi/hidtest/Makefile.am b/uf2-samdx1/lib/uf2/hidapi/hidtest/Makefile.am
new file mode 100644
index 00000000..d2786445
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/hidtest/Makefile.am
@@ -0,0 +1,20 @@
+AM_CPPFLAGS = -I$(top_srcdir)/hidapi/
+
+## Linux
+if OS_LINUX
+noinst_PROGRAMS = hidtest-libusb hidtest-hidraw
+
+hidtest_hidraw_SOURCES = hidtest.cpp
+hidtest_hidraw_LDADD = $(top_builddir)/linux/libhidapi-hidraw.la
+
+hidtest_libusb_SOURCES = hidtest.cpp
+hidtest_libusb_LDADD = $(top_builddir)/libusb/libhidapi-libusb.la
+else
+
+# Other OS's
+noinst_PROGRAMS = hidtest
+
+hidtest_SOURCES = hidtest.cpp
+hidtest_LDADD = $(top_builddir)/$(backend)/libhidapi.la
+
+endif
diff --git a/uf2-samdx1/lib/uf2/hidapi/hidtest/hidtest.cpp b/uf2-samdx1/lib/uf2/hidapi/hidtest/hidtest.cpp
new file mode 100644
index 00000000..94f0a5c2
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/hidtest/hidtest.cpp
@@ -0,0 +1,194 @@
+/*******************************************************
+ Windows HID simplification
+
+ Alan Ott
+ Signal 11 Software
+
+ 8/22/2009
+
+ Copyright 2009
+ 
+ This contents of this file may be used by anyone
+ for any reason without any conditions and may be
+ used as a starting point for your own applications
+ which use HIDAPI.
+********************************************************/
+
+#include <stdio.h>
+#include <wchar.h>
+#include <string.h>
+#include <stdlib.h>
+#include "hidapi.h"
+
+// Headers needed for sleeping.
+#ifdef _WIN32
+	#include <windows.h>
+#else
+	#include <unistd.h>
+#endif
+
+int main(int argc, char* argv[])
+{
+	int res;
+	unsigned char buf[256];
+	#define MAX_STR 255
+	wchar_t wstr[MAX_STR];
+	hid_device *handle;
+	int i;
+
+#ifdef WIN32
+	UNREFERENCED_PARAMETER(argc);
+	UNREFERENCED_PARAMETER(argv);
+#endif
+
+	struct hid_device_info *devs, *cur_dev;
+	
+	if (hid_init())
+		return -1;
+
+	devs = hid_enumerate(0x0, 0x0);
+	cur_dev = devs;	
+	while (cur_dev) {
+		printf("Device Found\n  type: %04hx %04hx\n  path: %s\n  serial_number: %ls", cur_dev->vendor_id, cur_dev->product_id, cur_dev->path, cur_dev->serial_number);
+		printf("\n");
+		printf("  Manufacturer: %ls\n", cur_dev->manufacturer_string);
+		printf("  Product:      %ls\n", cur_dev->product_string);
+		printf("  Release:      %hx\n", cur_dev->release_number);
+		printf("  Interface:    %d\n",  cur_dev->interface_number);
+		printf("\n");
+		cur_dev = cur_dev->next;
+	}
+	hid_free_enumeration(devs);
+
+	// Set up the command buffer.
+	memset(buf,0x00,sizeof(buf));
+	buf[0] = 0x01;
+	buf[1] = 0x81;
+	
+
+	// Open the device using the VID, PID,
+	// and optionally the Serial number.
+	////handle = hid_open(0x4d8, 0x3f, L"12345");
+	handle = hid_open(0x4d8, 0x3f, NULL);
+	if (!handle) {
+		printf("unable to open device\n");
+ 		return 1;
+	}
+
+	// Read the Manufacturer String
+	wstr[0] = 0x0000;
+	res = hid_get_manufacturer_string(handle, wstr, MAX_STR);
+	if (res < 0)
+		printf("Unable to read manufacturer string\n");
+	printf("Manufacturer String: %ls\n", wstr);
+
+	// Read the Product String
+	wstr[0] = 0x0000;
+	res = hid_get_product_string(handle, wstr, MAX_STR);
+	if (res < 0)
+		printf("Unable to read product string\n");
+	printf("Product String: %ls\n", wstr);
+
+	// Read the Serial Number String
+	wstr[0] = 0x0000;
+	res = hid_get_serial_number_string(handle, wstr, MAX_STR);
+	if (res < 0)
+		printf("Unable to read serial number string\n");
+	printf("Serial Number String: (%d) %ls", wstr[0], wstr);
+	printf("\n");
+
+	// Read Indexed String 1
+	wstr[0] = 0x0000;
+	res = hid_get_indexed_string(handle, 1, wstr, MAX_STR);
+	if (res < 0)
+		printf("Unable to read indexed string 1\n");
+	printf("Indexed String 1: %ls\n", wstr);
+
+	// Set the hid_read() function to be non-blocking.
+	hid_set_nonblocking(handle, 1);
+	
+	// Try to read from the device. There shoud be no
+	// data here, but execution should not block.
+	res = hid_read(handle, buf, 17);
+
+	// Send a Feature Report to the device
+	buf[0] = 0x2;
+	buf[1] = 0xa0;
+	buf[2] = 0x0a;
+	buf[3] = 0x00;
+	buf[4] = 0x00;
+	res = hid_send_feature_report(handle, buf, 17);
+	if (res < 0) {
+		printf("Unable to send a feature report.\n");
+	}
+
+	memset(buf,0,sizeof(buf));
+
+	// Read a Feature Report from the device
+	buf[0] = 0x2;
+	res = hid_get_feature_report(handle, buf, sizeof(buf));
+	if (res < 0) {
+		printf("Unable to get a feature report.\n");
+		printf("%ls", hid_error(handle));
+	}
+	else {
+		// Print out the returned buffer.
+		printf("Feature Report\n   ");
+		for (i = 0; i < res; i++)
+			printf("%02hhx ", buf[i]);
+		printf("\n");
+	}
+
+	memset(buf,0,sizeof(buf));
+
+	// Toggle LED (cmd 0x80). The first byte is the report number (0x1).
+	buf[0] = 0x1;
+	buf[1] = 0x80;
+	res = hid_write(handle, buf, 17);
+	if (res < 0) {
+		printf("Unable to write()\n");
+		printf("Error: %ls\n", hid_error(handle));
+	}
+	
+
+	// Request state (cmd 0x81). The first byte is the report number (0x1).
+	buf[0] = 0x1;
+	buf[1] = 0x81;
+	hid_write(handle, buf, 17);
+	if (res < 0)
+		printf("Unable to write() (2)\n");
+
+	// Read requested state. hid_read() has been set to be
+	// non-blocking by the call to hid_set_nonblocking() above.
+	// This loop demonstrates the non-blocking nature of hid_read().
+	res = 0;
+	while (res == 0) {
+		res = hid_read(handle, buf, sizeof(buf));
+		if (res == 0)
+			printf("waiting...\n");
+		if (res < 0)
+			printf("Unable to read()\n");
+		#ifdef WIN32
+		Sleep(500);
+		#else
+		usleep(500*1000);
+		#endif
+	}
+
+	printf("Data read:\n   ");
+	// Print out the returned buffer.
+	for (i = 0; i < res; i++)
+		printf("%02hhx ", buf[i]);
+	printf("\n");
+
+	hid_close(handle);
+
+	/* Free static HIDAPI objects. */
+	hid_exit();
+
+#ifdef WIN32
+	system("pause");
+#endif
+
+	return 0;
+}
diff --git a/uf2-samdx1/lib/uf2/hidapi/libusb/.gitignore b/uf2-samdx1/lib/uf2/hidapi/libusb/.gitignore
new file mode 100644
index 00000000..67460db9
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/libusb/.gitignore
@@ -0,0 +1,8 @@
+*.o
+*.so
+*.la
+*.lo
+*.a
+.libs
+.deps
+hidtest-libusb
diff --git a/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile-manual b/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile-manual
new file mode 100644
index 00000000..c0fe8680
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile-manual
@@ -0,0 +1,18 @@
+
+
+OS=$(shell uname)
+
+ifeq ($(OS), Linux)
+	FILE=Makefile.linux
+endif
+
+ifeq ($(OS), FreeBSD)
+	FILE=Makefile.freebsd
+endif
+
+ifeq ($(FILE), )
+all:
+	$(error Your platform ${OS} is not supported by hidapi/libusb at this time.)
+endif
+
+include $(FILE)
diff --git a/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile.am b/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile.am
new file mode 100644
index 00000000..13c9d355
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile.am
@@ -0,0 +1,27 @@
+AM_CPPFLAGS = -I$(top_srcdir)/hidapi $(CFLAGS_LIBUSB)
+
+if OS_LINUX
+lib_LTLIBRARIES = libhidapi-libusb.la
+libhidapi_libusb_la_SOURCES = hid.c
+libhidapi_libusb_la_LDFLAGS = $(LTLDFLAGS) $(PTHREAD_CFLAGS)
+libhidapi_libusb_la_LIBADD = $(LIBS_LIBUSB)
+endif
+
+if OS_FREEBSD
+lib_LTLIBRARIES = libhidapi.la
+libhidapi_la_SOURCES = hid.c
+libhidapi_la_LDFLAGS = $(LTLDFLAGS)
+libhidapi_la_LIBADD = $(LIBS_LIBUSB)
+endif
+
+if OS_KFREEBSD
+lib_LTLIBRARIES = libhidapi.la
+libhidapi_la_SOURCES = hid.c
+libhidapi_la_LDFLAGS = $(LTLDFLAGS)
+libhidapi_la_LIBADD = $(LIBS_LIBUSB)
+endif
+
+hdrdir = $(includedir)/hidapi
+hdr_HEADERS = $(top_srcdir)/hidapi/hidapi.h
+
+EXTRA_DIST = Makefile-manual
diff --git a/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile.freebsd b/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile.freebsd
new file mode 100644
index 00000000..5e69e77d
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile.freebsd
@@ -0,0 +1,46 @@
+###########################################
+# Simple Makefile for HIDAPI test program
+#
+# Alan Ott
+# Signal 11 Software
+# 2010-06-01
+###########################################
+
+all: hidtest libs
+
+libs: libhidapi.so
+
+CC       ?= cc
+CFLAGS   ?= -Wall -g -fPIC
+
+CXX      ?= c++
+CXXFLAGS ?= -Wall -g
+
+COBJS     = hid.o
+CPPOBJS   = ../hidtest/hidtest.o
+OBJS      = $(COBJS) $(CPPOBJS)
+INCLUDES  = -I../hidapi -I/usr/local/include
+LDFLAGS   = -L/usr/local/lib
+LIBS      = -lusb -liconv -pthread
+
+
+# Console Test Program
+hidtest: $(OBJS)
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $^ -o $@ $(LIBS)
+
+# Shared Libs
+libhidapi.so: $(COBJS)
+	$(CC) $(LDFLAGS) -shared -Wl,-soname,$@.0 $^ -o $@ $(LIBS)
+
+# Objects
+$(COBJS): %.o: %.c
+	$(CC) $(CFLAGS) -c $(INCLUDES) $< -o $@
+
+$(CPPOBJS): %.o: %.cpp
+	$(CXX) $(CXXFLAGS) -c $(INCLUDES) $< -o $@
+
+
+clean:
+	rm -f $(OBJS) hidtest libhidapi.so ../hidtest/hidtest.o
+
+.PHONY: clean libs
diff --git a/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile.linux b/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile.linux
new file mode 100644
index 00000000..337b556e
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/libusb/Makefile.linux
@@ -0,0 +1,49 @@
+###########################################
+# Simple Makefile for HIDAPI test program
+#
+# Alan Ott
+# Signal 11 Software
+# 2010-06-01
+###########################################
+
+all: hidtest-libusb libs
+
+libs: libhidapi-libusb.so
+
+CC       ?= gcc
+CFLAGS   ?= -Wall -g -fpic
+
+CXX      ?= g++
+CXXFLAGS ?= -Wall -g -fpic
+
+LDFLAGS  ?= -Wall -g
+
+COBJS_LIBUSB = hid.o
+COBJS = $(COBJS_LIBUSB)
+CPPOBJS   = ../hidtest/hidtest.o
+OBJS      = $(COBJS) $(CPPOBJS)
+LIBS_USB  = `pkg-config libusb-1.0 --libs` -lrt -lpthread
+LIBS      = $(LIBS_USB)
+INCLUDES ?= -I../hidapi `pkg-config libusb-1.0 --cflags`
+
+
+# Console Test Program
+hidtest-libusb: $(COBJS_LIBUSB) $(CPPOBJS)
+	$(CXX) $(LDFLAGS) $^ $(LIBS_USB) -o $@
+
+# Shared Libs
+libhidapi-libusb.so: $(COBJS_LIBUSB)
+	$(CC) $(LDFLAGS) $(LIBS_USB) -shared -fpic -Wl,-soname,$@.0 $^ -o $@
+
+# Objects
+$(COBJS): %.o: %.c
+	$(CC) $(CFLAGS) -c $(INCLUDES) $< -o $@
+
+$(CPPOBJS): %.o: %.cpp
+	$(CXX) $(CXXFLAGS) -c $(INCLUDES) $< -o $@
+
+
+clean:
+	rm -f $(OBJS) hidtest-libusb libhidapi-libusb.so ../hidtest/hidtest.o
+
+.PHONY: clean libs
diff --git a/uf2-samdx1/lib/uf2/hidapi/libusb/hid.c b/uf2-samdx1/lib/uf2/hidapi/libusb/hid.c
new file mode 100644
index 00000000..3c6d877f
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/libusb/hid.c
@@ -0,0 +1,1514 @@
+/*******************************************************
+ HIDAPI - Multi-Platform library for
+ communication with HID devices.
+
+ Alan Ott
+ Signal 11 Software
+
+ 8/22/2009
+ Linux Version - 6/2/2010
+ Libusb Version - 8/13/2010
+ FreeBSD Version - 11/1/2011
+
+ Copyright 2009, All Rights Reserved.
+
+ At the discretion of the user of this library,
+ this software may be licensed under the terms of the
+ GNU General Public License v3, a BSD-Style license, or the
+ original HIDAPI license as outlined in the LICENSE.txt,
+ LICENSE-gpl3.txt, LICENSE-bsd.txt, and LICENSE-orig.txt
+ files located at the root of the source distribution.
+ These files may also be found in the public source
+ code repository located at:
+        http://github.com/signal11/hidapi .
+********************************************************/
+
+#define _GNU_SOURCE /* needed for wcsdup() before glibc 2.10 */
+
+/* C */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <locale.h>
+#include <errno.h>
+
+/* Unix */
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <sys/utsname.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <wchar.h>
+
+/* GNU / LibUSB */
+#include <libusb.h>
+#ifndef __ANDROID__
+#include <iconv.h>
+#endif
+
+#include "hidapi.h"
+
+#ifdef __ANDROID__
+
+/* Barrier implementation because Android/Bionic don't have pthread_barrier.
+   This implementation came from Brent Priddy and was posted on
+   StackOverflow. It is used with his permission. */
+typedef int pthread_barrierattr_t;
+typedef struct pthread_barrier {
+    pthread_mutex_t mutex;
+    pthread_cond_t cond;
+    int count;
+    int trip_count;
+} pthread_barrier_t;
+
+static int pthread_barrier_init(pthread_barrier_t *barrier, const pthread_barrierattr_t *attr, unsigned int count)
+{
+	if(count == 0) {
+		errno = EINVAL;
+		return -1;
+	}
+
+	if(pthread_mutex_init(&barrier->mutex, 0) < 0) {
+		return -1;
+	}
+	if(pthread_cond_init(&barrier->cond, 0) < 0) {
+		pthread_mutex_destroy(&barrier->mutex);
+		return -1;
+	}
+	barrier->trip_count = count;
+	barrier->count = 0;
+
+	return 0;
+}
+
+static int pthread_barrier_destroy(pthread_barrier_t *barrier)
+{
+	pthread_cond_destroy(&barrier->cond);
+	pthread_mutex_destroy(&barrier->mutex);
+	return 0;
+}
+
+static int pthread_barrier_wait(pthread_barrier_t *barrier)
+{
+	pthread_mutex_lock(&barrier->mutex);
+	++(barrier->count);
+	if(barrier->count >= barrier->trip_count)
+	{
+		barrier->count = 0;
+		pthread_cond_broadcast(&barrier->cond);
+		pthread_mutex_unlock(&barrier->mutex);
+		return 1;
+	}
+	else
+	{
+		pthread_cond_wait(&barrier->cond, &(barrier->mutex));
+		pthread_mutex_unlock(&barrier->mutex);
+		return 0;
+	}
+}
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef DEBUG_PRINTF
+#define LOG(...) fprintf(stderr, __VA_ARGS__)
+#else
+#define LOG(...) do {} while (0)
+#endif
+
+#ifndef __FreeBSD__
+#define DETACH_KERNEL_DRIVER
+#endif
+
+/* Uncomment to enable the retrieval of Usage and Usage Page in
+hid_enumerate(). Warning, on platforms different from FreeBSD
+this is very invasive as it requires the detach
+and re-attach of the kernel driver. See comments inside hid_enumerate().
+libusb HIDAPI programs are encouraged to use the interface number
+instead to differentiate between interfaces on a composite HID device. */
+/*#define INVASIVE_GET_USAGE*/
+
+/* Linked List of input reports received from the device. */
+struct input_report {
+	uint8_t *data;
+	size_t len;
+	struct input_report *next;
+};
+
+
+struct hid_device_ {
+	/* Handle to the actual device. */
+	libusb_device_handle *device_handle;
+
+	/* Endpoint information */
+	int input_endpoint;
+	int output_endpoint;
+	int input_ep_max_packet_size;
+
+	/* The interface number of the HID */
+	int interface;
+
+	/* Indexes of Strings */
+	int manufacturer_index;
+	int product_index;
+	int serial_index;
+
+	/* Whether blocking reads are used */
+	int blocking; /* boolean */
+
+	/* Read thread objects */
+	pthread_t thread;
+	pthread_mutex_t mutex; /* Protects input_reports */
+	pthread_cond_t condition;
+	pthread_barrier_t barrier; /* Ensures correct startup sequence */
+	int shutdown_thread;
+	int cancelled;
+	struct libusb_transfer *transfer;
+
+	/* List of received input reports. */
+	struct input_report *input_reports;
+};
+
+static libusb_context *usb_context = NULL;
+
+uint16_t get_usb_code_for_current_locale(void);
+static int return_data(hid_device *dev, unsigned char *data, size_t length);
+
+static hid_device *new_hid_device(void)
+{
+	hid_device *dev = calloc(1, sizeof(hid_device));
+	dev->blocking = 1;
+
+	pthread_mutex_init(&dev->mutex, NULL);
+	pthread_cond_init(&dev->condition, NULL);
+	pthread_barrier_init(&dev->barrier, NULL, 2);
+
+	return dev;
+}
+
+static void free_hid_device(hid_device *dev)
+{
+	/* Clean up the thread objects */
+	pthread_barrier_destroy(&dev->barrier);
+	pthread_cond_destroy(&dev->condition);
+	pthread_mutex_destroy(&dev->mutex);
+
+	/* Free the device itself */
+	free(dev);
+}
+
+#if 0
+/*TODO: Implement this funciton on hidapi/libusb.. */
+static void register_error(hid_device *device, const char *op)
+{
+
+}
+#endif
+
+#ifdef INVASIVE_GET_USAGE
+/* Get bytes from a HID Report Descriptor.
+   Only call with a num_bytes of 0, 1, 2, or 4. */
+static uint32_t get_bytes(uint8_t *rpt, size_t len, size_t num_bytes, size_t cur)
+{
+	/* Return if there aren't enough bytes. */
+	if (cur + num_bytes >= len)
+		return 0;
+
+	if (num_bytes == 0)
+		return 0;
+	else if (num_bytes == 1) {
+		return rpt[cur+1];
+	}
+	else if (num_bytes == 2) {
+		return (rpt[cur+2] * 256 + rpt[cur+1]);
+	}
+	else if (num_bytes == 4) {
+		return (rpt[cur+4] * 0x01000000 +
+		        rpt[cur+3] * 0x00010000 +
+		        rpt[cur+2] * 0x00000100 +
+		        rpt[cur+1] * 0x00000001);
+	}
+	else
+		return 0;
+}
+
+/* Retrieves the device's Usage Page and Usage from the report
+   descriptor. The algorithm is simple, as it just returns the first
+   Usage and Usage Page that it finds in the descriptor.
+   The return value is 0 on success and -1 on failure. */
+static int get_usage(uint8_t *report_descriptor, size_t size,
+                     unsigned short *usage_page, unsigned short *usage)
+{
+	unsigned int i = 0;
+	int size_code;
+	int data_len, key_size;
+	int usage_found = 0, usage_page_found = 0;
+
+	while (i < size) {
+		int key = report_descriptor[i];
+		int key_cmd = key & 0xfc;
+
+		//printf("key: %02hhx\n", key);
+
+		if ((key & 0xf0) == 0xf0) {
+			/* This is a Long Item. The next byte contains the
+			   length of the data section (value) for this key.
+			   See the HID specification, version 1.11, section
+			   6.2.2.3, titled "Long Items." */
+			if (i+1 < size)
+				data_len = report_descriptor[i+1];
+			else
+				data_len = 0; /* malformed report */
+			key_size = 3;
+		}
+		else {
+			/* This is a Short Item. The bottom two bits of the
+			   key contain the size code for the data section
+			   (value) for this key.  Refer to the HID
+			   specification, version 1.11, section 6.2.2.2,
+			   titled "Short Items." */
+			size_code = key & 0x3;
+			switch (size_code) {
+			case 0:
+			case 1:
+			case 2:
+				data_len = size_code;
+				break;
+			case 3:
+				data_len = 4;
+				break;
+			default:
+				/* Can't ever happen since size_code is & 0x3 */
+				data_len = 0;
+				break;
+			};
+			key_size = 1;
+		}
+
+		if (key_cmd == 0x4) {
+			*usage_page  = get_bytes(report_descriptor, size, data_len, i);
+			usage_page_found = 1;
+			//printf("Usage Page: %x\n", (uint32_t)*usage_page);
+		}
+		if (key_cmd == 0x8) {
+			*usage = get_bytes(report_descriptor, size, data_len, i);
+			usage_found = 1;
+			//printf("Usage: %x\n", (uint32_t)*usage);
+		}
+
+		if (usage_page_found && usage_found)
+			return 0; /* success */
+
+		/* Skip over this key and it's associated data */
+		i += data_len + key_size;
+	}
+
+	return -1; /* failure */
+}
+#endif /* INVASIVE_GET_USAGE */
+
+#if defined(__FreeBSD__) && __FreeBSD__ < 10
+/* The libusb version included in FreeBSD < 10 doesn't have this function. In
+   mainline libusb, it's inlined in libusb.h. This function will bear a striking
+   resemblance to that one, because there's about one way to code it.
+
+   Note that the data parameter is Unicode in UTF-16LE encoding.
+   Return value is the number of bytes in data, or LIBUSB_ERROR_*.
+ */
+static inline int libusb_get_string_descriptor(libusb_device_handle *dev,
+	uint8_t descriptor_index, uint16_t lang_id,
+	unsigned char *data, int length)
+{
+	return libusb_control_transfer(dev,
+		LIBUSB_ENDPOINT_IN | 0x0, /* Endpoint 0 IN */
+		LIBUSB_REQUEST_GET_DESCRIPTOR,
+		(LIBUSB_DT_STRING << 8) | descriptor_index,
+		lang_id, data, (uint16_t) length, 1000);
+}
+
+#endif
+
+
+/* Get the first language the device says it reports. This comes from
+   USB string #0. */
+static uint16_t get_first_language(libusb_device_handle *dev)
+{
+	uint16_t buf[32];
+	int len;
+
+	/* Get the string from libusb. */
+	len = libusb_get_string_descriptor(dev,
+			0x0, /* String ID */
+			0x0, /* Language */
+			(unsigned char*)buf,
+			sizeof(buf));
+	if (len < 4)
+		return 0x0;
+
+	return buf[1]; /* First two bytes are len and descriptor type. */
+}
+
+static int is_language_supported(libusb_device_handle *dev, uint16_t lang)
+{
+	uint16_t buf[32];
+	int len;
+	int i;
+
+	/* Get the string from libusb. */
+	len = libusb_get_string_descriptor(dev,
+			0x0, /* String ID */
+			0x0, /* Language */
+			(unsigned char*)buf,
+			sizeof(buf));
+	if (len < 4)
+		return 0x0;
+
+
+	len /= 2; /* language IDs are two-bytes each. */
+	/* Start at index 1 because there are two bytes of protocol data. */
+	for (i = 1; i < len; i++) {
+		if (buf[i] == lang)
+			return 1;
+	}
+
+	return 0;
+}
+
+
+/* This function returns a newly allocated wide string containing the USB
+   device string numbered by the index. The returned string must be freed
+   by using free(). */
+static wchar_t *get_usb_string(libusb_device_handle *dev, uint8_t idx)
+{
+	char buf[512];
+	int len;
+	wchar_t *str = NULL;
+
+#ifndef __ANDROID__ /* we don't use iconv on Android */
+	wchar_t wbuf[256];
+	/* iconv variables */
+	iconv_t ic;
+	size_t inbytes;
+	size_t outbytes;
+	size_t res;
+#ifdef __FreeBSD__
+	const char *inptr;
+#else
+	char *inptr;
+#endif
+	char *outptr;
+#endif
+
+	/* Determine which language to use. */
+	uint16_t lang;
+	lang = get_usb_code_for_current_locale();
+	if (!is_language_supported(dev, lang))
+		lang = get_first_language(dev);
+
+	/* Get the string from libusb. */
+	len = libusb_get_string_descriptor(dev,
+			idx,
+			lang,
+			(unsigned char*)buf,
+			sizeof(buf));
+	if (len < 0)
+		return NULL;
+
+#ifdef __ANDROID__
+
+	/* Bionic does not have iconv support nor wcsdup() function, so it
+	   has to be done manually.  The following code will only work for
+	   code points that can be represented as a single UTF-16 character,
+	   and will incorrectly convert any code points which require more
+	   than one UTF-16 character.
+
+	   Skip over the first character (2-bytes).  */
+	len -= 2;
+	str = malloc((len / 2 + 1) * sizeof(wchar_t));
+	int i;
+	for (i = 0; i < len / 2; i++) {
+		str[i] = buf[i * 2 + 2] | (buf[i * 2 + 3] << 8);
+	}
+	str[len / 2] = 0x00000000;
+
+#else
+
+	/* buf does not need to be explicitly NULL-terminated because
+	   it is only passed into iconv() which does not need it. */
+
+	/* Initialize iconv. */
+	ic = iconv_open("WCHAR_T", "UTF-16LE");
+	if (ic == (iconv_t)-1) {
+		LOG("iconv_open() failed\n");
+		return NULL;
+	}
+
+	/* Convert to native wchar_t (UTF-32 on glibc/BSD systems).
+	   Skip the first character (2-bytes). */
+	inptr = buf+2;
+	inbytes = len-2;
+	outptr = (char*) wbuf;
+	outbytes = sizeof(wbuf);
+	res = iconv(ic, &inptr, &inbytes, &outptr, &outbytes);
+	if (res == (size_t)-1) {
+		LOG("iconv() failed\n");
+		goto err;
+	}
+
+	/* Write the terminating NULL. */
+	wbuf[sizeof(wbuf)/sizeof(wbuf[0])-1] = 0x00000000;
+	if (outbytes >= sizeof(wbuf[0]))
+		*((wchar_t*)outptr) = 0x00000000;
+
+	/* Allocate and copy the string. */
+	str = wcsdup(wbuf);
+
+err:
+	iconv_close(ic);
+
+#endif
+
+	return str;
+}
+
+static char *make_path(libusb_device *dev, int interface_number)
+{
+	char str[64];
+	snprintf(str, sizeof(str), "%04x:%04x:%02x",
+		libusb_get_bus_number(dev),
+		libusb_get_device_address(dev),
+		interface_number);
+	str[sizeof(str)-1] = '\0';
+
+	return strdup(str);
+}
+
+
+int HID_API_EXPORT hid_init(void)
+{
+	if (!usb_context) {
+		const char *locale;
+
+		/* Init Libusb */
+		if (libusb_init(&usb_context))
+			return -1;
+
+		/* Set the locale if it's not set. */
+		locale = setlocale(LC_CTYPE, NULL);
+		if (!locale)
+			setlocale(LC_CTYPE, "");
+	}
+
+	return 0;
+}
+
+int HID_API_EXPORT hid_exit(void)
+{
+	if (usb_context) {
+		libusb_exit(usb_context);
+		usb_context = NULL;
+	}
+
+	return 0;
+}
+
+struct hid_device_info  HID_API_EXPORT *hid_enumerate(unsigned short vendor_id, unsigned short product_id)
+{
+	libusb_device **devs;
+	libusb_device *dev;
+	libusb_device_handle *handle;
+	ssize_t num_devs;
+	int i = 0;
+
+	struct hid_device_info *root = NULL; /* return object */
+	struct hid_device_info *cur_dev = NULL;
+
+	if(hid_init() < 0)
+		return NULL;
+
+	num_devs = libusb_get_device_list(usb_context, &devs);
+	if (num_devs < 0)
+		return NULL;
+	while ((dev = devs[i++]) != NULL) {
+		struct libusb_device_descriptor desc;
+		struct libusb_config_descriptor *conf_desc = NULL;
+		int j, k;
+		int interface_num = 0;
+
+		int res = libusb_get_device_descriptor(dev, &desc);
+		unsigned short dev_vid = desc.idVendor;
+		unsigned short dev_pid = desc.idProduct;
+
+		res = libusb_get_active_config_descriptor(dev, &conf_desc);
+		if (res < 0)
+			libusb_get_config_descriptor(dev, 0, &conf_desc);
+		if (conf_desc) {
+			for (j = 0; j < conf_desc->bNumInterfaces; j++) {
+				const struct libusb_interface *intf = &conf_desc->interface[j];
+				for (k = 0; k < intf->num_altsetting; k++) {
+					const struct libusb_interface_descriptor *intf_desc;
+					intf_desc = &intf->altsetting[k];
+					if (intf_desc->bInterfaceClass == LIBUSB_CLASS_HID) {
+						interface_num = intf_desc->bInterfaceNumber;
+
+						/* Check the VID/PID against the arguments */
+						if ((vendor_id == 0x0 || vendor_id == dev_vid) &&
+						    (product_id == 0x0 || product_id == dev_pid)) {
+							struct hid_device_info *tmp;
+
+							/* VID/PID match. Create the record. */
+							tmp = calloc(1, sizeof(struct hid_device_info));
+							if (cur_dev) {
+								cur_dev->next = tmp;
+							}
+							else {
+								root = tmp;
+							}
+							cur_dev = tmp;
+
+							/* Fill out the record */
+							cur_dev->next = NULL;
+							cur_dev->path = make_path(dev, interface_num);
+
+							res = libusb_open(dev, &handle);
+
+							if (res >= 0) {
+								/* Serial Number */
+								if (desc.iSerialNumber > 0)
+									cur_dev->serial_number =
+										get_usb_string(handle, desc.iSerialNumber);
+
+								/* Manufacturer and Product strings */
+								if (desc.iManufacturer > 0)
+									cur_dev->manufacturer_string =
+										get_usb_string(handle, desc.iManufacturer);
+								if (desc.iProduct > 0)
+									cur_dev->product_string =
+										get_usb_string(handle, desc.iProduct);
+
+#ifdef INVASIVE_GET_USAGE
+{
+							/*
+							This section is removed because it is too
+							invasive on the system. Getting a Usage Page
+							and Usage requires parsing the HID Report
+							descriptor. Getting a HID Report descriptor
+							involves claiming the interface. Claiming the
+							interface involves detaching the kernel driver.
+							Detaching the kernel driver is hard on the system
+							because it will unclaim interfaces (if another
+							app has them claimed) and the re-attachment of
+							the driver will sometimes change /dev entry names.
+							It is for these reasons that this section is
+							#if 0. For composite devices, use the interface
+							field in the hid_device_info struct to distinguish
+							between interfaces. */
+								unsigned char data[256];
+#ifdef DETACH_KERNEL_DRIVER
+								int detached = 0;
+								/* Usage Page and Usage */
+								res = libusb_kernel_driver_active(handle, interface_num);
+								if (res == 1) {
+									res = libusb_detach_kernel_driver(handle, interface_num);
+									if (res < 0)
+										LOG("Couldn't detach kernel driver, even though a kernel driver was attached.");
+									else
+										detached = 1;
+								}
+#endif
+								res = libusb_claim_interface(handle, interface_num);
+								if (res >= 0) {
+									/* Get the HID Report Descriptor. */
+									res = libusb_control_transfer(handle, LIBUSB_ENDPOINT_IN|LIBUSB_RECIPIENT_INTERFACE, LIBUSB_REQUEST_GET_DESCRIPTOR, (LIBUSB_DT_REPORT << 8)|interface_num, 0, data, sizeof(data), 5000);
+									if (res >= 0) {
+										unsigned short page=0, usage=0;
+										/* Parse the usage and usage page
+										   out of the report descriptor. */
+										get_usage(data, res,  &page, &usage);
+										cur_dev->usage_page = page;
+										cur_dev->usage = usage;
+									}
+									else
+										LOG("libusb_control_transfer() for getting the HID report failed with %d\n", res);
+
+									/* Release the interface */
+									res = libusb_release_interface(handle, interface_num);
+									if (res < 0)
+										LOG("Can't release the interface.\n");
+								}
+								else
+									LOG("Can't claim interface %d\n", res);
+#ifdef DETACH_KERNEL_DRIVER
+								/* Re-attach kernel driver if necessary. */
+								if (detached) {
+									res = libusb_attach_kernel_driver(handle, interface_num);
+									if (res < 0)
+										LOG("Couldn't re-attach kernel driver.\n");
+								}
+#endif
+}
+#endif /* INVASIVE_GET_USAGE */
+
+								libusb_close(handle);
+							}
+							/* VID/PID */
+							cur_dev->vendor_id = dev_vid;
+							cur_dev->product_id = dev_pid;
+
+							/* Release Number */
+							cur_dev->release_number = desc.bcdDevice;
+
+							/* Interface Number */
+							cur_dev->interface_number = interface_num;
+						}
+					}
+				} /* altsettings */
+			} /* interfaces */
+			libusb_free_config_descriptor(conf_desc);
+		}
+	}
+
+	libusb_free_device_list(devs, 1);
+
+	return root;
+}
+
+void  HID_API_EXPORT hid_free_enumeration(struct hid_device_info *devs)
+{
+	struct hid_device_info *d = devs;
+	while (d) {
+		struct hid_device_info *next = d->next;
+		free(d->path);
+		free(d->serial_number);
+		free(d->manufacturer_string);
+		free(d->product_string);
+		free(d);
+		d = next;
+	}
+}
+
+hid_device * hid_open(unsigned short vendor_id, unsigned short product_id, const wchar_t *serial_number)
+{
+	struct hid_device_info *devs, *cur_dev;
+	const char *path_to_open = NULL;
+	hid_device *handle = NULL;
+
+	devs = hid_enumerate(vendor_id, product_id);
+	cur_dev = devs;
+	while (cur_dev) {
+		if (cur_dev->vendor_id == vendor_id &&
+		    cur_dev->product_id == product_id) {
+			if (serial_number) {
+				if (cur_dev->serial_number &&
+				    wcscmp(serial_number, cur_dev->serial_number) == 0) {
+					path_to_open = cur_dev->path;
+					break;
+				}
+			}
+			else {
+				path_to_open = cur_dev->path;
+				break;
+			}
+		}
+		cur_dev = cur_dev->next;
+	}
+
+	if (path_to_open) {
+		/* Open the device */
+		handle = hid_open_path(path_to_open);
+	}
+
+	hid_free_enumeration(devs);
+
+	return handle;
+}
+
+static void read_callback(struct libusb_transfer *transfer)
+{
+	hid_device *dev = transfer->user_data;
+	int res;
+
+	if (transfer->status == LIBUSB_TRANSFER_COMPLETED) {
+
+		struct input_report *rpt = malloc(sizeof(*rpt));
+		rpt->data = malloc(transfer->actual_length);
+		memcpy(rpt->data, transfer->buffer, transfer->actual_length);
+		rpt->len = transfer->actual_length;
+		rpt->next = NULL;
+
+		pthread_mutex_lock(&dev->mutex);
+
+		/* Attach the new report object to the end of the list. */
+		if (dev->input_reports == NULL) {
+			/* The list is empty. Put it at the root. */
+			dev->input_reports = rpt;
+			pthread_cond_signal(&dev->condition);
+		}
+		else {
+			/* Find the end of the list and attach. */
+			struct input_report *cur = dev->input_reports;
+			int num_queued = 0;
+			while (cur->next != NULL) {
+				cur = cur->next;
+				num_queued++;
+			}
+			cur->next = rpt;
+
+			/* Pop one off if we've reached 30 in the queue. This
+			   way we don't grow forever if the user never reads
+			   anything from the device. */
+			if (num_queued > 30) {
+				return_data(dev, NULL, 0);
+			}
+		}
+		pthread_mutex_unlock(&dev->mutex);
+	}
+	else if (transfer->status == LIBUSB_TRANSFER_CANCELLED) {
+		dev->shutdown_thread = 1;
+		dev->cancelled = 1;
+		return;
+	}
+	else if (transfer->status == LIBUSB_TRANSFER_NO_DEVICE) {
+		dev->shutdown_thread = 1;
+		dev->cancelled = 1;
+		return;
+	}
+	else if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) {
+		//LOG("Timeout (normal)\n");
+	}
+	else {
+		LOG("Unknown transfer code: %d\n", transfer->status);
+	}
+
+	/* Re-submit the transfer object. */
+	res = libusb_submit_transfer(transfer);
+	if (res != 0) {
+		LOG("Unable to submit URB. libusb error code: %d\n", res);
+		dev->shutdown_thread = 1;
+		dev->cancelled = 1;
+	}
+}
+
+
+static void *read_thread(void *param)
+{
+	hid_device *dev = param;
+	unsigned char *buf;
+	const size_t length = dev->input_ep_max_packet_size;
+
+	/* Set up the transfer object. */
+	buf = malloc(length);
+	dev->transfer = libusb_alloc_transfer(0);
+	libusb_fill_interrupt_transfer(dev->transfer,
+		dev->device_handle,
+		dev->input_endpoint,
+		buf,
+		length,
+		read_callback,
+		dev,
+		5000/*timeout*/);
+
+	/* Make the first submission. Further submissions are made
+	   from inside read_callback() */
+	libusb_submit_transfer(dev->transfer);
+
+	/* Notify the main thread that the read thread is up and running. */
+	pthread_barrier_wait(&dev->barrier);
+
+	/* Handle all the events. */
+	while (!dev->shutdown_thread) {
+		int res;
+		res = libusb_handle_events(usb_context);
+		if (res < 0) {
+			/* There was an error. */
+			LOG("read_thread(): libusb reports error # %d\n", res);
+
+			/* Break out of this loop only on fatal error.*/
+			if (res != LIBUSB_ERROR_BUSY &&
+			    res != LIBUSB_ERROR_TIMEOUT &&
+			    res != LIBUSB_ERROR_OVERFLOW &&
+			    res != LIBUSB_ERROR_INTERRUPTED) {
+				break;
+			}
+		}
+	}
+
+	/* Cancel any transfer that may be pending. This call will fail
+	   if no transfers are pending, but that's OK. */
+	libusb_cancel_transfer(dev->transfer);
+
+	while (!dev->cancelled)
+		libusb_handle_events_completed(usb_context, &dev->cancelled);
+
+	/* Now that the read thread is stopping, Wake any threads which are
+	   waiting on data (in hid_read_timeout()). Do this under a mutex to
+	   make sure that a thread which is about to go to sleep waiting on
+	   the condition actually will go to sleep before the condition is
+	   signaled. */
+	pthread_mutex_lock(&dev->mutex);
+	pthread_cond_broadcast(&dev->condition);
+	pthread_mutex_unlock(&dev->mutex);
+
+	/* The dev->transfer->buffer and dev->transfer objects are cleaned up
+	   in hid_close(). They are not cleaned up here because this thread
+	   could end either due to a disconnect or due to a user
+	   call to hid_close(). In both cases the objects can be safely
+	   cleaned up after the call to pthread_join() (in hid_close()), but
+	   since hid_close() calls libusb_cancel_transfer(), on these objects,
+	   they can not be cleaned up here. */
+
+	return NULL;
+}
+
+
+hid_device * HID_API_EXPORT hid_open_path(const char *path)
+{
+	hid_device *dev = NULL;
+
+	libusb_device **devs;
+	libusb_device *usb_dev;
+	int res;
+	int d = 0;
+	int good_open = 0;
+
+	if(hid_init() < 0)
+		return NULL;
+
+	dev = new_hid_device();
+
+	libusb_get_device_list(usb_context, &devs);
+	while ((usb_dev = devs[d++]) != NULL) {
+		struct libusb_device_descriptor desc;
+		struct libusb_config_descriptor *conf_desc = NULL;
+		int i,j,k;
+		libusb_get_device_descriptor(usb_dev, &desc);
+
+		if (libusb_get_active_config_descriptor(usb_dev, &conf_desc) < 0)
+			continue;
+		for (j = 0; j < conf_desc->bNumInterfaces; j++) {
+			const struct libusb_interface *intf = &conf_desc->interface[j];
+			for (k = 0; k < intf->num_altsetting; k++) {
+				const struct libusb_interface_descriptor *intf_desc;
+				intf_desc = &intf->altsetting[k];
+				if (intf_desc->bInterfaceClass == LIBUSB_CLASS_HID) {
+					char *dev_path = make_path(usb_dev, intf_desc->bInterfaceNumber);
+					if (!strcmp(dev_path, path)) {
+						/* Matched Paths. Open this device */
+
+						/* OPEN HERE */
+						res = libusb_open(usb_dev, &dev->device_handle);
+						if (res < 0) {
+							LOG("can't open device\n");
+							free(dev_path);
+							break;
+						}
+						good_open = 1;
+#ifdef DETACH_KERNEL_DRIVER
+						/* Detach the kernel driver, but only if the
+						   device is managed by the kernel */
+						if (libusb_kernel_driver_active(dev->device_handle, intf_desc->bInterfaceNumber) == 1) {
+							res = libusb_detach_kernel_driver(dev->device_handle, intf_desc->bInterfaceNumber);
+							if (res < 0) {
+								libusb_close(dev->device_handle);
+								LOG("Unable to detach Kernel Driver\n");
+								free(dev_path);
+								good_open = 0;
+								break;
+							}
+						}
+#endif
+						res = libusb_claim_interface(dev->device_handle, intf_desc->bInterfaceNumber);
+						if (res < 0) {
+							LOG("can't claim interface %d: %d\n", intf_desc->bInterfaceNumber, res);
+							free(dev_path);
+							libusb_close(dev->device_handle);
+							good_open = 0;
+							break;
+						}
+
+						/* Store off the string descriptor indexes */
+						dev->manufacturer_index = desc.iManufacturer;
+						dev->product_index      = desc.iProduct;
+						dev->serial_index       = desc.iSerialNumber;
+
+						/* Store off the interface number */
+						dev->interface = intf_desc->bInterfaceNumber;
+
+						/* Find the INPUT and OUTPUT endpoints. An
+						   OUTPUT endpoint is not required. */
+						for (i = 0; i < intf_desc->bNumEndpoints; i++) {
+							const struct libusb_endpoint_descriptor *ep
+								= &intf_desc->endpoint[i];
+
+							/* Determine the type and direction of this
+							   endpoint. */
+							int is_interrupt =
+								(ep->bmAttributes & LIBUSB_TRANSFER_TYPE_MASK)
+							      == LIBUSB_TRANSFER_TYPE_INTERRUPT;
+							int is_output =
+								(ep->bEndpointAddress & LIBUSB_ENDPOINT_DIR_MASK)
+							      == LIBUSB_ENDPOINT_OUT;
+							int is_input =
+								(ep->bEndpointAddress & LIBUSB_ENDPOINT_DIR_MASK)
+							      == LIBUSB_ENDPOINT_IN;
+
+							/* Decide whether to use it for input or output. */
+							if (dev->input_endpoint == 0 &&
+							    is_interrupt && is_input) {
+								/* Use this endpoint for INPUT */
+								dev->input_endpoint = ep->bEndpointAddress;
+								dev->input_ep_max_packet_size = ep->wMaxPacketSize;
+							}
+							if (dev->output_endpoint == 0 &&
+							    is_interrupt && is_output) {
+								/* Use this endpoint for OUTPUT */
+								dev->output_endpoint = ep->bEndpointAddress;
+							}
+						}
+
+						pthread_create(&dev->thread, NULL, read_thread, dev);
+
+						/* Wait here for the read thread to be initialized. */
+						pthread_barrier_wait(&dev->barrier);
+
+					}
+					free(dev_path);
+				}
+			}
+		}
+		libusb_free_config_descriptor(conf_desc);
+
+	}
+
+	libusb_free_device_list(devs, 1);
+
+	/* If we have a good handle, return it. */
+	if (good_open) {
+		return dev;
+	}
+	else {
+		/* Unable to open any devices. */
+		free_hid_device(dev);
+		return NULL;
+	}
+}
+
+
+int HID_API_EXPORT hid_write(hid_device *dev, const unsigned char *data, size_t length)
+{
+	int res;
+	int report_number = data[0];
+	int skipped_report_id = 0;
+
+	if (report_number == 0x0) {
+		data++;
+		length--;
+		skipped_report_id = 1;
+	}
+
+
+	if (dev->output_endpoint <= 0) {
+		/* No interrupt out endpoint. Use the Control Endpoint */
+		res = libusb_control_transfer(dev->device_handle,
+			LIBUSB_REQUEST_TYPE_CLASS|LIBUSB_RECIPIENT_INTERFACE|LIBUSB_ENDPOINT_OUT,
+			0x09/*HID Set_Report*/,
+			(2/*HID output*/ << 8) | report_number,
+			dev->interface,
+			(unsigned char *)data, length,
+			1000/*timeout millis*/);
+
+		if (res < 0)
+			return -1;
+
+		if (skipped_report_id)
+			length++;
+
+		return length;
+	}
+	else {
+		/* Use the interrupt out endpoint */
+		int actual_length;
+		res = libusb_interrupt_transfer(dev->device_handle,
+			dev->output_endpoint,
+			(unsigned char*)data,
+			length,
+			&actual_length, 1000);
+
+		if (res < 0)
+			return -1;
+
+		if (skipped_report_id)
+			actual_length++;
+
+		return actual_length;
+	}
+}
+
+/* Helper function, to simplify hid_read().
+   This should be called with dev->mutex locked. */
+static int return_data(hid_device *dev, unsigned char *data, size_t length)
+{
+	/* Copy the data out of the linked list item (rpt) into the
+	   return buffer (data), and delete the liked list item. */
+	struct input_report *rpt = dev->input_reports;
+	size_t len = (length < rpt->len)? length: rpt->len;
+	if (len > 0)
+		memcpy(data, rpt->data, len);
+	dev->input_reports = rpt->next;
+	free(rpt->data);
+	free(rpt);
+	return len;
+}
+
+static void cleanup_mutex(void *param)
+{
+	hid_device *dev = param;
+	pthread_mutex_unlock(&dev->mutex);
+}
+
+
+int HID_API_EXPORT hid_read_timeout(hid_device *dev, unsigned char *data, size_t length, int milliseconds)
+{
+	int bytes_read = -1;
+
+#if 0
+	int transferred;
+	int res = libusb_interrupt_transfer(dev->device_handle, dev->input_endpoint, data, length, &transferred, 5000);
+	LOG("transferred: %d\n", transferred);
+	return transferred;
+#endif
+
+	pthread_mutex_lock(&dev->mutex);
+	pthread_cleanup_push(&cleanup_mutex, dev);
+
+	/* There's an input report queued up. Return it. */
+	if (dev->input_reports) {
+		/* Return the first one */
+		bytes_read = return_data(dev, data, length);
+		goto ret;
+	}
+
+	if (dev->shutdown_thread) {
+		/* This means the device has been disconnected.
+		   An error code of -1 should be returned. */
+		bytes_read = -1;
+		goto ret;
+	}
+
+	if (milliseconds == -1) {
+		/* Blocking */
+		while (!dev->input_reports && !dev->shutdown_thread) {
+			pthread_cond_wait(&dev->condition, &dev->mutex);
+		}
+		if (dev->input_reports) {
+			bytes_read = return_data(dev, data, length);
+		}
+	}
+	else if (milliseconds > 0) {
+		/* Non-blocking, but called with timeout. */
+		int res;
+		struct timespec ts;
+		clock_gettime(CLOCK_REALTIME, &ts);
+		ts.tv_sec += milliseconds / 1000;
+		ts.tv_nsec += (milliseconds % 1000) * 1000000;
+		if (ts.tv_nsec >= 1000000000L) {
+			ts.tv_sec++;
+			ts.tv_nsec -= 1000000000L;
+		}
+
+		while (!dev->input_reports && !dev->shutdown_thread) {
+			res = pthread_cond_timedwait(&dev->condition, &dev->mutex, &ts);
+			if (res == 0) {
+				if (dev->input_reports) {
+					bytes_read = return_data(dev, data, length);
+					break;
+				}
+
+				/* If we're here, there was a spurious wake up
+				   or the read thread was shutdown. Run the
+				   loop again (ie: don't break). */
+			}
+			else if (res == ETIMEDOUT) {
+				/* Timed out. */
+				bytes_read = 0;
+				break;
+			}
+			else {
+				/* Error. */
+				bytes_read = -1;
+				break;
+			}
+		}
+	}
+	else {
+		/* Purely non-blocking */
+		bytes_read = 0;
+	}
+
+ret:
+	pthread_mutex_unlock(&dev->mutex);
+	pthread_cleanup_pop(0);
+
+	return bytes_read;
+}
+
+int HID_API_EXPORT hid_read(hid_device *dev, unsigned char *data, size_t length)
+{
+	return hid_read_timeout(dev, data, length, dev->blocking ? -1 : 0);
+}
+
+int HID_API_EXPORT hid_set_nonblocking(hid_device *dev, int nonblock)
+{
+	dev->blocking = !nonblock;
+
+	return 0;
+}
+
+
+int HID_API_EXPORT hid_send_feature_report(hid_device *dev, const unsigned char *data, size_t length)
+{
+	int res = -1;
+	int skipped_report_id = 0;
+	int report_number = data[0];
+
+	if (report_number == 0x0) {
+		data++;
+		length--;
+		skipped_report_id = 1;
+	}
+
+	res = libusb_control_transfer(dev->device_handle,
+		LIBUSB_REQUEST_TYPE_CLASS|LIBUSB_RECIPIENT_INTERFACE|LIBUSB_ENDPOINT_OUT,
+		0x09/*HID set_report*/,
+		(3/*HID feature*/ << 8) | report_number,
+		dev->interface,
+		(unsigned char *)data, length,
+		1000/*timeout millis*/);
+
+	if (res < 0)
+		return -1;
+
+	/* Account for the report ID */
+	if (skipped_report_id)
+		length++;
+
+	return length;
+}
+
+int HID_API_EXPORT hid_get_feature_report(hid_device *dev, unsigned char *data, size_t length)
+{
+	int res = -1;
+	int skipped_report_id = 0;
+	int report_number = data[0];
+
+	if (report_number == 0x0) {
+		/* Offset the return buffer by 1, so that the report ID
+		   will remain in byte 0. */
+		data++;
+		length--;
+		skipped_report_id = 1;
+	}
+	res = libusb_control_transfer(dev->device_handle,
+		LIBUSB_REQUEST_TYPE_CLASS|LIBUSB_RECIPIENT_INTERFACE|LIBUSB_ENDPOINT_IN,
+		0x01/*HID get_report*/,
+		(3/*HID feature*/ << 8) | report_number,
+		dev->interface,
+		(unsigned char *)data, length,
+		1000/*timeout millis*/);
+
+	if (res < 0)
+		return -1;
+
+	if (skipped_report_id)
+		res++;
+
+	return res;
+}
+
+
+void HID_API_EXPORT hid_close(hid_device *dev)
+{
+	if (!dev)
+		return;
+
+	/* Cause read_thread() to stop. */
+	dev->shutdown_thread = 1;
+	libusb_cancel_transfer(dev->transfer);
+
+	/* Wait for read_thread() to end. */
+	pthread_join(dev->thread, NULL);
+
+	/* Clean up the Transfer objects allocated in read_thread(). */
+	free(dev->transfer->buffer);
+	libusb_free_transfer(dev->transfer);
+
+	/* release the interface */
+	libusb_release_interface(dev->device_handle, dev->interface);
+
+	/* Close the handle */
+	libusb_close(dev->device_handle);
+
+	/* Clear out the queue of received reports. */
+	pthread_mutex_lock(&dev->mutex);
+	while (dev->input_reports) {
+		return_data(dev, NULL, 0);
+	}
+	pthread_mutex_unlock(&dev->mutex);
+
+	free_hid_device(dev);
+}
+
+
+int HID_API_EXPORT_CALL hid_get_manufacturer_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	return hid_get_indexed_string(dev, dev->manufacturer_index, string, maxlen);
+}
+
+int HID_API_EXPORT_CALL hid_get_product_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	return hid_get_indexed_string(dev, dev->product_index, string, maxlen);
+}
+
+int HID_API_EXPORT_CALL hid_get_serial_number_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	return hid_get_indexed_string(dev, dev->serial_index, string, maxlen);
+}
+
+int HID_API_EXPORT_CALL hid_get_indexed_string(hid_device *dev, int string_index, wchar_t *string, size_t maxlen)
+{
+	wchar_t *str;
+
+	str = get_usb_string(dev->device_handle, string_index);
+	if (str) {
+		wcsncpy(string, str, maxlen);
+		string[maxlen-1] = L'\0';
+		free(str);
+		return 0;
+	}
+	else
+		return -1;
+}
+
+
+HID_API_EXPORT const wchar_t * HID_API_CALL  hid_error(hid_device *dev)
+{
+	return NULL;
+}
+
+
+struct lang_map_entry {
+	const char *name;
+	const char *string_code;
+	uint16_t usb_code;
+};
+
+#define LANG(name,code,usb_code) { name, code, usb_code }
+static struct lang_map_entry lang_map[] = {
+	LANG("Afrikaans", "af", 0x0436),
+	LANG("Albanian", "sq", 0x041C),
+	LANG("Arabic - United Arab Emirates", "ar_ae", 0x3801),
+	LANG("Arabic - Bahrain", "ar_bh", 0x3C01),
+	LANG("Arabic - Algeria", "ar_dz", 0x1401),
+	LANG("Arabic - Egypt", "ar_eg", 0x0C01),
+	LANG("Arabic - Iraq", "ar_iq", 0x0801),
+	LANG("Arabic - Jordan", "ar_jo", 0x2C01),
+	LANG("Arabic - Kuwait", "ar_kw", 0x3401),
+	LANG("Arabic - Lebanon", "ar_lb", 0x3001),
+	LANG("Arabic - Libya", "ar_ly", 0x1001),
+	LANG("Arabic - Morocco", "ar_ma", 0x1801),
+	LANG("Arabic - Oman", "ar_om", 0x2001),
+	LANG("Arabic - Qatar", "ar_qa", 0x4001),
+	LANG("Arabic - Saudi Arabia", "ar_sa", 0x0401),
+	LANG("Arabic - Syria", "ar_sy", 0x2801),
+	LANG("Arabic - Tunisia", "ar_tn", 0x1C01),
+	LANG("Arabic - Yemen", "ar_ye", 0x2401),
+	LANG("Armenian", "hy", 0x042B),
+	LANG("Azeri - Latin", "az_az", 0x042C),
+	LANG("Azeri - Cyrillic", "az_az", 0x082C),
+	LANG("Basque", "eu", 0x042D),
+	LANG("Belarusian", "be", 0x0423),
+	LANG("Bulgarian", "bg", 0x0402),
+	LANG("Catalan", "ca", 0x0403),
+	LANG("Chinese - China", "zh_cn", 0x0804),
+	LANG("Chinese - Hong Kong SAR", "zh_hk", 0x0C04),
+	LANG("Chinese - Macau SAR", "zh_mo", 0x1404),
+	LANG("Chinese - Singapore", "zh_sg", 0x1004),
+	LANG("Chinese - Taiwan", "zh_tw", 0x0404),
+	LANG("Croatian", "hr", 0x041A),
+	LANG("Czech", "cs", 0x0405),
+	LANG("Danish", "da", 0x0406),
+	LANG("Dutch - Netherlands", "nl_nl", 0x0413),
+	LANG("Dutch - Belgium", "nl_be", 0x0813),
+	LANG("English - Australia", "en_au", 0x0C09),
+	LANG("English - Belize", "en_bz", 0x2809),
+	LANG("English - Canada", "en_ca", 0x1009),
+	LANG("English - Caribbean", "en_cb", 0x2409),
+	LANG("English - Ireland", "en_ie", 0x1809),
+	LANG("English - Jamaica", "en_jm", 0x2009),
+	LANG("English - New Zealand", "en_nz", 0x1409),
+	LANG("English - Phillippines", "en_ph", 0x3409),
+	LANG("English - Southern Africa", "en_za", 0x1C09),
+	LANG("English - Trinidad", "en_tt", 0x2C09),
+	LANG("English - Great Britain", "en_gb", 0x0809),
+	LANG("English - United States", "en_us", 0x0409),
+	LANG("Estonian", "et", 0x0425),
+	LANG("Farsi", "fa", 0x0429),
+	LANG("Finnish", "fi", 0x040B),
+	LANG("Faroese", "fo", 0x0438),
+	LANG("French - France", "fr_fr", 0x040C),
+	LANG("French - Belgium", "fr_be", 0x080C),
+	LANG("French - Canada", "fr_ca", 0x0C0C),
+	LANG("French - Luxembourg", "fr_lu", 0x140C),
+	LANG("French - Switzerland", "fr_ch", 0x100C),
+	LANG("Gaelic - Ireland", "gd_ie", 0x083C),
+	LANG("Gaelic - Scotland", "gd", 0x043C),
+	LANG("German - Germany", "de_de", 0x0407),
+	LANG("German - Austria", "de_at", 0x0C07),
+	LANG("German - Liechtenstein", "de_li", 0x1407),
+	LANG("German - Luxembourg", "de_lu", 0x1007),
+	LANG("German - Switzerland", "de_ch", 0x0807),
+	LANG("Greek", "el", 0x0408),
+	LANG("Hebrew", "he", 0x040D),
+	LANG("Hindi", "hi", 0x0439),
+	LANG("Hungarian", "hu", 0x040E),
+	LANG("Icelandic", "is", 0x040F),
+	LANG("Indonesian", "id", 0x0421),
+	LANG("Italian - Italy", "it_it", 0x0410),
+	LANG("Italian - Switzerland", "it_ch", 0x0810),
+	LANG("Japanese", "ja", 0x0411),
+	LANG("Korean", "ko", 0x0412),
+	LANG("Latvian", "lv", 0x0426),
+	LANG("Lithuanian", "lt", 0x0427),
+	LANG("F.Y.R.O. Macedonia", "mk", 0x042F),
+	LANG("Malay - Malaysia", "ms_my", 0x043E),
+	LANG("Malay – Brunei", "ms_bn", 0x083E),
+	LANG("Maltese", "mt", 0x043A),
+	LANG("Marathi", "mr", 0x044E),
+	LANG("Norwegian - Bokml", "no_no", 0x0414),
+	LANG("Norwegian - Nynorsk", "no_no", 0x0814),
+	LANG("Polish", "pl", 0x0415),
+	LANG("Portuguese - Portugal", "pt_pt", 0x0816),
+	LANG("Portuguese - Brazil", "pt_br", 0x0416),
+	LANG("Raeto-Romance", "rm", 0x0417),
+	LANG("Romanian - Romania", "ro", 0x0418),
+	LANG("Romanian - Republic of Moldova", "ro_mo", 0x0818),
+	LANG("Russian", "ru", 0x0419),
+	LANG("Russian - Republic of Moldova", "ru_mo", 0x0819),
+	LANG("Sanskrit", "sa", 0x044F),
+	LANG("Serbian - Cyrillic", "sr_sp", 0x0C1A),
+	LANG("Serbian - Latin", "sr_sp", 0x081A),
+	LANG("Setsuana", "tn", 0x0432),
+	LANG("Slovenian", "sl", 0x0424),
+	LANG("Slovak", "sk", 0x041B),
+	LANG("Sorbian", "sb", 0x042E),
+	LANG("Spanish - Spain (Traditional)", "es_es", 0x040A),
+	LANG("Spanish - Argentina", "es_ar", 0x2C0A),
+	LANG("Spanish - Bolivia", "es_bo", 0x400A),
+	LANG("Spanish - Chile", "es_cl", 0x340A),
+	LANG("Spanish - Colombia", "es_co", 0x240A),
+	LANG("Spanish - Costa Rica", "es_cr", 0x140A),
+	LANG("Spanish - Dominican Republic", "es_do", 0x1C0A),
+	LANG("Spanish - Ecuador", "es_ec", 0x300A),
+	LANG("Spanish - Guatemala", "es_gt", 0x100A),
+	LANG("Spanish - Honduras", "es_hn", 0x480A),
+	LANG("Spanish - Mexico", "es_mx", 0x080A),
+	LANG("Spanish - Nicaragua", "es_ni", 0x4C0A),
+	LANG("Spanish - Panama", "es_pa", 0x180A),
+	LANG("Spanish - Peru", "es_pe", 0x280A),
+	LANG("Spanish - Puerto Rico", "es_pr", 0x500A),
+	LANG("Spanish - Paraguay", "es_py", 0x3C0A),
+	LANG("Spanish - El Salvador", "es_sv", 0x440A),
+	LANG("Spanish - Uruguay", "es_uy", 0x380A),
+	LANG("Spanish - Venezuela", "es_ve", 0x200A),
+	LANG("Southern Sotho", "st", 0x0430),
+	LANG("Swahili", "sw", 0x0441),
+	LANG("Swedish - Sweden", "sv_se", 0x041D),
+	LANG("Swedish - Finland", "sv_fi", 0x081D),
+	LANG("Tamil", "ta", 0x0449),
+	LANG("Tatar", "tt", 0X0444),
+	LANG("Thai", "th", 0x041E),
+	LANG("Turkish", "tr", 0x041F),
+	LANG("Tsonga", "ts", 0x0431),
+	LANG("Ukrainian", "uk", 0x0422),
+	LANG("Urdu", "ur", 0x0420),
+	LANG("Uzbek - Cyrillic", "uz_uz", 0x0843),
+	LANG("Uzbek – Latin", "uz_uz", 0x0443),
+	LANG("Vietnamese", "vi", 0x042A),
+	LANG("Xhosa", "xh", 0x0434),
+	LANG("Yiddish", "yi", 0x043D),
+	LANG("Zulu", "zu", 0x0435),
+	LANG(NULL, NULL, 0x0),
+};
+
+uint16_t get_usb_code_for_current_locale(void)
+{
+	char *locale;
+	char search_string[64];
+	char *ptr;
+	struct lang_map_entry *lang;
+
+	/* Get the current locale. */
+	locale = setlocale(0, NULL);
+	if (!locale)
+		return 0x0;
+
+	/* Make a copy of the current locale string. */
+	strncpy(search_string, locale, sizeof(search_string));
+	search_string[sizeof(search_string)-1] = '\0';
+
+	/* Chop off the encoding part, and make it lower case. */
+	ptr = search_string;
+	while (*ptr) {
+		*ptr = tolower(*ptr);
+		if (*ptr == '.') {
+			*ptr = '\0';
+			break;
+		}
+		ptr++;
+	}
+
+	/* Find the entry which matches the string code of our locale. */
+	lang = lang_map;
+	while (lang->string_code) {
+		if (!strcmp(lang->string_code, search_string)) {
+			return lang->usb_code;
+		}
+		lang++;
+	}
+
+	/* There was no match. Find with just the language only. */
+	/* Chop off the variant. Chop it off at the '_'. */
+	ptr = search_string;
+	while (*ptr) {
+		*ptr = tolower(*ptr);
+		if (*ptr == '_') {
+			*ptr = '\0';
+			break;
+		}
+		ptr++;
+	}
+
+#if 0 /* TODO: Do we need this? */
+	/* Find the entry which matches the string code of our language. */
+	lang = lang_map;
+	while (lang->string_code) {
+		if (!strcmp(lang->string_code, search_string)) {
+			return lang->usb_code;
+		}
+		lang++;
+	}
+#endif
+
+	/* Found nothing. */
+	return 0x0;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/uf2-samdx1/lib/uf2/hidapi/linux/.gitignore b/uf2-samdx1/lib/uf2/hidapi/linux/.gitignore
new file mode 100644
index 00000000..127bf37d
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/linux/.gitignore
@@ -0,0 +1,18 @@
+Debug
+Release
+*.exp
+*.ilk
+*.lib
+*.suo
+*.vcproj.*
+*.ncb
+*.suo
+*.dll
+*.pdb
+*.o
+*.so
+hidtest-hidraw
+.deps
+.libs
+*.lo
+*.la
diff --git a/uf2-samdx1/lib/uf2/hidapi/linux/Makefile-manual b/uf2-samdx1/lib/uf2/hidapi/linux/Makefile-manual
new file mode 100644
index 00000000..04ce1de4
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/linux/Makefile-manual
@@ -0,0 +1,49 @@
+###########################################
+# Simple Makefile for HIDAPI test program
+#
+# Alan Ott
+# Signal 11 Software
+# 2010-06-01
+###########################################
+
+all: hidtest-hidraw libs
+
+libs: libhidapi-hidraw.so
+
+CC       ?= gcc
+CFLAGS   ?= -Wall -g -fpic
+
+CXX      ?= g++
+CXXFLAGS ?= -Wall -g -fpic
+
+LDFLAGS  ?= -Wall -g
+
+
+COBJS     = hid.o
+CPPOBJS   = ../hidtest/hidtest.o
+OBJS      = $(COBJS) $(CPPOBJS)
+LIBS_UDEV = `pkg-config libudev --libs` -lrt
+LIBS      = $(LIBS_UDEV)
+INCLUDES ?= -I../hidapi `pkg-config libusb-1.0 --cflags`
+
+
+# Console Test Program
+hidtest-hidraw: $(COBJS) $(CPPOBJS)
+	$(CXX) $(LDFLAGS) $^ $(LIBS_UDEV) -o $@
+
+# Shared Libs
+libhidapi-hidraw.so: $(COBJS)
+	$(CC) $(LDFLAGS) $(LIBS_UDEV) -shared -fpic -Wl,-soname,$@.0 $^ -o $@
+
+# Objects
+$(COBJS): %.o: %.c
+	$(CC) $(CFLAGS) -c $(INCLUDES) $< -o $@
+
+$(CPPOBJS): %.o: %.cpp
+	$(CXX) $(CXXFLAGS) -c $(INCLUDES) $< -o $@
+
+
+clean:
+	rm -f $(OBJS) hidtest-hidraw libhidapi-hidraw.so ../hidtest/hidtest.o
+
+.PHONY: clean libs
diff --git a/uf2-samdx1/lib/uf2/hidapi/linux/Makefile.am b/uf2-samdx1/lib/uf2/hidapi/linux/Makefile.am
new file mode 100644
index 00000000..230eeb75
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/linux/Makefile.am
@@ -0,0 +1,10 @@
+lib_LTLIBRARIES = libhidapi-hidraw.la
+libhidapi_hidraw_la_SOURCES = hid.c
+libhidapi_hidraw_la_LDFLAGS = $(LTLDFLAGS)
+AM_CPPFLAGS = -I$(top_srcdir)/hidapi/ $(CFLAGS_HIDRAW)
+libhidapi_hidraw_la_LIBADD = $(LIBS_HIDRAW)
+
+hdrdir = $(includedir)/hidapi
+hdr_HEADERS = $(top_srcdir)/hidapi/hidapi.h
+
+EXTRA_DIST = Makefile-manual
diff --git a/uf2-samdx1/lib/uf2/hidapi/linux/README.txt b/uf2-samdx1/lib/uf2/hidapi/linux/README.txt
new file mode 100644
index 00000000..80066949
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/linux/README.txt
@@ -0,0 +1,59 @@
+
+There are two implementations of HIDAPI for Linux. One (linux/hid.c) uses the
+Linux hidraw driver, and the other (libusb/hid.c) uses libusb. Which one you
+use depends on your application. Complete functionality of the hidraw
+version depends on patches to the Linux kernel which are not currently in
+the mainline. These patches have to do with sending and receiving feature
+reports. The libusb implementation uses libusb to talk directly to the
+device, bypassing any Linux HID driver. The disadvantage of the libusb
+version is that it will only work with USB devices, while the hidraw
+implementation will work with Bluetooth devices as well.
+
+To use HIDAPI, simply drop either linux/hid.c or libusb/hid.c into your
+application and build using the build parameters in the Makefile.
+
+
+Libusb Implementation notes
+----------------------------
+For the libusb implementation, libusb-1.0 must be installed. Libusb 1.0 is
+different than the legacy libusb 0.1 which is installed on many systems. To
+install libusb-1.0 on Ubuntu and other Debian-based systems, run:
+	sudo apt-get install libusb-1.0-0-dev
+
+
+Hidraw Implementation notes
+----------------------------
+For the hidraw implementation, libudev headers and libraries are required to
+build hidapi programs.  To install libudev libraries on Ubuntu,
+and other Debian-based systems, run:
+	sudo apt-get install libudev-dev
+
+On Redhat-based systems, run the following as root:
+	yum install libudev-devel
+
+Unfortunately, the hidraw driver, which the linux version of hidapi is based
+on, contains bugs in kernel versions < 2.6.36, which the client application
+should be aware of.
+
+Bugs (hidraw implementation only):
+-----------------------------------
+On Kernel versions < 2.6.34, if your device uses numbered reports, an extra
+byte will be returned at the beginning of all reports returned from read()
+for hidraw devices. This is worked around in the libary. No action should be
+necessary in the client library.
+
+On Kernel versions < 2.6.35, reports will only be sent using a Set_Report
+transfer on the CONTROL endpoint. No data will ever be sent on an Interrupt
+Out endpoint if one exists. This is fixed in 2.6.35. In 2.6.35, OUTPUT
+reports will be sent to the device on the first INTERRUPT OUT endpoint if it
+exists; If it does not exist, OUTPUT reports will be sent on the CONTROL
+endpoint.
+
+On Kernel versions < 2.6.36, add an extra byte containing the report number
+to sent reports if numbered reports are used, and the device does not
+contain an INTERRPUT OUT endpoint for OUTPUT transfers.  For example, if
+your device uses numbered reports and wants to send {0x2 0xff 0xff 0xff} to
+the device (0x2 is the report number), you must send {0x2 0x2 0xff 0xff
+0xff}. If your device has the optional Interrupt OUT endpoint, this does not
+apply (but really on 2.6.35 only, because 2.6.34 won't use the interrupt
+out endpoint).
diff --git a/uf2-samdx1/lib/uf2/hidapi/linux/hid.c b/uf2-samdx1/lib/uf2/hidapi/linux/hid.c
new file mode 100644
index 00000000..56dac0fa
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/linux/hid.c
@@ -0,0 +1,797 @@
+/*******************************************************
+ HIDAPI - Multi-Platform library for
+ communication with HID devices.
+
+ Alan Ott
+ Signal 11 Software
+
+ 8/22/2009
+ Linux Version - 6/2/2009
+
+ Copyright 2009, All Rights Reserved.
+
+ At the discretion of the user of this library,
+ this software may be licensed under the terms of the
+ GNU General Public License v3, a BSD-Style license, or the
+ original HIDAPI license as outlined in the LICENSE.txt,
+ LICENSE-gpl3.txt, LICENSE-bsd.txt, and LICENSE-orig.txt
+ files located at the root of the source distribution.
+ These files may also be found in the public source
+ code repository located at:
+        http://github.com/signal11/hidapi .
+********************************************************/
+
+/* C */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <locale.h>
+#include <errno.h>
+
+/* Unix */
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <sys/utsname.h>
+#include <fcntl.h>
+#include <poll.h>
+
+/* Linux */
+#include <linux/hidraw.h>
+#include <linux/version.h>
+#include <linux/input.h>
+#include <libudev.h>
+
+#include "hidapi.h"
+
+/* Definitions from linux/hidraw.h. Since these are new, some distros
+   may not have header files which contain them. */
+#ifndef HIDIOCSFEATURE
+#define HIDIOCSFEATURE(len)    _IOC(_IOC_WRITE|_IOC_READ, 'H', 0x06, len)
+#endif
+#ifndef HIDIOCGFEATURE
+#define HIDIOCGFEATURE(len)    _IOC(_IOC_WRITE|_IOC_READ, 'H', 0x07, len)
+#endif
+
+
+/* USB HID device property names */
+const char *device_string_names[] = {
+	"manufacturer",
+	"product",
+	"serial",
+};
+
+/* Symbolic names for the properties above */
+enum device_string_id {
+	DEVICE_STRING_MANUFACTURER,
+	DEVICE_STRING_PRODUCT,
+	DEVICE_STRING_SERIAL,
+
+	DEVICE_STRING_COUNT,
+};
+
+struct hid_device_ {
+	int device_handle;
+	int blocking;
+	int uses_numbered_reports;
+};
+
+
+static __u32 kernel_version = 0;
+
+static __u32 detect_kernel_version(void)
+{
+	struct utsname name;
+	int major, minor, release;
+	int ret;
+
+	uname(&name);
+	ret = sscanf(name.release, "%d.%d.%d", &major, &minor, &release);
+	if (ret == 3) {
+		return KERNEL_VERSION(major, minor, release);
+	}
+
+	ret = sscanf(name.release, "%d.%d", &major, &minor);
+	if (ret == 2) {
+		return KERNEL_VERSION(major, minor, 0);
+	}
+
+	printf("Couldn't determine kernel version from version string \"%s\"\n", name.release);
+	return 0;
+}
+
+static hid_device *new_hid_device(void)
+{
+	hid_device *dev = calloc(1, sizeof(hid_device));
+	dev->device_handle = -1;
+	dev->blocking = 1;
+	dev->uses_numbered_reports = 0;
+
+	return dev;
+}
+
+
+/* The caller must free the returned string with free(). */
+static wchar_t *utf8_to_wchar_t(const char *utf8)
+{
+	wchar_t *ret = NULL;
+
+	if (utf8) {
+		size_t wlen = mbstowcs(NULL, utf8, 0);
+		if ((size_t) -1 == wlen) {
+			return wcsdup(L"");
+		}
+		ret = calloc(wlen+1, sizeof(wchar_t));
+		mbstowcs(ret, utf8, wlen+1);
+		ret[wlen] = 0x0000;
+	}
+
+	return ret;
+}
+
+/* Get an attribute value from a udev_device and return it as a whar_t
+   string. The returned string must be freed with free() when done.*/
+static wchar_t *copy_udev_string(struct udev_device *dev, const char *udev_name)
+{
+	return utf8_to_wchar_t(udev_device_get_sysattr_value(dev, udev_name));
+}
+
+/* uses_numbered_reports() returns 1 if report_descriptor describes a device
+   which contains numbered reports. */
+static int uses_numbered_reports(__u8 *report_descriptor, __u32 size) {
+	unsigned int i = 0;
+	int size_code;
+	int data_len, key_size;
+
+	while (i < size) {
+		int key = report_descriptor[i];
+
+		/* Check for the Report ID key */
+		if (key == 0x85/*Report ID*/) {
+			/* This device has a Report ID, which means it uses
+			   numbered reports. */
+			return 1;
+		}
+
+		//printf("key: %02hhx\n", key);
+
+		if ((key & 0xf0) == 0xf0) {
+			/* This is a Long Item. The next byte contains the
+			   length of the data section (value) for this key.
+			   See the HID specification, version 1.11, section
+			   6.2.2.3, titled "Long Items." */
+			if (i+1 < size)
+				data_len = report_descriptor[i+1];
+			else
+				data_len = 0; /* malformed report */
+			key_size = 3;
+		}
+		else {
+			/* This is a Short Item. The bottom two bits of the
+			   key contain the size code for the data section
+			   (value) for this key.  Refer to the HID
+			   specification, version 1.11, section 6.2.2.2,
+			   titled "Short Items." */
+			size_code = key & 0x3;
+			switch (size_code) {
+			case 0:
+			case 1:
+			case 2:
+				data_len = size_code;
+				break;
+			case 3:
+				data_len = 4;
+				break;
+			default:
+				/* Can't ever happen since size_code is & 0x3 */
+				data_len = 0;
+				break;
+			};
+			key_size = 1;
+		}
+
+		/* Skip over this key and it's associated data */
+		i += data_len + key_size;
+	}
+
+	/* Didn't find a Report ID key. Device doesn't use numbered reports. */
+	return 0;
+}
+
+/*
+ * The caller is responsible for free()ing the (newly-allocated) character
+ * strings pointed to by serial_number_utf8 and product_name_utf8 after use.
+ */
+static int
+parse_uevent_info(const char *uevent, int *bus_type,
+	unsigned short *vendor_id, unsigned short *product_id,
+	char **serial_number_utf8, char **product_name_utf8)
+{
+	char *tmp = strdup(uevent);
+	char *saveptr = NULL;
+	char *line;
+	char *key;
+	char *value;
+
+	int found_id = 0;
+	int found_serial = 0;
+	int found_name = 0;
+
+	line = strtok_r(tmp, "\n", &saveptr);
+	while (line != NULL) {
+		/* line: "KEY=value" */
+		key = line;
+		value = strchr(line, '=');
+		if (!value) {
+			goto next_line;
+		}
+		*value = '\0';
+		value++;
+
+		if (strcmp(key, "HID_ID") == 0) {
+			/**
+			 *        type vendor   product
+			 * HID_ID=0003:000005AC:00008242
+			 **/
+			int ret = sscanf(value, "%x:%hx:%hx", bus_type, vendor_id, product_id);
+			if (ret == 3) {
+				found_id = 1;
+			}
+		} else if (strcmp(key, "HID_NAME") == 0) {
+			/* The caller has to free the product name */
+			*product_name_utf8 = strdup(value);
+			found_name = 1;
+		} else if (strcmp(key, "HID_UNIQ") == 0) {
+			/* The caller has to free the serial number */
+			*serial_number_utf8 = strdup(value);
+			found_serial = 1;
+		}
+
+next_line:
+		line = strtok_r(NULL, "\n", &saveptr);
+	}
+
+	free(tmp);
+	return (found_id && found_name && found_serial);
+}
+
+
+static int get_device_string(hid_device *dev, enum device_string_id key, wchar_t *string, size_t maxlen)
+{
+	struct udev *udev;
+	struct udev_device *udev_dev, *parent, *hid_dev;
+	struct stat s;
+	int ret = -1;
+        char *serial_number_utf8 = NULL;
+        char *product_name_utf8 = NULL;
+
+	/* Create the udev object */
+	udev = udev_new();
+	if (!udev) {
+		printf("Can't create udev\n");
+		return -1;
+	}
+
+	/* Get the dev_t (major/minor numbers) from the file handle. */
+	ret = fstat(dev->device_handle, &s);
+	if (-1 == ret)
+		return ret;
+	/* Open a udev device from the dev_t. 'c' means character device. */
+	udev_dev = udev_device_new_from_devnum(udev, 'c', s.st_rdev);
+	if (udev_dev) {
+		hid_dev = udev_device_get_parent_with_subsystem_devtype(
+			udev_dev,
+			"hid",
+			NULL);
+		if (hid_dev) {
+			unsigned short dev_vid;
+			unsigned short dev_pid;
+			int bus_type;
+			size_t retm;
+
+			ret = parse_uevent_info(
+			           udev_device_get_sysattr_value(hid_dev, "uevent"),
+			           &bus_type,
+			           &dev_vid,
+			           &dev_pid,
+			           &serial_number_utf8,
+			           &product_name_utf8);
+
+			if (bus_type == BUS_BLUETOOTH) {
+				switch (key) {
+					case DEVICE_STRING_MANUFACTURER:
+						wcsncpy(string, L"", maxlen);
+						ret = 0;
+						break;
+					case DEVICE_STRING_PRODUCT:
+						retm = mbstowcs(string, product_name_utf8, maxlen);
+						ret = (retm == (size_t)-1)? -1: 0;
+						break;
+					case DEVICE_STRING_SERIAL:
+						retm = mbstowcs(string, serial_number_utf8, maxlen);
+						ret = (retm == (size_t)-1)? -1: 0;
+						break;
+					case DEVICE_STRING_COUNT:
+					default:
+						ret = -1;
+						break;
+				}
+			}
+			else {
+				/* This is a USB device. Find its parent USB Device node. */
+				parent = udev_device_get_parent_with_subsystem_devtype(
+					   udev_dev,
+					   "usb",
+					   "usb_device");
+				if (parent) {
+					const char *str;
+					const char *key_str = NULL;
+
+					if (key >= 0 && key < DEVICE_STRING_COUNT) {
+						key_str = device_string_names[key];
+					} else {
+						ret = -1;
+						goto end;
+					}
+
+					str = udev_device_get_sysattr_value(parent, key_str);
+					if (str) {
+						/* Convert the string from UTF-8 to wchar_t */
+						retm = mbstowcs(string, str, maxlen);
+						ret = (retm == (size_t)-1)? -1: 0;
+						goto end;
+					}
+				}
+			}
+		}
+	}
+
+end:
+        free(serial_number_utf8);
+        free(product_name_utf8);
+
+	udev_device_unref(udev_dev);
+	/* parent and hid_dev don't need to be (and can't be) unref'd.
+	   I'm not sure why, but they'll throw double-free() errors. */
+	udev_unref(udev);
+
+	return ret;
+}
+
+int HID_API_EXPORT hid_init(void)
+{
+	const char *locale;
+
+	/* Set the locale if it's not set. */
+	locale = setlocale(LC_CTYPE, NULL);
+	if (!locale)
+		setlocale(LC_CTYPE, "");
+
+	kernel_version = detect_kernel_version();
+
+	return 0;
+}
+
+int HID_API_EXPORT hid_exit(void)
+{
+	/* Nothing to do for this in the Linux/hidraw implementation. */
+	return 0;
+}
+
+
+struct hid_device_info  HID_API_EXPORT *hid_enumerate(unsigned short vendor_id, unsigned short product_id)
+{
+	struct udev *udev;
+	struct udev_enumerate *enumerate;
+	struct udev_list_entry *devices, *dev_list_entry;
+
+	struct hid_device_info *root = NULL; /* return object */
+	struct hid_device_info *cur_dev = NULL;
+	struct hid_device_info *prev_dev = NULL; /* previous device */
+
+	hid_init();
+
+	/* Create the udev object */
+	udev = udev_new();
+	if (!udev) {
+		printf("Can't create udev\n");
+		return NULL;
+	}
+
+	/* Create a list of the devices in the 'hidraw' subsystem. */
+	enumerate = udev_enumerate_new(udev);
+	udev_enumerate_add_match_subsystem(enumerate, "hidraw");
+	udev_enumerate_scan_devices(enumerate);
+	devices = udev_enumerate_get_list_entry(enumerate);
+	/* For each item, see if it matches the vid/pid, and if so
+	   create a udev_device record for it */
+	udev_list_entry_foreach(dev_list_entry, devices) {
+		const char *sysfs_path;
+		const char *dev_path;
+		const char *str;
+		struct udev_device *raw_dev; /* The device's hidraw udev node. */
+		struct udev_device *hid_dev; /* The device's HID udev node. */
+		struct udev_device *usb_dev; /* The device's USB udev node. */
+		struct udev_device *intf_dev; /* The device's interface (in the USB sense). */
+		unsigned short dev_vid;
+		unsigned short dev_pid;
+		char *serial_number_utf8 = NULL;
+		char *product_name_utf8 = NULL;
+		int bus_type;
+		int result;
+
+		/* Get the filename of the /sys entry for the device
+		   and create a udev_device object (dev) representing it */
+		sysfs_path = udev_list_entry_get_name(dev_list_entry);
+		raw_dev = udev_device_new_from_syspath(udev, sysfs_path);
+		dev_path = udev_device_get_devnode(raw_dev);
+
+		hid_dev = udev_device_get_parent_with_subsystem_devtype(
+			raw_dev,
+			"hid",
+			NULL);
+
+		if (!hid_dev) {
+			/* Unable to find parent hid device. */
+			goto next;
+		}
+
+		result = parse_uevent_info(
+			udev_device_get_sysattr_value(hid_dev, "uevent"),
+			&bus_type,
+			&dev_vid,
+			&dev_pid,
+			&serial_number_utf8,
+			&product_name_utf8);
+
+		if (!result) {
+			/* parse_uevent_info() failed for at least one field. */
+			goto next;
+		}
+
+		if (bus_type != BUS_USB && bus_type != BUS_BLUETOOTH) {
+			/* We only know how to handle USB and BT devices. */
+			goto next;
+		}
+
+		/* Check the VID/PID against the arguments */
+		if ((vendor_id == 0x0 || vendor_id == dev_vid) &&
+		    (product_id == 0x0 || product_id == dev_pid)) {
+			struct hid_device_info *tmp;
+
+			/* VID/PID match. Create the record. */
+			tmp = malloc(sizeof(struct hid_device_info));
+			if (cur_dev) {
+				cur_dev->next = tmp;
+			}
+			else {
+				root = tmp;
+			}
+			prev_dev = cur_dev;
+			cur_dev = tmp;
+
+			/* Fill out the record */
+			cur_dev->next = NULL;
+			cur_dev->path = dev_path? strdup(dev_path): NULL;
+
+			/* VID/PID */
+			cur_dev->vendor_id = dev_vid;
+			cur_dev->product_id = dev_pid;
+
+			/* Serial Number */
+			cur_dev->serial_number = utf8_to_wchar_t(serial_number_utf8);
+
+			/* Release Number */
+			cur_dev->release_number = 0x0;
+
+			/* Interface Number */
+			cur_dev->interface_number = -1;
+
+			switch (bus_type) {
+				case BUS_USB:
+					/* The device pointed to by raw_dev contains information about
+					   the hidraw device. In order to get information about the
+					   USB device, get the parent device with the
+					   subsystem/devtype pair of "usb"/"usb_device". This will
+					   be several levels up the tree, but the function will find
+					   it. */
+					usb_dev = udev_device_get_parent_with_subsystem_devtype(
+							raw_dev,
+							"usb",
+							"usb_device");
+
+					if (!usb_dev) {
+						/* Free this device */
+						free(cur_dev->serial_number);
+						free(cur_dev->path);
+						free(cur_dev);
+
+						/* Take it off the device list. */
+						if (prev_dev) {
+							prev_dev->next = NULL;
+							cur_dev = prev_dev;
+						}
+						else {
+							cur_dev = root = NULL;
+						}
+
+						goto next;
+					}
+
+					/* Manufacturer and Product strings */
+					cur_dev->manufacturer_string = copy_udev_string(usb_dev, device_string_names[DEVICE_STRING_MANUFACTURER]);
+					cur_dev->product_string = copy_udev_string(usb_dev, device_string_names[DEVICE_STRING_PRODUCT]);
+
+					/* Release Number */
+					str = udev_device_get_sysattr_value(usb_dev, "bcdDevice");
+					cur_dev->release_number = (str)? strtol(str, NULL, 16): 0x0;
+
+					/* Get a handle to the interface's udev node. */
+					intf_dev = udev_device_get_parent_with_subsystem_devtype(
+							raw_dev,
+							"usb",
+							"usb_interface");
+					if (intf_dev) {
+						str = udev_device_get_sysattr_value(intf_dev, "bInterfaceNumber");
+						cur_dev->interface_number = (str)? strtol(str, NULL, 16): -1;
+					}
+
+					break;
+
+				case BUS_BLUETOOTH:
+					/* Manufacturer and Product strings */
+					cur_dev->manufacturer_string = wcsdup(L"");
+					cur_dev->product_string = utf8_to_wchar_t(product_name_utf8);
+
+					break;
+
+				default:
+					/* Unknown device type - this should never happen, as we
+					 * check for USB and Bluetooth devices above */
+					break;
+			}
+		}
+
+	next:
+		free(serial_number_utf8);
+		free(product_name_utf8);
+		udev_device_unref(raw_dev);
+		/* hid_dev, usb_dev and intf_dev don't need to be (and can't be)
+		   unref()d.  It will cause a double-free() error.  I'm not
+		   sure why.  */
+	}
+	/* Free the enumerator and udev objects. */
+	udev_enumerate_unref(enumerate);
+	udev_unref(udev);
+
+	return root;
+}
+
+void  HID_API_EXPORT hid_free_enumeration(struct hid_device_info *devs)
+{
+	struct hid_device_info *d = devs;
+	while (d) {
+		struct hid_device_info *next = d->next;
+		free(d->path);
+		free(d->serial_number);
+		free(d->manufacturer_string);
+		free(d->product_string);
+		free(d);
+		d = next;
+	}
+}
+
+hid_device * hid_open(unsigned short vendor_id, unsigned short product_id, const wchar_t *serial_number)
+{
+	struct hid_device_info *devs, *cur_dev;
+	const char *path_to_open = NULL;
+	hid_device *handle = NULL;
+
+	devs = hid_enumerate(vendor_id, product_id);
+	cur_dev = devs;
+	while (cur_dev) {
+		if (cur_dev->vendor_id == vendor_id &&
+		    cur_dev->product_id == product_id) {
+			if (serial_number) {
+				if (wcscmp(serial_number, cur_dev->serial_number) == 0) {
+					path_to_open = cur_dev->path;
+					break;
+				}
+			}
+			else {
+				path_to_open = cur_dev->path;
+				break;
+			}
+		}
+		cur_dev = cur_dev->next;
+	}
+
+	if (path_to_open) {
+		/* Open the device */
+		handle = hid_open_path(path_to_open);
+	}
+
+	hid_free_enumeration(devs);
+
+	return handle;
+}
+
+hid_device * HID_API_EXPORT hid_open_path(const char *path)
+{
+	hid_device *dev = NULL;
+
+	hid_init();
+
+	dev = new_hid_device();
+
+	/* OPEN HERE */
+	dev->device_handle = open(path, O_RDWR);
+
+	/* If we have a good handle, return it. */
+	if (dev->device_handle > 0) {
+
+		/* Get the report descriptor */
+		int res, desc_size = 0;
+		struct hidraw_report_descriptor rpt_desc;
+
+		memset(&rpt_desc, 0x0, sizeof(rpt_desc));
+
+		/* Get Report Descriptor Size */
+		res = ioctl(dev->device_handle, HIDIOCGRDESCSIZE, &desc_size);
+		if (res < 0)
+			perror("HIDIOCGRDESCSIZE");
+
+
+		/* Get Report Descriptor */
+		rpt_desc.size = desc_size;
+		res = ioctl(dev->device_handle, HIDIOCGRDESC, &rpt_desc);
+		if (res < 0) {
+			perror("HIDIOCGRDESC");
+		} else {
+			/* Determine if this device uses numbered reports. */
+			dev->uses_numbered_reports =
+				uses_numbered_reports(rpt_desc.value,
+				                      rpt_desc.size);
+		}
+
+		return dev;
+	}
+	else {
+		/* Unable to open any devices. */
+		free(dev);
+		return NULL;
+	}
+}
+
+
+int HID_API_EXPORT hid_write(hid_device *dev, const unsigned char *data, size_t length)
+{
+	int bytes_written;
+
+	bytes_written = write(dev->device_handle, data, length);
+
+	return bytes_written;
+}
+
+
+int HID_API_EXPORT hid_read_timeout(hid_device *dev, unsigned char *data, size_t length, int milliseconds)
+{
+	int bytes_read;
+
+	if (milliseconds >= 0) {
+		/* Milliseconds is either 0 (non-blocking) or > 0 (contains
+		   a valid timeout). In both cases we want to call poll()
+		   and wait for data to arrive.  Don't rely on non-blocking
+		   operation (O_NONBLOCK) since some kernels don't seem to
+		   properly report device disconnection through read() when
+		   in non-blocking mode.  */
+		int ret;
+		struct pollfd fds;
+
+		fds.fd = dev->device_handle;
+		fds.events = POLLIN;
+		fds.revents = 0;
+		ret = poll(&fds, 1, milliseconds);
+		if (ret == -1 || ret == 0) {
+			/* Error or timeout */
+			return ret;
+		}
+		else {
+			/* Check for errors on the file descriptor. This will
+			   indicate a device disconnection. */
+			if (fds.revents & (POLLERR | POLLHUP | POLLNVAL))
+				return -1;
+		}
+	}
+
+	bytes_read = read(dev->device_handle, data, length);
+	if (bytes_read < 0 && (errno == EAGAIN || errno == EINPROGRESS))
+		bytes_read = 0;
+
+	if (bytes_read >= 0 &&
+	    kernel_version != 0 &&
+	    kernel_version < KERNEL_VERSION(2,6,34) &&
+	    dev->uses_numbered_reports) {
+		/* Work around a kernel bug. Chop off the first byte. */
+		memmove(data, data+1, bytes_read);
+		bytes_read--;
+	}
+
+	return bytes_read;
+}
+
+int HID_API_EXPORT hid_read(hid_device *dev, unsigned char *data, size_t length)
+{
+	return hid_read_timeout(dev, data, length, (dev->blocking)? -1: 0);
+}
+
+int HID_API_EXPORT hid_set_nonblocking(hid_device *dev, int nonblock)
+{
+	/* Do all non-blocking in userspace using poll(), since it looks
+	   like there's a bug in the kernel in some versions where
+	   read() will not return -1 on disconnection of the USB device */
+
+	dev->blocking = !nonblock;
+	return 0; /* Success */
+}
+
+
+int HID_API_EXPORT hid_send_feature_report(hid_device *dev, const unsigned char *data, size_t length)
+{
+	int res;
+
+	res = ioctl(dev->device_handle, HIDIOCSFEATURE(length), data);
+	if (res < 0)
+		perror("ioctl (SFEATURE)");
+
+	return res;
+}
+
+int HID_API_EXPORT hid_get_feature_report(hid_device *dev, unsigned char *data, size_t length)
+{
+	int res;
+
+	res = ioctl(dev->device_handle, HIDIOCGFEATURE(length), data);
+	if (res < 0)
+		perror("ioctl (GFEATURE)");
+
+
+	return res;
+}
+
+
+void HID_API_EXPORT hid_close(hid_device *dev)
+{
+	if (!dev)
+		return;
+	close(dev->device_handle);
+	free(dev);
+}
+
+
+int HID_API_EXPORT_CALL hid_get_manufacturer_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	return get_device_string(dev, DEVICE_STRING_MANUFACTURER, string, maxlen);
+}
+
+int HID_API_EXPORT_CALL hid_get_product_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	return get_device_string(dev, DEVICE_STRING_PRODUCT, string, maxlen);
+}
+
+int HID_API_EXPORT_CALL hid_get_serial_number_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	return get_device_string(dev, DEVICE_STRING_SERIAL, string, maxlen);
+}
+
+int HID_API_EXPORT_CALL hid_get_indexed_string(hid_device *dev, int string_index, wchar_t *string, size_t maxlen)
+{
+	return -1;
+}
+
+
+HID_API_EXPORT const wchar_t * HID_API_CALL  hid_error(hid_device *dev)
+{
+	return NULL;
+}
diff --git a/uf2-samdx1/lib/uf2/hidapi/m4/.gitignore b/uf2-samdx1/lib/uf2/hidapi/m4/.gitignore
new file mode 100644
index 00000000..8f79b020
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/m4/.gitignore
@@ -0,0 +1,5 @@
+# Ignore All, except pkg.m4, and of course this file.
+*
+!.gitignore
+!pkg.m4
+!ax_pthread.m4
diff --git a/uf2-samdx1/lib/uf2/hidapi/m4/ax_pthread.m4 b/uf2-samdx1/lib/uf2/hidapi/m4/ax_pthread.m4
new file mode 100644
index 00000000..d90de34d
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/m4/ax_pthread.m4
@@ -0,0 +1,309 @@
+# ===========================================================================
+#        http://www.gnu.org/software/autoconf-archive/ax_pthread.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_PTHREAD([ACTION-IF-FOUND[, ACTION-IF-NOT-FOUND]])
+#
+# DESCRIPTION
+#
+#   This macro figures out how to build C programs using POSIX threads. It
+#   sets the PTHREAD_LIBS output variable to the threads library and linker
+#   flags, and the PTHREAD_CFLAGS output variable to any special C compiler
+#   flags that are needed. (The user can also force certain compiler
+#   flags/libs to be tested by setting these environment variables.)
+#
+#   Also sets PTHREAD_CC to any special C compiler that is needed for
+#   multi-threaded programs (defaults to the value of CC otherwise). (This
+#   is necessary on AIX to use the special cc_r compiler alias.)
+#
+#   NOTE: You are assumed to not only compile your program with these flags,
+#   but also link it with them as well. e.g. you should link with
+#   $PTHREAD_CC $CFLAGS $PTHREAD_CFLAGS $LDFLAGS ... $PTHREAD_LIBS $LIBS
+#
+#   If you are only building threads programs, you may wish to use these
+#   variables in your default LIBS, CFLAGS, and CC:
+#
+#     LIBS="$PTHREAD_LIBS $LIBS"
+#     CFLAGS="$CFLAGS $PTHREAD_CFLAGS"
+#     CC="$PTHREAD_CC"
+#
+#   In addition, if the PTHREAD_CREATE_JOINABLE thread-attribute constant
+#   has a nonstandard name, defines PTHREAD_CREATE_JOINABLE to that name
+#   (e.g. PTHREAD_CREATE_UNDETACHED on AIX).
+#
+#   Also HAVE_PTHREAD_PRIO_INHERIT is defined if pthread is found and the
+#   PTHREAD_PRIO_INHERIT symbol is defined when compiling with
+#   PTHREAD_CFLAGS.
+#
+#   ACTION-IF-FOUND is a list of shell commands to run if a threads library
+#   is found, and ACTION-IF-NOT-FOUND is a list of commands to run it if it
+#   is not found. If ACTION-IF-FOUND is not specified, the default action
+#   will define HAVE_PTHREAD.
+#
+#   Please let the authors know if this macro fails on any platform, or if
+#   you have any other suggestions or comments. This macro was based on work
+#   by SGJ on autoconf scripts for FFTW (http://www.fftw.org/) (with help
+#   from M. Frigo), as well as ac_pthread and hb_pthread macros posted by
+#   Alejandro Forero Cuervo to the autoconf macro repository. We are also
+#   grateful for the helpful feedback of numerous users.
+#
+#   Updated for Autoconf 2.68 by Daniel Richard G.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Steven G. Johnson <stevenj@alum.mit.edu>
+#   Copyright (c) 2011 Daniel Richard G. <skunk@iSKUNK.ORG>
+#
+#   This program is free software: you can redistribute it and/or modify it
+#   under the terms of the GNU General Public License as published by the
+#   Free Software Foundation, either version 3 of the License, or (at your
+#   option) any later version.
+#
+#   This program is distributed in the hope that it will be useful, but
+#   WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+#   Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License along
+#   with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#   As a special exception, the respective Autoconf Macro's copyright owner
+#   gives unlimited permission to copy, distribute and modify the configure
+#   scripts that are the output of Autoconf when processing the Macro. You
+#   need not follow the terms of the GNU General Public License when using
+#   or distributing such scripts, even though portions of the text of the
+#   Macro appear in them. The GNU General Public License (GPL) does govern
+#   all other use of the material that constitutes the Autoconf Macro.
+#
+#   This special exception to the GPL applies to versions of the Autoconf
+#   Macro released by the Autoconf Archive. When you make and distribute a
+#   modified version of the Autoconf Macro, you may extend this special
+#   exception to the GPL to apply to your modified version as well.
+
+#serial 18
+
+AU_ALIAS([ACX_PTHREAD], [AX_PTHREAD])
+AC_DEFUN([AX_PTHREAD], [
+AC_REQUIRE([AC_CANONICAL_HOST])
+AC_LANG_PUSH([C])
+ax_pthread_ok=no
+
+# We used to check for pthread.h first, but this fails if pthread.h
+# requires special compiler flags (e.g. on True64 or Sequent).
+# It gets checked for in the link test anyway.
+
+# First of all, check if the user has set any of the PTHREAD_LIBS,
+# etcetera environment variables, and if threads linking works using
+# them:
+if test x"$PTHREAD_LIBS$PTHREAD_CFLAGS" != x; then
+        save_CFLAGS="$CFLAGS"
+        CFLAGS="$CFLAGS $PTHREAD_CFLAGS"
+        save_LIBS="$LIBS"
+        LIBS="$PTHREAD_LIBS $LIBS"
+        AC_MSG_CHECKING([for pthread_join in LIBS=$PTHREAD_LIBS with CFLAGS=$PTHREAD_CFLAGS])
+        AC_TRY_LINK_FUNC(pthread_join, ax_pthread_ok=yes)
+        AC_MSG_RESULT($ax_pthread_ok)
+        if test x"$ax_pthread_ok" = xno; then
+                PTHREAD_LIBS=""
+                PTHREAD_CFLAGS=""
+        fi
+        LIBS="$save_LIBS"
+        CFLAGS="$save_CFLAGS"
+fi
+
+# We must check for the threads library under a number of different
+# names; the ordering is very important because some systems
+# (e.g. DEC) have both -lpthread and -lpthreads, where one of the
+# libraries is broken (non-POSIX).
+
+# Create a list of thread flags to try.  Items starting with a "-" are
+# C compiler flags, and other items are library names, except for "none"
+# which indicates that we try without any flags at all, and "pthread-config"
+# which is a program returning the flags for the Pth emulation library.
+
+ax_pthread_flags="pthreads none -Kthread -kthread lthread -pthread -pthreads -mthreads pthread --thread-safe -mt pthread-config"
+
+# The ordering *is* (sometimes) important.  Some notes on the
+# individual items follow:
+
+# pthreads: AIX (must check this before -lpthread)
+# none: in case threads are in libc; should be tried before -Kthread and
+#       other compiler flags to prevent continual compiler warnings
+# -Kthread: Sequent (threads in libc, but -Kthread needed for pthread.h)
+# -kthread: FreeBSD kernel threads (preferred to -pthread since SMP-able)
+# lthread: LinuxThreads port on FreeBSD (also preferred to -pthread)
+# -pthread: Linux/gcc (kernel threads), BSD/gcc (userland threads)
+# -pthreads: Solaris/gcc
+# -mthreads: Mingw32/gcc, Lynx/gcc
+# -mt: Sun Workshop C (may only link SunOS threads [-lthread], but it
+#      doesn't hurt to check since this sometimes defines pthreads too;
+#      also defines -D_REENTRANT)
+#      ... -mt is also the pthreads flag for HP/aCC
+# pthread: Linux, etcetera
+# --thread-safe: KAI C++
+# pthread-config: use pthread-config program (for GNU Pth library)
+
+case ${host_os} in
+        solaris*)
+
+        # On Solaris (at least, for some versions), libc contains stubbed
+        # (non-functional) versions of the pthreads routines, so link-based
+        # tests will erroneously succeed.  (We need to link with -pthreads/-mt/
+        # -lpthread.)  (The stubs are missing pthread_cleanup_push, or rather
+        # a function called by this macro, so we could check for that, but
+        # who knows whether they'll stub that too in a future libc.)  So,
+        # we'll just look for -pthreads and -lpthread first:
+
+        ax_pthread_flags="-pthreads pthread -mt -pthread $ax_pthread_flags"
+        ;;
+
+        darwin*)
+        ax_pthread_flags="-pthread $ax_pthread_flags"
+        ;;
+esac
+
+if test x"$ax_pthread_ok" = xno; then
+for flag in $ax_pthread_flags; do
+
+        case $flag in
+                none)
+                AC_MSG_CHECKING([whether pthreads work without any flags])
+                ;;
+
+                -*)
+                AC_MSG_CHECKING([whether pthreads work with $flag])
+                PTHREAD_CFLAGS="$flag"
+                ;;
+
+                pthread-config)
+                AC_CHECK_PROG(ax_pthread_config, pthread-config, yes, no)
+                if test x"$ax_pthread_config" = xno; then continue; fi
+                PTHREAD_CFLAGS="`pthread-config --cflags`"
+                PTHREAD_LIBS="`pthread-config --ldflags` `pthread-config --libs`"
+                ;;
+
+                *)
+                AC_MSG_CHECKING([for the pthreads library -l$flag])
+                PTHREAD_LIBS="-l$flag"
+                ;;
+        esac
+
+        save_LIBS="$LIBS"
+        save_CFLAGS="$CFLAGS"
+        LIBS="$PTHREAD_LIBS $LIBS"
+        CFLAGS="$CFLAGS $PTHREAD_CFLAGS"
+
+        # Check for various functions.  We must include pthread.h,
+        # since some functions may be macros.  (On the Sequent, we
+        # need a special flag -Kthread to make this header compile.)
+        # We check for pthread_join because it is in -lpthread on IRIX
+        # while pthread_create is in libc.  We check for pthread_attr_init
+        # due to DEC craziness with -lpthreads.  We check for
+        # pthread_cleanup_push because it is one of the few pthread
+        # functions on Solaris that doesn't have a non-functional libc stub.
+        # We try pthread_create on general principles.
+        AC_LINK_IFELSE([AC_LANG_PROGRAM([#include <pthread.h>
+                        static void routine(void *a) { a = 0; }
+                        static void *start_routine(void *a) { return a; }],
+                       [pthread_t th; pthread_attr_t attr;
+                        pthread_create(&th, 0, start_routine, 0);
+                        pthread_join(th, 0);
+                        pthread_attr_init(&attr);
+                        pthread_cleanup_push(routine, 0);
+                        pthread_cleanup_pop(0) /* ; */])],
+                [ax_pthread_ok=yes],
+                [])
+
+        LIBS="$save_LIBS"
+        CFLAGS="$save_CFLAGS"
+
+        AC_MSG_RESULT($ax_pthread_ok)
+        if test "x$ax_pthread_ok" = xyes; then
+                break;
+        fi
+
+        PTHREAD_LIBS=""
+        PTHREAD_CFLAGS=""
+done
+fi
+
+# Various other checks:
+if test "x$ax_pthread_ok" = xyes; then
+        save_LIBS="$LIBS"
+        LIBS="$PTHREAD_LIBS $LIBS"
+        save_CFLAGS="$CFLAGS"
+        CFLAGS="$CFLAGS $PTHREAD_CFLAGS"
+
+        # Detect AIX lossage: JOINABLE attribute is called UNDETACHED.
+        AC_MSG_CHECKING([for joinable pthread attribute])
+        attr_name=unknown
+        for attr in PTHREAD_CREATE_JOINABLE PTHREAD_CREATE_UNDETACHED; do
+            AC_LINK_IFELSE([AC_LANG_PROGRAM([#include <pthread.h>],
+                           [int attr = $attr; return attr /* ; */])],
+                [attr_name=$attr; break],
+                [])
+        done
+        AC_MSG_RESULT($attr_name)
+        if test "$attr_name" != PTHREAD_CREATE_JOINABLE; then
+            AC_DEFINE_UNQUOTED(PTHREAD_CREATE_JOINABLE, $attr_name,
+                               [Define to necessary symbol if this constant
+                                uses a non-standard name on your system.])
+        fi
+
+        AC_MSG_CHECKING([if more special flags are required for pthreads])
+        flag=no
+        case ${host_os} in
+            aix* | freebsd* | darwin*) flag="-D_THREAD_SAFE";;
+            osf* | hpux*) flag="-D_REENTRANT";;
+            solaris*)
+            if test "$GCC" = "yes"; then
+                flag="-D_REENTRANT"
+            else
+                flag="-mt -D_REENTRANT"
+            fi
+            ;;
+        esac
+        AC_MSG_RESULT(${flag})
+        if test "x$flag" != xno; then
+            PTHREAD_CFLAGS="$flag $PTHREAD_CFLAGS"
+        fi
+
+        AC_CACHE_CHECK([for PTHREAD_PRIO_INHERIT],
+            ax_cv_PTHREAD_PRIO_INHERIT, [
+                AC_LINK_IFELSE([
+                    AC_LANG_PROGRAM([[#include <pthread.h>]], [[int i = PTHREAD_PRIO_INHERIT;]])],
+                    [ax_cv_PTHREAD_PRIO_INHERIT=yes],
+                    [ax_cv_PTHREAD_PRIO_INHERIT=no])
+            ])
+        AS_IF([test "x$ax_cv_PTHREAD_PRIO_INHERIT" = "xyes"],
+            AC_DEFINE([HAVE_PTHREAD_PRIO_INHERIT], 1, [Have PTHREAD_PRIO_INHERIT.]))
+
+        LIBS="$save_LIBS"
+        CFLAGS="$save_CFLAGS"
+
+        # More AIX lossage: must compile with xlc_r or cc_r
+        if test x"$GCC" != xyes; then
+          AC_CHECK_PROGS(PTHREAD_CC, xlc_r cc_r, ${CC})
+        else
+          PTHREAD_CC=$CC
+        fi
+else
+        PTHREAD_CC="$CC"
+fi
+
+AC_SUBST(PTHREAD_LIBS)
+AC_SUBST(PTHREAD_CFLAGS)
+AC_SUBST(PTHREAD_CC)
+
+# Finally, execute ACTION-IF-FOUND/ACTION-IF-NOT-FOUND:
+if test x"$ax_pthread_ok" = xyes; then
+        ifelse([$1],,AC_DEFINE(HAVE_PTHREAD,1,[Define if you have POSIX threads libraries and header files.]),[$1])
+        :
+else
+        ax_pthread_ok=no
+        $2
+fi
+AC_LANG_POP
+])dnl AX_PTHREAD
diff --git a/uf2-samdx1/lib/uf2/hidapi/m4/pkg.m4 b/uf2-samdx1/lib/uf2/hidapi/m4/pkg.m4
new file mode 100644
index 00000000..0048a3fa
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/m4/pkg.m4
@@ -0,0 +1,157 @@
+# pkg.m4 - Macros to locate and utilise pkg-config.            -*- Autoconf -*-
+# 
+# Copyright © 2004 Scott James Remnant <scott@netsplit.com>.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that program.
+
+# PKG_PROG_PKG_CONFIG([MIN-VERSION])
+# ----------------------------------
+AC_DEFUN([PKG_PROG_PKG_CONFIG],
+[m4_pattern_forbid([^_?PKG_[A-Z_]+$])
+m4_pattern_allow([^PKG_CONFIG(_PATH)?$])
+AC_ARG_VAR([PKG_CONFIG], [path to pkg-config utility])dnl
+if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then
+	AC_PATH_TOOL([PKG_CONFIG], [pkg-config])
+fi
+if test -n "$PKG_CONFIG"; then
+	_pkg_min_version=m4_default([$1], [0.9.0])
+	AC_MSG_CHECKING([pkg-config is at least version $_pkg_min_version])
+	if $PKG_CONFIG --atleast-pkgconfig-version $_pkg_min_version; then
+		AC_MSG_RESULT([yes])
+	else
+		AC_MSG_RESULT([no])
+		PKG_CONFIG=""
+	fi
+		
+fi[]dnl
+])# PKG_PROG_PKG_CONFIG
+
+# PKG_CHECK_EXISTS(MODULES, [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND])
+#
+# Check to see whether a particular set of modules exists.  Similar
+# to PKG_CHECK_MODULES(), but does not set variables or print errors.
+#
+#
+# Similar to PKG_CHECK_MODULES, make sure that the first instance of
+# this or PKG_CHECK_MODULES is called, or make sure to call
+# PKG_CHECK_EXISTS manually
+# --------------------------------------------------------------
+AC_DEFUN([PKG_CHECK_EXISTS],
+[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
+if test -n "$PKG_CONFIG" && \
+    AC_RUN_LOG([$PKG_CONFIG --exists --print-errors "$1"]); then
+  m4_ifval([$2], [$2], [:])
+m4_ifvaln([$3], [else
+  $3])dnl
+fi])
+
+
+# _PKG_CONFIG([VARIABLE], [COMMAND], [MODULES])
+# ---------------------------------------------
+m4_define([_PKG_CONFIG],
+[if test -n "$PKG_CONFIG"; then
+    if test -n "$$1"; then
+        pkg_cv_[]$1="$$1"
+    else
+        PKG_CHECK_EXISTS([$3],
+                         [pkg_cv_[]$1=`$PKG_CONFIG --[]$2 "$3" 2>/dev/null`],
+			 [pkg_failed=yes])
+    fi
+else
+	pkg_failed=untried
+fi[]dnl
+])# _PKG_CONFIG
+
+# _PKG_SHORT_ERRORS_SUPPORTED
+# -----------------------------
+AC_DEFUN([_PKG_SHORT_ERRORS_SUPPORTED],
+[AC_REQUIRE([PKG_PROG_PKG_CONFIG])
+if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then
+        _pkg_short_errors_supported=yes
+else
+        _pkg_short_errors_supported=no
+fi[]dnl
+])# _PKG_SHORT_ERRORS_SUPPORTED
+
+
+# PKG_CHECK_MODULES(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND],
+# [ACTION-IF-NOT-FOUND])
+#
+#
+# Note that if there is a possibility the first call to
+# PKG_CHECK_MODULES might not happen, you should be sure to include an
+# explicit call to PKG_PROG_PKG_CONFIG in your configure.ac
+#
+#
+# --------------------------------------------------------------
+AC_DEFUN([PKG_CHECK_MODULES],
+[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
+AC_ARG_VAR([$1][_CFLAGS], [C compiler flags for $1, overriding pkg-config])dnl
+AC_ARG_VAR([$1][_LIBS], [linker flags for $1, overriding pkg-config])dnl
+
+pkg_failed=no
+AC_MSG_CHECKING([for $1])
+
+_PKG_CONFIG([$1][_CFLAGS], [cflags], [$2])
+_PKG_CONFIG([$1][_LIBS], [libs], [$2])
+
+m4_define([_PKG_TEXT], [Alternatively, you may set the environment variables $1[]_CFLAGS
+and $1[]_LIBS to avoid the need to call pkg-config.
+See the pkg-config man page for more details.])
+
+if test $pkg_failed = yes; then
+        _PKG_SHORT_ERRORS_SUPPORTED
+        if test $_pkg_short_errors_supported = yes; then
+	        $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --errors-to-stdout --print-errors "$2"`
+        else 
+	        $1[]_PKG_ERRORS=`$PKG_CONFIG --errors-to-stdout --print-errors "$2"`
+        fi
+	# Put the nasty error message in config.log where it belongs
+	echo "$$1[]_PKG_ERRORS" >&AS_MESSAGE_LOG_FD
+
+	ifelse([$4], , [AC_MSG_ERROR(dnl
+[Package requirements ($2) were not met:
+
+$$1_PKG_ERRORS
+
+Consider adjusting the PKG_CONFIG_PATH environment variable if you
+installed software in a non-standard prefix.
+
+_PKG_TEXT
+])],
+		[AC_MSG_RESULT([no])
+                $4])
+elif test $pkg_failed = untried; then
+	ifelse([$4], , [AC_MSG_FAILURE(dnl
+[The pkg-config script could not be found or is too old.  Make sure it
+is in your PATH or set the PKG_CONFIG environment variable to the full
+path to pkg-config.
+
+_PKG_TEXT
+
+To get pkg-config, see <http://pkg-config.freedesktop.org/>.])],
+		[$4])
+else
+	$1[]_CFLAGS=$pkg_cv_[]$1[]_CFLAGS
+	$1[]_LIBS=$pkg_cv_[]$1[]_LIBS
+        AC_MSG_RESULT([yes])
+	ifelse([$3], , :, [$3])
+fi[]dnl
+])# PKG_CHECK_MODULES
diff --git a/uf2-samdx1/lib/uf2/hidapi/mac/.gitignore b/uf2-samdx1/lib/uf2/hidapi/mac/.gitignore
new file mode 100644
index 00000000..7cc3f0d0
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/mac/.gitignore
@@ -0,0 +1,17 @@
+Debug
+Release
+*.exp
+*.ilk
+*.lib
+*.suo
+*.vcproj.*
+*.ncb
+*.suo
+*.dll
+*.pdb
+*.o
+hidapi-hidtest
+.deps
+.libs
+*.la
+*.lo
diff --git a/uf2-samdx1/lib/uf2/hidapi/mac/Makefile-manual b/uf2-samdx1/lib/uf2/hidapi/mac/Makefile-manual
new file mode 100644
index 00000000..5399b5a7
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/mac/Makefile-manual
@@ -0,0 +1,32 @@
+###########################################
+# Simple Makefile for HIDAPI test program
+#
+# Alan Ott
+# Signal 11 Software
+# 2010-07-03
+###########################################
+
+all: hidtest
+
+CC=gcc
+CXX=g++
+COBJS=hid.o
+CPPOBJS=../hidtest/hidtest.o
+OBJS=$(COBJS) $(CPPOBJS)
+CFLAGS+=-I../hidapi -Wall -g -c 
+LIBS=-framework IOKit -framework CoreFoundation
+
+
+hidtest: $(OBJS)
+	g++ -Wall -g $^ $(LIBS) -o hidtest
+
+$(COBJS): %.o: %.c
+	$(CC) $(CFLAGS) $< -o $@
+
+$(CPPOBJS): %.o: %.cpp
+	$(CXX) $(CFLAGS) $< -o $@
+
+clean:
+	rm -f *.o hidtest $(CPPOBJS)
+
+.PHONY: clean
diff --git a/uf2-samdx1/lib/uf2/hidapi/mac/Makefile.am b/uf2-samdx1/lib/uf2/hidapi/mac/Makefile.am
new file mode 100644
index 00000000..23d96e08
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/mac/Makefile.am
@@ -0,0 +1,9 @@
+lib_LTLIBRARIES = libhidapi.la
+libhidapi_la_SOURCES = hid.c
+libhidapi_la_LDFLAGS = $(LTLDFLAGS)
+AM_CPPFLAGS = -I$(top_srcdir)/hidapi/
+
+hdrdir = $(includedir)/hidapi
+hdr_HEADERS = $(top_srcdir)/hidapi/hidapi.h
+
+EXTRA_DIST = Makefile-manual
diff --git a/uf2-samdx1/lib/uf2/hidapi/mac/hid.c b/uf2-samdx1/lib/uf2/hidapi/mac/hid.c
new file mode 100644
index 00000000..e0756a15
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/mac/hid.c
@@ -0,0 +1,1110 @@
+/*******************************************************
+ HIDAPI - Multi-Platform library for
+ communication with HID devices.
+
+ Alan Ott
+ Signal 11 Software
+
+ 2010-07-03
+
+ Copyright 2010, All Rights Reserved.
+
+ At the discretion of the user of this library,
+ this software may be licensed under the terms of the
+ GNU General Public License v3, a BSD-Style license, or the
+ original HIDAPI license as outlined in the LICENSE.txt,
+ LICENSE-gpl3.txt, LICENSE-bsd.txt, and LICENSE-orig.txt
+ files located at the root of the source distribution.
+ These files may also be found in the public source
+ code repository located at:
+        http://github.com/signal11/hidapi .
+********************************************************/
+
+/* See Apple Technical Note TN2187 for details on IOHidManager. */
+
+#include <IOKit/hid/IOHIDManager.h>
+#include <IOKit/hid/IOHIDKeys.h>
+#include <IOKit/IOKitLib.h>
+#include <CoreFoundation/CoreFoundation.h>
+#include <wchar.h>
+#include <locale.h>
+#include <pthread.h>
+#include <sys/time.h>
+#include <unistd.h>
+#include <dlfcn.h>
+
+#include "hidapi.h"
+
+/* Barrier implementation because Mac OSX doesn't have pthread_barrier.
+   It also doesn't have clock_gettime(). So much for POSIX and SUSv2.
+   This implementation came from Brent Priddy and was posted on
+   StackOverflow. It is used with his permission. */
+typedef int pthread_barrierattr_t;
+typedef struct pthread_barrier {
+    pthread_mutex_t mutex;
+    pthread_cond_t cond;
+    int count;
+    int trip_count;
+} pthread_barrier_t;
+
+static int pthread_barrier_init(pthread_barrier_t *barrier, const pthread_barrierattr_t *attr, unsigned int count)
+{
+	if(count == 0) {
+		errno = EINVAL;
+		return -1;
+	}
+
+	if(pthread_mutex_init(&barrier->mutex, 0) < 0) {
+		return -1;
+	}
+	if(pthread_cond_init(&barrier->cond, 0) < 0) {
+		pthread_mutex_destroy(&barrier->mutex);
+		return -1;
+	}
+	barrier->trip_count = count;
+	barrier->count = 0;
+
+	return 0;
+}
+
+static int pthread_barrier_destroy(pthread_barrier_t *barrier)
+{
+	pthread_cond_destroy(&barrier->cond);
+	pthread_mutex_destroy(&barrier->mutex);
+	return 0;
+}
+
+static int pthread_barrier_wait(pthread_barrier_t *barrier)
+{
+	pthread_mutex_lock(&barrier->mutex);
+	++(barrier->count);
+	if(barrier->count >= barrier->trip_count)
+	{
+		barrier->count = 0;
+		pthread_cond_broadcast(&barrier->cond);
+		pthread_mutex_unlock(&barrier->mutex);
+		return 1;
+	}
+	else
+	{
+		pthread_cond_wait(&barrier->cond, &(barrier->mutex));
+		pthread_mutex_unlock(&barrier->mutex);
+		return 0;
+	}
+}
+
+static int return_data(hid_device *dev, unsigned char *data, size_t length);
+
+/* Linked List of input reports received from the device. */
+struct input_report {
+	uint8_t *data;
+	size_t len;
+	struct input_report *next;
+};
+
+struct hid_device_ {
+	IOHIDDeviceRef device_handle;
+	int blocking;
+	int uses_numbered_reports;
+	int disconnected;
+	CFStringRef run_loop_mode;
+	CFRunLoopRef run_loop;
+	CFRunLoopSourceRef source;
+	uint8_t *input_report_buf;
+	CFIndex max_input_report_len;
+	struct input_report *input_reports;
+
+	pthread_t thread;
+	pthread_mutex_t mutex; /* Protects input_reports */
+	pthread_cond_t condition;
+	pthread_barrier_t barrier; /* Ensures correct startup sequence */
+	pthread_barrier_t shutdown_barrier; /* Ensures correct shutdown sequence */
+	int shutdown_thread;
+};
+
+static hid_device *new_hid_device(void)
+{
+	hid_device *dev = calloc(1, sizeof(hid_device));
+	dev->device_handle = NULL;
+	dev->blocking = 1;
+	dev->uses_numbered_reports = 0;
+	dev->disconnected = 0;
+	dev->run_loop_mode = NULL;
+	dev->run_loop = NULL;
+	dev->source = NULL;
+	dev->input_report_buf = NULL;
+	dev->input_reports = NULL;
+	dev->shutdown_thread = 0;
+
+	/* Thread objects */
+	pthread_mutex_init(&dev->mutex, NULL);
+	pthread_cond_init(&dev->condition, NULL);
+	pthread_barrier_init(&dev->barrier, NULL, 2);
+	pthread_barrier_init(&dev->shutdown_barrier, NULL, 2);
+
+	return dev;
+}
+
+static void free_hid_device(hid_device *dev)
+{
+	if (!dev)
+		return;
+
+	/* Delete any input reports still left over. */
+	struct input_report *rpt = dev->input_reports;
+	while (rpt) {
+		struct input_report *next = rpt->next;
+		free(rpt->data);
+		free(rpt);
+		rpt = next;
+	}
+
+	/* Free the string and the report buffer. The check for NULL
+	   is necessary here as CFRelease() doesn't handle NULL like
+	   free() and others do. */
+	if (dev->run_loop_mode)
+		CFRelease(dev->run_loop_mode);
+	if (dev->source)
+		CFRelease(dev->source);
+	free(dev->input_report_buf);
+
+	/* Clean up the thread objects */
+	pthread_barrier_destroy(&dev->shutdown_barrier);
+	pthread_barrier_destroy(&dev->barrier);
+	pthread_cond_destroy(&dev->condition);
+	pthread_mutex_destroy(&dev->mutex);
+
+	/* Free the structure itself. */
+	free(dev);
+}
+
+static	IOHIDManagerRef hid_mgr = 0x0;
+
+
+#if 0
+static void register_error(hid_device *device, const char *op)
+{
+
+}
+#endif
+
+
+static int32_t get_int_property(IOHIDDeviceRef device, CFStringRef key)
+{
+	CFTypeRef ref;
+	int32_t value;
+
+	ref = IOHIDDeviceGetProperty(device, key);
+	if (ref) {
+		if (CFGetTypeID(ref) == CFNumberGetTypeID()) {
+			CFNumberGetValue((CFNumberRef) ref, kCFNumberSInt32Type, &value);
+			return value;
+		}
+	}
+	return 0;
+}
+
+static unsigned short get_vendor_id(IOHIDDeviceRef device)
+{
+	return get_int_property(device, CFSTR(kIOHIDVendorIDKey));
+}
+
+static unsigned short get_product_id(IOHIDDeviceRef device)
+{
+	return get_int_property(device, CFSTR(kIOHIDProductIDKey));
+}
+
+static int32_t get_max_report_length(IOHIDDeviceRef device)
+{
+	return get_int_property(device, CFSTR(kIOHIDMaxInputReportSizeKey));
+}
+
+static int get_string_property(IOHIDDeviceRef device, CFStringRef prop, wchar_t *buf, size_t len)
+{
+	CFStringRef str;
+
+	if (!len)
+		return 0;
+
+	str = IOHIDDeviceGetProperty(device, prop);
+
+	buf[0] = 0;
+
+	if (str) {
+		CFIndex str_len = CFStringGetLength(str);
+		CFRange range;
+		CFIndex used_buf_len;
+		CFIndex chars_copied;
+
+		len --;
+
+		range.location = 0;
+		range.length = ((size_t)str_len > len)? len: (size_t)str_len;
+		chars_copied = CFStringGetBytes(str,
+			range,
+			kCFStringEncodingUTF32LE,
+			(char)'?',
+			FALSE,
+			(UInt8*)buf,
+			len * sizeof(wchar_t),
+			&used_buf_len);
+
+		if (chars_copied == len)
+			buf[len] = 0; /* len is decremented above */
+		else
+			buf[chars_copied] = 0;
+
+		return 0;
+	}
+	else
+		return -1;
+
+}
+
+static int get_serial_number(IOHIDDeviceRef device, wchar_t *buf, size_t len)
+{
+	return get_string_property(device, CFSTR(kIOHIDSerialNumberKey), buf, len);
+}
+
+static int get_manufacturer_string(IOHIDDeviceRef device, wchar_t *buf, size_t len)
+{
+	return get_string_property(device, CFSTR(kIOHIDManufacturerKey), buf, len);
+}
+
+static int get_product_string(IOHIDDeviceRef device, wchar_t *buf, size_t len)
+{
+	return get_string_property(device, CFSTR(kIOHIDProductKey), buf, len);
+}
+
+
+/* Implementation of wcsdup() for Mac. */
+static wchar_t *dup_wcs(const wchar_t *s)
+{
+	size_t len = wcslen(s);
+	wchar_t *ret = malloc((len+1)*sizeof(wchar_t));
+	wcscpy(ret, s);
+
+	return ret;
+}
+
+/* hidapi_IOHIDDeviceGetService()
+ *
+ * Return the io_service_t corresponding to a given IOHIDDeviceRef, either by:
+ * - on OS X 10.6 and above, calling IOHIDDeviceGetService()
+ * - on OS X 10.5, extract it from the IOHIDDevice struct
+ */
+static io_service_t hidapi_IOHIDDeviceGetService(IOHIDDeviceRef device)
+{
+	static void *iokit_framework = NULL;
+	static io_service_t (*dynamic_IOHIDDeviceGetService)(IOHIDDeviceRef device) = NULL;
+
+	/* Use dlopen()/dlsym() to get a pointer to IOHIDDeviceGetService() if it exists.
+	 * If any of these steps fail, dynamic_IOHIDDeviceGetService will be left NULL
+	 * and the fallback method will be used.
+	 */
+	if (iokit_framework == NULL) {
+		iokit_framework = dlopen("/System/Library/IOKit.framework/IOKit", RTLD_LAZY);
+
+		if (iokit_framework != NULL)
+			dynamic_IOHIDDeviceGetService = dlsym(iokit_framework, "IOHIDDeviceGetService");
+	}
+
+	if (dynamic_IOHIDDeviceGetService != NULL) {
+		/* Running on OS X 10.6 and above: IOHIDDeviceGetService() exists */
+		return dynamic_IOHIDDeviceGetService(device);
+	}
+	else
+	{
+		/* Running on OS X 10.5: IOHIDDeviceGetService() doesn't exist.
+		 *
+		 * Be naughty and pull the service out of the IOHIDDevice.
+		 * IOHIDDevice is an opaque struct not exposed to applications, but its
+		 * layout is stable through all available versions of OS X.
+		 * Tested and working on OS X 10.5.8 i386, x86_64, and ppc.
+		 */
+		struct IOHIDDevice_internal {
+			/* The first field of the IOHIDDevice struct is a
+			 * CFRuntimeBase (which is a private CF struct).
+			 *
+			 * a, b, and c are the 3 fields that make up a CFRuntimeBase.
+			 * See http://opensource.apple.com/source/CF/CF-476.18/CFRuntime.h
+			 *
+			 * The second field of the IOHIDDevice is the io_service_t we're looking for.
+			 */
+			uintptr_t a;
+			uint8_t b[4];
+#if __LP64__
+			uint32_t c;
+#endif
+			io_service_t service;
+		};
+		struct IOHIDDevice_internal *tmp = (struct IOHIDDevice_internal *)device;
+
+		return tmp->service;
+	}
+}
+
+/* Initialize the IOHIDManager. Return 0 for success and -1 for failure. */
+static int init_hid_manager(void)
+{
+	/* Initialize all the HID Manager Objects */
+	hid_mgr = IOHIDManagerCreate(kCFAllocatorDefault, kIOHIDOptionsTypeNone);
+	if (hid_mgr) {
+		IOHIDManagerSetDeviceMatching(hid_mgr, NULL);
+		IOHIDManagerScheduleWithRunLoop(hid_mgr, CFRunLoopGetCurrent(), kCFRunLoopDefaultMode);
+		return 0;
+	}
+
+	return -1;
+}
+
+/* Initialize the IOHIDManager if necessary. This is the public function, and
+   it is safe to call this function repeatedly. Return 0 for success and -1
+   for failure. */
+int HID_API_EXPORT hid_init(void)
+{
+	if (!hid_mgr) {
+		return init_hid_manager();
+	}
+
+	/* Already initialized. */
+	return 0;
+}
+
+int HID_API_EXPORT hid_exit(void)
+{
+	if (hid_mgr) {
+		/* Close the HID manager. */
+		IOHIDManagerClose(hid_mgr, kIOHIDOptionsTypeNone);
+		CFRelease(hid_mgr);
+		hid_mgr = NULL;
+	}
+
+	return 0;
+}
+
+static void process_pending_events(void) {
+	SInt32 res;
+	do {
+		res = CFRunLoopRunInMode(kCFRunLoopDefaultMode, 0.001, FALSE);
+	} while(res != kCFRunLoopRunFinished && res != kCFRunLoopRunTimedOut);
+}
+
+struct hid_device_info  HID_API_EXPORT *hid_enumerate(unsigned short vendor_id, unsigned short product_id)
+{
+	struct hid_device_info *root = NULL; /* return object */
+	struct hid_device_info *cur_dev = NULL;
+	CFIndex num_devices;
+	int i;
+
+	/* Set up the HID Manager if it hasn't been done */
+	if (hid_init() < 0)
+		return NULL;
+
+	/* give the IOHIDManager a chance to update itself */
+	process_pending_events();
+
+	/* Get a list of the Devices */
+	IOHIDManagerSetDeviceMatching(hid_mgr, NULL);
+	CFSetRef device_set = IOHIDManagerCopyDevices(hid_mgr);
+
+	/* Convert the list into a C array so we can iterate easily. */
+	num_devices = CFSetGetCount(device_set);
+	IOHIDDeviceRef *device_array = calloc(num_devices, sizeof(IOHIDDeviceRef));
+	CFSetGetValues(device_set, (const void **) device_array);
+
+	/* Iterate over each device, making an entry for it. */
+	for (i = 0; i < num_devices; i++) {
+		unsigned short dev_vid;
+		unsigned short dev_pid;
+		#define BUF_LEN 256
+		wchar_t buf[BUF_LEN];
+
+		IOHIDDeviceRef dev = device_array[i];
+
+        if (!dev) {
+            continue;
+        }
+		dev_vid = get_vendor_id(dev);
+		dev_pid = get_product_id(dev);
+
+		/* Check the VID/PID against the arguments */
+		if ((vendor_id == 0x0 || vendor_id == dev_vid) &&
+		    (product_id == 0x0 || product_id == dev_pid)) {
+			struct hid_device_info *tmp;
+			io_object_t iokit_dev;
+			kern_return_t res;
+			io_string_t path;
+
+			/* VID/PID match. Create the record. */
+			tmp = malloc(sizeof(struct hid_device_info));
+			if (cur_dev) {
+				cur_dev->next = tmp;
+			}
+			else {
+				root = tmp;
+			}
+			cur_dev = tmp;
+
+			/* Get the Usage Page and Usage for this device. */
+			cur_dev->usage_page = get_int_property(dev, CFSTR(kIOHIDPrimaryUsagePageKey));
+			cur_dev->usage = get_int_property(dev, CFSTR(kIOHIDPrimaryUsageKey));
+
+			/* Fill out the record */
+			cur_dev->next = NULL;
+
+			/* Fill in the path (IOService plane) */
+			iokit_dev = hidapi_IOHIDDeviceGetService(dev);
+			res = IORegistryEntryGetPath(iokit_dev, kIOServicePlane, path);
+			if (res == KERN_SUCCESS)
+				cur_dev->path = strdup(path);
+			else
+				cur_dev->path = strdup("");
+
+			/* Serial Number */
+			get_serial_number(dev, buf, BUF_LEN);
+			cur_dev->serial_number = dup_wcs(buf);
+
+			/* Manufacturer and Product strings */
+			get_manufacturer_string(dev, buf, BUF_LEN);
+			cur_dev->manufacturer_string = dup_wcs(buf);
+			get_product_string(dev, buf, BUF_LEN);
+			cur_dev->product_string = dup_wcs(buf);
+
+			/* VID/PID */
+			cur_dev->vendor_id = dev_vid;
+			cur_dev->product_id = dev_pid;
+
+			/* Release Number */
+			cur_dev->release_number = get_int_property(dev, CFSTR(kIOHIDVersionNumberKey));
+
+			/* Interface Number (Unsupported on Mac)*/
+			cur_dev->interface_number = -1;
+		}
+	}
+
+	free(device_array);
+	CFRelease(device_set);
+
+	return root;
+}
+
+void  HID_API_EXPORT hid_free_enumeration(struct hid_device_info *devs)
+{
+	/* This function is identical to the Linux version. Platform independent. */
+	struct hid_device_info *d = devs;
+	while (d) {
+		struct hid_device_info *next = d->next;
+		free(d->path);
+		free(d->serial_number);
+		free(d->manufacturer_string);
+		free(d->product_string);
+		free(d);
+		d = next;
+	}
+}
+
+hid_device * HID_API_EXPORT hid_open(unsigned short vendor_id, unsigned short product_id, const wchar_t *serial_number)
+{
+	/* This function is identical to the Linux version. Platform independent. */
+	struct hid_device_info *devs, *cur_dev;
+	const char *path_to_open = NULL;
+	hid_device * handle = NULL;
+
+	devs = hid_enumerate(vendor_id, product_id);
+	cur_dev = devs;
+	while (cur_dev) {
+		if (cur_dev->vendor_id == vendor_id &&
+		    cur_dev->product_id == product_id) {
+			if (serial_number) {
+				if (wcscmp(serial_number, cur_dev->serial_number) == 0) {
+					path_to_open = cur_dev->path;
+					break;
+				}
+			}
+			else {
+				path_to_open = cur_dev->path;
+				break;
+			}
+		}
+		cur_dev = cur_dev->next;
+	}
+
+	if (path_to_open) {
+		/* Open the device */
+		handle = hid_open_path(path_to_open);
+	}
+
+	hid_free_enumeration(devs);
+
+	return handle;
+}
+
+static void hid_device_removal_callback(void *context, IOReturn result,
+                                        void *sender)
+{
+	/* Stop the Run Loop for this device. */
+	hid_device *d = context;
+
+	d->disconnected = 1;
+	CFRunLoopStop(d->run_loop);
+}
+
+/* The Run Loop calls this function for each input report received.
+   This function puts the data into a linked list to be picked up by
+   hid_read(). */
+static void hid_report_callback(void *context, IOReturn result, void *sender,
+                         IOHIDReportType report_type, uint32_t report_id,
+                         uint8_t *report, CFIndex report_length)
+{
+	struct input_report *rpt;
+	hid_device *dev = context;
+
+	/* Make a new Input Report object */
+	rpt = calloc(1, sizeof(struct input_report));
+	rpt->data = calloc(1, report_length);
+	memcpy(rpt->data, report, report_length);
+	rpt->len = report_length;
+	rpt->next = NULL;
+
+	/* Lock this section */
+	pthread_mutex_lock(&dev->mutex);
+
+	/* Attach the new report object to the end of the list. */
+	if (dev->input_reports == NULL) {
+		/* The list is empty. Put it at the root. */
+		dev->input_reports = rpt;
+	}
+	else {
+		/* Find the end of the list and attach. */
+		struct input_report *cur = dev->input_reports;
+		int num_queued = 0;
+		while (cur->next != NULL) {
+			cur = cur->next;
+			num_queued++;
+		}
+		cur->next = rpt;
+
+		/* Pop one off if we've reached 30 in the queue. This
+		   way we don't grow forever if the user never reads
+		   anything from the device. */
+		if (num_queued > 30) {
+			return_data(dev, NULL, 0);
+		}
+	}
+
+	/* Signal a waiting thread that there is data. */
+	pthread_cond_signal(&dev->condition);
+
+	/* Unlock */
+	pthread_mutex_unlock(&dev->mutex);
+
+}
+
+/* This gets called when the read_thread's run loop gets signaled by
+   hid_close(), and serves to stop the read_thread's run loop. */
+static void perform_signal_callback(void *context)
+{
+	hid_device *dev = context;
+	CFRunLoopStop(dev->run_loop); /*TODO: CFRunLoopGetCurrent()*/
+}
+
+static void *read_thread(void *param)
+{
+	hid_device *dev = param;
+	SInt32 code;
+
+	/* Move the device's run loop to this thread. */
+	IOHIDDeviceScheduleWithRunLoop(dev->device_handle, CFRunLoopGetCurrent(), dev->run_loop_mode);
+
+	/* Create the RunLoopSource which is used to signal the
+	   event loop to stop when hid_close() is called. */
+	CFRunLoopSourceContext ctx;
+	memset(&ctx, 0, sizeof(ctx));
+	ctx.version = 0;
+	ctx.info = dev;
+	ctx.perform = &perform_signal_callback;
+	dev->source = CFRunLoopSourceCreate(kCFAllocatorDefault, 0/*order*/, &ctx);
+	CFRunLoopAddSource(CFRunLoopGetCurrent(), dev->source, dev->run_loop_mode);
+
+	/* Store off the Run Loop so it can be stopped from hid_close()
+	   and on device disconnection. */
+	dev->run_loop = CFRunLoopGetCurrent();
+
+	/* Notify the main thread that the read thread is up and running. */
+	pthread_barrier_wait(&dev->barrier);
+
+	/* Run the Event Loop. CFRunLoopRunInMode() will dispatch HID input
+	   reports into the hid_report_callback(). */
+	while (!dev->shutdown_thread && !dev->disconnected) {
+		code = CFRunLoopRunInMode(dev->run_loop_mode, 1000/*sec*/, FALSE);
+		/* Return if the device has been disconnected */
+		if (code == kCFRunLoopRunFinished) {
+			dev->disconnected = 1;
+			break;
+		}
+
+
+		/* Break if The Run Loop returns Finished or Stopped. */
+		if (code != kCFRunLoopRunTimedOut &&
+		    code != kCFRunLoopRunHandledSource) {
+			/* There was some kind of error. Setting
+			   shutdown seems to make sense, but
+			   there may be something else more appropriate */
+			dev->shutdown_thread = 1;
+			break;
+		}
+	}
+
+	/* Now that the read thread is stopping, Wake any threads which are
+	   waiting on data (in hid_read_timeout()). Do this under a mutex to
+	   make sure that a thread which is about to go to sleep waiting on
+	   the condition actually will go to sleep before the condition is
+	   signaled. */
+	pthread_mutex_lock(&dev->mutex);
+	pthread_cond_broadcast(&dev->condition);
+	pthread_mutex_unlock(&dev->mutex);
+
+	/* Wait here until hid_close() is called and makes it past
+	   the call to CFRunLoopWakeUp(). This thread still needs to
+	   be valid when that function is called on the other thread. */
+	pthread_barrier_wait(&dev->shutdown_barrier);
+
+	return NULL;
+}
+
+/* hid_open_path()
+ *
+ * path must be a valid path to an IOHIDDevice in the IOService plane
+ * Example: "IOService:/AppleACPIPlatformExpert/PCI0@0/AppleACPIPCI/EHC1@1D,7/AppleUSBEHCI/PLAYSTATION(R)3 Controller@fd120000/IOUSBInterface@0/IOUSBHIDDriver"
+ */
+hid_device * HID_API_EXPORT hid_open_path(const char *path)
+{
+	hid_device *dev = NULL;
+	io_registry_entry_t entry = MACH_PORT_NULL;
+
+	dev = new_hid_device();
+
+	/* Set up the HID Manager if it hasn't been done */
+	if (hid_init() < 0)
+		return NULL;
+
+	/* Get the IORegistry entry for the given path */
+	entry = IORegistryEntryFromPath(kIOMasterPortDefault, path);
+	if (entry == MACH_PORT_NULL) {
+		/* Path wasn't valid (maybe device was removed?) */
+		goto return_error;
+	}
+
+	/* Create an IOHIDDevice for the entry */
+	dev->device_handle = IOHIDDeviceCreate(kCFAllocatorDefault, entry);
+	if (dev->device_handle == NULL) {
+		/* Error creating the HID device */
+		goto return_error;
+	}
+
+	/* Open the IOHIDDevice */
+	IOReturn ret = IOHIDDeviceOpen(dev->device_handle, kIOHIDOptionsTypeSeizeDevice);
+	if (ret == kIOReturnSuccess) {
+		char str[32];
+
+		/* Create the buffers for receiving data */
+		dev->max_input_report_len = (CFIndex) get_max_report_length(dev->device_handle);
+		dev->input_report_buf = calloc(dev->max_input_report_len, sizeof(uint8_t));
+
+		/* Create the Run Loop Mode for this device.
+		   printing the reference seems to work. */
+		sprintf(str, "HIDAPI_%p", dev->device_handle);
+		dev->run_loop_mode =
+			CFStringCreateWithCString(NULL, str, kCFStringEncodingASCII);
+
+		/* Attach the device to a Run Loop */
+		IOHIDDeviceRegisterInputReportCallback(
+			dev->device_handle, dev->input_report_buf, dev->max_input_report_len,
+			&hid_report_callback, dev);
+		IOHIDDeviceRegisterRemovalCallback(dev->device_handle, hid_device_removal_callback, dev);
+
+		/* Start the read thread */
+		pthread_create(&dev->thread, NULL, read_thread, dev);
+
+		/* Wait here for the read thread to be initialized. */
+		pthread_barrier_wait(&dev->barrier);
+
+		IOObjectRelease(entry);
+		return dev;
+	}
+	else {
+		goto return_error;
+	}
+
+return_error:
+	if (dev->device_handle != NULL)
+		CFRelease(dev->device_handle);
+
+	if (entry != MACH_PORT_NULL)
+		IOObjectRelease(entry);
+
+	free_hid_device(dev);
+	return NULL;
+}
+
+static int set_report(hid_device *dev, IOHIDReportType type, const unsigned char *data, size_t length)
+{
+	const unsigned char *data_to_send;
+	size_t length_to_send;
+	IOReturn res;
+
+	/* Return if the device has been disconnected. */
+	if (dev->disconnected)
+		return -1;
+
+	if (data[0] == 0x0) {
+		/* Not using numbered Reports.
+		   Don't send the report number. */
+		data_to_send = data+1;
+		length_to_send = length-1;
+	}
+	else {
+		/* Using numbered Reports.
+		   Send the Report Number */
+		data_to_send = data;
+		length_to_send = length;
+	}
+
+	if (!dev->disconnected) {
+		res = IOHIDDeviceSetReport(dev->device_handle,
+					   type,
+					   data[0], /* Report ID*/
+					   data_to_send, length_to_send);
+
+		if (res == kIOReturnSuccess) {
+			return length;
+		}
+		else
+			return -1;
+	}
+
+	return -1;
+}
+
+int HID_API_EXPORT hid_write(hid_device *dev, const unsigned char *data, size_t length)
+{
+	return set_report(dev, kIOHIDReportTypeOutput, data, length);
+}
+
+/* Helper function, so that this isn't duplicated in hid_read(). */
+static int return_data(hid_device *dev, unsigned char *data, size_t length)
+{
+	/* Copy the data out of the linked list item (rpt) into the
+	   return buffer (data), and delete the liked list item. */
+	struct input_report *rpt = dev->input_reports;
+	size_t len = (length < rpt->len)? length: rpt->len;
+	memcpy(data, rpt->data, len);
+	dev->input_reports = rpt->next;
+	free(rpt->data);
+	free(rpt);
+	return len;
+}
+
+static int cond_wait(const hid_device *dev, pthread_cond_t *cond, pthread_mutex_t *mutex)
+{
+	while (!dev->input_reports) {
+		int res = pthread_cond_wait(cond, mutex);
+		if (res != 0)
+			return res;
+
+		/* A res of 0 means we may have been signaled or it may
+		   be a spurious wakeup. Check to see that there's acutally
+		   data in the queue before returning, and if not, go back
+		   to sleep. See the pthread_cond_timedwait() man page for
+		   details. */
+
+		if (dev->shutdown_thread || dev->disconnected)
+			return -1;
+	}
+
+	return 0;
+}
+
+static int cond_timedwait(const hid_device *dev, pthread_cond_t *cond, pthread_mutex_t *mutex, const struct timespec *abstime)
+{
+	while (!dev->input_reports) {
+		int res = pthread_cond_timedwait(cond, mutex, abstime);
+		if (res != 0)
+			return res;
+
+		/* A res of 0 means we may have been signaled or it may
+		   be a spurious wakeup. Check to see that there's acutally
+		   data in the queue before returning, and if not, go back
+		   to sleep. See the pthread_cond_timedwait() man page for
+		   details. */
+
+		if (dev->shutdown_thread || dev->disconnected)
+			return -1;
+	}
+
+	return 0;
+
+}
+
+int HID_API_EXPORT hid_read_timeout(hid_device *dev, unsigned char *data, size_t length, int milliseconds)
+{
+	int bytes_read = -1;
+
+	/* Lock the access to the report list. */
+	pthread_mutex_lock(&dev->mutex);
+
+	/* There's an input report queued up. Return it. */
+	if (dev->input_reports) {
+		/* Return the first one */
+		bytes_read = return_data(dev, data, length);
+		goto ret;
+	}
+
+	/* Return if the device has been disconnected. */
+	if (dev->disconnected) {
+		bytes_read = -1;
+		goto ret;
+	}
+
+	if (dev->shutdown_thread) {
+		/* This means the device has been closed (or there
+		   has been an error. An error code of -1 should
+		   be returned. */
+		bytes_read = -1;
+		goto ret;
+	}
+
+	/* There is no data. Go to sleep and wait for data. */
+
+	if (milliseconds == -1) {
+		/* Blocking */
+		int res;
+		res = cond_wait(dev, &dev->condition, &dev->mutex);
+		if (res == 0)
+			bytes_read = return_data(dev, data, length);
+		else {
+			/* There was an error, or a device disconnection. */
+			bytes_read = -1;
+		}
+	}
+	else if (milliseconds > 0) {
+		/* Non-blocking, but called with timeout. */
+		int res;
+		struct timespec ts;
+		struct timeval tv;
+		gettimeofday(&tv, NULL);
+		TIMEVAL_TO_TIMESPEC(&tv, &ts);
+		ts.tv_sec += milliseconds / 1000;
+		ts.tv_nsec += (milliseconds % 1000) * 1000000;
+		if (ts.tv_nsec >= 1000000000L) {
+			ts.tv_sec++;
+			ts.tv_nsec -= 1000000000L;
+		}
+
+		res = cond_timedwait(dev, &dev->condition, &dev->mutex, &ts);
+		if (res == 0)
+			bytes_read = return_data(dev, data, length);
+		else if (res == ETIMEDOUT)
+			bytes_read = 0;
+		else
+			bytes_read = -1;
+	}
+	else {
+		/* Purely non-blocking */
+		bytes_read = 0;
+	}
+
+ret:
+	/* Unlock */
+	pthread_mutex_unlock(&dev->mutex);
+	return bytes_read;
+}
+
+int HID_API_EXPORT hid_read(hid_device *dev, unsigned char *data, size_t length)
+{
+	return hid_read_timeout(dev, data, length, (dev->blocking)? -1: 0);
+}
+
+int HID_API_EXPORT hid_set_nonblocking(hid_device *dev, int nonblock)
+{
+	/* All Nonblocking operation is handled by the library. */
+	dev->blocking = !nonblock;
+
+	return 0;
+}
+
+int HID_API_EXPORT hid_send_feature_report(hid_device *dev, const unsigned char *data, size_t length)
+{
+	return set_report(dev, kIOHIDReportTypeFeature, data, length);
+}
+
+int HID_API_EXPORT hid_get_feature_report(hid_device *dev, unsigned char *data, size_t length)
+{
+	CFIndex len = length;
+	IOReturn res;
+
+	/* Return if the device has been unplugged. */
+	if (dev->disconnected)
+		return -1;
+
+	res = IOHIDDeviceGetReport(dev->device_handle,
+	                           kIOHIDReportTypeFeature,
+	                           data[0], /* Report ID */
+	                           data, &len);
+	if (res == kIOReturnSuccess)
+		return len;
+	else
+		return -1;
+}
+
+
+void HID_API_EXPORT hid_close(hid_device *dev)
+{
+	if (!dev)
+		return;
+
+	/* Disconnect the report callback before close. */
+	if (!dev->disconnected) {
+		IOHIDDeviceRegisterInputReportCallback(
+			dev->device_handle, dev->input_report_buf, dev->max_input_report_len,
+			NULL, dev);
+		IOHIDDeviceRegisterRemovalCallback(dev->device_handle, NULL, dev);
+		IOHIDDeviceUnscheduleFromRunLoop(dev->device_handle, dev->run_loop, dev->run_loop_mode);
+		IOHIDDeviceScheduleWithRunLoop(dev->device_handle, CFRunLoopGetMain(), kCFRunLoopDefaultMode);
+	}
+
+	/* Cause read_thread() to stop. */
+	dev->shutdown_thread = 1;
+
+	/* Wake up the run thread's event loop so that the thread can exit. */
+	CFRunLoopSourceSignal(dev->source);
+	CFRunLoopWakeUp(dev->run_loop);
+
+	/* Notify the read thread that it can shut down now. */
+	pthread_barrier_wait(&dev->shutdown_barrier);
+
+	/* Wait for read_thread() to end. */
+	pthread_join(dev->thread, NULL);
+
+	/* Close the OS handle to the device, but only if it's not
+	   been unplugged. If it's been unplugged, then calling
+	   IOHIDDeviceClose() will crash. */
+	if (!dev->disconnected) {
+		IOHIDDeviceClose(dev->device_handle, kIOHIDOptionsTypeSeizeDevice);
+	}
+
+	/* Clear out the queue of received reports. */
+	pthread_mutex_lock(&dev->mutex);
+	while (dev->input_reports) {
+		return_data(dev, NULL, 0);
+	}
+	pthread_mutex_unlock(&dev->mutex);
+	CFRelease(dev->device_handle);
+
+	free_hid_device(dev);
+}
+
+int HID_API_EXPORT_CALL hid_get_manufacturer_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	return get_manufacturer_string(dev->device_handle, string, maxlen);
+}
+
+int HID_API_EXPORT_CALL hid_get_product_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	return get_product_string(dev->device_handle, string, maxlen);
+}
+
+int HID_API_EXPORT_CALL hid_get_serial_number_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	return get_serial_number(dev->device_handle, string, maxlen);
+}
+
+int HID_API_EXPORT_CALL hid_get_indexed_string(hid_device *dev, int string_index, wchar_t *string, size_t maxlen)
+{
+	/* TODO: */
+
+	return 0;
+}
+
+
+HID_API_EXPORT const wchar_t * HID_API_CALL  hid_error(hid_device *dev)
+{
+	/* TODO: */
+
+	return NULL;
+}
+
+
+
+
+
+
+
+#if 0
+static int32_t get_location_id(IOHIDDeviceRef device)
+{
+	return get_int_property(device, CFSTR(kIOHIDLocationIDKey));
+}
+
+static int32_t get_usage(IOHIDDeviceRef device)
+{
+	int32_t res;
+	res = get_int_property(device, CFSTR(kIOHIDDeviceUsageKey));
+	if (!res)
+		res = get_int_property(device, CFSTR(kIOHIDPrimaryUsageKey));
+	return res;
+}
+
+static int32_t get_usage_page(IOHIDDeviceRef device)
+{
+	int32_t res;
+	res = get_int_property(device, CFSTR(kIOHIDDeviceUsagePageKey));
+	if (!res)
+		res = get_int_property(device, CFSTR(kIOHIDPrimaryUsagePageKey));
+	return res;
+}
+
+static int get_transport(IOHIDDeviceRef device, wchar_t *buf, size_t len)
+{
+	return get_string_property(device, CFSTR(kIOHIDTransportKey), buf, len);
+}
+
+
+int main(void)
+{
+	IOHIDManagerRef mgr;
+	int i;
+
+	mgr = IOHIDManagerCreate(kCFAllocatorDefault, kIOHIDOptionsTypeNone);
+	IOHIDManagerSetDeviceMatching(mgr, NULL);
+	IOHIDManagerOpen(mgr, kIOHIDOptionsTypeNone);
+
+	CFSetRef device_set = IOHIDManagerCopyDevices(mgr);
+
+	CFIndex num_devices = CFSetGetCount(device_set);
+	IOHIDDeviceRef *device_array = calloc(num_devices, sizeof(IOHIDDeviceRef));
+	CFSetGetValues(device_set, (const void **) device_array);
+
+	for (i = 0; i < num_devices; i++) {
+		IOHIDDeviceRef dev = device_array[i];
+		printf("Device: %p\n", dev);
+		printf("  %04hx %04hx\n", get_vendor_id(dev), get_product_id(dev));
+
+		wchar_t serial[256], buf[256];
+		char cbuf[256];
+		get_serial_number(dev, serial, 256);
+
+
+		printf("  Serial: %ls\n", serial);
+		printf("  Loc: %ld\n", get_location_id(dev));
+		get_transport(dev, buf, 256);
+		printf("  Trans: %ls\n", buf);
+		make_path(dev, cbuf, 256);
+		printf("  Path: %s\n", cbuf);
+
+	}
+
+	return 0;
+}
+#endif
diff --git a/uf2-samdx1/lib/uf2/hidapi/pc/.gitignore b/uf2-samdx1/lib/uf2/hidapi/pc/.gitignore
new file mode 100644
index 00000000..6fd0ef02
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/pc/.gitignore
@@ -0,0 +1 @@
+*.pc
diff --git a/uf2-samdx1/lib/uf2/hidapi/pc/hidapi-hidraw.pc.in b/uf2-samdx1/lib/uf2/hidapi/pc/hidapi-hidraw.pc.in
new file mode 100644
index 00000000..e20558d5
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/pc/hidapi-hidraw.pc.in
@@ -0,0 +1,10 @@
+prefix=@prefix@
+exec_prefix=@exec_prefix@
+libdir=@libdir@
+includedir=@includedir@
+
+Name: hidapi-hidraw
+Description: C Library for USB/Bluetooth HID device access from Linux, Mac OS X, FreeBSD, and Windows. This is the hidraw implementation.
+Version: @VERSION@
+Libs: -L${libdir} -lhidapi-hidraw
+Cflags: -I${includedir}/hidapi
diff --git a/uf2-samdx1/lib/uf2/hidapi/pc/hidapi-libusb.pc.in b/uf2-samdx1/lib/uf2/hidapi/pc/hidapi-libusb.pc.in
new file mode 100644
index 00000000..2e495065
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/pc/hidapi-libusb.pc.in
@@ -0,0 +1,10 @@
+prefix=@prefix@
+exec_prefix=@exec_prefix@
+libdir=@libdir@
+includedir=@includedir@
+
+Name: hidapi-libusb
+Description: C Library for USB HID device access from Linux, Mac OS X, FreeBSD, and Windows. This is the libusb implementation.
+Version: @VERSION@
+Libs: -L${libdir} -lhidapi-libusb
+Cflags: -I${includedir}/hidapi
diff --git a/uf2-samdx1/lib/uf2/hidapi/pc/hidapi.pc.in b/uf2-samdx1/lib/uf2/hidapi/pc/hidapi.pc.in
new file mode 100644
index 00000000..5835c99b
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/pc/hidapi.pc.in
@@ -0,0 +1,10 @@
+prefix=@prefix@
+exec_prefix=@exec_prefix@
+libdir=@libdir@
+includedir=@includedir@
+
+Name: hidapi
+Description: C Library for USB/Bluetooth HID device access from Linux, Mac OS X, FreeBSD, and Windows.
+Version: @VERSION@
+Libs: -L${libdir} -lhidapi
+Cflags: -I${includedir}/hidapi
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/.gitignore b/uf2-samdx1/lib/uf2/hidapi/testgui/.gitignore
new file mode 100644
index 00000000..f989ea8c
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/.gitignore
@@ -0,0 +1,20 @@
+Debug
+Release
+*.exp
+*.ilk
+*.lib
+*.suo
+*.vcproj.*
+*.ncb
+*.suo
+*.dll
+*.pdb
+*.o
+hidapi-testgui
+hidapi-hidraw-testgui
+hidapi-libusb-testgui
+.deps
+.libs
+*.la
+*.lo
+TestGUI.app
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile-manual b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile-manual
new file mode 100644
index 00000000..3f61705f
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile-manual
@@ -0,0 +1,26 @@
+
+
+OS=$(shell uname)
+
+ifeq ($(OS), Darwin)
+	FILE=Makefile.mac
+endif
+
+ifneq (,$(findstring MINGW,$(OS)))
+	FILE=Makefile.mingw
+endif
+
+ifeq ($(OS), Linux)
+	FILE=Makefile.linux
+endif
+
+ifeq ($(OS), FreeBSD)
+	FILE=Makefile.freebsd
+endif
+
+ifeq ($(FILE), )
+all:
+	$(error Your platform ${OS} is not supported at this time.)
+endif
+
+include $(FILE)
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.am b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.am
new file mode 100644
index 00000000..1c02f3f2
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.am
@@ -0,0 +1,43 @@
+
+AM_CPPFLAGS = -I$(top_srcdir)/hidapi/ $(CFLAGS_TESTGUI)
+
+if OS_LINUX
+## Linux
+bin_PROGRAMS = hidapi-hidraw-testgui hidapi-libusb-testgui
+
+hidapi_hidraw_testgui_SOURCES = test.cpp
+hidapi_hidraw_testgui_LDADD = $(top_builddir)/linux/libhidapi-hidraw.la $(LIBS_TESTGUI)
+
+hidapi_libusb_testgui_SOURCES = test.cpp
+hidapi_libusb_testgui_LDADD = $(top_builddir)/libusb/libhidapi-libusb.la $(LIBS_TESTGUI)
+else
+## Other OS's
+bin_PROGRAMS = hidapi-testgui
+
+hidapi_testgui_SOURCES = test.cpp
+hidapi_testgui_LDADD = $(top_builddir)/$(backend)/libhidapi.la $(LIBS_TESTGUI)
+endif
+
+if OS_DARWIN
+hidapi_testgui_SOURCES = test.cpp mac_support_cocoa.m mac_support.h
+# Rules for copying the binary and its dependencies into the app bundle.
+TestGUI.app/Contents/MacOS/hidapi-testgui$(EXEEXT): hidapi-testgui$(EXEEXT)
+	$(srcdir)/copy_to_bundle.sh
+
+all: all-am TestGUI.app/Contents/MacOS/hidapi-testgui$(EXEEXT)
+
+endif
+
+EXTRA_DIST = \
+ copy_to_bundle.sh \
+ Makefile-manual \
+ Makefile.freebsd \
+ Makefile.linux \
+ Makefile.mac \
+ Makefile.mingw \
+ TestGUI.app.in \
+ testgui.sln \
+ testgui.vcproj
+
+distclean-local:
+	rm -rf TestGUI.app
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.freebsd b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.freebsd
new file mode 100644
index 00000000..09a24737
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.freebsd
@@ -0,0 +1,33 @@
+###########################################
+# Simple Makefile for HIDAPI test program
+#
+# Alan Ott
+# Signal 11 Software
+# 2010-06-01
+###########################################
+
+all: testgui
+
+CC=cc
+CXX=c++
+COBJS=../libusb/hid.o
+CPPOBJS=test.o
+OBJS=$(COBJS) $(CPPOBJS)
+CFLAGS=-I../hidapi -I/usr/local/include `fox-config --cflags` -Wall -g -c
+LDFLAGS= -L/usr/local/lib
+LIBS= -lusb -liconv `fox-config --libs` -pthread
+
+
+testgui: $(OBJS)
+	$(CXX) -Wall -g $^ $(LDFLAGS) -o $@ $(LIBS)
+
+$(COBJS): %.o: %.c
+	$(CC) $(CFLAGS) $< -o $@
+
+$(CPPOBJS): %.o: %.cpp
+	$(CXX) $(CFLAGS) $< -o $@
+
+clean:
+	rm *.o testgui
+
+.PHONY: clean
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.linux b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.linux
new file mode 100644
index 00000000..d32e1631
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.linux
@@ -0,0 +1,32 @@
+###########################################
+# Simple Makefile for HIDAPI test program
+#
+# Alan Ott
+# Signal 11 Software
+# 2010-06-01
+###########################################
+
+all: testgui
+
+CC=gcc
+CXX=g++
+COBJS=../libusb/hid.o
+CPPOBJS=test.o
+OBJS=$(COBJS) $(CPPOBJS)
+CFLAGS=-I../hidapi -Wall -g -c `fox-config --cflags` `pkg-config libusb-1.0 --cflags`
+LIBS=-ludev -lrt -lpthread `fox-config --libs` `pkg-config libusb-1.0 --libs`
+
+
+testgui: $(OBJS)
+	g++ -Wall -g $^ $(LIBS) -o testgui
+
+$(COBJS): %.o: %.c
+	$(CC) $(CFLAGS) $< -o $@
+
+$(CPPOBJS): %.o: %.cpp
+	$(CXX) $(CFLAGS) $< -o $@
+
+clean:
+	rm *.o testgui
+
+.PHONY: clean
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.mac b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.mac
new file mode 100644
index 00000000..cda7d49e
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.mac
@@ -0,0 +1,46 @@
+###########################################
+# Simple Makefile for HIDAPI test program
+#
+# Alan Ott
+# Signal 11 Software
+# 2010-07-03
+###########################################
+
+all: hidapi-testgui
+
+CC=gcc
+CXX=g++
+COBJS=../mac/hid.o
+CPPOBJS=test.o
+OBJCOBJS=mac_support_cocoa.o
+OBJS=$(COBJS) $(CPPOBJS) $(OBJCOBJS)
+CFLAGS=-I../hidapi -Wall -g -c `fox-config --cflags`
+LDFLAGS=-L/usr/X11R6/lib
+LIBS=`fox-config --libs` -framework IOKit -framework CoreFoundation -framework Cocoa
+
+
+hidapi-testgui: $(OBJS) TestGUI.app
+	g++ -Wall -g $(OBJS) $(LIBS) $(LDFLAGS) -o hidapi-testgui
+	./copy_to_bundle.sh
+	#cp TestGUI.app/Contents/MacOS/hidapi-testgui  TestGUI.app/Contents/MacOS/tg
+	#cp start.sh TestGUI.app/Contents/MacOS/hidapi-testgui
+
+$(COBJS): %.o: %.c
+	$(CC) $(CFLAGS) $< -o $@
+
+$(CPPOBJS): %.o: %.cpp
+	$(CXX) $(CFLAGS) $< -o $@
+
+$(OBJCOBJS): %.o: %.m
+	$(CXX) $(CFLAGS) -x objective-c++ $< -o $@
+
+TestGUI.app: TestGUI.app.in
+	rm -Rf TestGUI.app
+	mkdir -p TestGUI.app
+	cp -R TestGUI.app.in/ TestGUI.app
+
+clean:
+	rm -f $(OBJS) hidapi-testgui
+	rm -Rf TestGUI.app
+
+.PHONY: clean
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.mingw b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.mingw
new file mode 100644
index 00000000..df0f69d1
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/Makefile.mingw
@@ -0,0 +1,32 @@
+###########################################
+# Simple Makefile for HIDAPI test program
+#
+# Alan Ott
+# Signal 11 Software
+# 2010-06-01
+###########################################
+
+all: hidapi-testgui
+
+CC=gcc
+CXX=g++
+COBJS=../windows/hid.o
+CPPOBJS=test.o
+OBJS=$(COBJS) $(CPPOBJS)
+CFLAGS=-I../hidapi -I../../hidapi-externals/fox/include -g -c
+LIBS= -mwindows -lsetupapi -L../../hidapi-externals/fox/lib -Wl,-Bstatic -lFOX-1.6 -Wl,-Bdynamic -lgdi32 -Wl,--enable-auto-import -static-libgcc -static-libstdc++ -lkernel32
+
+
+hidapi-testgui: $(OBJS)
+	g++ -g $^ $(LIBS) -o hidapi-testgui
+
+$(COBJS): %.o: %.c
+	$(CC) $(CFLAGS) $< -o $@
+
+$(CPPOBJS): %.o: %.cpp
+	$(CXX) $(CFLAGS) $< -o $@
+
+clean:
+	rm -f *.o hidapi-testgui.exe
+
+.PHONY: clean
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/Info.plist b/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/Info.plist
new file mode 100644
index 00000000..ab473d53
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/Info.plist
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
+<plist version="1.0">
+<dict>
+	<key>CFBundleDevelopmentRegion</key>
+	<string>English</string>
+	<key>CFBundleDisplayName</key>
+	<string></string>
+	<key>CFBundleExecutable</key>
+	<string>hidapi-testgui</string>
+	<key>CFBundleIconFile</key>
+	<string>Signal11.icns</string>
+	<key>CFBundleIdentifier</key>
+	<string>us.signal11.hidtestgui</string>
+	<key>CFBundleInfoDictionaryVersion</key>
+	<string>6.0</string>
+	<key>CFBundleName</key>
+	<string>testgui</string>
+	<key>CFBundlePackageType</key>
+	<string>APPL</string>
+	<key>CFBundleSignature</key>
+	<string>????</string>
+	<key>CFBundleVersion</key>
+	<string>1.0</string>
+	<key>CSResourcesFileMapped</key>
+	<true/>
+</dict>
+</plist>
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/PkgInfo b/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/PkgInfo
new file mode 100644
index 00000000..bd04210f
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/PkgInfo
@@ -0,0 +1 @@
+APPL????
\ No newline at end of file
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/Resources/English.lproj/InfoPlist.strings b/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/Resources/English.lproj/InfoPlist.strings
new file mode 100644
index 0000000000000000000000000000000000000000..dea12de4cad936a6204d4da70d2ca96aef900b31
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diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/Resources/Signal11.icns b/uf2-samdx1/lib/uf2/hidapi/testgui/TestGUI.app.in/Contents/Resources/Signal11.icns
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z4k5+V{M>=GF>^e%|EdFX8kS<}`FktQpL&kftR1Kws2!*ss2!*ss2!*ss2!*sxVsLV
PJ$&>TqQCdaKgRqA{2bi%

literal 0
HcmV?d00001

diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/copy_to_bundle.sh b/uf2-samdx1/lib/uf2/hidapi/testgui/copy_to_bundle.sh
new file mode 100644
index 00000000..f0fc767a
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/copy_to_bundle.sh
@@ -0,0 +1,97 @@
+#!/bin/bash
+
+#### Configuration:
+# The name of the executable. It is assumed
+# that it is in the current working directory.
+EXE_NAME=hidapi-testgui
+# Path to the executable directory inside the bundle.
+# This must be an absolute path, so use $PWD.
+EXEPATH=$PWD/TestGUI.app/Contents/MacOS
+# Libraries to explicitly bundle, even though they
+# may not be in /opt/local. One per line. These
+# are used with grep, so only a portion of the name
+# is required. eg: libFOX, libz, etc.
+LIBS_TO_BUNDLE=libFOX
+
+
+function copydeps {
+	local file=$1
+	# echo "Copying deps for $file...."
+	local BASE_OF_EXE=`basename $file`
+
+	# A will contain the dependencies of this library
+	local A=`otool -LX $file |cut -f 1 -d " "`
+	local i
+	for i in $A; do
+		local BASE=`basename $i`
+
+		# See if it's a lib we specifically want to bundle
+		local bundle_this_lib=0
+		local j
+		for j in $LIBS_TO_BUNDLE; do
+			echo $i |grep -q $j
+			if [ $? -eq 0 ]; then
+				bundle_this_lib=1
+				echo "bundling $i because it's in the list."
+				break;
+			fi
+		done
+
+		# See if it's in /opt/local. Bundle all in /opt/local
+		local isOptLocal=0
+		echo $i |grep -q /opt/local
+		if [ $? -eq 0 ]; then
+			isOptLocal=1
+			echo "bundling $i because it's in /opt/local."
+		fi
+		
+		# Bundle the library
+		if [ $isOptLocal -ne 0 ] || [ $bundle_this_lib -ne 0 ]; then
+
+			# Copy the file into the bundle if it exists.
+			if [ -f $EXEPATH/$BASE ]; then
+				z=0
+			else
+				cp $i $EXEPATH
+				chmod 755 $EXEPATH/$BASE
+			fi
+			
+			
+			# echo "$BASE_OF_EXE depends on $BASE"
+			
+			# Fix the paths using install_name_tool and then
+			# call this function recursively for each dependency
+			# of this library. 
+			if [ $BASE_OF_EXE != $BASE ]; then
+			
+				# Fix the paths
+				install_name_tool -id @executable_path/$BASE $EXEPATH/$BASE
+				install_name_tool -change $i @executable_path/$BASE $EXEPATH/$BASE_OF_EXE
+
+				# Call this function (recursive) on
+				# on each dependency of this library.
+				copydeps $EXEPATH/$BASE
+			fi
+		fi
+	done
+}
+
+rm -f $EXEPATH/*
+
+# Copy the binary into the bundle. Use ../libtool to do this if it's
+# available beacuse if $EXE_NAME was built with autotools, it will be
+# necessary.  If ../libtool not available, just use cp to do the copy, but
+# only if $EXE_NAME is a binary.
+if [ -x ../libtool ]; then
+	../libtool --mode=install cp $EXE_NAME $EXEPATH
+else
+	file -bI $EXE_NAME |grep binary
+	if [ $? -ne 0 ]; then
+		echo "There is no ../libtool and $EXE_NAME is not a binary."
+		echo "I'm not sure what to do."
+		exit 1
+	else
+		cp $EXE_NAME $EXEPATH
+	fi
+fi
+copydeps $EXEPATH/$EXE_NAME
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/mac_support.cpp b/uf2-samdx1/lib/uf2/hidapi/testgui/mac_support.cpp
new file mode 100644
index 00000000..e1e38744
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/mac_support.cpp
@@ -0,0 +1,134 @@
+/*******************************
+ Mac support for HID Test GUI
+ 
+ Alan Ott
+ Signal 11 Software
+
+ Some of this code is from Apple Documentation, most notably
+ http://developer.apple.com/legacy/mac/library/documentation/AppleScript/Conceptual/AppleEvents/AppleEvents.pdf 
+*******************************/
+
+#include <Carbon/Carbon.h>
+#include <fx.h>
+
+
+extern FXMainWindow *g_main_window;
+
+static pascal OSErr HandleQuitMessage(const AppleEvent *theAppleEvent, AppleEvent 
+									  *reply, long handlerRefcon) 
+{
+	puts("Quitting\n");
+	FXApp::instance()->exit();
+	return 0;
+}
+
+static pascal OSErr HandleReopenMessage(const AppleEvent *theAppleEvent, AppleEvent 
+									  *reply, long handlerRefcon) 
+{
+	puts("Showing");
+	g_main_window->show();
+	return 0;
+}
+
+static pascal OSErr HandleWildCardMessage(const AppleEvent *theAppleEvent, AppleEvent 
+									  *reply, long handlerRefcon) 
+{
+	puts("WildCard\n");
+	return 0;
+}
+
+OSStatus AEHandler(EventHandlerCallRef inCaller, EventRef inEvent, void* inRefcon) 
+{ 
+    Boolean     release = false; 
+    EventRecord eventRecord; 
+    OSErr       ignoreErrForThisSample; 
+	
+    // Events of type kEventAppleEvent must be removed from the queue 
+    //  before being passed to AEProcessAppleEvent. 
+    if (IsEventInQueue(GetMainEventQueue(), inEvent)) 
+    { 
+        // RemoveEventFromQueue will release the event, which will 
+        //  destroy it if we don't retain it first. 
+        RetainEvent(inEvent); 
+        release = true; 
+        RemoveEventFromQueue(GetMainEventQueue(), inEvent); 
+    } 
+    // Convert the event ref to the type AEProcessAppleEvent expects. 
+    ConvertEventRefToEventRecord(inEvent, &eventRecord); 
+    ignoreErrForThisSample = AEProcessAppleEvent(&eventRecord); 
+    if (release) 
+        ReleaseEvent(inEvent); 
+    // This Carbon event has been handled, even if no AppleEvent handlers 
+    //  were installed for the Apple event. 
+    return noErr; 
+}
+
+static void HandleEvent(EventRecord *event) 
+{ 
+	//printf("What: %d message %x\n", event->what, event->message);
+	if (event->what == osEvt) {
+		if (((event->message >> 24) & 0xff) == suspendResumeMessage) {
+			if (event->message & resumeFlag) {
+				g_main_window->show();				
+			}
+		}
+	}
+
+#if 0
+    switch (event->what) 
+    { 
+        case mouseDown: 
+            //HandleMouseDown(event); 
+            break; 
+        case keyDown: 
+        case autoKey: 
+            //HandleKeyPress(event); 
+            break; 
+        case kHighLevelEvent: 
+			puts("Calling ProcessAppleEvent\n");
+            AEProcessAppleEvent(event); 
+            break; 
+    } 
+#endif
+} 
+
+void
+init_apple_message_system()
+{
+	OSErr err;
+	static const EventTypeSpec appleEvents[] = 
+	{
+		{ kEventClassAppleEvent, kEventAppleEvent }
+	};
+	
+	/* Install the handler for Apple Events */
+	InstallApplicationEventHandler(NewEventHandlerUPP(AEHandler), 
+	              GetEventTypeCount(appleEvents), appleEvents, 0, NULL); 
+
+	/* Install handlers for the individual Apple Events that come
+	   from the Dock icon: the Reopen (click), and the Quit messages. */
+	err = AEInstallEventHandler(kCoreEventClass, kAEQuitApplication, 
+	              NewAEEventHandlerUPP(HandleQuitMessage), 0, false);
+	err = AEInstallEventHandler(kCoreEventClass, kAEReopenApplication, 
+	              NewAEEventHandlerUPP(HandleReopenMessage), 0, false);
+#if 0
+	// Left as an example of a wild card match.
+	err = AEInstallEventHandler(kCoreEventClass, typeWildCard, 
+	              NewAEEventHandlerUPP(HandleWildMessage), 0, false);
+#endif
+}
+
+void
+check_apple_events()
+{
+	RgnHandle       cursorRgn = NULL; 
+	Boolean         gotEvent=TRUE; 
+	EventRecord     event; 
+
+	while (gotEvent) { 
+		gotEvent = WaitNextEvent(everyEvent, &event, 0L/*timeout*/, cursorRgn); 
+		if (gotEvent) { 
+			HandleEvent(&event); 
+		} 
+	}
+}
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/mac_support.h b/uf2-samdx1/lib/uf2/hidapi/testgui/mac_support.h
new file mode 100644
index 00000000..7d9ab493
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/mac_support.h
@@ -0,0 +1,17 @@
+/*******************************
+ Mac support for HID Test GUI
+ 
+ Alan Ott
+ Signal 11 Software
+ 
+*******************************/
+
+#ifndef MAC_SUPPORT_H__
+#define MAC_SUPPORT_H__
+
+extern "C" {
+	void init_apple_message_system();
+	void check_apple_events();
+}
+
+#endif
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/mac_support_cocoa.m b/uf2-samdx1/lib/uf2/hidapi/testgui/mac_support_cocoa.m
new file mode 100644
index 00000000..75de7e9c
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/mac_support_cocoa.m
@@ -0,0 +1,94 @@
+/*******************************
+ Mac support for HID Test GUI
+ 
+ Alan Ott
+ Signal 11 Software
+*******************************/
+
+#include <fx.h>
+#import <Cocoa/Cocoa.h>
+
+extern FXMainWindow *g_main_window;
+
+
+@interface MyAppDelegate : NSObject
+{
+} 
+@end
+
+@implementation MyAppDelegate
+- (void) applicationWillBecomeActive:(NSNotification*)notif
+{
+	printf("WillBecomeActive\n");
+	g_main_window->show();
+
+}
+
+- (void) applicationWillTerminate:(NSNotification*)notif
+{
+	/* Doesn't get called. Not sure why */
+	printf("WillTerminate\n");
+	FXApp::instance()->exit();
+}
+
+- (NSApplicationTerminateReply) applicationShouldTerminate:(NSApplication*)sender
+{
+	/* Doesn't get called. Not sure why */
+	printf("ShouldTerminate\n");
+	return YES;
+}
+
+- (void) applicationWillHide:(NSNotification*)notif
+{
+	printf("WillHide\n");
+	g_main_window->hide();
+}
+
+- (void) handleQuitEvent:(NSAppleEventDescriptor*)event withReplyEvent:(NSAppleEventDescriptor*)replyEvent
+{
+	printf("QuitEvent\n");
+	FXApp::instance()->exit();
+}
+
+@end
+
+extern "C" {
+
+void
+init_apple_message_system()
+{
+	static MyAppDelegate *d = [MyAppDelegate new];
+
+	[[NSApplication sharedApplication] setDelegate:d];
+
+	/* Register for Apple Events. */
+	/* This is from
+	   http://stackoverflow.com/questions/1768497/application-exit-event */
+	NSAppleEventManager *aem = [NSAppleEventManager sharedAppleEventManager];
+	[aem setEventHandler:d
+	     andSelector:@selector(handleQuitEvent:withReplyEvent:)
+	     forEventClass:kCoreEventClass andEventID:kAEQuitApplication];
+}
+
+void
+check_apple_events()
+{
+	NSApplication *app = [NSApplication sharedApplication];
+
+	NSAutoreleasePool *pool = [NSAutoreleasePool new];
+	while (1) {
+		NSEvent* event = [NSApp nextEventMatchingMask:NSAnyEventMask
+		                        untilDate:nil
+                                        inMode:NSDefaultRunLoopMode
+                                        dequeue:YES];
+		if (event == NULL)
+			break;
+		else {
+			//printf("Event happened: Type: %d\n", event->_type);
+			[app sendEvent: event];
+		}
+	}
+	[pool release];
+}
+
+} /* extern "C" */
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/start.sh b/uf2-samdx1/lib/uf2/hidapi/testgui/start.sh
new file mode 100644
index 00000000..980635d9
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/start.sh
@@ -0,0 +1,2 @@
+#!/bin/bash
+xterm -e /Users/alan/work/hidapi/testgui/TestGUI.app/Contents/MacOS/tg
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/test.cpp b/uf2-samdx1/lib/uf2/hidapi/testgui/test.cpp
new file mode 100644
index 00000000..538db791
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/test.cpp
@@ -0,0 +1,532 @@
+/*******************************************************
+ Demo Program for HIDAPI
+ 
+ Alan Ott
+ Signal 11 Software
+
+ 2010-07-20
+
+ Copyright 2010, All Rights Reserved
+ 
+ This contents of this file may be used by anyone
+ for any reason without any conditions and may be
+ used as a starting point for your own applications
+ which use HIDAPI.
+********************************************************/
+
+
+#include <fx.h>
+
+#include "hidapi.h"
+#include "mac_support.h"
+#include <string.h>
+#include <stdlib.h>
+#include <limits.h>
+
+#ifdef _WIN32
+	// Thanks Microsoft, but I know how to use strncpy().
+	#pragma warning(disable:4996)
+#endif
+
+class MainWindow : public FXMainWindow {
+	FXDECLARE(MainWindow)
+	
+public:
+	enum {
+		ID_FIRST = FXMainWindow::ID_LAST,
+		ID_CONNECT,
+		ID_DISCONNECT,
+		ID_RESCAN,
+		ID_SEND_OUTPUT_REPORT,
+		ID_SEND_FEATURE_REPORT,
+		ID_GET_FEATURE_REPORT,
+		ID_CLEAR,
+		ID_TIMER,
+		ID_MAC_TIMER,
+		ID_LAST,
+	};
+	
+private:
+	FXList *device_list;
+	FXButton *connect_button;
+	FXButton *disconnect_button;
+	FXButton *rescan_button;
+	FXButton *output_button;
+	FXLabel *connected_label;
+	FXTextField *output_text;
+	FXTextField *output_len;
+	FXButton *feature_button;
+	FXButton *get_feature_button;
+	FXTextField *feature_text;
+	FXTextField *feature_len;
+	FXTextField *get_feature_text;
+	FXText *input_text;
+	FXFont *title_font;
+	
+	struct hid_device_info *devices;
+	hid_device *connected_device;
+	size_t getDataFromTextField(FXTextField *tf, char *buf, size_t len);
+	int getLengthFromTextField(FXTextField *tf);
+
+
+protected:
+	MainWindow() {};
+public:
+	MainWindow(FXApp *a);
+	~MainWindow();
+	virtual void create();
+	
+	long onConnect(FXObject *sender, FXSelector sel, void *ptr);
+	long onDisconnect(FXObject *sender, FXSelector sel, void *ptr);
+	long onRescan(FXObject *sender, FXSelector sel, void *ptr);
+	long onSendOutputReport(FXObject *sender, FXSelector sel, void *ptr);
+	long onSendFeatureReport(FXObject *sender, FXSelector sel, void *ptr);
+	long onGetFeatureReport(FXObject *sender, FXSelector sel, void *ptr);
+	long onClear(FXObject *sender, FXSelector sel, void *ptr);
+	long onTimeout(FXObject *sender, FXSelector sel, void *ptr);
+	long onMacTimeout(FXObject *sender, FXSelector sel, void *ptr);
+};
+
+// FOX 1.7 changes the timeouts to all be nanoseconds.
+// Fox 1.6 had all timeouts as milliseconds.
+#if (FOX_MINOR >= 7)
+	const int timeout_scalar = 1000*1000;
+#else
+	const int timeout_scalar = 1;
+#endif
+
+FXMainWindow *g_main_window;
+
+
+FXDEFMAP(MainWindow) MainWindowMap [] = {
+	FXMAPFUNC(SEL_COMMAND, MainWindow::ID_CONNECT, MainWindow::onConnect ),
+	FXMAPFUNC(SEL_COMMAND, MainWindow::ID_DISCONNECT, MainWindow::onDisconnect ),
+	FXMAPFUNC(SEL_COMMAND, MainWindow::ID_RESCAN, MainWindow::onRescan ),
+	FXMAPFUNC(SEL_COMMAND, MainWindow::ID_SEND_OUTPUT_REPORT, MainWindow::onSendOutputReport ),
+	FXMAPFUNC(SEL_COMMAND, MainWindow::ID_SEND_FEATURE_REPORT, MainWindow::onSendFeatureReport ),
+	FXMAPFUNC(SEL_COMMAND, MainWindow::ID_GET_FEATURE_REPORT, MainWindow::onGetFeatureReport ),
+	FXMAPFUNC(SEL_COMMAND, MainWindow::ID_CLEAR, MainWindow::onClear ),
+	FXMAPFUNC(SEL_TIMEOUT, MainWindow::ID_TIMER, MainWindow::onTimeout ),
+	FXMAPFUNC(SEL_TIMEOUT, MainWindow::ID_MAC_TIMER, MainWindow::onMacTimeout ),
+};
+
+FXIMPLEMENT(MainWindow, FXMainWindow, MainWindowMap, ARRAYNUMBER(MainWindowMap));
+
+MainWindow::MainWindow(FXApp *app)
+	: FXMainWindow(app, "HIDAPI Test Application", NULL, NULL, DECOR_ALL, 200,100, 425,700)
+{
+	devices = NULL;
+	connected_device = NULL;
+
+	FXVerticalFrame *vf = new FXVerticalFrame(this, LAYOUT_FILL_Y|LAYOUT_FILL_X);
+
+	FXLabel *label = new FXLabel(vf, "HIDAPI Test Tool");
+	title_font = new FXFont(getApp(), "Arial", 14, FXFont::Bold);
+	label->setFont(title_font);
+	
+	new FXLabel(vf,
+		"Select a device and press Connect.", NULL, JUSTIFY_LEFT);
+	new FXLabel(vf,
+		"Output data bytes can be entered in the Output section, \n"
+		"separated by space, comma or brackets. Data starting with 0x\n"
+		"is treated as hex. Data beginning with a 0 is treated as \n"
+		"octal. All other data is treated as decimal.", NULL, JUSTIFY_LEFT);
+	new FXLabel(vf,
+		"Data received from the device appears in the Input section.",
+		NULL, JUSTIFY_LEFT);
+	new FXLabel(vf,
+		"Optionally, a report length may be specified. Extra bytes are\n"
+		"padded with zeros. If no length is specified, the length is \n"
+		"inferred from the data.",
+		NULL, JUSTIFY_LEFT);
+	new FXLabel(vf, "");
+
+	// Device List and Connect/Disconnect buttons
+	FXHorizontalFrame *hf = new FXHorizontalFrame(vf, LAYOUT_FILL_X);
+	//device_list = new FXList(new FXHorizontalFrame(hf,FRAME_SUNKEN|FRAME_THICK, 0,0,0,0, 0,0,0,0), NULL, 0, LISTBOX_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_Y|LAYOUT_FIX_WIDTH|LAYOUT_FIX_HEIGHT, 0,0,300,200);
+	device_list = new FXList(new FXHorizontalFrame(hf,FRAME_SUNKEN|FRAME_THICK|LAYOUT_FILL_X|LAYOUT_FILL_Y, 0,0,0,0, 0,0,0,0), NULL, 0, LISTBOX_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_Y, 0,0,300,200);
+	FXVerticalFrame *buttonVF = new FXVerticalFrame(hf);
+	connect_button = new FXButton(buttonVF, "Connect", NULL, this, ID_CONNECT, BUTTON_NORMAL|LAYOUT_FILL_X);
+	disconnect_button = new FXButton(buttonVF, "Disconnect", NULL, this, ID_DISCONNECT, BUTTON_NORMAL|LAYOUT_FILL_X);
+	disconnect_button->disable();
+	rescan_button = new FXButton(buttonVF, "Re-Scan devices", NULL, this, ID_RESCAN, BUTTON_NORMAL|LAYOUT_FILL_X);
+	new FXHorizontalFrame(buttonVF, 0, 0,0,0,0, 0,0,50,0);
+
+	connected_label = new FXLabel(vf, "Disconnected");
+	
+	new FXHorizontalFrame(vf);
+	
+	// Output Group Box
+	FXGroupBox *gb = new FXGroupBox(vf, "Output", FRAME_GROOVE|LAYOUT_FILL_X);
+	FXMatrix *matrix = new FXMatrix(gb, 3, MATRIX_BY_COLUMNS|LAYOUT_FILL_X);
+	new FXLabel(matrix, "Data");
+	new FXLabel(matrix, "Length");
+	new FXLabel(matrix, "");
+
+	//hf = new FXHorizontalFrame(gb, LAYOUT_FILL_X);
+	output_text = new FXTextField(matrix, 30, NULL, 0, TEXTFIELD_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_COLUMN);
+	output_text->setText("1 0x81 0");
+	output_len = new FXTextField(matrix, 5, NULL, 0, TEXTFIELD_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_COLUMN);
+	output_button = new FXButton(matrix, "Send Output Report", NULL, this, ID_SEND_OUTPUT_REPORT, BUTTON_NORMAL|LAYOUT_FILL_X);
+	output_button->disable();
+	//new FXHorizontalFrame(matrix, LAYOUT_FILL_X);
+
+	//hf = new FXHorizontalFrame(gb, LAYOUT_FILL_X);
+	feature_text = new FXTextField(matrix, 30, NULL, 0, TEXTFIELD_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_COLUMN);
+	feature_len = new FXTextField(matrix, 5, NULL, 0, TEXTFIELD_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_COLUMN);
+	feature_button = new FXButton(matrix, "Send Feature Report", NULL, this, ID_SEND_FEATURE_REPORT, BUTTON_NORMAL|LAYOUT_FILL_X);
+	feature_button->disable();
+
+	get_feature_text = new FXTextField(matrix, 30, NULL, 0, TEXTFIELD_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_COLUMN);
+	new FXWindow(matrix);
+	get_feature_button = new FXButton(matrix, "Get Feature Report", NULL, this, ID_GET_FEATURE_REPORT, BUTTON_NORMAL|LAYOUT_FILL_X);
+	get_feature_button->disable();
+
+
+	// Input Group Box
+	gb = new FXGroupBox(vf, "Input", FRAME_GROOVE|LAYOUT_FILL_X|LAYOUT_FILL_Y);
+	FXVerticalFrame *innerVF = new FXVerticalFrame(gb, LAYOUT_FILL_X|LAYOUT_FILL_Y);
+	input_text = new FXText(new FXHorizontalFrame(innerVF,LAYOUT_FILL_X|LAYOUT_FILL_Y|FRAME_SUNKEN|FRAME_THICK, 0,0,0,0, 0,0,0,0), NULL, 0, LAYOUT_FILL_X|LAYOUT_FILL_Y);
+	input_text->setEditable(false);
+	new FXButton(innerVF, "Clear", NULL, this, ID_CLEAR, BUTTON_NORMAL|LAYOUT_RIGHT);
+	
+
+}
+
+MainWindow::~MainWindow()
+{
+	if (connected_device)
+		hid_close(connected_device);
+	hid_exit();
+	delete title_font;
+}
+
+void
+MainWindow::create()
+{
+	FXMainWindow::create();
+	show();
+
+	onRescan(NULL, 0, NULL);
+	
+
+#ifdef __APPLE__
+	init_apple_message_system();
+#endif
+	
+	getApp()->addTimeout(this, ID_MAC_TIMER,
+		50 * timeout_scalar /*50ms*/);
+}
+
+long
+MainWindow::onConnect(FXObject *sender, FXSelector sel, void *ptr)
+{
+	if (connected_device != NULL)
+		return 1;
+	
+	FXint cur_item = device_list->getCurrentItem();
+	if (cur_item < 0)
+		return -1;
+	FXListItem *item = device_list->getItem(cur_item);
+	if (!item)
+		return -1;
+	struct hid_device_info *device_info = (struct hid_device_info*) item->getData();
+	if (!device_info)
+		return -1;
+	
+	connected_device =  hid_open_path(device_info->path);
+	
+	if (!connected_device) {
+		FXMessageBox::error(this, MBOX_OK, "Device Error", "Unable To Connect to Device");
+		return -1;
+	}
+	
+	hid_set_nonblocking(connected_device, 1);
+
+	getApp()->addTimeout(this, ID_TIMER,
+		5 * timeout_scalar /*5ms*/);
+	
+	FXString s;
+	s.format("Connected to: %04hx:%04hx -", device_info->vendor_id, device_info->product_id);
+	s += FXString(" ") + device_info->manufacturer_string;
+	s += FXString(" ") + device_info->product_string;
+	connected_label->setText(s);
+	output_button->enable();
+	feature_button->enable();
+	get_feature_button->enable();
+	connect_button->disable();
+	disconnect_button->enable();
+	input_text->setText("");
+
+
+	return 1;
+}
+
+long
+MainWindow::onDisconnect(FXObject *sender, FXSelector sel, void *ptr)
+{
+	hid_close(connected_device);
+	connected_device = NULL;
+	connected_label->setText("Disconnected");
+	output_button->disable();
+	feature_button->disable();
+	get_feature_button->disable();
+	connect_button->enable();
+	disconnect_button->disable();
+
+	getApp()->removeTimeout(this, ID_TIMER);
+	
+	return 1;
+}
+
+long
+MainWindow::onRescan(FXObject *sender, FXSelector sel, void *ptr)
+{
+	struct hid_device_info *cur_dev;
+
+	device_list->clearItems();
+	
+	// List the Devices
+	hid_free_enumeration(devices);
+	devices = hid_enumerate(0x0, 0x0);
+	cur_dev = devices;	
+	while (cur_dev) {
+		// Add it to the List Box.
+		FXString s;
+		FXString usage_str;
+		s.format("%04hx:%04hx -", cur_dev->vendor_id, cur_dev->product_id);
+		s += FXString(" ") + cur_dev->manufacturer_string;
+		s += FXString(" ") + cur_dev->product_string;
+		usage_str.format(" (usage: %04hx:%04hx) ", cur_dev->usage_page, cur_dev->usage);
+		s += usage_str;
+		FXListItem *li = new FXListItem(s, NULL, cur_dev);
+		device_list->appendItem(li);
+		
+		cur_dev = cur_dev->next;
+	}
+
+	if (device_list->getNumItems() == 0)
+		device_list->appendItem("*** No Devices Connected ***");
+	else {
+		device_list->selectItem(0);
+	}
+
+	return 1;
+}
+
+size_t
+MainWindow::getDataFromTextField(FXTextField *tf, char *buf, size_t len)
+{
+	const char *delim = " ,{}\t\r\n";
+	FXString data = tf->getText();
+	const FXchar *d = data.text();
+	size_t i = 0;
+	
+	// Copy the string from the GUI.
+	size_t sz = strlen(d);
+	char *str = (char*) malloc(sz+1);
+	strcpy(str, d);
+	
+	// For each token in the string, parse and store in buf[].
+	char *token = strtok(str, delim);
+	while (token) {
+		char *endptr;
+		long int val = strtol(token, &endptr, 0);
+		buf[i++] = val;
+		token = strtok(NULL, delim);
+	}
+	
+	free(str);
+	return i;
+}
+
+/* getLengthFromTextField()
+   Returns length:
+	 0: empty text field
+	>0: valid length
+	-1: invalid length */
+int
+MainWindow::getLengthFromTextField(FXTextField *tf)
+{
+	long int len;
+	FXString str = tf->getText();
+	size_t sz = str.length();
+
+	if (sz > 0) {
+		char *endptr;
+		len = strtol(str.text(), &endptr, 0);
+		if (endptr != str.text() && *endptr == '\0') {
+			if (len <= 0) {
+				FXMessageBox::error(this, MBOX_OK, "Invalid length", "Enter a length greater than zero.");
+				return -1;
+			}
+			return len;
+		}
+		else
+			return -1;
+	}
+
+	return 0;
+}
+
+long
+MainWindow::onSendOutputReport(FXObject *sender, FXSelector sel, void *ptr)
+{
+	char buf[256];
+	size_t data_len, len;
+	int textfield_len;
+
+	memset(buf, 0x0, sizeof(buf));
+	textfield_len = getLengthFromTextField(output_len);
+	data_len = getDataFromTextField(output_text, buf, sizeof(buf));
+
+	if (textfield_len < 0) {
+		FXMessageBox::error(this, MBOX_OK, "Invalid length", "Length field is invalid. Please enter a number in hex, octal, or decimal.");
+		return 1;
+	}
+
+	if (textfield_len > sizeof(buf)) {
+		FXMessageBox::error(this, MBOX_OK, "Invalid length", "Length field is too long.");
+		return 1;
+	}
+
+	len = (textfield_len)? textfield_len: data_len;
+
+	int res = hid_write(connected_device, (const unsigned char*)buf, len);
+	if (res < 0) {
+		FXMessageBox::error(this, MBOX_OK, "Error Writing", "Could not write to device. Error reported was: %ls", hid_error(connected_device));
+	}
+	
+	return 1;
+}
+
+long
+MainWindow::onSendFeatureReport(FXObject *sender, FXSelector sel, void *ptr)
+{
+	char buf[256];
+	size_t data_len, len;
+	int textfield_len;
+
+	memset(buf, 0x0, sizeof(buf));
+	textfield_len = getLengthFromTextField(feature_len);
+	data_len = getDataFromTextField(feature_text, buf, sizeof(buf));
+
+	if (textfield_len < 0) {
+		FXMessageBox::error(this, MBOX_OK, "Invalid length", "Length field is invalid. Please enter a number in hex, octal, or decimal.");
+		return 1;
+	}
+
+	if (textfield_len > sizeof(buf)) {
+		FXMessageBox::error(this, MBOX_OK, "Invalid length", "Length field is too long.");
+		return 1;
+	}
+
+	len = (textfield_len)? textfield_len: data_len;
+
+	int res = hid_send_feature_report(connected_device, (const unsigned char*)buf, len); 
+	if (res < 0) {
+		FXMessageBox::error(this, MBOX_OK, "Error Writing", "Could not send feature report to device. Error reported was: %ls", hid_error(connected_device));
+	}
+
+	return 1;
+}
+
+long
+MainWindow::onGetFeatureReport(FXObject *sender, FXSelector sel, void *ptr)
+{
+	char buf[256];
+	size_t len;
+
+	memset(buf, 0x0, sizeof(buf));
+	len = getDataFromTextField(get_feature_text, buf, sizeof(buf));
+
+	if (len != 1) {
+		FXMessageBox::error(this, MBOX_OK, "Too many numbers", "Enter only a single report number in the text field");
+	}
+
+	int res = hid_get_feature_report(connected_device, (unsigned char*)buf, sizeof(buf));
+	if (res < 0) {
+		FXMessageBox::error(this, MBOX_OK, "Error Getting Report", "Could not get feature report from device. Error reported was: %ls", hid_error(connected_device));
+	}
+
+	if (res > 0) {
+		FXString s;
+		s.format("Returned Feature Report. %d bytes:\n", res);
+		for (int i = 0; i < res; i++) {
+			FXString t;
+			t.format("%02hhx ", buf[i]);
+			s += t;
+			if ((i+1) % 4 == 0)
+				s += " ";
+			if ((i+1) % 16 == 0)
+				s += "\n";
+		}
+		s += "\n";
+		input_text->appendText(s);
+		input_text->setBottomLine(INT_MAX);
+	}
+	
+	return 1;
+}
+
+long
+MainWindow::onClear(FXObject *sender, FXSelector sel, void *ptr)
+{
+	input_text->setText("");
+	return 1;
+}
+
+long
+MainWindow::onTimeout(FXObject *sender, FXSelector sel, void *ptr)
+{
+	unsigned char buf[256];
+	int res = hid_read(connected_device, buf, sizeof(buf));
+	
+	if (res > 0) {
+		FXString s;
+		s.format("Received %d bytes:\n", res);
+		for (int i = 0; i < res; i++) {
+			FXString t;
+			t.format("%02hhx ", buf[i]);
+			s += t;
+			if ((i+1) % 4 == 0)
+				s += " ";
+			if ((i+1) % 16 == 0)
+				s += "\n";
+		}
+		s += "\n";
+		input_text->appendText(s);
+		input_text->setBottomLine(INT_MAX);
+	}
+	if (res < 0) {
+		input_text->appendText("hid_read() returned error\n");
+		input_text->setBottomLine(INT_MAX);
+	}
+
+	getApp()->addTimeout(this, ID_TIMER,
+		5 * timeout_scalar /*5ms*/);
+	return 1;
+}
+
+long
+MainWindow::onMacTimeout(FXObject *sender, FXSelector sel, void *ptr)
+{
+#ifdef __APPLE__
+	check_apple_events();
+	
+	getApp()->addTimeout(this, ID_MAC_TIMER,
+		50 * timeout_scalar /*50ms*/);
+#endif
+
+	return 1;
+}
+
+int main(int argc, char **argv)
+{
+	FXApp app("HIDAPI Test Application", "Signal 11 Software");
+	app.init(argc, argv);
+	g_main_window = new MainWindow(&app);
+	app.create();
+	app.run();
+	return 0;
+}
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/testgui.sln b/uf2-samdx1/lib/uf2/hidapi/testgui/testgui.sln
new file mode 100644
index 00000000..56be6c6a
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/testgui.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 10.00
+# Visual C++ Express 2008
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "testgui", "testgui.vcproj", "{08769AC3-785A-4DDC-BFC7-1775414B7AB7}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Win32 = Debug|Win32
+		Release|Win32 = Release|Win32
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{08769AC3-785A-4DDC-BFC7-1775414B7AB7}.Debug|Win32.ActiveCfg = Debug|Win32
+		{08769AC3-785A-4DDC-BFC7-1775414B7AB7}.Debug|Win32.Build.0 = Debug|Win32
+		{08769AC3-785A-4DDC-BFC7-1775414B7AB7}.Release|Win32.ActiveCfg = Release|Win32
+		{08769AC3-785A-4DDC-BFC7-1775414B7AB7}.Release|Win32.Build.0 = Release|Win32
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/uf2-samdx1/lib/uf2/hidapi/testgui/testgui.vcproj b/uf2-samdx1/lib/uf2/hidapi/testgui/testgui.vcproj
new file mode 100644
index 00000000..0f73a013
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/testgui/testgui.vcproj
@@ -0,0 +1,217 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<VisualStudioProject
+	ProjectType="Visual C++"
+	Version="9.00"
+	Name="testgui"
+	ProjectGUID="{08769AC3-785A-4DDC-BFC7-1775414B7AB7}"
+	RootNamespace="testgui"
+	Keyword="Win32Proj"
+	TargetFrameworkVersion="196613"
+	>
+	<Platforms>
+		<Platform
+			Name="Win32"
+		/>
+	</Platforms>
+	<ToolFiles>
+	</ToolFiles>
+	<Configurations>
+		<Configuration
+			Name="Debug|Win32"
+			OutputDirectory="$(SolutionDir)$(ConfigurationName)"
+			IntermediateDirectory="$(ConfigurationName)"
+			ConfigurationType="1"
+			CharacterSet="1"
+			>
+			<Tool
+				Name="VCPreBuildEventTool"
+			/>
+			<Tool
+				Name="VCCustomBuildTool"
+			/>
+			<Tool
+				Name="VCXMLDataGeneratorTool"
+			/>
+			<Tool
+				Name="VCWebServiceProxyGeneratorTool"
+			/>
+			<Tool
+				Name="VCMIDLTool"
+			/>
+			<Tool
+				Name="VCCLCompilerTool"
+				Optimization="0"
+				AdditionalIncludeDirectories="&quot;..\..\hidapi-externals\fox\include&quot;;..\hidapi"
+				PreprocessorDefinitions="WIN32;_DEBUG;_WINDOWS"
+				MinimalRebuild="true"
+				BasicRuntimeChecks="3"
+				RuntimeLibrary="3"
+				UsePrecompiledHeader="0"
+				WarningLevel="3"
+				DebugInformationFormat="4"
+			/>
+			<Tool
+				Name="VCManagedResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCPreLinkEventTool"
+			/>
+			<Tool
+				Name="VCLinkerTool"
+				AdditionalDependencies="setupapi.lib fox-1.6.lib"
+				OutputFile="$(ProjectName).exe"
+				LinkIncremental="2"
+				AdditionalLibraryDirectories="..\hidapi\objfre_wxp_x86\i386;&quot;..\..\hidapi-externals\fox\lib&quot;"
+				GenerateDebugInformation="true"
+				SubSystem="2"
+				EntryPointSymbol="mainCRTStartup"
+				TargetMachine="1"
+			/>
+			<Tool
+				Name="VCALinkTool"
+			/>
+			<Tool
+				Name="VCManifestTool"
+			/>
+			<Tool
+				Name="VCXDCMakeTool"
+			/>
+			<Tool
+				Name="VCBscMakeTool"
+			/>
+			<Tool
+				Name="VCFxCopTool"
+			/>
+			<Tool
+				Name="VCAppVerifierTool"
+			/>
+			<Tool
+				Name="VCPostBuildEventTool"
+				CommandLine=""
+			/>
+		</Configuration>
+		<Configuration
+			Name="Release|Win32"
+			OutputDirectory="$(SolutionDir)$(ConfigurationName)"
+			IntermediateDirectory="$(ConfigurationName)"
+			ConfigurationType="1"
+			CharacterSet="1"
+			WholeProgramOptimization="1"
+			>
+			<Tool
+				Name="VCPreBuildEventTool"
+			/>
+			<Tool
+				Name="VCCustomBuildTool"
+			/>
+			<Tool
+				Name="VCXMLDataGeneratorTool"
+			/>
+			<Tool
+				Name="VCWebServiceProxyGeneratorTool"
+			/>
+			<Tool
+				Name="VCMIDLTool"
+			/>
+			<Tool
+				Name="VCCLCompilerTool"
+				Optimization="2"
+				EnableIntrinsicFunctions="true"
+				AdditionalIncludeDirectories="&quot;..\..\hidapi-externals\fox\include&quot;;..\hidapi"
+				PreprocessorDefinitions="WIN32;NDEBUG;_WINDOWS"
+				RuntimeLibrary="2"
+				EnableFunctionLevelLinking="true"
+				UsePrecompiledHeader="0"
+				WarningLevel="3"
+				DebugInformationFormat="3"
+			/>
+			<Tool
+				Name="VCManagedResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCPreLinkEventTool"
+			/>
+			<Tool
+				Name="VCLinkerTool"
+				AdditionalDependencies="setupapi.lib fox-1.6.lib"
+				OutputFile="$(ProjectName).exe"
+				LinkIncremental="1"
+				AdditionalLibraryDirectories="..\hidapi\objfre_wxp_x86\i386;&quot;..\..\hidapi-externals\fox\lib&quot;"
+				GenerateDebugInformation="true"
+				SubSystem="2"
+				OptimizeReferences="2"
+				EnableCOMDATFolding="2"
+				EntryPointSymbol="mainCRTStartup"
+				TargetMachine="1"
+			/>
+			<Tool
+				Name="VCALinkTool"
+			/>
+			<Tool
+				Name="VCManifestTool"
+			/>
+			<Tool
+				Name="VCXDCMakeTool"
+			/>
+			<Tool
+				Name="VCBscMakeTool"
+			/>
+			<Tool
+				Name="VCFxCopTool"
+			/>
+			<Tool
+				Name="VCAppVerifierTool"
+			/>
+			<Tool
+				Name="VCPostBuildEventTool"
+				CommandLine=""
+			/>
+		</Configuration>
+	</Configurations>
+	<References>
+	</References>
+	<Files>
+		<Filter
+			Name="Source Files"
+			Filter="cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx"
+			UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}"
+			>
+			<File
+				RelativePath="..\windows\hid.c"
+				>
+			</File>
+			<File
+				RelativePath=".\test.cpp"
+				>
+			</File>
+		</Filter>
+		<Filter
+			Name="Header Files"
+			Filter="h;hpp;hxx;hm;inl;inc;xsd"
+			UniqueIdentifier="{93995380-89BD-4b04-88EB-625FBE52EBFB}"
+			>
+			<File
+				RelativePath="..\hidapi\hidapi.h"
+				>
+			</File>
+		</Filter>
+		<Filter
+			Name="Resource Files"
+			Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav"
+			UniqueIdentifier="{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}"
+			>
+		</Filter>
+		<File
+			RelativePath=".\ReadMe.txt"
+			>
+		</File>
+	</Files>
+	<Globals>
+	</Globals>
+</VisualStudioProject>
diff --git a/uf2-samdx1/lib/uf2/hidapi/udev/99-hid.rules b/uf2-samdx1/lib/uf2/hidapi/udev/99-hid.rules
new file mode 100644
index 00000000..0385f50b
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/udev/99-hid.rules
@@ -0,0 +1,33 @@
+# This is a sample udev file for HIDAPI devices which changes the permissions
+# to 0666 (world readable/writable) for a specified device on Linux systems.
+
+
+# If you are using the libusb implementation of hidapi (libusb/hid.c), then
+# use something like the following line, substituting the VID and PID with
+# those of your device. Note that for kernels before 2.6.24, you will need
+# to substitute "usb" with "usb_device". It shouldn't hurt to use two lines
+# (one each way) for compatibility with older systems.
+
+# HIDAPI/libusb
+SUBSYSTEM=="usb", ATTRS{idVendor}=="04d8", ATTRS{idProduct}=="003f", MODE="0666"
+
+
+# If you are using the hidraw implementation (linux/hid.c), then do something
+# like the following, substituting the VID and PID with your device. Busnum 1
+# is USB.
+
+# HIDAPI/hidraw
+KERNEL=="hidraw*", ATTRS{busnum}=="1", ATTRS{idVendor}=="04d8", ATTRS{idProduct}=="003f", MODE="0666"
+
+# Once done, optionally rename this file for your device, and drop it into
+# /etc/udev/rules.d and unplug and re-plug your device. This is all that is
+# necessary to see the new permissions. Udev does not have to be restarted.
+
+# Note that the hexadecimal values for VID and PID are case sensitive and
+# must be lower case.
+
+# If you think permissions of 0666 are too loose, then see:
+# http://reactivated.net/writing_udev_rules.html for more information on finer
+# grained permission setting. For example, it might be sufficient to just
+# set the group or user owner for specific devices (for example the plugdev
+# group on some systems).
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/.gitignore b/uf2-samdx1/lib/uf2/hidapi/windows/.gitignore
new file mode 100644
index 00000000..a3f6d875
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/.gitignore
@@ -0,0 +1,15 @@
+Debug
+Release
+*.exp
+*.ilk
+*.lib
+*.suo
+*.vcproj.*
+*.ncb
+*.suo
+*.dll
+*.pdb
+.deps
+.libs
+*.lo
+*.la
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/Makefile-manual b/uf2-samdx1/lib/uf2/hidapi/windows/Makefile-manual
new file mode 100644
index 00000000..ac471d66
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/Makefile-manual
@@ -0,0 +1,14 @@
+
+
+OS=$(shell uname)
+
+ifneq (,$(findstring MINGW,$(OS)))
+	FILE=Makefile.mingw
+endif
+
+ifeq ($(FILE), )
+all:
+	$(error Your platform ${OS} is not supported at this time.)
+endif
+
+include $(FILE)
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/Makefile.am b/uf2-samdx1/lib/uf2/hidapi/windows/Makefile.am
new file mode 100644
index 00000000..97e261ac
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/Makefile.am
@@ -0,0 +1,16 @@
+lib_LTLIBRARIES = libhidapi.la
+libhidapi_la_SOURCES = hid.c
+libhidapi_la_LDFLAGS = $(LTLDFLAGS)
+AM_CPPFLAGS = -I$(top_srcdir)/hidapi/
+libhidapi_la_LIBADD = $(LIBS)
+
+hdrdir = $(includedir)/hidapi
+hdr_HEADERS = $(top_srcdir)/hidapi/hidapi.h
+
+EXTRA_DIST = \
+  ddk_build \
+  hidapi.vcproj \
+  hidtest.vcproj \
+  Makefile-manual \
+  Makefile.mingw \
+  hidapi.sln
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/Makefile.mingw b/uf2-samdx1/lib/uf2/hidapi/windows/Makefile.mingw
new file mode 100644
index 00000000..b8000041
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/Makefile.mingw
@@ -0,0 +1,35 @@
+###########################################
+# Simple Makefile for HIDAPI test program
+#
+# Alan Ott
+# Signal 11 Software
+# 2010-06-01
+###########################################
+
+all: hidtest libhidapi.dll
+
+CC=gcc
+CXX=g++
+COBJS=hid.o
+CPPOBJS=../hidtest/hidtest.o
+OBJS=$(COBJS) $(CPPOBJS)
+CFLAGS=-I../hidapi -g -c
+LIBS= -lsetupapi
+DLL_LDFLAGS = -mwindows -lsetupapi
+
+hidtest: $(OBJS)
+	g++ -g $^ $(LIBS) -o hidtest
+
+libhidapi.dll: $(OBJS)
+	$(CC) -g $^ $(DLL_LDFLAGS) -o libhidapi.dll
+
+$(COBJS): %.o: %.c
+	$(CC) $(CFLAGS) $< -o $@
+
+$(CPPOBJS): %.o: %.cpp
+	$(CXX) $(CFLAGS) $< -o $@
+
+clean:
+	rm *.o ../hidtest/*.o hidtest.exe
+
+.PHONY: clean
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/ddk_build/.gitignore b/uf2-samdx1/lib/uf2/hidapi/windows/ddk_build/.gitignore
new file mode 100644
index 00000000..823ff0b2
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/ddk_build/.gitignore
@@ -0,0 +1,2 @@
+*.log
+obj*_*_*
\ No newline at end of file
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/ddk_build/hidapi.def b/uf2-samdx1/lib/uf2/hidapi/windows/ddk_build/hidapi.def
new file mode 100644
index 00000000..05e35afd
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/ddk_build/hidapi.def
@@ -0,0 +1,17 @@
+LIBRARY   hidapi
+EXPORTS
+   hid_open    @1
+   hid_write   @2
+   hid_read    @3
+   hid_close   @4
+   hid_get_product_string @5
+   hid_get_manufacturer_string @6
+   hid_get_serial_number_string @7
+   hid_get_indexed_string @8
+   hid_error @9
+   hid_set_nonblocking @10
+   hid_enumerate @11
+   hid_open_path @12
+   hid_send_feature_report @13
+   hid_get_feature_report @14
+   
\ No newline at end of file
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/ddk_build/sources b/uf2-samdx1/lib/uf2/hidapi/windows/ddk_build/sources
new file mode 100644
index 00000000..7f06a096
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/ddk_build/sources
@@ -0,0 +1,23 @@
+TARGETNAME=hidapi
+TARGETTYPE=DYNLINK
+UMTYPE=console
+UMENTRY=main
+
+MSC_WARNING_LEVEL=/W3 /WX
+
+TARGETLIBS=$(SDK_LIB_PATH)\hid.lib \
+           $(SDK_LIB_PATH)\setupapi.lib \
+           $(SDK_LIB_PATH)\kernel32.lib \
+           $(SDK_LIB_PATH)\comdlg32.lib
+
+USE_MSVCRT=1
+
+INCLUDES= ..\..\hidapi
+SOURCES= ..\hid.c \
+
+
+TARGET_DESTINATION=retail
+
+MUI=0
+MUI_COMMENT="HID Interface DLL"
+
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/hid.c b/uf2-samdx1/lib/uf2/hidapi/windows/hid.c
new file mode 100644
index 00000000..86810d7e
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/hid.c
@@ -0,0 +1,944 @@
+/*******************************************************
+ HIDAPI - Multi-Platform library for
+ communication with HID devices.
+
+ Alan Ott
+ Signal 11 Software
+
+ 8/22/2009
+
+ Copyright 2009, All Rights Reserved.
+ 
+ At the discretion of the user of this library,
+ this software may be licensed under the terms of the
+ GNU General Public License v3, a BSD-Style license, or the
+ original HIDAPI license as outlined in the LICENSE.txt,
+ LICENSE-gpl3.txt, LICENSE-bsd.txt, and LICENSE-orig.txt
+ files located at the root of the source distribution.
+ These files may also be found in the public source
+ code repository located at:
+        http://github.com/signal11/hidapi .
+********************************************************/
+
+#include <windows.h>
+
+#ifndef _NTDEF_
+typedef LONG NTSTATUS;
+#endif
+
+#ifdef __MINGW32__
+#include <ntdef.h>
+#include <winbase.h>
+#endif
+
+#ifdef __CYGWIN__
+#include <ntdef.h>
+#define _wcsdup wcsdup
+#endif
+
+/* The maximum number of characters that can be passed into the
+   HidD_Get*String() functions without it failing.*/
+#define MAX_STRING_WCHARS 0xFFF
+
+/*#define HIDAPI_USE_DDK*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+	#include <setupapi.h>
+	#include <winioctl.h>
+	#ifdef HIDAPI_USE_DDK
+		#include <hidsdi.h>
+	#endif
+
+	/* Copied from inc/ddk/hidclass.h, part of the Windows DDK. */
+	#define HID_OUT_CTL_CODE(id)  \
+		CTL_CODE(FILE_DEVICE_KEYBOARD, (id), METHOD_OUT_DIRECT, FILE_ANY_ACCESS)
+	#define IOCTL_HID_GET_FEATURE                   HID_OUT_CTL_CODE(100)
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+
+
+#include "hidapi.h"
+
+#undef MIN
+#define MIN(x,y) ((x) < (y)? (x): (y))
+
+#ifdef _MSC_VER
+	/* Thanks Microsoft, but I know how to use strncpy(). */
+	#pragma warning(disable:4996)
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef HIDAPI_USE_DDK
+	/* Since we're not building with the DDK, and the HID header
+	   files aren't part of the SDK, we have to define all this
+	   stuff here. In lookup_functions(), the function pointers
+	   defined below are set. */
+	typedef struct _HIDD_ATTRIBUTES{
+		ULONG Size;
+		USHORT VendorID;
+		USHORT ProductID;
+		USHORT VersionNumber;
+	} HIDD_ATTRIBUTES, *PHIDD_ATTRIBUTES;
+
+	typedef USHORT USAGE;
+	typedef struct _HIDP_CAPS {
+		USAGE Usage;
+		USAGE UsagePage;
+		USHORT InputReportByteLength;
+		USHORT OutputReportByteLength;
+		USHORT FeatureReportByteLength;
+		USHORT Reserved[17];
+		USHORT fields_not_used_by_hidapi[10];
+	} HIDP_CAPS, *PHIDP_CAPS;
+	typedef void* PHIDP_PREPARSED_DATA;
+	#define HIDP_STATUS_SUCCESS 0x110000
+
+	typedef BOOLEAN (__stdcall *HidD_GetAttributes_)(HANDLE device, PHIDD_ATTRIBUTES attrib);
+	typedef BOOLEAN (__stdcall *HidD_GetSerialNumberString_)(HANDLE device, PVOID buffer, ULONG buffer_len);
+	typedef BOOLEAN (__stdcall *HidD_GetManufacturerString_)(HANDLE handle, PVOID buffer, ULONG buffer_len);
+	typedef BOOLEAN (__stdcall *HidD_GetProductString_)(HANDLE handle, PVOID buffer, ULONG buffer_len);
+	typedef BOOLEAN (__stdcall *HidD_SetFeature_)(HANDLE handle, PVOID data, ULONG length);
+	typedef BOOLEAN (__stdcall *HidD_GetFeature_)(HANDLE handle, PVOID data, ULONG length);
+	typedef BOOLEAN (__stdcall *HidD_GetIndexedString_)(HANDLE handle, ULONG string_index, PVOID buffer, ULONG buffer_len);
+	typedef BOOLEAN (__stdcall *HidD_GetPreparsedData_)(HANDLE handle, PHIDP_PREPARSED_DATA *preparsed_data);
+	typedef BOOLEAN (__stdcall *HidD_FreePreparsedData_)(PHIDP_PREPARSED_DATA preparsed_data);
+	typedef NTSTATUS (__stdcall *HidP_GetCaps_)(PHIDP_PREPARSED_DATA preparsed_data, HIDP_CAPS *caps);
+	typedef BOOLEAN (__stdcall *HidD_SetNumInputBuffers_)(HANDLE handle, ULONG number_buffers);
+
+	static HidD_GetAttributes_ HidD_GetAttributes;
+	static HidD_GetSerialNumberString_ HidD_GetSerialNumberString;
+	static HidD_GetManufacturerString_ HidD_GetManufacturerString;
+	static HidD_GetProductString_ HidD_GetProductString;
+	static HidD_SetFeature_ HidD_SetFeature;
+	static HidD_GetFeature_ HidD_GetFeature;
+	static HidD_GetIndexedString_ HidD_GetIndexedString;
+	static HidD_GetPreparsedData_ HidD_GetPreparsedData;
+	static HidD_FreePreparsedData_ HidD_FreePreparsedData;
+	static HidP_GetCaps_ HidP_GetCaps;
+	static HidD_SetNumInputBuffers_ HidD_SetNumInputBuffers;
+
+	static HMODULE lib_handle = NULL;
+	static BOOLEAN initialized = FALSE;
+#endif /* HIDAPI_USE_DDK */
+
+struct hid_device_ {
+		HANDLE device_handle;
+		BOOL blocking;
+		USHORT output_report_length;
+		size_t input_report_length;
+		void *last_error_str;
+		DWORD last_error_num;
+		BOOL read_pending;
+		char *read_buf;
+		OVERLAPPED ol;
+};
+
+static hid_device *new_hid_device()
+{
+	hid_device *dev = (hid_device*) calloc(1, sizeof(hid_device));
+	dev->device_handle = INVALID_HANDLE_VALUE;
+	dev->blocking = TRUE;
+	dev->output_report_length = 0;
+	dev->input_report_length = 0;
+	dev->last_error_str = NULL;
+	dev->last_error_num = 0;
+	dev->read_pending = FALSE;
+	dev->read_buf = NULL;
+	memset(&dev->ol, 0, sizeof(dev->ol));
+	dev->ol.hEvent = CreateEvent(NULL, FALSE, FALSE /*initial state f=nonsignaled*/, NULL);
+
+	return dev;
+}
+
+static void free_hid_device(hid_device *dev)
+{
+	CloseHandle(dev->ol.hEvent);
+	CloseHandle(dev->device_handle);
+	LocalFree(dev->last_error_str);
+	free(dev->read_buf);
+	free(dev);
+}
+
+static void register_error(hid_device *device, const char *op)
+{
+	WCHAR *ptr, *msg;
+
+	FormatMessageW(FORMAT_MESSAGE_ALLOCATE_BUFFER |
+		FORMAT_MESSAGE_FROM_SYSTEM |
+		FORMAT_MESSAGE_IGNORE_INSERTS,
+		NULL,
+		GetLastError(),
+		MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT),
+		(LPVOID)&msg, 0/*sz*/,
+		NULL);
+	
+	/* Get rid of the CR and LF that FormatMessage() sticks at the
+	   end of the message. Thanks Microsoft! */
+	ptr = msg;
+	while (*ptr) {
+		if (*ptr == '\r') {
+			*ptr = 0x0000;
+			break;
+		}
+		ptr++;
+	}
+
+	/* Store the message off in the Device entry so that
+	   the hid_error() function can pick it up. */
+	LocalFree(device->last_error_str);
+	device->last_error_str = msg;
+}
+
+#ifndef HIDAPI_USE_DDK
+static int lookup_functions()
+{
+	lib_handle = LoadLibraryA("hid.dll");
+	if (lib_handle) {
+#define RESOLVE(x) x = (x##_)GetProcAddress(lib_handle, #x); if (!x) return -1;
+		RESOLVE(HidD_GetAttributes);
+		RESOLVE(HidD_GetSerialNumberString);
+		RESOLVE(HidD_GetManufacturerString);
+		RESOLVE(HidD_GetProductString);
+		RESOLVE(HidD_SetFeature);
+		RESOLVE(HidD_GetFeature);
+		RESOLVE(HidD_GetIndexedString);
+		RESOLVE(HidD_GetPreparsedData);
+		RESOLVE(HidD_FreePreparsedData);
+		RESOLVE(HidP_GetCaps);
+		RESOLVE(HidD_SetNumInputBuffers);
+#undef RESOLVE
+	}
+	else
+		return -1;
+
+	return 0;
+}
+#endif
+
+static HANDLE open_device(const char *path, BOOL enumerate)
+{
+	HANDLE handle;
+	DWORD desired_access = (enumerate)? 0: (GENERIC_WRITE | GENERIC_READ);
+	DWORD share_mode = FILE_SHARE_READ|FILE_SHARE_WRITE;
+
+	handle = CreateFileA(path,
+		desired_access,
+		share_mode,
+		NULL,
+		OPEN_EXISTING,
+		FILE_FLAG_OVERLAPPED,/*FILE_ATTRIBUTE_NORMAL,*/
+		0);
+
+	return handle;
+}
+
+int HID_API_EXPORT hid_init(void)
+{
+#ifndef HIDAPI_USE_DDK
+	if (!initialized) {
+		if (lookup_functions() < 0) {
+			hid_exit();
+			return -1;
+		}
+		initialized = TRUE;
+	}
+#endif
+	return 0;
+}
+
+int HID_API_EXPORT hid_exit(void)
+{
+#ifndef HIDAPI_USE_DDK
+	if (lib_handle)
+		FreeLibrary(lib_handle);
+	lib_handle = NULL;
+	initialized = FALSE;
+#endif
+	return 0;
+}
+
+struct hid_device_info HID_API_EXPORT * HID_API_CALL hid_enumerate(unsigned short vendor_id, unsigned short product_id)
+{
+	BOOL res;
+	struct hid_device_info *root = NULL; /* return object */
+	struct hid_device_info *cur_dev = NULL;
+
+	/* Windows objects for interacting with the driver. */
+	GUID InterfaceClassGuid = {0x4d1e55b2, 0xf16f, 0x11cf, {0x88, 0xcb, 0x00, 0x11, 0x11, 0x00, 0x00, 0x30} };
+	SP_DEVINFO_DATA devinfo_data;
+	SP_DEVICE_INTERFACE_DATA device_interface_data;
+	SP_DEVICE_INTERFACE_DETAIL_DATA_A *device_interface_detail_data = NULL;
+	HDEVINFO device_info_set = INVALID_HANDLE_VALUE;
+	int device_index = 0;
+	int i;
+
+	if (hid_init() < 0)
+		return NULL;
+
+	/* Initialize the Windows objects. */
+	memset(&devinfo_data, 0x0, sizeof(devinfo_data));
+	devinfo_data.cbSize = sizeof(SP_DEVINFO_DATA);
+	device_interface_data.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA);
+
+	/* Get information for all the devices belonging to the HID class. */
+	device_info_set = SetupDiGetClassDevsA(&InterfaceClassGuid, NULL, NULL, DIGCF_PRESENT | DIGCF_DEVICEINTERFACE);
+	
+	/* Iterate over each device in the HID class, looking for the right one. */
+	
+	for (;;) {
+		HANDLE write_handle = INVALID_HANDLE_VALUE;
+		DWORD required_size = 0;
+		HIDD_ATTRIBUTES attrib;
+
+		res = SetupDiEnumDeviceInterfaces(device_info_set,
+			NULL,
+			&InterfaceClassGuid,
+			device_index,
+			&device_interface_data);
+		
+		if (!res) {
+			/* A return of FALSE from this function means that
+			   there are no more devices. */
+			break;
+		}
+
+		/* Call with 0-sized detail size, and let the function
+		   tell us how long the detail struct needs to be. The
+		   size is put in &required_size. */
+		res = SetupDiGetDeviceInterfaceDetailA(device_info_set,
+			&device_interface_data,
+			NULL,
+			0,
+			&required_size,
+			NULL);
+
+		/* Allocate a long enough structure for device_interface_detail_data. */
+		device_interface_detail_data = (SP_DEVICE_INTERFACE_DETAIL_DATA_A*) malloc(required_size);
+		device_interface_detail_data->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA_A);
+
+		/* Get the detailed data for this device. The detail data gives us
+		   the device path for this device, which is then passed into
+		   CreateFile() to get a handle to the device. */
+		res = SetupDiGetDeviceInterfaceDetailA(device_info_set,
+			&device_interface_data,
+			device_interface_detail_data,
+			required_size,
+			NULL,
+			NULL);
+
+		if (!res) {
+			/* register_error(dev, "Unable to call SetupDiGetDeviceInterfaceDetail");
+			   Continue to the next device. */
+			goto cont;
+		}
+
+		/* Make sure this device is of Setup Class "HIDClass" and has a
+		   driver bound to it. */
+		for (i = 0; ; i++) {
+			char driver_name[256];
+
+			/* Populate devinfo_data. This function will return failure
+			   when there are no more interfaces left. */
+			res = SetupDiEnumDeviceInfo(device_info_set, i, &devinfo_data);
+			if (!res)
+				goto cont;
+
+			res = SetupDiGetDeviceRegistryPropertyA(device_info_set, &devinfo_data,
+			               SPDRP_CLASS, NULL, (PBYTE)driver_name, sizeof(driver_name), NULL);
+			if (!res)
+				goto cont;
+
+			if (strcmp(driver_name, "HIDClass") == 0) {
+				/* See if there's a driver bound. */
+				res = SetupDiGetDeviceRegistryPropertyA(device_info_set, &devinfo_data,
+				           SPDRP_DRIVER, NULL, (PBYTE)driver_name, sizeof(driver_name), NULL);
+				if (res)
+					break;
+			}
+		}
+
+		//wprintf(L"HandleName: %s\n", device_interface_detail_data->DevicePath);
+
+		/* Open a handle to the device */
+		write_handle = open_device(device_interface_detail_data->DevicePath, TRUE);
+
+		/* Check validity of write_handle. */
+		if (write_handle == INVALID_HANDLE_VALUE) {
+			/* Unable to open the device. */
+			//register_error(dev, "CreateFile");
+			goto cont_close;
+		}		
+
+
+		/* Get the Vendor ID and Product ID for this device. */
+		attrib.Size = sizeof(HIDD_ATTRIBUTES);
+		HidD_GetAttributes(write_handle, &attrib);
+		//wprintf(L"Product/Vendor: %x %x\n", attrib.ProductID, attrib.VendorID);
+
+		/* Check the VID/PID to see if we should add this
+		   device to the enumeration list. */
+		if ((vendor_id == 0x0 || attrib.VendorID == vendor_id) &&
+		    (product_id == 0x0 || attrib.ProductID == product_id)) {
+
+			#define WSTR_LEN 512
+			const char *str;
+			struct hid_device_info *tmp;
+			PHIDP_PREPARSED_DATA pp_data = NULL;
+			HIDP_CAPS caps;
+			BOOLEAN res;
+			NTSTATUS nt_res;
+			wchar_t wstr[WSTR_LEN]; /* TODO: Determine Size */
+			size_t len;
+
+			/* VID/PID match. Create the record. */
+			tmp = (struct hid_device_info*) calloc(1, sizeof(struct hid_device_info));
+			if (cur_dev) {
+				cur_dev->next = tmp;
+			}
+			else {
+				root = tmp;
+			}
+			cur_dev = tmp;
+
+			/* Get the Usage Page and Usage for this device. */
+			res = HidD_GetPreparsedData(write_handle, &pp_data);
+			if (res) {
+				nt_res = HidP_GetCaps(pp_data, &caps);
+				if (nt_res == HIDP_STATUS_SUCCESS) {
+					cur_dev->usage_page = caps.UsagePage;
+					cur_dev->usage = caps.Usage;
+				}
+
+				HidD_FreePreparsedData(pp_data);
+			}
+			
+			/* Fill out the record */
+			cur_dev->next = NULL;
+			str = device_interface_detail_data->DevicePath;
+			if (str) {
+				len = strlen(str);
+				cur_dev->path = (char*) calloc(len+1, sizeof(char));
+				strncpy(cur_dev->path, str, len+1);
+				cur_dev->path[len] = '\0';
+			}
+			else
+				cur_dev->path = NULL;
+
+			/* Serial Number */
+			res = HidD_GetSerialNumberString(write_handle, wstr, sizeof(wstr));
+			wstr[WSTR_LEN-1] = 0x0000;
+			if (res) {
+				cur_dev->serial_number = _wcsdup(wstr);
+			}
+
+			/* Manufacturer String */
+			res = HidD_GetManufacturerString(write_handle, wstr, sizeof(wstr));
+			wstr[WSTR_LEN-1] = 0x0000;
+			if (res) {
+				cur_dev->manufacturer_string = _wcsdup(wstr);
+			}
+
+			/* Product String */
+			res = HidD_GetProductString(write_handle, wstr, sizeof(wstr));
+			wstr[WSTR_LEN-1] = 0x0000;
+			if (res) {
+				cur_dev->product_string = _wcsdup(wstr);
+			}
+
+			/* VID/PID */
+			cur_dev->vendor_id = attrib.VendorID;
+			cur_dev->product_id = attrib.ProductID;
+
+			/* Release Number */
+			cur_dev->release_number = attrib.VersionNumber;
+
+			/* Interface Number. It can sometimes be parsed out of the path
+			   on Windows if a device has multiple interfaces. See
+			   http://msdn.microsoft.com/en-us/windows/hardware/gg487473 or
+			   search for "Hardware IDs for HID Devices" at MSDN. If it's not
+			   in the path, it's set to -1. */
+			cur_dev->interface_number = -1;
+			if (cur_dev->path) {
+				char *interface_component = strstr(cur_dev->path, "&mi_");
+				if (interface_component) {
+					char *hex_str = interface_component + 4;
+					char *endptr = NULL;
+					cur_dev->interface_number = strtol(hex_str, &endptr, 16);
+					if (endptr == hex_str) {
+						/* The parsing failed. Set interface_number to -1. */
+						cur_dev->interface_number = -1;
+					}
+				}
+			}
+		}
+
+cont_close:
+		CloseHandle(write_handle);
+cont:
+		/* We no longer need the detail data. It can be freed */
+		free(device_interface_detail_data);
+
+		device_index++;
+
+	}
+
+	/* Close the device information handle. */
+	SetupDiDestroyDeviceInfoList(device_info_set);
+
+	return root;
+
+}
+
+void  HID_API_EXPORT HID_API_CALL hid_free_enumeration(struct hid_device_info *devs)
+{
+	/* TODO: Merge this with the Linux version. This function is platform-independent. */
+	struct hid_device_info *d = devs;
+	while (d) {
+		struct hid_device_info *next = d->next;
+		free(d->path);
+		free(d->serial_number);
+		free(d->manufacturer_string);
+		free(d->product_string);
+		free(d);
+		d = next;
+	}
+}
+
+
+HID_API_EXPORT hid_device * HID_API_CALL hid_open(unsigned short vendor_id, unsigned short product_id, const wchar_t *serial_number)
+{
+	/* TODO: Merge this functions with the Linux version. This function should be platform independent. */
+	struct hid_device_info *devs, *cur_dev;
+	const char *path_to_open = NULL;
+	hid_device *handle = NULL;
+	
+	devs = hid_enumerate(vendor_id, product_id);
+	cur_dev = devs;
+	while (cur_dev) {
+		if (cur_dev->vendor_id == vendor_id &&
+		    cur_dev->product_id == product_id) {
+			if (serial_number) {
+				if (wcscmp(serial_number, cur_dev->serial_number) == 0) {
+					path_to_open = cur_dev->path;
+					break;
+				}
+			}
+			else {
+				path_to_open = cur_dev->path;
+				break;
+			}
+		}
+		cur_dev = cur_dev->next;
+	}
+
+	if (path_to_open) {
+		/* Open the device */
+		handle = hid_open_path(path_to_open);
+	}
+
+	hid_free_enumeration(devs);
+	
+	return handle;
+}
+
+HID_API_EXPORT hid_device * HID_API_CALL hid_open_path(const char *path)
+{
+	hid_device *dev;
+	HIDP_CAPS caps;
+	PHIDP_PREPARSED_DATA pp_data = NULL;
+	BOOLEAN res;
+	NTSTATUS nt_res;
+
+	if (hid_init() < 0) {
+		return NULL;
+	}
+
+	dev = new_hid_device();
+
+	/* Open a handle to the device */
+	dev->device_handle = open_device(path, FALSE);
+
+	/* Check validity of write_handle. */
+	if (dev->device_handle == INVALID_HANDLE_VALUE) {
+		/* Unable to open the device. */
+		register_error(dev, "CreateFile");
+		goto err;
+	}
+
+	/* Set the Input Report buffer size to 64 reports. */
+	res = HidD_SetNumInputBuffers(dev->device_handle, 64);
+	if (!res) {
+		register_error(dev, "HidD_SetNumInputBuffers");
+		goto err;
+	}
+
+	/* Get the Input Report length for the device. */
+	res = HidD_GetPreparsedData(dev->device_handle, &pp_data);
+	if (!res) {
+		register_error(dev, "HidD_GetPreparsedData");
+		goto err;
+	}
+	nt_res = HidP_GetCaps(pp_data, &caps);
+	if (nt_res != HIDP_STATUS_SUCCESS) {
+		register_error(dev, "HidP_GetCaps");	
+		goto err_pp_data;
+	}
+	dev->output_report_length = caps.OutputReportByteLength;
+	dev->input_report_length = caps.InputReportByteLength;
+	HidD_FreePreparsedData(pp_data);
+
+	dev->read_buf = (char*) malloc(dev->input_report_length);
+
+	return dev;
+
+err_pp_data:
+		HidD_FreePreparsedData(pp_data);
+err:	
+		free_hid_device(dev);
+		return NULL;
+}
+
+int HID_API_EXPORT HID_API_CALL hid_write(hid_device *dev, const unsigned char *data, size_t length)
+{
+	DWORD bytes_written;
+	BOOL res;
+
+	OVERLAPPED ol;
+	unsigned char *buf;
+	memset(&ol, 0, sizeof(ol));
+
+	/* Make sure the right number of bytes are passed to WriteFile. Windows
+	   expects the number of bytes which are in the _longest_ report (plus
+	   one for the report number) bytes even if the data is a report
+	   which is shorter than that. Windows gives us this value in
+	   caps.OutputReportByteLength. If a user passes in fewer bytes than this,
+	   create a temporary buffer which is the proper size. */
+	if (length >= dev->output_report_length) {
+		/* The user passed the right number of bytes. Use the buffer as-is. */
+		buf = (unsigned char *) data;
+	} else {
+		/* Create a temporary buffer and copy the user's data
+		   into it, padding the rest with zeros. */
+		buf = (unsigned char *) malloc(dev->output_report_length);
+		memcpy(buf, data, length);
+		memset(buf + length, 0, dev->output_report_length - length);
+		length = dev->output_report_length;
+	}
+
+	res = WriteFile(dev->device_handle, buf, length, NULL, &ol);
+	
+	if (!res) {
+		if (GetLastError() != ERROR_IO_PENDING) {
+			/* WriteFile() failed. Return error. */
+			register_error(dev, "WriteFile");
+			bytes_written = -1;
+			goto end_of_function;
+		}
+	}
+
+	/* Wait here until the write is done. This makes
+	   hid_write() synchronous. */
+	res = GetOverlappedResult(dev->device_handle, &ol, &bytes_written, TRUE/*wait*/);
+	if (!res) {
+		/* The Write operation failed. */
+		register_error(dev, "WriteFile");
+		bytes_written = -1;
+		goto end_of_function;
+	}
+
+end_of_function:
+	if (buf != data)
+		free(buf);
+
+	return bytes_written;
+}
+
+
+int HID_API_EXPORT HID_API_CALL hid_read_timeout(hid_device *dev, unsigned char *data, size_t length, int milliseconds)
+{
+	DWORD bytes_read = 0;
+	size_t copy_len = 0;
+	BOOL res;
+
+	/* Copy the handle for convenience. */
+	HANDLE ev = dev->ol.hEvent;
+
+	if (!dev->read_pending) {
+		/* Start an Overlapped I/O read. */
+		dev->read_pending = TRUE;
+		memset(dev->read_buf, 0, dev->input_report_length);
+		ResetEvent(ev);
+		res = ReadFile(dev->device_handle, dev->read_buf, dev->input_report_length, &bytes_read, &dev->ol);
+		
+		if (!res) {
+			if (GetLastError() != ERROR_IO_PENDING) {
+				/* ReadFile() has failed.
+				   Clean up and return error. */
+				CancelIo(dev->device_handle);
+				dev->read_pending = FALSE;
+				goto end_of_function;
+			}
+		}
+	}
+
+	if (milliseconds >= 0) {
+		/* See if there is any data yet. */
+		res = WaitForSingleObject(ev, milliseconds);
+		if (res != WAIT_OBJECT_0) {
+			/* There was no data this time. Return zero bytes available,
+			   but leave the Overlapped I/O running. */
+			return 0;
+		}
+	}
+
+	/* Either WaitForSingleObject() told us that ReadFile has completed, or
+	   we are in non-blocking mode. Get the number of bytes read. The actual
+	   data has been copied to the data[] array which was passed to ReadFile(). */
+	res = GetOverlappedResult(dev->device_handle, &dev->ol, &bytes_read, TRUE/*wait*/);
+	
+	/* Set pending back to false, even if GetOverlappedResult() returned error. */
+	dev->read_pending = FALSE;
+
+	if (res && bytes_read > 0) {
+		if (dev->read_buf[0] == 0x0) {
+			/* If report numbers aren't being used, but Windows sticks a report
+			   number (0x0) on the beginning of the report anyway. To make this
+			   work like the other platforms, and to make it work more like the
+			   HID spec, we'll skip over this byte. */
+			bytes_read--;
+			copy_len = length > bytes_read ? bytes_read : length;
+			memcpy(data, dev->read_buf+1, copy_len);
+		}
+		else {
+			/* Copy the whole buffer, report number and all. */
+			copy_len = length > bytes_read ? bytes_read : length;
+			memcpy(data, dev->read_buf, copy_len);
+		}
+	}
+	
+end_of_function:
+	if (!res) {
+		register_error(dev, "GetOverlappedResult");
+		return -1;
+	}
+	
+	return copy_len;
+}
+
+int HID_API_EXPORT HID_API_CALL hid_read(hid_device *dev, unsigned char *data, size_t length)
+{
+	return hid_read_timeout(dev, data, length, (dev->blocking)? -1: 0);
+}
+
+int HID_API_EXPORT HID_API_CALL hid_set_nonblocking(hid_device *dev, int nonblock)
+{
+	dev->blocking = !nonblock;
+	return 0; /* Success */
+}
+
+int HID_API_EXPORT HID_API_CALL hid_send_feature_report(hid_device *dev, const unsigned char *data, size_t length)
+{
+	BOOL res = HidD_SetFeature(dev->device_handle, (PVOID)data, length);
+	if (!res) {
+		register_error(dev, "HidD_SetFeature");
+		return -1;
+	}
+
+	return length;
+}
+
+
+int HID_API_EXPORT HID_API_CALL hid_get_feature_report(hid_device *dev, unsigned char *data, size_t length)
+{
+	BOOL res;
+#if 0
+	res = HidD_GetFeature(dev->device_handle, data, length);
+	if (!res) {
+		register_error(dev, "HidD_GetFeature");
+		return -1;
+	}
+	return 0; /* HidD_GetFeature() doesn't give us an actual length, unfortunately */
+#else
+	DWORD bytes_returned;
+
+	OVERLAPPED ol;
+	memset(&ol, 0, sizeof(ol));
+
+	res = DeviceIoControl(dev->device_handle,
+		IOCTL_HID_GET_FEATURE,
+		data, length,
+		data, length,
+		&bytes_returned, &ol);
+
+	if (!res) {
+		if (GetLastError() != ERROR_IO_PENDING) {
+			/* DeviceIoControl() failed. Return error. */
+			register_error(dev, "Send Feature Report DeviceIoControl");
+			return -1;
+		}
+	}
+
+	/* Wait here until the write is done. This makes
+	   hid_get_feature_report() synchronous. */
+	res = GetOverlappedResult(dev->device_handle, &ol, &bytes_returned, TRUE/*wait*/);
+	if (!res) {
+		/* The operation failed. */
+		register_error(dev, "Send Feature Report GetOverLappedResult");
+		return -1;
+	}
+
+	/* bytes_returned does not include the first byte which contains the
+	   report ID. The data buffer actually contains one more byte than
+	   bytes_returned. */
+	bytes_returned++;
+
+	return bytes_returned;
+#endif
+}
+
+void HID_API_EXPORT HID_API_CALL hid_close(hid_device *dev)
+{
+	if (!dev)
+		return;
+	CancelIo(dev->device_handle);
+	free_hid_device(dev);
+}
+
+int HID_API_EXPORT_CALL HID_API_CALL hid_get_manufacturer_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	BOOL res;
+
+	res = HidD_GetManufacturerString(dev->device_handle, string, sizeof(wchar_t) * MIN(maxlen, MAX_STRING_WCHARS));
+	if (!res) {
+		register_error(dev, "HidD_GetManufacturerString");
+		return -1;
+	}
+
+	return 0;
+}
+
+int HID_API_EXPORT_CALL HID_API_CALL hid_get_product_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	BOOL res;
+
+	res = HidD_GetProductString(dev->device_handle, string, sizeof(wchar_t) * MIN(maxlen, MAX_STRING_WCHARS));
+	if (!res) {
+		register_error(dev, "HidD_GetProductString");
+		return -1;
+	}
+
+	return 0;
+}
+
+int HID_API_EXPORT_CALL HID_API_CALL hid_get_serial_number_string(hid_device *dev, wchar_t *string, size_t maxlen)
+{
+	BOOL res;
+
+	res = HidD_GetSerialNumberString(dev->device_handle, string, sizeof(wchar_t) * MIN(maxlen, MAX_STRING_WCHARS));
+	if (!res) {
+		register_error(dev, "HidD_GetSerialNumberString");
+		return -1;
+	}
+
+	return 0;
+}
+
+int HID_API_EXPORT_CALL HID_API_CALL hid_get_indexed_string(hid_device *dev, int string_index, wchar_t *string, size_t maxlen)
+{
+	BOOL res;
+
+	res = HidD_GetIndexedString(dev->device_handle, string_index, string, sizeof(wchar_t) * MIN(maxlen, MAX_STRING_WCHARS));
+	if (!res) {
+		register_error(dev, "HidD_GetIndexedString");
+		return -1;
+	}
+
+	return 0;
+}
+
+
+HID_API_EXPORT const wchar_t * HID_API_CALL  hid_error(hid_device *dev)
+{
+	return (wchar_t*)dev->last_error_str;
+}
+
+
+/*#define PICPGM*/
+/*#define S11*/
+#define P32
+#ifdef S11 
+  unsigned short VendorID = 0xa0a0;
+	unsigned short ProductID = 0x0001;
+#endif
+
+#ifdef P32
+  unsigned short VendorID = 0x04d8;
+	unsigned short ProductID = 0x3f;
+#endif
+
+
+#ifdef PICPGM
+  unsigned short VendorID = 0x04d8;
+  unsigned short ProductID = 0x0033;
+#endif
+
+
+#if 0
+int __cdecl main(int argc, char* argv[])
+{
+	int res;
+	unsigned char buf[65];
+
+	UNREFERENCED_PARAMETER(argc);
+	UNREFERENCED_PARAMETER(argv);
+
+	/* Set up the command buffer. */
+	memset(buf,0x00,sizeof(buf));
+	buf[0] = 0;
+	buf[1] = 0x81;
+	
+
+	/* Open the device. */
+	int handle = open(VendorID, ProductID, L"12345");
+	if (handle < 0)
+		printf("unable to open device\n");
+
+
+	/* Toggle LED (cmd 0x80) */
+	buf[1] = 0x80;
+	res = write(handle, buf, 65);
+	if (res < 0)
+		printf("Unable to write()\n");
+
+	/* Request state (cmd 0x81) */
+	buf[1] = 0x81;
+	write(handle, buf, 65);
+	if (res < 0)
+		printf("Unable to write() (2)\n");
+
+	/* Read requested state */
+	read(handle, buf, 65);
+	if (res < 0)
+		printf("Unable to read()\n");
+
+	/* Print out the returned buffer. */
+	for (int i = 0; i < 4; i++)
+		printf("buf[%d]: %d\n", i, buf[i]);
+
+	return 0;
+}
+#endif
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/hidapi.sln b/uf2-samdx1/lib/uf2/hidapi/windows/hidapi.sln
new file mode 100644
index 00000000..d45c397b
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/hidapi.sln
@@ -0,0 +1,29 @@
+
+Microsoft Visual Studio Solution File, Format Version 10.00
+# Visual C++ Express 2008
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "hidapi", "hidapi.vcproj", "{A107C21C-418A-4697-BB10-20C3AA60E2E4}"
+EndProject
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "hidtest", "hidtest.vcproj", "{23E9FF6A-49D1-4993-B2B5-BBB992C6C712}"
+	ProjectSection(ProjectDependencies) = postProject
+		{A107C21C-418A-4697-BB10-20C3AA60E2E4} = {A107C21C-418A-4697-BB10-20C3AA60E2E4}
+	EndProjectSection
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Win32 = Debug|Win32
+		Release|Win32 = Release|Win32
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{A107C21C-418A-4697-BB10-20C3AA60E2E4}.Debug|Win32.ActiveCfg = Debug|Win32
+		{A107C21C-418A-4697-BB10-20C3AA60E2E4}.Debug|Win32.Build.0 = Debug|Win32
+		{A107C21C-418A-4697-BB10-20C3AA60E2E4}.Release|Win32.ActiveCfg = Release|Win32
+		{A107C21C-418A-4697-BB10-20C3AA60E2E4}.Release|Win32.Build.0 = Release|Win32
+		{23E9FF6A-49D1-4993-B2B5-BBB992C6C712}.Debug|Win32.ActiveCfg = Debug|Win32
+		{23E9FF6A-49D1-4993-B2B5-BBB992C6C712}.Debug|Win32.Build.0 = Debug|Win32
+		{23E9FF6A-49D1-4993-B2B5-BBB992C6C712}.Release|Win32.ActiveCfg = Release|Win32
+		{23E9FF6A-49D1-4993-B2B5-BBB992C6C712}.Release|Win32.Build.0 = Release|Win32
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/hidapi.vcproj b/uf2-samdx1/lib/uf2/hidapi/windows/hidapi.vcproj
new file mode 100644
index 00000000..ee9569c7
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/hidapi.vcproj
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<VisualStudioProject
+	ProjectType="Visual C++"
+	Version="9.00"
+	Name="hidapi"
+	ProjectGUID="{A107C21C-418A-4697-BB10-20C3AA60E2E4}"
+	RootNamespace="hidapi"
+	Keyword="Win32Proj"
+	TargetFrameworkVersion="196613"
+	>
+	<Platforms>
+		<Platform
+			Name="Win32"
+		/>
+	</Platforms>
+	<ToolFiles>
+	</ToolFiles>
+	<Configurations>
+		<Configuration
+			Name="Debug|Win32"
+			OutputDirectory="$(SolutionDir)$(ConfigurationName)"
+			IntermediateDirectory="$(ConfigurationName)"
+			ConfigurationType="2"
+			CharacterSet="1"
+			>
+			<Tool
+				Name="VCPreBuildEventTool"
+			/>
+			<Tool
+				Name="VCCustomBuildTool"
+			/>
+			<Tool
+				Name="VCXMLDataGeneratorTool"
+			/>
+			<Tool
+				Name="VCWebServiceProxyGeneratorTool"
+			/>
+			<Tool
+				Name="VCMIDLTool"
+			/>
+			<Tool
+				Name="VCCLCompilerTool"
+				Optimization="0"
+				AdditionalIncludeDirectories="..\hidapi"
+				PreprocessorDefinitions="WIN32;_DEBUG;_WINDOWS;_USRDLL;HIDAPI_EXPORTS"
+				MinimalRebuild="true"
+				BasicRuntimeChecks="3"
+				RuntimeLibrary="3"
+				UsePrecompiledHeader="0"
+				WarningLevel="3"
+				DebugInformationFormat="4"
+			/>
+			<Tool
+				Name="VCManagedResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCPreLinkEventTool"
+			/>
+			<Tool
+				Name="VCLinkerTool"
+				AdditionalDependencies="setupapi.lib"
+				LinkIncremental="2"
+				GenerateDebugInformation="true"
+				SubSystem="2"
+				TargetMachine="1"
+			/>
+			<Tool
+				Name="VCALinkTool"
+			/>
+			<Tool
+				Name="VCManifestTool"
+			/>
+			<Tool
+				Name="VCXDCMakeTool"
+			/>
+			<Tool
+				Name="VCBscMakeTool"
+			/>
+			<Tool
+				Name="VCFxCopTool"
+			/>
+			<Tool
+				Name="VCAppVerifierTool"
+			/>
+			<Tool
+				Name="VCPostBuildEventTool"
+			/>
+		</Configuration>
+		<Configuration
+			Name="Release|Win32"
+			OutputDirectory="$(SolutionDir)$(ConfigurationName)"
+			IntermediateDirectory="$(ConfigurationName)"
+			ConfigurationType="2"
+			CharacterSet="1"
+			WholeProgramOptimization="1"
+			>
+			<Tool
+				Name="VCPreBuildEventTool"
+			/>
+			<Tool
+				Name="VCCustomBuildTool"
+			/>
+			<Tool
+				Name="VCXMLDataGeneratorTool"
+			/>
+			<Tool
+				Name="VCWebServiceProxyGeneratorTool"
+			/>
+			<Tool
+				Name="VCMIDLTool"
+			/>
+			<Tool
+				Name="VCCLCompilerTool"
+				Optimization="2"
+				EnableIntrinsicFunctions="true"
+				AdditionalIncludeDirectories="..\hidapi"
+				PreprocessorDefinitions="WIN32;NDEBUG;_WINDOWS;_USRDLL;HIDAPI_EXPORTS"
+				RuntimeLibrary="2"
+				EnableFunctionLevelLinking="true"
+				UsePrecompiledHeader="0"
+				WarningLevel="3"
+				DebugInformationFormat="3"
+			/>
+			<Tool
+				Name="VCManagedResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCPreLinkEventTool"
+			/>
+			<Tool
+				Name="VCLinkerTool"
+				AdditionalDependencies="setupapi.lib"
+				LinkIncremental="1"
+				GenerateDebugInformation="true"
+				SubSystem="2"
+				OptimizeReferences="2"
+				EnableCOMDATFolding="2"
+				TargetMachine="1"
+			/>
+			<Tool
+				Name="VCALinkTool"
+			/>
+			<Tool
+				Name="VCManifestTool"
+			/>
+			<Tool
+				Name="VCXDCMakeTool"
+			/>
+			<Tool
+				Name="VCBscMakeTool"
+			/>
+			<Tool
+				Name="VCFxCopTool"
+			/>
+			<Tool
+				Name="VCAppVerifierTool"
+			/>
+			<Tool
+				Name="VCPostBuildEventTool"
+			/>
+		</Configuration>
+	</Configurations>
+	<References>
+	</References>
+	<Files>
+		<Filter
+			Name="Source Files"
+			Filter="cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx"
+			UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}"
+			>
+			<File
+				RelativePath=".\hid.c"
+				>
+			</File>
+		</Filter>
+		<Filter
+			Name="Header Files"
+			Filter="h;hpp;hxx;hm;inl;inc;xsd"
+			UniqueIdentifier="{93995380-89BD-4b04-88EB-625FBE52EBFB}"
+			>
+			<File
+				RelativePath="..\hidapi\hidapi.h"
+				>
+			</File>
+		</Filter>
+		<Filter
+			Name="Resource Files"
+			Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav"
+			UniqueIdentifier="{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}"
+			>
+		</Filter>
+	</Files>
+	<Globals>
+	</Globals>
+</VisualStudioProject>
diff --git a/uf2-samdx1/lib/uf2/hidapi/windows/hidtest.vcproj b/uf2-samdx1/lib/uf2/hidapi/windows/hidtest.vcproj
new file mode 100644
index 00000000..db64f96c
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/hidapi/windows/hidtest.vcproj
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<VisualStudioProject
+	ProjectType="Visual C++"
+	Version="9.00"
+	Name="hidtest"
+	ProjectGUID="{23E9FF6A-49D1-4993-B2B5-BBB992C6C712}"
+	RootNamespace="hidtest"
+	TargetFrameworkVersion="196613"
+	>
+	<Platforms>
+		<Platform
+			Name="Win32"
+		/>
+	</Platforms>
+	<ToolFiles>
+	</ToolFiles>
+	<Configurations>
+		<Configuration
+			Name="Debug|Win32"
+			OutputDirectory="$(SolutionDir)$(ConfigurationName)"
+			IntermediateDirectory="$(ConfigurationName)"
+			ConfigurationType="1"
+			CharacterSet="2"
+			>
+			<Tool
+				Name="VCPreBuildEventTool"
+			/>
+			<Tool
+				Name="VCCustomBuildTool"
+			/>
+			<Tool
+				Name="VCXMLDataGeneratorTool"
+			/>
+			<Tool
+				Name="VCWebServiceProxyGeneratorTool"
+			/>
+			<Tool
+				Name="VCMIDLTool"
+			/>
+			<Tool
+				Name="VCCLCompilerTool"
+				Optimization="0"
+				AdditionalIncludeDirectories="..\hidapi"
+				MinimalRebuild="true"
+				BasicRuntimeChecks="3"
+				RuntimeLibrary="3"
+				WarningLevel="3"
+				DebugInformationFormat="4"
+			/>
+			<Tool
+				Name="VCManagedResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCPreLinkEventTool"
+			/>
+			<Tool
+				Name="VCLinkerTool"
+				AdditionalDependencies="hidapi.lib"
+				AdditionalLibraryDirectories="..\windows\Debug"
+				GenerateDebugInformation="true"
+				SubSystem="1"
+				TargetMachine="1"
+			/>
+			<Tool
+				Name="VCALinkTool"
+			/>
+			<Tool
+				Name="VCManifestTool"
+			/>
+			<Tool
+				Name="VCXDCMakeTool"
+			/>
+			<Tool
+				Name="VCBscMakeTool"
+			/>
+			<Tool
+				Name="VCFxCopTool"
+			/>
+			<Tool
+				Name="VCAppVerifierTool"
+			/>
+			<Tool
+				Name="VCPostBuildEventTool"
+				Description="Copying hidapi.dll to the local direcotry."
+				CommandLine=""
+			/>
+		</Configuration>
+		<Configuration
+			Name="Release|Win32"
+			OutputDirectory="$(SolutionDir)$(ConfigurationName)"
+			IntermediateDirectory="$(ConfigurationName)"
+			ConfigurationType="1"
+			CharacterSet="2"
+			WholeProgramOptimization="1"
+			>
+			<Tool
+				Name="VCPreBuildEventTool"
+			/>
+			<Tool
+				Name="VCCustomBuildTool"
+			/>
+			<Tool
+				Name="VCXMLDataGeneratorTool"
+			/>
+			<Tool
+				Name="VCWebServiceProxyGeneratorTool"
+			/>
+			<Tool
+				Name="VCMIDLTool"
+			/>
+			<Tool
+				Name="VCCLCompilerTool"
+				Optimization="2"
+				EnableIntrinsicFunctions="true"
+				AdditionalIncludeDirectories="..\hidapi"
+				RuntimeLibrary="2"
+				EnableFunctionLevelLinking="true"
+				WarningLevel="3"
+				DebugInformationFormat="3"
+			/>
+			<Tool
+				Name="VCManagedResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCPreLinkEventTool"
+			/>
+			<Tool
+				Name="VCLinkerTool"
+				AdditionalDependencies="hidapi.lib"
+				AdditionalLibraryDirectories="..\windows\Release"
+				GenerateDebugInformation="true"
+				SubSystem="1"
+				OptimizeReferences="2"
+				EnableCOMDATFolding="2"
+				TargetMachine="1"
+			/>
+			<Tool
+				Name="VCALinkTool"
+			/>
+			<Tool
+				Name="VCManifestTool"
+			/>
+			<Tool
+				Name="VCXDCMakeTool"
+			/>
+			<Tool
+				Name="VCBscMakeTool"
+			/>
+			<Tool
+				Name="VCFxCopTool"
+			/>
+			<Tool
+				Name="VCAppVerifierTool"
+			/>
+			<Tool
+				Name="VCPostBuildEventTool"
+				Description="Copying hidapi.dll to the local direcotry."
+				CommandLine=""
+			/>
+		</Configuration>
+	</Configurations>
+	<References>
+	</References>
+	<Files>
+		<Filter
+			Name="Source Files"
+			Filter="cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx"
+			UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}"
+			>
+			<File
+				RelativePath="..\hidtest\hidtest.cpp"
+				>
+			</File>
+		</Filter>
+		<Filter
+			Name="Header Files"
+			Filter="h;hpp;hxx;hm;inl;inc;xsd"
+			UniqueIdentifier="{93995380-89BD-4b04-88EB-625FBE52EBFB}"
+			>
+		</Filter>
+		<Filter
+			Name="Resource Files"
+			Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav"
+			UniqueIdentifier="{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}"
+			>
+		</Filter>
+	</Files>
+	<Globals>
+	</Globals>
+</VisualStudioProject>
diff --git a/uf2-samdx1/lib/uf2/patcher/index.html b/uf2-samdx1/lib/uf2/patcher/index.html
new file mode 100644
index 00000000..75c20ed6
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/patcher/index.html
@@ -0,0 +1,83 @@
+<!DOCTYPE html>
+<html lang="en-US">
+
+<head>
+  <meta charset="UTF-8">
+
+  <title>CF2 binary patcher</title>
+
+  <meta name="viewport" content="width=device-width, initial-scale=1">
+  <meta name="theme-color" content="#157878">
+  <link rel="stylesheet" href="https://microsoft.github.io/uf2/assets/css/style.css">
+  <script src="patcher.js"></script>
+  <script src="web.js"></script>
+  <style>
+    #patch {
+      font-family: Consolas, "Liberation Mono", Menlo, Courier, monospace;
+      font-size: 0.9rem;
+      width: 100%;
+      height: 12em;
+    }
+
+    .page-header {
+      padding: 2rem 2rem !important;
+    }
+
+    .btn-dl,
+    .btn-dl:hover {
+      background-color: green;
+      float: right;
+      color: white;
+    }
+
+    footer {
+      text-align: center;
+      margin-top: 5em;
+    }
+    footer a {
+      margin-right: 2em;
+    }
+  </style>
+</head>
+
+<body ondrop="dropHandler(event);" ondragover="dragOverHandler(event);">
+  <section class="page-header">
+    <h1 class="project-name">CF2 patcher</h1>
+  </section>
+
+  <section class="main-content">
+    <h2>Your patch</h2>
+    <textarea id="patch" spellcheck=false onchange="savePatch(event);"></textarea>
+    <a href="#" id="apply" class="btn btn-dl">Apply my patch</a>
+
+    <h2>Information</h2>
+    <pre><code id="currconfig">Drop UF2 or BIN file above to see its config.</code></pre>
+
+    <p>
+      <a href="https://github.com/Microsoft/uf2/blob/master/cf2.md">Learn more</a>
+      or
+      <a href="#" onclick="defines()">download configkeys.h</a>.
+    </p>
+
+    <p>
+      <a href="#" id="rnd">Generate random number</a>
+      <span id="rnd-res"></span>
+    </p>
+
+
+  <footer>
+    <a href="https://makecode.com/privacy" target="_blank" rel="noopener">Privacy &amp; Cookies</a>
+    <a href="https://makecode.com/termsofuse" target="_blank" rel="noopener"> Terms Of Use</a>
+    <a href="https://makecode.com/trademarks" target="_blank" rel="noopener">Trademarks</a>
+    <span>© 2019 Microsoft</span>
+  </footer>
+
+  </section>
+
+  <script>
+    restorePatch()
+  </script>
+
+</body>
+
+</html>
\ No newline at end of file
diff --git a/uf2-samdx1/lib/uf2/patcher/patcher.js b/uf2-samdx1/lib/uf2/patcher/patcher.js
new file mode 100644
index 00000000..50e5c23f
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/patcher/patcher.js
@@ -0,0 +1,1158 @@
+"use strict";
+
+// copy entire configkeys.h from https://github.com/microsoft/pxt-common-packages/blob/master/libs/base/configkeys.h
+const CONFIG_KEYS_H =
+    `
+#ifndef __PXT_CONFIGKEYS_H
+#define __PXT_CONFIGKEYS_H
+
+// used by pins.cpp to mask off the pin name from any config
+// lower 16 pins of value are the pin name
+#define CFG_PIN_NAME_MSK 0x0000ffff
+// upper 16 bits of value is any configuration of the pin.
+#define CFG_PIN_CONFIG_MSK 0xffff0000
+
+// begin optional pin configurations
+#define CFG_PIN_CONFIG_ACTIVE_LO 0x10000
+
+
+#define CFG_MAGIC0 0x1e9e10f1
+#define CFG_MAGIC1 0x20227a79
+
+// these define keys for getConfig() function
+#define CFG_PIN_ACCELEROMETER_INT 1
+#define CFG_PIN_ACCELEROMETER_SCL 2
+#define CFG_PIN_ACCELEROMETER_SDA 3
+#define CFG_PIN_BTN_A 4
+#define CFG_PIN_BTN_B 5
+#define CFG_PIN_BTN_SLIDE 6
+#define CFG_PIN_DOTSTAR_CLOCK 7
+#define CFG_PIN_DOTSTAR_DATA 8
+#define CFG_PIN_FLASH_CS 9
+#define CFG_PIN_FLASH_MISO 10
+#define CFG_PIN_FLASH_MOSI 11
+#define CFG_PIN_FLASH_SCK 12
+#define CFG_PIN_LED 13
+#define CFG_PIN_LIGHT 14
+#define CFG_PIN_MICROPHONE 15
+#define CFG_PIN_MIC_CLOCK 16
+#define CFG_PIN_MIC_DATA 17
+#define CFG_PIN_MISO 18
+#define CFG_PIN_MOSI 19
+// the preferred pin to drive an external neopixel strip
+#define CFG_PIN_NEOPIXEL 20
+#define CFG_PIN_RX 21
+#define CFG_PIN_RXLED 22
+#define CFG_PIN_SCK 23
+#define CFG_PIN_SCL 24
+#define CFG_PIN_SDA 25
+#define CFG_PIN_SPEAKER_AMP 26
+#define CFG_PIN_TEMPERATURE 27
+#define CFG_PIN_TX 28
+#define CFG_PIN_TXLED 29
+#define CFG_PIN_IR_OUT 30
+#define CFG_PIN_IR_IN 31
+#define CFG_PIN_DISPLAY_SCK 32
+#define CFG_PIN_DISPLAY_MISO 33
+#define CFG_PIN_DISPLAY_MOSI 34
+#define CFG_PIN_DISPLAY_CS 35
+#define CFG_PIN_DISPLAY_DC 36
+#define CFG_DISPLAY_WIDTH 37
+#define CFG_DISPLAY_HEIGHT 38
+#define CFG_DISPLAY_CFG0 39
+#define CFG_DISPLAY_CFG1 40
+#define CFG_DISPLAY_CFG2 41
+#define CFG_DISPLAY_CFG3 42
+#define CFG_PIN_DISPLAY_RST 43
+#define CFG_PIN_DISPLAY_BL 44
+#define CFG_PIN_SERVO_1 45
+#define CFG_PIN_SERVO_2 46
+#define CFG_PIN_BTN_LEFT 47
+#define CFG_PIN_BTN_RIGHT 48
+#define CFG_PIN_BTN_UP 49
+#define CFG_PIN_BTN_DOWN 50
+#define CFG_PIN_BTN_MENU 51
+#define CFG_PIN_LED_R 52
+#define CFG_PIN_LED_G 53
+#define CFG_PIN_LED_B 54
+#define CFG_PIN_LED1 55
+#define CFG_PIN_LED2 56
+#define CFG_PIN_LED3 57
+#define CFG_PIN_LED4 58
+#define CFG_SPEAKER_VOLUME 59
+
+#define CFG_PIN_JACK_TX 60
+#define CFG_PIN_JACK_SENSE 61
+#define CFG_PIN_JACK_HPEN 62
+#define CFG_PIN_JACK_BZEN 63
+#define CFG_PIN_JACK_PWREN 64
+#define CFG_PIN_JACK_SND 65
+#define CFG_PIN_JACK_BUSLED 66
+#define CFG_PIN_JACK_COMMLED 67
+
+#define CFG_PIN_BTN_SOFT_RESET 69
+#define CFG_ACCELEROMETER_TYPE 70
+#define CFG_PIN_BTNMX_LATCH 71
+#define CFG_PIN_BTNMX_CLOCK 72
+#define CFG_PIN_BTNMX_DATA 73
+#define CFG_PIN_BTN_MENU2 74
+#define CFG_PIN_BATTSENSE 75
+#define CFG_PIN_VIBRATION 76
+#define CFG_PIN_PWREN 77
+#define CFG_DISPLAY_TYPE 78
+
+#define CFG_PIN_ROTARY_ENCODER_A 79
+#define CFG_PIN_ROTARY_ENCODER_B 80
+
+#define CFG_ACCELEROMETER_SPACE 81
+
+#define CFG_PIN_WIFI_MOSI 82
+#define CFG_PIN_WIFI_MISO 83
+#define CFG_PIN_WIFI_SCK 84
+#define CFG_PIN_WIFI_TX 85
+#define CFG_PIN_WIFI_RX 86
+#define CFG_PIN_WIFI_CS 87
+#define CFG_PIN_WIFI_BUSY 88
+#define CFG_PIN_WIFI_RESET 89
+#define CFG_PIN_WIFI_GPIO0 90
+#define CFG_PIN_WIFI_AT_TX 91
+#define CFG_PIN_WIFI_AT_RX 92
+
+#define CFG_PIN_USB_POWER 93
+
+// default I2C address
+#define ACCELEROMETER_TYPE_LIS3DH 0x32
+#define ACCELEROMETER_TYPE_LIS3DH_ALT 0x30
+#define ACCELEROMETER_TYPE_MMA8453 0x38
+#define ACCELEROMETER_TYPE_FXOS8700 0x3C
+#define ACCELEROMETER_TYPE_MMA8653 0x3A
+#define ACCELEROMETER_TYPE_MSA300 0x4C
+#define ACCELEROMETER_TYPE_MPU6050 0x68
+
+#define DISPLAY_TYPE_ST7735 7735
+#define DISPLAY_TYPE_ILI9341 9341
+#define DISPLAY_TYPE_SMART 4242
+
+#define CFG_PIN_A0 100
+#define CFG_PIN_A1 101
+#define CFG_PIN_A2 102
+#define CFG_PIN_A3 103
+#define CFG_PIN_A4 104
+#define CFG_PIN_A5 105
+#define CFG_PIN_A6 106
+#define CFG_PIN_A7 107
+#define CFG_PIN_A8 108
+#define CFG_PIN_A9 109
+#define CFG_PIN_A10 110
+#define CFG_PIN_A11 111
+#define CFG_PIN_A12 112
+#define CFG_PIN_A13 113
+#define CFG_PIN_A14 114
+#define CFG_PIN_A15 115
+#define CFG_PIN_A16 116
+#define CFG_PIN_A17 117
+#define CFG_PIN_A18 118
+#define CFG_PIN_A19 119
+#define CFG_PIN_A20 120
+#define CFG_PIN_A21 121
+#define CFG_PIN_A22 122
+#define CFG_PIN_A23 123
+#define CFG_PIN_A24 124
+#define CFG_PIN_A25 125
+#define CFG_PIN_A26 126
+#define CFG_PIN_A27 127
+#define CFG_PIN_A28 128
+#define CFG_PIN_A29 129
+#define CFG_PIN_A30 130
+#define CFG_PIN_A31 131
+
+#define CFG_PIN_D0 150
+#define CFG_PIN_D1 151
+#define CFG_PIN_D2 152
+#define CFG_PIN_D3 153
+#define CFG_PIN_D4 154
+#define CFG_PIN_D5 155
+#define CFG_PIN_D6 156
+#define CFG_PIN_D7 157
+#define CFG_PIN_D8 158
+#define CFG_PIN_D9 159
+#define CFG_PIN_D10 160
+#define CFG_PIN_D11 161
+#define CFG_PIN_D12 162
+#define CFG_PIN_D13 163
+#define CFG_PIN_D14 164
+#define CFG_PIN_D15 165
+#define CFG_PIN_D16 166
+#define CFG_PIN_D17 167
+#define CFG_PIN_D18 168
+#define CFG_PIN_D19 169
+#define CFG_PIN_D20 170
+#define CFG_PIN_D21 171
+#define CFG_PIN_D22 172
+#define CFG_PIN_D23 173
+#define CFG_PIN_D24 174
+#define CFG_PIN_D25 175
+#define CFG_PIN_D26 176
+#define CFG_PIN_D27 177
+#define CFG_PIN_D28 178
+#define CFG_PIN_D29 179
+#define CFG_PIN_D30 180
+#define CFG_PIN_D31 181
+
+#define CFG_NUM_NEOPIXELS 200
+#define CFG_NUM_DOTSTARS 201
+#define CFG_DEFAULT_BUTTON_MODE 202
+#define CFG_SWD_ENABLED 203
+#define CFG_FLASH_BYTES 204
+#define CFG_RAM_BYTES 205
+#define CFG_SYSTEM_HEAP_BYTES 206
+#define CFG_LOW_MEM_SIMULATION_KB 207
+#define CFG_BOOTLOADER_BOARD_ID 208
+#define CFG_UF2_FAMILY 209
+#define CFG_PINS_PORT_SIZE 210
+#define CFG_BOOTLOADER_PROTECTION 211
+#define CFG_POWER_DEEPSLEEP_TIMEOUT 212
+#define CFG_ANALOG_BUTTON_THRESHOLD 213
+#define CFG_CPU_MHZ 214
+#define CFG_CONTROLLER_LIGHT_MAX_BRIGHTNESS 215
+#define CFG_ANALOG_JOYSTICK_MIN 216
+#define CFG_ANALOG_JOYSTICK_MAX 217
+#define CFG_TIMERS_TO_USE 218
+// configs to specify the onboard (built-in) dotstar or neopixel strips
+// some boards have a combination of dotstar, neopixel strips like neotrellis
+#define CFG_PIN_ONBOARD_DOTSTAR_CLOCK 219
+#define CFG_PIN_ONBOARD_DOTSTAR_DATA 220
+#define CFG_NUM_ONBOARD_DOTSTARS 221
+#define CFG_PIN_ONBOARD_NEOPIXEL 222
+#define CFG_NUM_ONBOARD_NEOPIXELS 223
+
+#define CFG_MATRIX_KEYPAD_MESSAGE_ID 239
+#define CFG_NUM_MATRIX_KEYPAD_ROWS 240
+#define CFG_PIN_MATRIX_KEYPAD_ROW0 241
+#define CFG_PIN_MATRIX_KEYPAD_ROW1 242
+#define CFG_PIN_MATRIX_KEYPAD_ROW2 243
+#define CFG_PIN_MATRIX_KEYPAD_ROW3 244
+#define CFG_PIN_MATRIX_KEYPAD_ROW4 245
+#define CFG_PIN_MATRIX_KEYPAD_ROW5 246
+#define CFG_PIN_MATRIX_KEYPAD_ROW6 247
+#define CFG_PIN_MATRIX_KEYPAD_ROW7 248
+#define CFG_NUM_MATRIX_KEYPAD_COLS 250
+#define CFG_PIN_MATRIX_KEYPAD_COL0 251
+#define CFG_PIN_MATRIX_KEYPAD_COL1 252
+#define CFG_PIN_MATRIX_KEYPAD_COL2 253
+#define CFG_PIN_MATRIX_KEYPAD_COL3 254
+#define CFG_PIN_MATRIX_KEYPAD_COL4 255
+#define CFG_PIN_MATRIX_KEYPAD_COL5 256
+#define CFG_PIN_MATRIX_KEYPAD_COL6 257
+#define CFG_PIN_MATRIX_KEYPAD_COL7 258
+
+#define CFG_PIN_B0 300
+#define CFG_PIN_B1 301
+#define CFG_PIN_B2 302
+#define CFG_PIN_B3 303
+#define CFG_PIN_B4 304
+#define CFG_PIN_B5 305
+#define CFG_PIN_B6 306
+#define CFG_PIN_B7 307
+#define CFG_PIN_B8 308
+#define CFG_PIN_B9 309
+#define CFG_PIN_B10 310
+#define CFG_PIN_B11 311
+#define CFG_PIN_B12 312
+#define CFG_PIN_B13 313
+#define CFG_PIN_B14 314
+#define CFG_PIN_B15 315
+#define CFG_PIN_B16 316
+#define CFG_PIN_B17 317
+#define CFG_PIN_B18 318
+#define CFG_PIN_B19 319
+#define CFG_PIN_B20 320
+#define CFG_PIN_B21 321
+#define CFG_PIN_B22 322
+#define CFG_PIN_B23 323
+#define CFG_PIN_B24 324
+#define CFG_PIN_B25 325
+#define CFG_PIN_B26 326
+#define CFG_PIN_B27 327
+#define CFG_PIN_B28 328
+#define CFG_PIN_B29 329
+#define CFG_PIN_B30 330
+#define CFG_PIN_B31 331
+
+#define CFG_PIN_C0 350
+#define CFG_PIN_C1 351
+#define CFG_PIN_C2 352
+#define CFG_PIN_C3 353
+#define CFG_PIN_C4 354
+#define CFG_PIN_C5 355
+#define CFG_PIN_C6 356
+#define CFG_PIN_C7 357
+#define CFG_PIN_C8 358
+#define CFG_PIN_C9 359
+#define CFG_PIN_C10 360
+#define CFG_PIN_C11 361
+#define CFG_PIN_C12 362
+#define CFG_PIN_C13 363
+#define CFG_PIN_C14 364
+#define CFG_PIN_C15 365
+#define CFG_PIN_C16 366
+#define CFG_PIN_C17 367
+#define CFG_PIN_C18 368
+#define CFG_PIN_C19 369
+#define CFG_PIN_C20 370
+#define CFG_PIN_C21 371
+#define CFG_PIN_C22 372
+#define CFG_PIN_C23 373
+#define CFG_PIN_C24 374
+#define CFG_PIN_C25 375
+#define CFG_PIN_C26 376
+#define CFG_PIN_C27 377
+#define CFG_PIN_C28 378
+#define CFG_PIN_C29 379
+#define CFG_PIN_C30 380
+#define CFG_PIN_C31 381
+
+#define CFG_PIN_P0 400
+#define CFG_PIN_P1 401
+#define CFG_PIN_P2 402
+#define CFG_PIN_P3 403
+#define CFG_PIN_P4 404
+#define CFG_PIN_P5 405
+#define CFG_PIN_P6 406
+#define CFG_PIN_P7 407
+#define CFG_PIN_P8 408
+#define CFG_PIN_P9 409
+#define CFG_PIN_P10 410
+#define CFG_PIN_P11 411
+#define CFG_PIN_P12 412
+#define CFG_PIN_P13 413
+#define CFG_PIN_P14 414
+#define CFG_PIN_P15 415
+#define CFG_PIN_P16 416
+#define CFG_PIN_P17 417
+#define CFG_PIN_P18 418
+#define CFG_PIN_P19 419
+#define CFG_PIN_P20 420
+#define CFG_PIN_P21 421
+#define CFG_PIN_P22 422
+#define CFG_PIN_P23 423
+#define CFG_PIN_P24 424
+#define CFG_PIN_P25 425
+#define CFG_PIN_P26 426
+#define CFG_PIN_P27 427
+#define CFG_PIN_P28 428
+#define CFG_PIN_P29 429
+#define CFG_PIN_P30 430
+#define CFG_PIN_P31 431
+#define CFG_PIN_P32 432
+#define CFG_PIN_P33 433
+#define CFG_PIN_P34 434
+#define CFG_PIN_P35 435
+#define CFG_PIN_P36 436
+#define CFG_PIN_P37 437
+#define CFG_PIN_P38 438
+#define CFG_PIN_P39 439
+#define CFG_PIN_P40 440
+#define CFG_PIN_P41 441
+#define CFG_PIN_P42 442
+#define CFG_PIN_P43 443
+#define CFG_PIN_P44 444
+#define CFG_PIN_P45 445
+#define CFG_PIN_P46 446
+#define CFG_PIN_P47 447
+#define CFG_PIN_P48 448
+#define CFG_PIN_P49 449
+#define CFG_PIN_P50 450
+#define CFG_PIN_P51 451
+#define CFG_PIN_P52 452
+#define CFG_PIN_P53 453
+#define CFG_PIN_P54 454
+#define CFG_PIN_P55 455
+#define CFG_PIN_P56 456
+#define CFG_PIN_P57 457
+#define CFG_PIN_P58 458
+#define CFG_PIN_P59 459
+#define CFG_PIN_P60 460
+#define CFG_PIN_P61 461
+#define CFG_PIN_P62 462
+#define CFG_PIN_P63 463
+
+#define CFG_PIN_LORA_MISO 1001
+#define CFG_PIN_LORA_MOSI 1002
+#define CFG_PIN_LORA_SCK 1003
+#define CFG_PIN_LORA_CS 1004
+#define CFG_PIN_LORA_BOOT 1005
+#define CFG_PIN_LORA_RESET 1006
+#define CFG_PIN_IRRXLED 1007
+#define CFG_PIN_IRTXLED 1008
+#define CFG_PIN_LCD_RESET 1009
+#define CFG_PIN_LCD_ENABLE 1010
+#define CFG_PIN_LCD_DATALINE4 1011
+#define CFG_PIN_LCD_DATALINE5 1012
+#define CFG_PIN_LCD_DATALINE6 1013
+#define CFG_PIN_LCD_DATALINE7 1014
+#define CFG_NUM_LCD_COLUMNS 1015
+#define CFG_NUM_LCD_ROWS 1016
+
+//RoboHAT MM1 pinout
+#define CFG_PIN_RCC0 1017
+#define CFG_PIN_RCC1 1018
+#define CFG_PIN_RCC2 1019
+#define CFG_PIN_RCC3 1020
+#define CFG_PIN_RCC4 1021
+#define CFG_PIN_RCC5 1022
+#define CFG_PIN_RCC6 1023
+#define CFG_PIN_RCC7 1024
+#define CFG_PIN_SERVO0 1025
+#define CFG_PIN_SERVO1 1026
+#define CFG_PIN_SERVO2 1027
+#define CFG_PIN_SERVO3 1028
+#define CFG_PIN_SERVO4 1029
+#define CFG_PIN_SERVO5 1030
+#define CFG_PIN_SERVO6 1031
+#define CFG_PIN_SERVO7 1032
+#define CFG_PIN_SERVO8 1033
+#define CFG_PIN_PI_TX 1034
+#define CFG_PIN_PI_RX 1035
+#define CFG_PIN_GPS_SDA 1036
+#define CFG_PIN_GPS_SCL 1037
+#define CFG_PIN_GPS_TX 1038
+#define CFG_PIN_GPS_RX 1039
+#define CFG_PIN_GROVE0 1040
+#define CFG_PIN_GROVE1 1041
+#define CFG_PIN_SS 1042
+
+// Adafruit Grand Central M4
+#define CFG_PIN_D33 183
+#define CFG_PIN_D34 184
+#define CFG_PIN_D35 185
+#define CFG_PIN_D36 186
+#define CFG_PIN_D37 187
+#define CFG_PIN_D38 188
+#define CFG_PIN_D39 189
+#define CFG_PIN_D40 190
+#define CFG_PIN_D41 191
+#define CFG_PIN_D42 192
+#define CFG_PIN_D43 193
+#define CFG_PIN_D44 194
+#define CFG_PIN_D45 195
+#define CFG_PIN_D46 196
+#define CFG_PIN_D47 197
+#define CFG_PIN_D48 198
+#define CFG_PIN_D49 199
+#define CFG_PIN_D50 259
+#define CFG_PIN_D51 260
+#define CFG_PIN_D52 261
+#define CFG_PIN_D53 262
+
+#define CFG_PIN_TX1 263
+#define CFG_PIN_TX2 264
+#define CFG_PIN_TX3 265
+#define CFG_PIN_RX1 266
+#define CFG_PIN_RX2 267
+#define CFG_PIN_RX3 268
+#define CFG_PIN_SCL1 269
+#define CFG_PIN_SDA1 270
+#define CFG_PIN_PCC_D0 271
+#define CFG_PIN_PCC_D1 272
+#define CFG_PIN_PCC_D2 273
+#define CFG_PIN_PCC_D3 274
+#define CFG_PIN_PCC_D4 275
+#define CFG_PIN_PCC_D5 276
+#define CFG_PIN_PCC_D6 277
+#define CFG_PIN_PCC_D7 278
+#define CFG_PIN_PCC_D8 279
+#define CFG_PIN_PCC_D9 280
+#define CFG_PIN_PCC_D10 281
+#define CFG_PIN_PCC_D11 282
+#define CFG_PIN_PCC_D12 283
+#define CFG_PIN_PCC_D13 284
+#define CFG_PIN_CC_DEN1 285
+#define CFG_PIN_CC_DEN2 286
+#define CFG_PIN_CC_CLK 287
+#define CFG_PIN_XCC_CLK 288
+
+
+#define CFG_PIN_JDPWR_PRE_SENSE 1100
+#define CFG_PIN_JDPWR_GND_SENSE 1101
+#define CFG_PIN_JDPWR_PULSE 1102
+#define CFG_PIN_JDPWR_OVERLOAD_LED 1103
+#define CFG_PIN_JDPWR_ENABLE 1104
+#define CFG_PIN_JDPWR_FAULT 1105
+
+#endif
+`
+
+const configKeys = {}
+CONFIG_KEYS_H.replace(/#define\s+CFG_(\w+)\s+(\w+)/g, function (m, name, value) {
+    configKeys[name] = parseInt(value);
+    return "";
+})
+
+const enums = {
+    // these are the same as the default I2C ID
+    ACCELEROMETER_TYPE: {
+        LIS3DH: 0x32,
+        LIS3DH_ALT: 0x30,
+        MMA8453: 0x38,
+        FXOS8700: 0x3C,
+        MMA8653: 0x3A,
+        MSA300: 0x4C,
+        MPU6050: 0x68,
+    },
+    UF2_FAMILY: {
+        ATSAMD21: 0x68ed2b88,
+        ATSAML21: 0x1851780a,
+        ATSAMD51: 0x55114460,
+        NRF52840: 0x1b57745f,
+        STM32F103: 0x5ee21072,
+        STM32F401: 0x57755a57,
+        ATMEGA32: 0x16573617,
+        CYPRESS_FX2: 0x5a18069b,
+    },
+    PINS_PORT_SIZE: {
+        PA_16: 0x10, // PA00-PA15, PB00-PB15, ... - STM32
+        PA_32: 0x20, // PA00-PA31, ... - ATSAMD
+        P0_16: 0x1010, // P0_0-P0_15, P1_0-P1_15, ...
+        P0_32: 0x1020, // P0_0-P0_32, ... - NRF
+    },
+    DEFAULT_BUTTON_MODE: {
+        ACTIVE_HIGH_PULL_DOWN: 0x11,
+        ACTIVE_HIGH_PULL_UP: 0x21,
+        ACTIVE_HIGH_PULL_NONE: 0x31,
+        ACTIVE_LOW_PULL_DOWN: 0x10,
+        ACTIVE_LOW_PULL_UP: 0x20,
+        ACTIVE_LOW_PULL_NONE: 0x30,
+    },
+    DISPLAY_TYPE: {
+        ST7735: 7735,
+        ILI9341: 9341,
+    },
+    ".": {
+        BTN_FLAG_ACTIVE_HIGH: 0x110000,
+        BTN_FLAG_ACTIVE_LOW: 0x200000,
+        BTN_OFFSET_ANALOG_PLUS: 1100,
+        BTN_OFFSET_ANALOG_MINUS: 1200,
+    }
+}
+
+
+let infoMsg = ""
+
+function log(msg) {
+    msg = "# " + msg
+    infoMsg += msg + "\n"
+    console.log(msg)
+}
+
+function help() {
+    console.log(`
+USAGE: node patch-cfg.js file.uf2 [patch.cf2]
+
+Without .cf2 file, it will parse config in the UF2 file and print it out
+(in .cf2 format).
+
+With .cf2 file, it will patch in-place the UF2 file with specified config.
+`)
+    process.exit(1)
+}
+
+function readBin(fn) {
+    const fs = require("fs")
+
+    if (!fn) {
+        console.log("Required argument missing.")
+        help()
+    }
+
+    try {
+        return fs.readFileSync(fn)
+    } catch (e) {
+        console.log("Cannot read file '" + fn + "': " + e.message)
+        help()
+    }
+}
+const configInvKeys = {}
+
+const UF2_MAGIC_START0 = 0x0A324655 // "UF2\n"
+const UF2_MAGIC_START1 = 0x9E5D5157 // Randomly selected
+const UF2_MAGIC_END = 0x0AB16F30 // Ditto
+
+const CFG_MAGIC0 = 0x1e9e10f1
+const CFG_MAGIC1 = 0x20227a79
+
+let all_defines = {}
+
+function configkeysH() {
+    let r = "#ifndef __CONFIGKEYS_H\n#define __CONFIGKEYS_H 1\n\n"
+
+    const add = (k, v) => {
+        all_defines[k] = v
+        if (v > 1000 || !/^CFG_/.test(k))
+            v = "0x" + v.toString(16)
+        else
+            v += ""
+        r += "#define " + k + " " + v + "\n"
+    }
+
+    add("CFG_MAGIC0", CFG_MAGIC0)
+    add("CFG_MAGIC1", CFG_MAGIC1)
+    r += "\n"
+
+    for (let k of Object.keys(configKeys)) {
+        add("CFG_" + k, configKeys[k])
+    }
+    for (let k of Object.keys(enums)) {
+        r += "\n"
+        for (let kk of Object.keys(enums[k])) {
+            let n = k == "." ? kk : `${k}_${kk}`
+            add(n, enums[k][kk])
+        }
+    }
+    r += "\n#endif // __CONFIGKEYS_H\n"
+    return r
+}
+
+function err(msg) {
+    log("Fatal error: " + msg)
+    if (typeof window == "undefined") {
+        process.exit(1)
+    } else {
+        throw new Error(msg)
+    }
+}
+
+function read32(buf, off) {
+    return (buf[off + 0] | (buf[off + 1] << 8) | (buf[off + 2] << 16) | (buf[off + 3] << 24)) >>> 0
+}
+
+function write32(buf, off, v) {
+    buf[off + 0] = v & 0xff
+    buf[off + 1] = (v >> 8) & 0xff
+    buf[off + 2] = (v >> 16) & 0xff
+    buf[off + 3] = (v >> 24) & 0xff
+}
+
+function patchHFile(file, patch) {
+    configkeysH()
+    let resFile = ""
+    let inZone = false
+    let flags = {}
+    let lineNo = 0
+    let nums = []
+    for (let line0 of file.split(/\n/)) {
+        lineNo++
+        let append = line0 + "\n"
+        let line = line0.trim().replace(/\/\/.*/, "")
+        if (inZone) {
+            if (line.indexOf("/* CF2 END */") >= 0) {
+                inZone = false
+                if (patch) {
+                    let portSize = lookupCfg(patch, configKeys.PINS_PORT_SIZE)
+                    let s = ""
+                    let size = flags["size"] || 100
+                    let numentries = patch.length >> 1
+                    size = Math.max(size, numentries + 4)
+                    s += `    ${CFG_MAGIC0}, ${CFG_MAGIC1}, // magic\n`
+                    s += `    ${numentries}, ${size},  // used entries, total entries\n`
+                    for (let i = 0; i < numentries; ++i) {
+                        let k = patch[i * 2]
+                        let v = patch[i * 2 + 1]
+                        s += `    ${k}, 0x${v.toString(16)}, // ${showKV(k, v, portSize, patch)}\n`
+                    }
+                    s += "   "
+                    for (let i = 0; i < size - numentries; ++i) {
+                        if (i && i % 16 == 0)
+                            s += "\n   "
+                        s += " 0, 0,"
+                    }
+                    s += "\n"
+                    append = s + line0 + "\n"
+                }
+            } else {
+                append = ""
+                let toks = line.split(/,\s*/).map(s => s.trim()).filter(s => !!s)
+                for (let tok of toks) {
+                    let n = parseInt(tok)
+                    if (isNaN(n)) {
+                        n = all_defines[tok]
+                        if (n === undefined) {
+                            let portSize = lookupCfg(nums, configKeys.PINS_PORT_SIZE)
+                            if (portSize) portSize &= 0xfff;
+                            let pp = parsePinName(tok.replace(/^PIN_/, ""), portSize)
+                            if (pp !== undefined) {
+                                n = pp
+                            } else {
+                                err(`unknown value ${tok} at line ${lineNo}`)
+                            }
+                        }
+                    }
+                    nums.push(n)
+                }
+            }
+        } else {
+            let m = /\/\* CF2 START (.*)/.exec(line)
+            if (m) {
+                inZone = true
+                for (let k of m[1].split(/\s+/)) {
+                    let mm = /^(\w+)=(\d+)$/.exec(k)
+                    if (mm)
+                        flags[mm[1]] = parseInt(mm[2])
+                    else
+                        flags[k] = true
+                }
+            }
+        }
+        resFile += append
+    }
+
+    if (nums.length) {
+        if (nums[0] != CFG_MAGIC0 || nums[1] != CFG_MAGIC1)
+            err("no magic in H file")
+        nums = nums.slice(4)
+        for (let i = 0; i < nums.length; i += 2) {
+            if (nums[i] == 0) {
+                if (nums.slice(i).some(x => x != 0))
+                    err("config keys follow zero terminator")
+                else
+                    nums = nums.slice(0, i)
+                break
+            }
+        }
+    }
+
+    return {
+        patched: resFile,
+        data: nums
+    }
+}
+
+function bufToString(buf) {
+    let s = ""
+    for (let i = 0; i < buf.length; ++i)
+        s += String.fromCharCode(buf[i])
+    return s
+}
+
+function stringToBuf(str) {
+    let buf = new Uint8Array(str.length)
+    for (let i = 0; i < buf.length; ++i)
+        buf[i] = str.charCodeAt(i)
+    return buf
+}
+
+function readWriteConfig(buf, patch) {
+    let patchPtr = null
+    let origData = []
+    let cfgLen = 0
+    let isUF2 = false
+    if (read32(buf, 0) == UF2_MAGIC_START0) {
+        isUF2 = true
+        log("detected UF2 file")
+    } else {
+        let stackBase = read32(buf, 0)
+        if ((stackBase & 0xff000003) == 0x20000000 &&
+            (read32(buf, 4) & 1) == 1) {
+            log("detected BIN file")
+        } else {
+            let str = bufToString(buf)
+            if (str.indexOf("/* CF2 START") >= 0) {
+                log("detected CF2 header file")
+                let rr = patchHFile(str, patch)
+                console.log(rr.data)
+                return patch ? stringToBuf(rr.patched) : rr.data
+            } else {
+                err("unknown file format")
+            }
+        }
+    }
+    if (patch)
+        patch.push(0, 0)
+    for (let off = 0; off < buf.length; off += 512) {
+        let start = 0
+        let payloadLen = 512
+        let addr = off
+
+        if (isUF2) {
+            start = 32
+            if (read32(buf, off) != UF2_MAGIC_START0 ||
+                read32(buf, off + 4) != UF2_MAGIC_START1) {
+                err("invalid data at " + off)
+            }
+            payloadLen = read32(buf, off + 16)
+            addr = read32(buf, off + 12) - 32
+        }
+
+        for (let i = start; i < start + payloadLen; i += 4) {
+            if (read32(buf, off + i) == CFG_MAGIC0 &&
+                read32(buf, off + i + 4) == CFG_MAGIC1) {
+                let addrS = "0x" + (addr + i).toString(16)
+                if (patchPtr === null) {
+                    log(`Found CFG DATA at ${addrS}`)
+                    patchPtr = -4
+                } else {
+                    if (patch) {
+                        log(`Also patching at ${addrS}`)
+                        patchPtr = -4
+                    } else {
+                        log(`Skipping second CFG DATA at ${addrS}`)
+                    }
+                }
+            }
+
+            if (patchPtr !== null) {
+                if (patchPtr == -2) {
+                    cfgLen = read32(buf, off + i)
+                    if (patch)
+                        write32(buf, off + i, (patch.length >> 1) - 1)
+                }
+
+                if (patchPtr >= 0) {
+                    if (origData.length < cfgLen * 2 + 40)
+                        origData.push(read32(buf, off + i))
+                    if (patch) {
+                        if (patchPtr < patch.length) {
+                            write32(buf, off + i, patch[patchPtr])
+                        }
+                    }
+                }
+                patchPtr++
+            }
+        }
+    }
+
+    let len0 = cfgLen * 2
+    origData.push(0, 0)
+    while (origData[len0])
+        len0 += 2
+    origData = origData.slice(0, len0 + 2)
+    if (len0 != cfgLen * 2)
+        log("size information incorrect; continuing anyway")
+
+    if (origData.length == 0)
+        err("config data not found")
+    if (patch && patchPtr < patch.length)
+        err("no space for config data")
+    let tail = origData.slice(origData.length - 2)
+    if (tail.some(x => x != 0))
+        err("config data not zero terminated: " + tail.join(","))
+    origData = origData.slice(0, origData.length - 2)
+    return patch ? buf : origData
+}
+
+function lookupCfg(cfgdata, key) {
+    for (let i = 0; i < cfgdata.length; i += 2)
+        if (cfgdata[i] == key)
+            return cfgdata[i + 1]
+    return null
+}
+
+function pinToString(pinNo, portSize) {
+    if (!portSize || pinNo >= 1000)
+        return "P_" + pinNo
+
+    let useLetters = true
+    let theSize = portSize & 0xfff
+    if (portSize & 0x1000) {
+        useLetters = true
+    }
+    let port = (pinNo / theSize) | 0
+    let pin = pinNo % theSize
+    if (useLetters) {
+        return "P" + String.fromCharCode(65 + port) + ("0" + pin.toString()).slice(-2)
+    } else {
+        return "P" + port + "_" + pin
+    }
+}
+
+function isHeaderPin(n) {
+    return /^PIN_(MOSI|MISO|SCK|SDA|SCL|RX|TX|[AD]\d+)$/.test(n)
+}
+
+function keyWeight(k) {
+    if (k == "PINS_PORT_SIZE")
+        return 10
+    if (isHeaderPin(k))
+        return 20
+    if (/^PIN_/.test(k))
+        return 30
+    return 40
+}
+
+function expandNum(k) {
+    return k.replace(/\d+/g, f => {
+        if (f.length > 4)
+            return f
+        return ("0000" + f).slice(-4)
+    })
+}
+
+function cmpKeys(a, b) {
+    a = a.replace(/ =.*/, "")
+    b = b.replace(/ =.*/, "")
+    if (a == b)
+        return 0
+    let d = keyWeight(a) - keyWeight(b)
+    if (d) return d
+    let aa = expandNum(a)
+    let bb = expandNum(b)
+    if (aa < bb) return -1
+    else if (bb < aa) return 1
+    else if (a < b) return -1
+    else return 1
+}
+
+function showKV(k, v, portSize, data) {
+    let vn = ""
+
+    let kn = configInvKeys[k + ""] || ""
+
+    if (enums[kn]) {
+        for (let en of Object.keys(enums[kn])) {
+            if (enums[kn][en] == v) {
+                vn = en
+                break
+            }
+        }
+    }
+
+    if (vn == "") {
+        if (/_CFG/.test(kn) || v > 10000)
+            vn = "0x" + v.toString(16)
+        else if (/^PIN_/.test(kn)) {
+            if (data && !isHeaderPin(kn)) {
+                for (let pn of Object.keys(configKeys)) {
+                    if (isHeaderPin(pn) && lookupCfg(data, configKeys[pn]) === v) {
+                        vn = pn
+                        break
+                    }
+                }
+            }
+            if (!vn)
+                vn = pinToString(v, portSize)
+        } else
+            vn = v + ""
+    }
+
+    if (kn == "")
+        kn = "_" + k
+
+    return `${kn} = ${vn}`
+}
+
+function readConfig(buf) {
+    init()
+    let cfgdata = readWriteConfig(buf, null)
+    let portSize = lookupCfg(cfgdata, configKeys.PINS_PORT_SIZE)
+    let numentries = cfgdata.length >> 1
+    let lines = []
+    for (let i = 0; i < numentries; ++i) {
+        lines.push(showKV(cfgdata[i * 2], cfgdata[i * 2 + 1], portSize, cfgdata))
+    }
+    lines.sort(cmpKeys)
+    return lines.length ? lines.join("\n") : "Empty config."
+}
+
+function parsePinName(v, portSize) {
+    let thePort = -1
+    let pin = -1
+
+    v = v.trim()
+
+    v = v.replace(/^DAL\./, "")
+
+    const env = enums["."][v]
+    if (env !== undefined)
+        return env
+
+    let m = /(.*)([\|+])(.*)/.exec(v)
+    if (m) {
+        let v0 = parsePinName(m[1], portSize)
+        let v1 = parsePinName(m[3], portSize)
+        if (v0 === undefined || v1 === undefined)
+            return undefined
+        v0 = parseInt(v0)
+        v1 = parseInt(v1)
+        return "" + (m[2] == "|" ? v0 | v1 : v0 + v1)
+    }
+
+    m = /^P([A-Z])_?(\d+)$/.exec(v)
+    if (m) {
+        pin = parseInt(m[2])
+        thePort = m[1].charCodeAt(0) - 65
+    }
+
+    m = /^P(\d+)_(\d+)$/.exec(v)
+    if (m) {
+        pin = parseInt(m[2])
+        thePort = parseInt(m[1])
+    }
+
+    if (thePort >= 0) {
+        if (!portSize) err("PINS_PORT_SIZE not specified, while trying to parse PIN " + v)
+        if (pin >= portSize) err("Pin name invalid: " + v)
+        return (thePort * portSize + pin) + ""
+    }
+
+    m = /^P_?(\d+)$/.exec(v)
+    if (m)
+        return m[1]
+
+    return undefined
+}
+
+function patchConfig(buf, cfg) {
+    init()
+    const cfgMap = {}
+    let lineNo = 0
+    for (let line of cfg.split(/\n/)) {
+        lineNo++
+        line = line.replace(/(#|\/\/).*/, "")
+        line = line.trim()
+        if (!line)
+            continue
+        let m = /(\w+)\s*=\s*([^#]+)/.exec(line)
+        if (!m)
+            err("syntax error at config line " + lineNo)
+        let kn = m[1].toUpperCase()
+        let k = configKeys[kn]
+        if (!k && /^_\d+$/.test(kn))
+            k = parseInt(kn.slice(1))
+        if (!k)
+            err("Unrecognized key name: " + kn)
+        cfgMap[k + ""] = m[2]
+    }
+
+    let cfgdata = readWriteConfig(buf, null)
+
+    for (let i = 0; i < cfgdata.length; i += 2) {
+        let k = cfgdata[i] + ""
+        if (!cfgMap.hasOwnProperty(k))
+            cfgMap[k] = cfgdata[i + 1] + ""
+    }
+
+    const forAll = f => {
+        for (let k of Object.keys(cfgMap)) {
+            let kn = configInvKeys[k]
+            f(kn, k, cfgMap[k])
+        }
+    }
+
+    // expand enums
+    forAll((kn, k, v) => {
+        let e = enums[kn]
+        if (e && e[v.toUpperCase()])
+            cfgMap[k] = e[v] + ""
+    })
+
+    let portSize = cfgMap[configKeys.PINS_PORT_SIZE]
+    if (portSize) portSize = parseInt(portSize)
+    let portSize0 = portSize
+    if (portSize)
+        portSize &= 0xfff;
+
+    // expand pin names
+    forAll((kn, k, v) => {
+        let p = parsePinName(v, portSize)
+        if (p)
+            cfgMap[k] = p
+    })
+
+    // expand existing keys
+    for (let i = 0; i < 10; ++i)
+        forAll((kn, k, v) => {
+            if (configKeys[v]) {
+                let curr = cfgMap[configKeys[v] + ""]
+                if (curr == null)
+                    err("Value not specified, but referenced: " + v)
+                cfgMap[k] = curr
+            }
+        })
+
+    let changes = ""
+    forAll((kn, k, v) => {
+        v = v.toUpperCase()
+        if (v == "NULL" || v == "UNDEFINED") {
+            let old = lookupCfg(cfgdata, k)
+            changes += "remove " + showKV(k, old, portSize0) + "\n"
+            delete cfgMap[k]
+        }
+    })
+
+    forAll((kn, k, v) => {
+        if (isNaN(parseInt(v)))
+            err("Value not understood: " + v)
+    })
+
+    let sorted = Object.keys(cfgMap)
+    sorted.sort((a, b) => parseInt(a) - parseInt(b))
+    let patch = []
+    for (let k of sorted) {
+        patch.push(parseInt(k))
+        patch.push(parseInt(cfgMap[k]))
+    }
+
+    for (let i = 0; i < patch.length; i += 2) {
+        let k = patch[i]
+        let v = patch[i + 1]
+        let old = lookupCfg(cfgdata, k)
+        if (old != v) {
+            let newOne = showKV(k, v, portSize0)
+            if (old !== null) {
+                let oldOne = showKV(k, old, portSize0)
+                newOne += " (was: " + oldOne.replace(/.* = /, "") + ")"
+            }
+            changes += newOne + "\n"
+        }
+    }
+
+    let patched = readWriteConfig(buf, patch)
+
+    return {
+        changes,
+        patched
+    }
+}
+
+function parseHFile(hFile) {
+    if (!hFile) return
+    for (let line of hFile.split(/\n/)) {
+        line = line.trim()
+        let m = /#define\s+CFG_(\w+)\s+(\d+)/.exec(line)
+        if (m) {
+            let k = m[1]
+            let v = parseInt(m[2])
+            configKeys[k] = parseInt(v)
+            configInvKeys[v + ""] = k
+            console.log(`  ${k}: ${v},`)
+        }
+    }
+}
+
+function init() {
+    for (let k of Object.keys(configKeys)) {
+        let v = configKeys[k]
+        configInvKeys[v + ""] = k
+    }
+}
+
+function main() {
+    let uf2 = readBin(process.argv[2])
+
+    if (process.argv[3]) {
+        let cfg = readBin(process.argv[3]).toString("utf8")
+        let r = patchConfig(uf2, cfg)
+        if (!r.changes)
+            console.log("No changes.")
+        else
+            console.log("\nChanges:\n" + r.changes)
+        console.log("# Writing config...")
+        fs.writeFileSync(process.argv[2], r.patched)
+    } else {
+        console.log(readConfig(uf2))
+    }
+}
+
+
+if (typeof window == "undefined")
+    main()
\ No newline at end of file
diff --git a/uf2-samdx1/lib/uf2/patcher/web.js b/uf2-samdx1/lib/uf2/patcher/web.js
new file mode 100644
index 00000000..180fb18a
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/patcher/web.js
@@ -0,0 +1,109 @@
+"use strict";
+
+function savePatch(ev) {
+    let text = document.getElementById("patch")
+    localStorage["UF2_PATCH"] = text.value
+}
+
+function genRnd(ev) {
+    ev.preventDefault()
+    let vals = new Uint32Array(1)
+    window.crypto.getRandomValues(vals)
+    document.getElementById("rnd-res").textContent = "Random number: 0x" + 
+        ("000000000" + vals[0].toString(16)).slice(-8)
+}
+
+function restorePatch() {
+    let text = document.getElementById("patch")
+    text.value = localStorage["UF2_PATCH"] || ""
+    document.getElementById("apply").onclick = applyPatch
+    document.getElementById("rnd").onclick = genRnd
+}
+
+function download(buf, name) {
+    let blob = new Blob([buf], {
+        type: "application/x-uf2"
+    });
+    let url = URL.createObjectURL(blob);
+
+    let a = document.createElement("a");
+    document.body.appendChild(a);
+    a.style = "display: none";
+    a.href = url;
+    a.download = name;
+    a.click();
+    window.URL.revokeObjectURL(url);
+}
+
+let currUF2 = null
+let currUF2Name = ""
+
+function showMSG() {
+    if (infoMsg)
+        document.getElementById("currconfig").textContent = infoMsg
+}
+
+function wrap(f) {
+    try {
+        infoMsg = ""
+        f()
+        showMSG()
+    } catch (e) {
+        log("Exception: " + e.message)
+        showMSG()
+    }
+}
+
+function defines() {
+    download(configkeysH(), "configkeys.h")
+}
+
+function applyPatch() {
+    wrap(() => {
+        let text = document.getElementById("patch")
+        let newcfg = text.value.trim()
+        if (!currUF2)
+            log("You have to drop a UF2 or BIN file with bootloader above before applying patches.")
+        else if (!newcfg)
+            log("You didn't give any patch to apply.")
+        else {
+            let buf = currUF2.slice()
+            let r = patchConfig(buf, newcfg)
+            if (!r.changes) {
+                log("No changes.")
+            } else {
+                log("\nChanges:\n" + r.changes)
+            }
+            log("Downloading " + currUF2Name)
+            download(r.patched, currUF2Name)
+        }
+    })
+}
+
+function dropHandler(ev) {
+    ev.preventDefault();
+
+    for (let i = 0; i < ev.dataTransfer.items.length; i++) {
+        if (ev.dataTransfer.items[i].kind === 'file') {
+            let file = ev.dataTransfer.items[i].getAsFile();
+            let reader = new FileReader();
+            infoMsg = ""
+            reader.onload = e => {
+                wrap(() => {
+                    let buf = new Uint8Array(reader.result)
+                    let cfg = readConfig(buf)
+                    currUF2 = buf
+                    infoMsg += "\n" + cfg
+                    currUF2Name = file.name
+                })
+            }
+            reader.readAsArrayBuffer(file);
+            break
+        }
+    }
+}
+
+function dragOverHandler(ev) {
+    ev.preventDefault();
+    ev.dataTransfer.dropEffect = 'copy';
+}
\ No newline at end of file
diff --git a/uf2-samdx1/lib/uf2/uf2.h b/uf2-samdx1/lib/uf2/uf2.h
new file mode 100644
index 00000000..2128adc7
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/uf2.h
@@ -0,0 +1,67 @@
+/**
+
+Microsoft UF2
+
+The MIT License (MIT)
+
+Copyright (c) Microsoft Corporation
+
+All rights reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
+*/
+#ifndef UF2FORMAT_H
+#define UF2FORMAT_H 1
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// All entries are little endian.
+
+#define UF2_MAGIC_START0 0x0A324655UL // "UF2\n"
+#define UF2_MAGIC_START1 0x9E5D5157UL // Randomly selected
+#define UF2_MAGIC_END 0x0AB16F30UL    // Ditto
+
+// If set, the block is "comment" and should not be flashed to the device
+#define UF2_FLAG_NOFLASH        0x00000001
+#define UF2_FLAG_FILECONTAINER  0x00001000 // fle container
+#define UF2_FLAG_FAMILY_ID      0x00002000 // familyID present
+#define UF2_FLAG_MD5_CHKSUM     0x00004000 // MD5 checksum present
+#define UF2_FLAG_EXTENSION_TAGS 0x00008000 // extension tags present
+
+typedef struct {
+    // 32 byte header
+    uint32_t magicStart0;
+    uint32_t magicStart1;
+    uint32_t flags;
+    uint32_t targetAddr;
+    uint32_t payloadSize;
+    uint32_t blockNo;
+    uint32_t numBlocks;
+    uint32_t reserved;
+
+    // raw data;
+    uint8_t data[476];
+
+    // store magic also at the end to limit damage from partial block reads
+    uint32_t magicEnd;
+} UF2_Block;
+
+#endif
diff --git a/uf2-samdx1/lib/uf2/uf2tool/Makefile b/uf2-samdx1/lib/uf2/uf2tool/Makefile
new file mode 100644
index 00000000..efc615be
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/uf2tool/Makefile
@@ -0,0 +1,3 @@
+all:
+	mkdir -p ../built
+	$(CC) -g -Wall tool.c ../hidapi/mac/hid.c -I../../uf2-samd21/inc -I../hidapi/hidapi -I. -framework IOKit -framework CoreFoundation -o ../built/uf2tool
diff --git a/uf2-samdx1/lib/uf2/uf2tool/tool.c b/uf2-samdx1/lib/uf2/uf2tool/tool.c
new file mode 100644
index 00000000..9ec20a7e
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/uf2tool/tool.c
@@ -0,0 +1,359 @@
+#ifdef WIN32
+#include <windows.h>
+#endif
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/time.h>
+#include <stdbool.h>
+#include <pthread.h>
+#include "hidapi.h"
+#include "uf2hid.h"
+
+#define EP_SIZE 64
+
+typedef struct {
+    hid_device *dev;
+    uint16_t size;
+    uint8_t serial;
+    uint16_t seqNo;
+    uint16_t pageSize;
+    uint32_t flashSize;
+    uint32_t msgSize;
+    union {
+        uint8_t buf[64 * 1024];
+        HF2_Response resp;
+    };
+} HID_Dev;
+
+uint64_t millis() {
+    struct timeval tv;
+    gettimeofday(&tv, 0);
+    return tv.tv_sec * 1000 + tv.tv_usec / 1000;
+}
+
+void fatal(const char *msg) {
+    fprintf(stderr, "Fatal error: %s\n", msg);
+    exit(1);
+}
+
+void write16(uint8_t *ptr, uint16_t v) {
+    ptr[0] = v;
+    ptr[1] = v >> 8;
+}
+
+void write32(uint8_t *ptr, uint32_t v) {
+    ptr[0] = v;
+    ptr[1] = v >> 8;
+    ptr[2] = v >> 16;
+    ptr[3] = v >> 24;
+}
+
+uint32_t read32(uint8_t *ptr) { return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); }
+
+uint32_t read16(uint8_t *ptr) { return ptr[0] | (ptr[1] << 8); }
+
+int recv_hid(HID_Dev *pkt, int timeout) {
+    uint8_t buf0[EP_SIZE + 1];
+    uint8_t *buf;
+
+    pkt->size = 0;
+    memset(pkt->buf, 0, sizeof(pkt->buf));
+
+    for (;;) {
+        int sz = hid_read_timeout(pkt->dev, buf0, sizeof(buf0), timeout);
+        if (sz <= 0) {
+            if (timeout < 0)
+                fatal("read error");
+            return 0;
+        }
+        buf = buf0;
+        if (!*buf)
+            buf++; // skip report number if passed
+
+        uint8_t tag = buf[0];
+        if (pkt->size && (tag & HF2_FLAG_SERIAL_OUT))
+            fatal("invalid serial transfer");
+        uint32_t newsize = pkt->size + (tag & HF2_SIZE_MASK);
+        if (newsize > sizeof(pkt->buf))
+            fatal("too large packet");
+        memcpy(pkt->buf + pkt->size, buf + 1, tag & HF2_SIZE_MASK);
+        pkt->size = newsize;
+
+        tag &= HF2_FLAG_MASK;
+        if (tag != HF2_FLAG_CMDPKT_BODY) {
+            pkt->serial = //
+                tag == HF2_FLAG_SERIAL_OUT ? 1 : tag == HF2_FLAG_SERIAL_ERR ? 2 : 0;
+            return 1;
+        }
+
+        timeout = -1; // next read is blocking
+    }
+}
+
+void send_hid(hid_device *dev, const void *data, int size) {
+    uint8_t buf[EP_SIZE + 1] = {0};
+    const uint8_t *ptr = data;
+
+    for (;;) {
+        int s;
+        if (size <= EP_SIZE - 1) {
+            s = size;
+            buf[1] = HF2_FLAG_CMDPKT_LAST | size;
+        } else {
+            s = EP_SIZE - 1;
+            buf[1] = HF2_FLAG_CMDPKT_BODY | (EP_SIZE - 1);
+        }
+        memcpy(buf + 2, ptr, s);
+        int sz = hid_write(dev, buf, EP_SIZE + 1);
+        if (sz != EP_SIZE + 1)
+            fatal("write error");
+        ptr += s;
+        size -= s;
+        if (!size)
+            break;
+    }
+}
+
+void talk_hid(HID_Dev *pkt, int cmd, const void *data, uint32_t len) {
+    if (len >= sizeof(pkt->buf) - 8)
+        fatal("buffer overflow");
+    if (data)
+        memcpy(pkt->buf + 8, data, len);
+    write32(pkt->buf, cmd);
+    write16(pkt->buf + 4, ++pkt->seqNo);
+    write16(pkt->buf + 6, 0);
+    send_hid(pkt->dev, pkt->buf, 8 + len);
+
+    if (cmd == HF2_CMD_RESET_INTO_APP)
+        return; // no response expected
+
+    recv_hid(pkt, -1);
+    if (read16(pkt->buf) != pkt->seqNo)
+        fatal("invalid sequence number");
+    if (read16(pkt->buf + 2))
+        fatal("invalid status");
+}
+
+uint8_t flashbuf[2 * 1024 * 1024];
+
+unsigned short add_crc(char ptr, unsigned short crc) {
+    unsigned short cmpt;
+    crc = crc ^ (int)ptr << 8;
+    for (cmpt = 0; cmpt < 8; cmpt++) {
+        if (crc & 0x8000)
+            crc = crc << 1 ^ 0x1021;
+        else
+            crc = crc << 1;
+    }
+    return (crc & 0xFFFF);
+}
+
+void verify(HID_Dev *cmd, uint8_t *buf, int size, int offset) {
+    int maxSize = (cmd->pageSize / 2 - 12) * cmd->pageSize;
+    while (size > maxSize) {
+        verify(cmd, buf, maxSize, offset);
+        buf += maxSize;
+        offset += maxSize;
+        size -= maxSize;
+    }
+    int numpages = size / cmd->pageSize;
+    write32(cmd->buf + 8, offset);
+    write32(cmd->buf + 12, numpages);
+    talk_hid(cmd, HF2_CMD_CHKSUM_PAGES, 0, 8);
+    for (int i = 0; i < numpages; ++i) {
+        int sum = read16(cmd->buf + 4 + i * 2);
+        uint16_t crc = 0;
+        for (int j = 0; j < cmd->pageSize; ++j) {
+            crc = add_crc(buf[j], crc);
+        }
+        if (sum != crc)
+            fatal("verification failed");
+        buf += cmd->pageSize;
+    }
+}
+
+void *forward_stdin(void *cmd0) {
+    uint8_t buf[EP_SIZE + 1];
+    HID_Dev *cmd = cmd0;
+    for (;;) {
+        memset(buf, 0, sizeof(buf));
+        int sz = read(0, buf + 2, EP_SIZE - 1);
+        if (sz > 0) {
+            buf[1] = HF2_FLAG_SERIAL_OUT | sz;
+            hid_write(cmd->dev, buf, EP_SIZE + 1);
+        }
+        if (sz == 0)
+            break;
+    }
+    return NULL;
+}
+
+void serial(HID_Dev *cmd) {
+    pthread_t stdinFwd;
+    pthread_create(&stdinFwd, NULL, forward_stdin, cmd);
+    for (;;) {
+        if (recv_hid(cmd, -1)) {
+            if (cmd->serial)
+                write(cmd->serial, cmd->buf, cmd->size);
+        }
+    }
+}
+
+int main(int argc, char *argv[]) {
+    int res;
+    HID_Dev cmd = {0};
+
+    if (argc != 2) {
+        printf("usage: %s COMMAND [ARGUMENTS...]\n", argv[0]);
+        printf("Commands include:\n");
+        printf("   serial           - run 'serial' port forwarding\n");
+        printf("   list             - list devices\n");
+        printf("   dmesg            - dump internal runtime logs from the device\n");
+        printf("   info             - dump information about the device\n");
+        printf("   FILE             - write specified BIN or UF2 file\n");
+        printf("   random           - write randomly generated bin file\n");
+        return 1;
+    }
+
+    const char *filename = argv[1];
+
+    // Initialize the hidapi library
+    res = hid_init();
+
+    bool listMode = strcmp(filename, "list") == 0;
+
+    struct hid_device_info *devs = hid_enumerate(0, 0);
+    for (struct hid_device_info *p = devs; p; p = p->next) {
+        int isOK = (p->release_number & 0xff00) == 0x4200;
+        const char *path = strstr(p->path, "@1400");
+        if (!path)
+            path = p->path;
+        if (listMode) {
+            // exclude Apple devices
+            if (p->vendor_id != 0x05ac)
+                printf("%s: %04x:%04x %04x %s\n", isOK ? "HF2" : "...", p->vendor_id, p->product_id,
+                       p->release_number, path);
+        }
+        if (isOK) {
+            cmd.dev = hid_open_path(p->path);
+        }
+    }
+    hid_free_enumeration(devs);
+    if (listMode)
+        return 0;
+    if (!cmd.dev) {
+        printf("no devices\n");
+        return 1;
+    }
+
+    if (strcmp(filename, "serial") == 0) {
+        serial(&cmd);
+        return 0;
+    }
+
+    if (strcmp(filename, "dmesg") == 0) {
+        talk_hid(&cmd, HF2_CMD_DMESG, 0, 0);
+        printf("%s\n", cmd.buf + 4);
+        return 0;
+    }
+
+    talk_hid(&cmd, HF2_CMD_INFO, 0, 0);
+    printf("INFO: %s\n", cmd.buf + 4);
+
+    talk_hid(&cmd, HF2_CMD_START_FLASH, 0, 0);
+
+    talk_hid(&cmd, HF2_CMD_BININFO, 0, 0);
+    if (cmd.buf[4] != HF2_MODE_BOOTLOADER)
+        fatal("not bootloader");
+
+    cmd.pageSize = read32(cmd.buf + 8);
+    cmd.flashSize = read32(cmd.buf + 12) * cmd.pageSize;
+    cmd.msgSize = read32(cmd.buf + 16);
+    printf("page size: %d, total: %dkB\n", cmd.pageSize, cmd.flashSize / 1024);
+
+    if (strcmp(filename, "info") == 0) {
+        return 0;
+    }
+
+    int i;
+    size_t filesize;
+    int isUF2 = 0;
+
+    if (strcmp(filename, "random") == 0) {
+        srand(millis());
+        filesize = 230 * 1024;
+        for (i = 0; i < filesize; ++i)
+            flashbuf[i] = rand();
+    } else {
+        FILE *f = fopen(filename, "rb");
+        if (!f) {
+            fatal("cannot open file");
+        }
+        int len = 1;
+        filesize = 0;
+        while (len) {
+            len = fread(flashbuf + filesize, 1, sizeof(flashbuf) - filesize, f);
+            filesize += len;
+        }
+        if (strncmp((const char *)flashbuf, "UF2\nWQ]\x9E", 8) == 0) {
+            printf("detected UF2 file\n");
+            if (cmd.pageSize != 256)
+                fatal("wrong page size");
+            isUF2 = 1;
+        } else {
+            filesize = (filesize + (cmd.pageSize - 1)) / cmd.pageSize * cmd.pageSize;
+        }
+        printf("read %ld bytes from %s\n", filesize, filename);
+        fclose(f);
+    }
+
+    uint64_t start = millis();
+    uint32_t addr = 0x2000;
+    uint32_t blockSize = cmd.pageSize;
+
+    if (isUF2)
+        blockSize = 512;
+
+    for (i = 0; i < filesize; i += blockSize) {
+        if (isUF2) {
+            addr = read32(flashbuf + i + 12);
+            memcpy(cmd.buf + 12, flashbuf + i + 32, cmd.pageSize);
+        } else {
+            memcpy(cmd.buf + 12, flashbuf + i, cmd.pageSize);
+        }
+        write32(cmd.buf + 8, addr);
+        talk_hid(&cmd, HF2_CMD_WRITE_FLASH_PAGE, 0, cmd.pageSize + 4);
+        addr += cmd.pageSize;
+    }
+
+    printf("time: %d\n", (int)(millis() - start));
+    start = millis();
+
+#if 0
+    for (i = 0; i < filesize; i += cmd.pageSize) {
+        write32(cmd.buf + 8, i + 0x2000);
+        write32(cmd.buf + 12, cmd.pageSize / 4);
+        talk_hid(&cmd, HF2_CMD_MEM_READ_WORDS, 0, 8);
+        if (memcmp(cmd.buf + 4, flashbuf + i, cmd.pageSize)) {
+            printf("%d,%d,%d != %d?\n", cmd.buf[8], cmd.buf[9], cmd.buf[10], flashbuf[i]);
+            fatal("verification failed");
+        }
+    }
+#else
+    if (!isUF2)
+        verify(&cmd, flashbuf, filesize, 0x2000);
+#endif
+
+    printf("verify time: %d\n", (int)(millis() - start));
+
+    talk_hid(&cmd, HF2_CMD_RESET_INTO_APP, 0, 0);
+
+    printf("device reset.\n");
+
+    // Finalize the hidapi library
+    res = hid_exit();
+
+    return 0;
+}
diff --git a/uf2-samdx1/lib/uf2/utils/uf2conv.c b/uf2-samdx1/lib/uf2/utils/uf2conv.c
new file mode 100644
index 00000000..0f5f16ee
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/utils/uf2conv.c
@@ -0,0 +1,45 @@
+#include <stdio.h>
+#include <string.h>
+#include "uf2format.h"
+
+int main(int argc, char **argv) {
+    if (argc < 2) {
+        fprintf(stderr, "USAGE: %s file.bin [file.uf2]\n", argv[0]);
+        return 1;
+    }
+    FILE *f = fopen(argv[1], "rb");
+    if (!f) {
+        fprintf(stderr, "No such file: %s\n", argv[1]);
+        return 1;
+    }
+
+    fseek(f, 0L, SEEK_END);
+    uint32_t sz = ftell(f);
+    fseek(f, 0L, SEEK_SET);
+
+    const char *outname = argc > 2 ? argv[2] : "flash.uf2";
+
+    FILE *fout = fopen(outname, "wb");
+
+    UF2_Block bl;
+    memset(&bl, 0, sizeof(bl));
+
+    bl.magicStart0 = UF2_MAGIC_START0;
+    bl.magicStart1 = UF2_MAGIC_START1;
+    bl.magicEnd = UF2_MAGIC_END;
+    bl.targetAddr = APP_START_ADDRESS;
+    bl.numBlocks = (sz + 255) / 256;
+    bl.payloadSize = 256;
+    int numbl = 0;
+    while (fread(bl.data, 1, bl.payloadSize, f)) {
+        bl.blockNo = numbl++;
+        fwrite(&bl, 1, sizeof(bl), fout);
+        bl.targetAddr += bl.payloadSize;
+        // clear for next iteration, in case we get a short read
+        memset(bl.data, 0, sizeof(bl.data));
+    }
+    fclose(fout);
+    fclose(f);
+    printf("Wrote %d blocks to %s\n", numbl, outname);
+    return 0;
+}
\ No newline at end of file
diff --git a/uf2-samdx1/lib/uf2/utils/uf2conv.md b/uf2-samdx1/lib/uf2/utils/uf2conv.md
new file mode 100644
index 00000000..6c818c25
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/utils/uf2conv.md
@@ -0,0 +1,68 @@
+# uf2conv -- Packing and unpacking UF2 files
+
+## SYNOPSIS
+
+**uf2conv.py** [-h] [-l]
+
+**uf2conv.py** [-b BASE] [-f FAMILY] [-o FILE] [-d DEVICE_PATH] [-l] [-c] [-D]
+               [-w] [-C]
+               [HEX or BIN FILE]
+
+**uf2conv.py** [-c] [-D] [-w] [-i] [UF2 FILE]
+
+## DESCRIPTION
+
+## EXAMPLES
+
+### Pack a .bin/.hex to .uf2
+
+```uf2conv.py cpx/firmware.bin --convert --output cpx/firmware.uf2```
+
+```uf2conv.py metro_m4/firmware.bin --base 0x4000 --convert --output metro_m4/firmware.uf2```
+
+```uf2conv.py nrf52840_xxaa.hex --family 0xADA52840 --convert --output nrf52840_xxaa.uf2```
+
+### Unpack a .uf2 to .bin
+
+```uf2conv.py current.uf2 --convert --output current.bin```
+
+## OPTIONS
+`-b`
+`--base`
+: set base address of application for BIN format (default: 0x2000)
+
+`-f`
+`--family`
+: specify familyID - number or name (default: 0x0)
+
+`-o`
+`--output`
+: write output to named file (defaults to "flash.uf2" or "flash.bin" where sensible)
+
+`-d`
+`--device`
+: select a device path to flash
+
+`-l`
+`--list`
+: list connected devices
+
+`-c`
+`--convert`
+: do not flash, just convert
+
+`-D`
+`--deploy`
+: just flash, do not convert
+
+`-w`
+`--wait`
+: wait for device to flash
+
+`-C`
+`--carray`
+: convert binary file to a C array, not UF2
+
+`-i`
+`--info`
+: display header information from UF2, do not convert
diff --git a/uf2-samdx1/lib/uf2/utils/uf2conv.py b/uf2-samdx1/lib/uf2/utils/uf2conv.py
new file mode 100644
index 00000000..5a862c3a
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/utils/uf2conv.py
@@ -0,0 +1,363 @@
+#!/usr/bin/env python3
+import sys
+import struct
+import subprocess
+import re
+import os
+import os.path
+import argparse
+import json
+from time import sleep
+
+
+UF2_MAGIC_START0 = 0x0A324655 # "UF2\n"
+UF2_MAGIC_START1 = 0x9E5D5157 # Randomly selected
+UF2_MAGIC_END    = 0x0AB16F30 # Ditto
+
+INFO_FILE = "/INFO_UF2.TXT"
+
+appstartaddr = 0x2000
+familyid = 0x0
+
+
+def is_uf2(buf):
+    w = struct.unpack("<II", buf[0:8])
+    return w[0] == UF2_MAGIC_START0 and w[1] == UF2_MAGIC_START1
+
+def is_hex(buf):
+    try:
+        w = buf[0:30].decode("utf-8")
+    except UnicodeDecodeError:
+        return False
+    if w[0] == ':' and re.match(rb"^[:0-9a-fA-F\r\n]+$", buf):
+        return True
+    return False
+
+def convert_from_uf2(buf):
+    global appstartaddr
+    global familyid
+    numblocks = len(buf) // 512
+    curraddr = None
+    currfamilyid = None
+    families_found = {}
+    prev_flag = None
+    all_flags_same = True
+    outp = []
+    for blockno in range(numblocks):
+        ptr = blockno * 512
+        block = buf[ptr:ptr + 512]
+        hd = struct.unpack(b"<IIIIIIII", block[0:32])
+        if hd[0] != UF2_MAGIC_START0 or hd[1] != UF2_MAGIC_START1:
+            print("Skipping block at " + ptr + "; bad magic")
+            continue
+        if hd[2] & 1:
+            # NO-flash flag set; skip block
+            continue
+        datalen = hd[4]
+        if datalen > 476:
+            assert False, "Invalid UF2 data size at " + ptr
+        newaddr = hd[3]
+        if (hd[2] & 0x2000) and (currfamilyid == None):
+            currfamilyid = hd[7]
+        if curraddr == None or ((hd[2] & 0x2000) and hd[7] != currfamilyid):
+            currfamilyid = hd[7]
+            curraddr = newaddr
+            if familyid == 0x0 or familyid == hd[7]:
+                appstartaddr = newaddr
+        padding = newaddr - curraddr
+        if padding < 0:
+            assert False, "Block out of order at " + ptr
+        if padding > 10*1024*1024:
+            assert False, "More than 10M of padding needed at " + ptr
+        if padding % 4 != 0:
+            assert False, "Non-word padding size at " + ptr
+        while padding > 0:
+            padding -= 4
+            outp.append(b"\x00\x00\x00\x00")
+        if familyid == 0x0 or ((hd[2] & 0x2000) and familyid == hd[7]):
+            outp.append(block[32 : 32 + datalen])
+        curraddr = newaddr + datalen
+        if hd[2] & 0x2000:
+            if hd[7] in families_found.keys():
+                if families_found[hd[7]] > newaddr:
+                    families_found[hd[7]] = newaddr
+            else:
+                families_found[hd[7]] = newaddr
+        if prev_flag == None:
+            prev_flag = hd[2]
+        if prev_flag != hd[2]:
+            all_flags_same = False
+        if blockno == (numblocks - 1):
+            print("--- UF2 File Header Info ---")
+            families = load_families()
+            for family_hex in families_found.keys():
+                family_short_name = ""
+                for name, value in families.items():
+                    if value == family_hex:
+                        family_short_name = name
+                print("Family ID is {:s}, hex value is 0x{:08x}".format(family_short_name,family_hex))
+                print("Target Address is 0x{:08x}".format(families_found[family_hex]))
+            if all_flags_same:
+                print("All block flag values consistent, 0x{:04x}".format(hd[2]))
+            else:
+                print("Flags were not all the same")
+            print("----------------------------")
+            if len(families_found) > 1 and familyid == 0x0:
+                outp = []
+                appstartaddr = 0x0
+    return b"".join(outp)
+
+def convert_to_carray(file_content):
+    outp = "const unsigned long bindata_len = %d;\n" % len(file_content)
+    outp += "const unsigned char bindata[] __attribute__((aligned(16))) = {"
+    for i in range(len(file_content)):
+        if i % 16 == 0:
+            outp += "\n"
+        outp += "0x%02x, " % file_content[i]
+    outp += "\n};\n"
+    return bytes(outp, "utf-8")
+
+def convert_to_uf2(file_content):
+    global familyid
+    datapadding = b""
+    while len(datapadding) < 512 - 256 - 32 - 4:
+        datapadding += b"\x00\x00\x00\x00"
+    numblocks = (len(file_content) + 255) // 256
+    outp = []
+    for blockno in range(numblocks):
+        ptr = 256 * blockno
+        chunk = file_content[ptr:ptr + 256]
+        flags = 0x0
+        if familyid:
+            flags |= 0x2000
+        hd = struct.pack(b"<IIIIIIII",
+            UF2_MAGIC_START0, UF2_MAGIC_START1,
+            flags, ptr + appstartaddr, 256, blockno, numblocks, familyid)
+        while len(chunk) < 256:
+            chunk += b"\x00"
+        block = hd + chunk + datapadding + struct.pack(b"<I", UF2_MAGIC_END)
+        assert len(block) == 512
+        outp.append(block)
+    return b"".join(outp)
+
+class Block:
+    def __init__(self, addr, default_data=0xFF):
+        self.addr = addr
+        self.bytes = bytearray([default_data] * 256)
+
+    def encode(self, blockno, numblocks):
+        global familyid
+        flags = 0x0
+        if familyid:
+            flags |= 0x2000
+        hd = struct.pack("<IIIIIIII",
+            UF2_MAGIC_START0, UF2_MAGIC_START1,
+            flags, self.addr, 256, blockno, numblocks, familyid)
+        hd += self.bytes[0:256]
+        while len(hd) < 512 - 4:
+            hd += b"\x00"
+        hd += struct.pack("<I", UF2_MAGIC_END)
+        return hd
+
+def convert_from_hex_to_uf2(buf):
+    global appstartaddr
+    appstartaddr = None
+    upper = 0
+    currblock = None
+    blocks = []
+    for line in buf.split('\n'):
+        if line[0] != ":":
+            continue
+        i = 1
+        rec = []
+        while i < len(line) - 1:
+            rec.append(int(line[i:i+2], 16))
+            i += 2
+        tp = rec[3]
+        if tp == 4:
+            upper = ((rec[4] << 8) | rec[5]) << 16
+        elif tp == 2:
+            upper = ((rec[4] << 8) | rec[5]) << 4
+        elif tp == 1:
+            break
+        elif tp == 0:
+            addr = upper + ((rec[1] << 8) | rec[2])
+            if appstartaddr == None:
+                appstartaddr = addr
+            i = 4
+            while i < len(rec) - 1:
+                if not currblock or currblock.addr & ~0xff != addr & ~0xff:
+                    currblock = Block(addr & ~0xff)
+                    blocks.append(currblock)
+                currblock.bytes[addr & 0xff] = rec[i]
+                addr += 1
+                i += 1
+    numblocks = len(blocks)
+    resfile = b""
+    for i in range(0, numblocks):
+        resfile += blocks[i].encode(i, numblocks)
+    return resfile
+
+def to_str(b):
+    return b.decode("utf-8")
+
+def get_drives():
+    drives = []
+    if sys.platform == "win32":
+        r = subprocess.check_output([
+            "powershell",
+            "-Command",
+            '(Get-WmiObject Win32_LogicalDisk -Filter "FileSystem=\'FAT\'").DeviceID'
+            ])
+        drives = [drive.strip() for drive in to_str(r).splitlines()]
+    else:
+        searchpaths = ["/mnt", "/media"]
+        if sys.platform == "darwin":
+            searchpaths = ["/Volumes"]
+        elif sys.platform == "linux":
+            searchpaths += ["/media/" + os.environ["USER"], "/run/media/" + os.environ["USER"]]
+            if "SUDO_USER" in os.environ.keys():
+                searchpaths += ["/media/" + os.environ["SUDO_USER"]]
+                searchpaths += ["/run/media/" + os.environ["SUDO_USER"]]
+
+        for rootpath in searchpaths:
+            if os.path.isdir(rootpath):
+                for d in os.listdir(rootpath):
+                    if os.path.isdir(os.path.join(rootpath, d)):
+                        drives.append(os.path.join(rootpath, d))
+
+
+    def has_info(d):
+        try:
+            return os.path.isfile(d + INFO_FILE)
+        except:
+            return False
+
+    return list(filter(has_info, drives))
+
+
+def board_id(path):
+    with open(path + INFO_FILE, mode='r') as file:
+        file_content = file.read()
+    return re.search(r"Board-ID: ([^\r\n]*)", file_content).group(1)
+
+
+def list_drives():
+    for d in get_drives():
+        print(d, board_id(d))
+
+
+def write_file(name, buf):
+    with open(name, "wb") as f:
+        f.write(buf)
+    print("Wrote %d bytes to %s" % (len(buf), name))
+
+
+def load_families():
+    # The expectation is that the `uf2families.json` file is in the same
+    # directory as this script. Make a path that works using `__file__`
+    # which contains the full path to this script.
+    filename = "uf2families.json"
+    pathname = os.path.join(os.path.dirname(os.path.abspath(__file__)), filename)
+    with open(pathname) as f:
+        raw_families = json.load(f)
+
+    families = {}
+    for family in raw_families:
+        families[family["short_name"]] = int(family["id"], 0)
+
+    return families
+
+
+def main():
+    global appstartaddr, familyid
+    def error(msg):
+        print(msg, file=sys.stderr)
+        sys.exit(1)
+    parser = argparse.ArgumentParser(description='Convert to UF2 or flash directly.')
+    parser.add_argument('input', metavar='INPUT', type=str, nargs='?',
+                        help='input file (HEX, BIN or UF2)')
+    parser.add_argument('-b', '--base', dest='base', type=str,
+                        default="0x2000",
+                        help='set base address of application for BIN format (default: 0x2000)')
+    parser.add_argument('-f', '--family', dest='family', type=str,
+                        default="0x0",
+                        help='specify familyID - number or name (default: 0x0)')
+    parser.add_argument('-o', '--output', metavar="FILE", dest='output', type=str,
+                        help='write output to named file; defaults to "flash.uf2" or "flash.bin" where sensible')
+    parser.add_argument('-d', '--device', dest="device_path",
+                        help='select a device path to flash')
+    parser.add_argument('-l', '--list', action='store_true',
+                        help='list connected devices')
+    parser.add_argument('-c', '--convert', action='store_true',
+                        help='do not flash, just convert')
+    parser.add_argument('-D', '--deploy', action='store_true',
+                        help='just flash, do not convert')
+    parser.add_argument('-w', '--wait', action='store_true',
+                        help='wait for device to flash')
+    parser.add_argument('-C', '--carray', action='store_true',
+                        help='convert binary file to a C array, not UF2')
+    parser.add_argument('-i', '--info', action='store_true',
+                        help='display header information from UF2, do not convert')
+    args = parser.parse_args()
+    appstartaddr = int(args.base, 0)
+
+    families = load_families()
+
+    if args.family.upper() in families:
+        familyid = families[args.family.upper()]
+    else:
+        try:
+            familyid = int(args.family, 0)
+        except ValueError:
+            error("Family ID needs to be a number or one of: " + ", ".join(families.keys()))
+
+    if args.list:
+        list_drives()
+    else:
+        if not args.input:
+            error("Need input file")
+        with open(args.input, mode='rb') as f:
+            inpbuf = f.read()
+        from_uf2 = is_uf2(inpbuf)
+        ext = "uf2"
+        if args.deploy:
+            outbuf = inpbuf
+        elif from_uf2 and not args.info:
+            outbuf = convert_from_uf2(inpbuf)
+            ext = "bin"
+        elif from_uf2 and args.info:
+            outbuf = ""
+            convert_from_uf2(inpbuf)
+        elif is_hex(inpbuf):
+            outbuf = convert_from_hex_to_uf2(inpbuf.decode("utf-8"))
+        elif args.carray:
+            outbuf = convert_to_carray(inpbuf)
+            ext = "h"
+        else:
+            outbuf = convert_to_uf2(inpbuf)
+        if not args.deploy and not args.info:
+            print("Converted to %s, output size: %d, start address: 0x%x" %
+                  (ext, len(outbuf), appstartaddr))
+        if args.convert or ext != "uf2":
+            if args.output == None:
+                args.output = "flash." + ext
+        if args.output:
+            write_file(args.output, outbuf)
+        if ext == "uf2" and not args.convert and not args.info:
+            drives = get_drives()
+            if len(drives) == 0:
+                if args.wait:
+                    print("Waiting for drive to deploy...")
+                    while len(drives) == 0:
+                        sleep(0.1)
+                        drives = get_drives()
+                elif not args.output:
+                    error("No drive to deploy.")
+            for d in drives:
+                print("Flashing %s (%s)" % (d, board_id(d)))
+                write_file(d + "/NEW.UF2", outbuf)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/uf2-samdx1/lib/uf2/utils/uf2families.json b/uf2-samdx1/lib/uf2/utils/uf2families.json
new file mode 100644
index 00000000..3e516b5c
--- /dev/null
+++ b/uf2-samdx1/lib/uf2/utils/uf2families.json
@@ -0,0 +1,392 @@
+[
+    {
+        "id": "0x16573617",
+        "short_name": "ATMEGA32",
+        "description": "Microchip (Atmel) ATmega32"
+    },
+    {
+        "id": "0x1851780a",
+        "short_name": "SAML21",
+        "description": "Microchip (Atmel) SAML21"
+    },
+    {
+        "id": "0x1b57745f",
+        "short_name": "NRF52",
+        "description": "Nordic NRF52"
+    },
+    {
+        "id": "0x1c5f21b0",
+        "short_name": "ESP32",
+        "description": "ESP32"
+    },
+    {
+        "id": "0x1e1f432d",
+        "short_name": "STM32L1",
+        "description": "ST STM32L1xx"
+    },
+    {
+        "id": "0x202e3a91",
+        "short_name": "STM32L0",
+        "description": "ST STM32L0xx"
+    },
+    {
+        "id": "0x21460ff0",
+        "short_name": "STM32WL",
+        "description": "ST STM32WLxx"
+    },
+    {
+        "id": "0x22e0d6fc",
+        "short_name": "RTL8710B",
+        "description": "Realtek AmebaZ RTL8710B"
+    },
+    {
+        "id": "0x2abc77ec",
+        "short_name": "LPC55",
+        "description": "NXP LPC55xx"
+    },
+    {
+        "id": "0x300f5633",
+        "short_name": "STM32G0",
+        "description": "ST STM32G0xx"
+    },
+    {
+        "id": "0x31d228c6",
+        "short_name": "GD32F350",
+        "description": "GD32F350"
+    },
+    {
+        "id": "0x3379CFE2",
+        "short_name": "RTL8720D",
+        "description": "Realtek AmebaD RTL8720D"
+    },
+    {
+        "id": "0x04240bdf",
+        "short_name": "STM32L5",
+        "description": "ST STM32L5xx"
+    },
+    {
+        "id": "0x4c71240a",
+        "short_name": "STM32G4",
+        "description": "ST STM32G4xx"
+    },
+    {
+        "id": "0x4fb2d5bd",
+        "short_name": "MIMXRT10XX",
+        "description": "NXP i.MX RT10XX"
+    },
+    {
+        "id": "0x51e903a8",
+        "short_name": "XR809",
+        "description": "Xradiotech 809"
+    },
+    {
+        "id": "0x53b80f00",
+        "short_name": "STM32F7",
+        "description": "ST STM32F7xx"
+    },
+    {
+        "id": "0x55114460",
+        "short_name": "SAMD51",
+        "description": "Microchip (Atmel) SAMD51"
+    },
+    {
+        "id": "0x57755a57",
+        "short_name": "STM32F4",
+        "description": "ST STM32F4xx"
+    },
+    {
+        "id": "0x5a18069b",
+        "short_name": "FX2",
+        "description": "Cypress FX2"
+    },
+    {
+        "id": "0x5d1a0a2e",
+        "short_name": "STM32F2",
+        "description": "ST STM32F2xx"
+    },
+    {
+        "id": "0x5ee21072",
+        "short_name": "STM32F1",
+        "description": "ST STM32F103"
+    },
+    {
+        "id": "0x621e937a",
+        "short_name": "NRF52833",
+        "description": "Nordic NRF52833"
+    },
+    {
+        "id": "0x647824b6",
+        "short_name": "STM32F0",
+        "description": "ST STM32F0xx"
+    },
+    {
+        "id": "0x675a40b0",
+        "short_name": "BK7231U",
+        "description": "Beken 7231U/7231T"
+    },
+    {
+        "id": "0x68ed2b88",
+        "short_name": "SAMD21",
+        "description": "Microchip (Atmel) SAMD21"
+    },
+    {
+        "id": "0x6a82cc42",
+        "short_name": "BK7251",
+        "description": "Beken 7251/7252"
+    },
+    {
+        "id": "0x6b846188",
+        "short_name": "STM32F3",
+        "description": "ST STM32F3xx"
+    },
+    {
+        "id": "0x6d0922fa",
+        "short_name": "STM32F407",
+        "description": "ST STM32F407"
+    },
+    {
+        "id": "0x4e8f1c5d",
+        "short_name": "STM32H5",
+        "description": "ST STM32H5xx"
+    },
+    {
+        "id": "0x6db66082",
+        "short_name": "STM32H7",
+        "description": "ST STM32H7xx"
+    },
+    {
+        "id": "0x70d16653",
+        "short_name": "STM32WB",
+        "description": "ST STM32WBxx"
+    },
+    {
+        "id": "0x7b3ef230",
+        "short_name": "BK7231N",
+        "description": "Beken 7231N"
+    },
+    {
+        "id": "0x7eab61ed",
+        "short_name": "ESP8266",
+        "description": "ESP8266"
+    },
+    {
+        "id": "0x7f83e793",
+        "short_name": "KL32L2",
+        "description": "NXP KL32L2x"
+    },
+    {
+        "id": "0x8fb060fe",
+        "short_name": "STM32F407VG",
+        "description": "ST STM32F407VG"
+    },
+    {
+        "id": "0x9fffd543",
+        "short_name": "RTL8710A",
+        "description": "Realtek Ameba1 RTL8710A"
+    },
+    {
+        "id": "0xada52840",
+        "short_name": "NRF52840",
+        "description": "Nordic NRF52840"
+    },
+    {
+        "id": "0x820d9a5f",
+        "short_name": "NRF52820",
+        "description": "Nordic NRF52820_xxAA"
+    },
+    {
+        "id": "0xbfdd4eee",
+        "short_name": "ESP32S2",
+        "description": "ESP32-S2"
+    },
+    {
+        "id": "0xc47e5767",
+        "short_name": "ESP32S3",
+        "description": "ESP32-S3"
+    },
+    {
+        "id": "0xd42ba06c",
+        "short_name": "ESP32C3",
+        "description": "ESP32-C3"
+    },
+    {
+        "id": "0x2b88d29c",
+        "short_name": "ESP32C2",
+        "description": "ESP32-C2"
+    },
+    {
+        "id": "0x332726f6",
+        "short_name": "ESP32H2",
+        "description": "ESP32-H2"
+    },
+    {
+        "id": "0x540ddf62",
+        "short_name": "ESP32C6",
+        "description": "ESP32-C6"
+    },
+    {
+        "id": "0x3d308e94",
+        "short_name": "ESP32P4",
+        "description": "ESP32-P4"
+    },
+    {
+        "id": "0xf71c0343",
+        "short_name": "ESP32C5",
+        "description": "ESP32-C5"
+    },
+    {
+        "id": "0x77d850c4",
+        "short_name": "ESP32C61",
+        "description": "ESP32-C61"
+    },
+    {
+        "id": "0xb6dd00af",
+        "short_name": "ESP32H21",
+        "description": "ESP32-H21"
+    },
+    {
+        "id": "0x9e0baa8a",
+        "short_name": "ESP32H4",
+        "description": "ESP32-H4"
+    },
+    {
+        "id": "0x3101f7c1",
+        "short_name": "ESP32S31",
+        "description": "ESP32-S31"
+    },
+    {
+        "id": "0xde1270b7",
+        "short_name": "BL602",
+        "description": "Boufallo 602"
+    },
+    {
+        "id": "0xe08f7564",
+        "short_name": "RTL8720C",
+        "description": "Realtek AmebaZ2 RTL8720C"
+    },
+    {
+        "id": "0xe48bff56",
+        "short_name": "RP2040",
+        "description": "Raspberry Pi RP2040"
+    },
+    {
+        "id": "0xe48bff57",
+        "short_name": "RP2XXX_ABSOLUTE",
+        "description": "Raspberry Pi Microcontrollers: Absolute (unpartitioned) download"
+    },
+    {
+        "id": "0xe48bff58",
+        "short_name": "RP2XXX_DATA",
+        "description": "Raspberry Pi Microcontrollers: Data partition download"
+    },
+    {
+        "id": "0xe48bff59",
+        "short_name": "RP2350_ARM_S",
+        "description": "Raspberry Pi RP2350, Secure Arm image"
+    },
+    {
+        "id": "0xe48bff5a",
+        "short_name": "RP2350_RISCV",
+        "description": "Raspberry Pi RP2350, RISC-V image"
+    },
+    {
+        "id": "0xe48bff5b",
+        "short_name": "RP2350_ARM_NS",
+        "description": "Raspberry Pi RP2350, Non-secure Arm image"
+    },
+    {
+        "id": "0x00ff6919",
+        "short_name": "STM32L4",
+        "description": "ST STM32L4xx"
+    },
+    {
+        "id": "0x9af03e33",
+        "short_name": "GD32VF103",
+        "description": "GigaDevice GD32VF103"
+    },
+    {
+        "id": "0x4f6ace52",
+        "short_name": "CSK4",
+        "description": "LISTENAI CSK300x/400x"
+    },
+    {
+        "id": "0x6e7348a8",
+        "short_name": "CSK6",
+        "description": "LISTENAI CSK60xx"
+    },
+    {
+        "id": "0x11de784a",
+        "short_name": "M0SENSE",
+        "description": "M0SENSE BL702"
+    },
+    {
+        "id": "0x4b684d71",
+        "short_name": "MaixPlay-U4",
+        "description": "Sipeed MaixPlay-U4(BL618)"
+    },
+    {
+        "id": "0x9517422f",
+        "short_name": "RZA1LU",
+        "description": "Renesas RZ/A1LU (R7S7210xx)"
+    },
+    {
+        "id": "0x2dc309c5",
+        "short_name": "STM32F411xE",
+        "description": "ST STM32F411xE"
+    },
+    {
+        "id": "0x06d1097b",
+        "short_name": "STM32F411xC",
+        "description": "ST STM32F411xC"
+    },
+    {
+        "id": "0x72721d4e",
+        "short_name": "NRF52832xxAA",
+        "description": "Nordic NRF52832xxAA"
+    },
+    {
+        "id": "0x6f752678",
+        "short_name": "NRF52832xxAB",
+        "description": "Nordic NRF52832xxAB"
+    },
+    {
+        "id": "0xa0c97b8e",
+        "short_name": "AT32F415",
+        "description": "ArteryTek AT32F415"
+    },
+    {
+        "id": "0x699b62ec",
+        "short_name": "CH32V",
+        "description": "WCH CH32V2xx and CH32V3xx"
+    },
+    {
+        "id": "0x7be8976d",
+        "short_name": "RA4M1",
+        "description": "Renesas RA4M1"
+    },
+    {
+        "id": "0x7410520a",
+        "short_name": "MAX32690",
+        "description": "Analog Devices MAX32690"
+    },
+    {
+        "id": "0xd63f8632",
+        "short_name": "MAX32650",
+        "description": "Analog Devices MAX32650/1/2"
+    },
+    {
+        "id": "0xf0c30d71",
+        "short_name": "MAX32666",
+        "description": "Analog Devices MAX32665/6"
+    },
+    {
+        "id": "0x91d3fd18",
+        "short_name": "MAX78002",
+        "description": "Analog Devices MAX78002"
+    },
+    {
+        "id": "0x7d7a66ef",
+        "short_name": "PY32F071-UVK5-V3",
+        "description": "Quansheng UV-K5 V3 amateur radio based on Puya Semiconductor PY32F071"
+    }
+]
diff --git a/uf2-samdx1/lib/usb_msc/sbc_protocol.h b/uf2-samdx1/lib/usb_msc/sbc_protocol.h
new file mode 100644
index 00000000..f2b9be19
--- /dev/null
+++ b/uf2-samdx1/lib/usb_msc/sbc_protocol.h
@@ -0,0 +1,165 @@
+/**
+ * \file
+ *
+ * \brief SCSI Block Commands
+ *
+ * This file contains definitions of some of the commands found in the
+ * SCSI SBC-2 standard.
+ *
+ * Note that the SBC specification depends on several commands defined
+ * by the SCSI Primary Commands (SPC) standard. Each version of the SBC
+ * standard is meant to be used in conjunction with a specific version
+ * of the SPC standard, as follows:
+ *   - SBC   depends on SPC
+ *   - SBC-2 depends on SPC-3
+ *   - SBC-3 depends on SPC-4
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _SBC_PROTOCOL_H_
+#define _SBC_PROTOCOL_H_
+
+#include "lib/usb_msc/usb_includes.h"
+
+/**
+ * \ingroup usb_msc_protocol
+ * \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions
+ *
+ * @{
+ */
+
+/** \name SCSI commands defined by SBC-2 */
+#define SBC_FORMAT_UNIT 0x04
+#define SBC_READ6 0x08
+#define SBC_WRITE6 0x0A
+#define SBC_START_STOP_UNIT 0x1B
+#define SBC_READ_CAPACITY10 0x25
+#define SBC_READ10 0x28
+#define SBC_WRITE10 0x2A
+#define SBC_VERIFY10 0x2F
+
+/** \name SBC-2 Mode page definitions */
+enum scsi_sbc_mode {
+	SCSI_MS_MODE_RW_ERR_RECOV  = 0x01, /**< Read-Write Error Recovery mode page */
+	SCSI_MS_MODE_FORMAT_DEVICE = 0x03, /**< Format Device mode page */
+	SCSI_MS_MODE_FLEXIBLE_DISK = 0x05, /**< Flexible Disk mode page */
+	SCSI_MS_MODE_CACHING       = 0x08
+};
+
+/** \name SBC-2 Device-Specific Parameter */
+#define SCSI_MS_SBC_WP 0x80     /**< Write Protected */
+#define SCSI_MS_SBC_DPOFUA 0x10 /**< DPO and FUA supported */
+
+/**
+ * \brief SBC-2 Short LBA mode parameter block descriptor
+ * \note Fields are MSB first (BE)
+ */
+struct sbc_slba_block_desc {
+	be32_t nr_blocks;                       /**< Number of Blocks (BE32) */
+	be32_t block_len;                       /**< Block Length (BE32) */
+#define SBC_SLBA_BLOCK_LEN_MASK 0x00FFFFFFU /**< Mask reserved bits */
+};
+
+/**
+ * \brief SBC-2 Caching mode page
+ * \note Fields are MSB first (BE)
+ */
+struct sbc_caching_mode_page {
+	uint8_t page_code;
+	uint8_t page_length;
+	uint8_t flags2;
+#define SBC_MP_CACHE_IC (1 << 7)   /**< Initiator Control */
+#define SBC_MP_CACHE_ABPF (1 << 6) /**< Abort Pre-Fetch */
+#define SBC_MP_CACHE_CAP (1 << 5)  /**< Catching Analysis Permitted */
+#define SBC_MP_CACHE_DISC (1 << 4) /**< Discontinuity */
+#define SBC_MP_CACHE_SIZE (1 << 3) /**< Size enable */
+#define SBC_MP_CACHE_WCE (1 << 2)  /**< Write back Cache Enable */
+#define SBC_MP_CACHE_MF (1 << 1)   /**< Multiplication Factor */
+#define SBC_MP_CACHE_RCD (1 << 0)  /**< Read Cache Disable */
+	uint8_t retention;
+	be16_t  dis_pf_transfer_len;
+	be16_t  min_prefetch;
+	be16_t  max_prefetch;
+	be16_t  max_prefetch_ceil;
+	uint8_t flags12;
+#define SBC_MP_CACHE_FSW (1 << 7)    /**< Force Sequential Write */
+#define SBC_MP_CACHE_LBCSS (1 << 6)  /**< Logical Blk Cache Seg Sz */
+#define SBC_MP_CACHE_DRA (1 << 5)    /**< Disable Read-Ahead */
+#define SBC_MP_CACHE_NV_DIS (1 << 0) /**< Non-Volatile Cache Disable */
+	uint8_t nr_cache_segments;
+	be16_t  cache_segment_size;
+	uint8_t reserved[4];
+};
+
+/**
+ * \brief SBC-2 Read-Write Error Recovery mode page
+ * \note Fields are MSB first (BE)
+ */
+struct sbc_rdwr_error_recovery_mode_page {
+	uint8_t page_code;
+	uint8_t page_length;
+#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A
+	uint8_t flags1;
+#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7)
+#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6)
+#define SBC_MP_RW_ERR_RECOV_TB (1 << 5)
+#define SBC_MP_RW_ERR_RECOV_RC (1 << 4)
+#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3)
+#define SBC_MP_RW_ERR_RECOV_PER (1 << 2)
+#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1)
+#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0)
+	uint8_t read_retry_count;
+	uint8_t correction_span;
+	uint8_t head_offset_count;
+	uint8_t data_strobe_offset_count;
+	uint8_t flags2;
+	uint8_t write_retry_count;
+	uint8_t flags3;
+	be16_t  recovery_time_limit;
+};
+
+/**
+ * \brief SBC-2 READ CAPACITY (10) parameter data (8 bytes)
+ * \note Fields are MSB first (BE)
+ */
+struct sbc_read_capacity10_data {
+	be32_t max_lba;   /**< LBA of last logical block (BE32) */
+	be32_t block_len; /**< Number of bytes in the last logical block (BE32) */
+};
+
+#endif /*_SBC_PROTOCOL_H_*/
diff --git a/uf2-samdx1/lib/usb_msc/spc_protocol.h b/uf2-samdx1/lib/usb_msc/spc_protocol.h
new file mode 100644
index 00000000..2a682165
--- /dev/null
+++ b/uf2-samdx1/lib/usb_msc/spc_protocol.h
@@ -0,0 +1,342 @@
+/**
+ * \file
+ *
+ * \brief SCSI Primary Commands
+ *
+ * This file contains definitions of some of the commands found in the
+ * SPC-2 standard.
+ *
+ * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _SPC_PROTOCOL_H_
+#define _SPC_PROTOCOL_H_
+
+#include "lib/usb_msc/usb_includes.h"
+
+/**
+ * \ingroup usb_msc_protocol
+ * \defgroup usb_spc_protocol SCSI Primary Commands protocol definitions
+ *
+ *
+ */
+
+/**< \name SCSI commands defined by SPC-2 */
+#define SPC_TEST_UNIT_READY 0x00
+#define SPC_REQUEST_SENSE 0x03
+#define SPC_INQUIRY 0x12
+#define SPC_MODE_SELECT6 0x15
+#define SPC_MODE_SENSE6 0x1A
+#define SPC_SEND_DIAGNOSTIC 0x1D
+#define SPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E
+#define SPC_MODE_SENSE10 0x5A
+#define SPC_REPORT_LUNS 0xA0
+
+/**< \brief May be set in byte 0 of the INQUIRY CDB */
+/**< Enable Vital Product Data */
+#define SCSI_INQ_REQ_EVPD 0x01
+/**< Command Support Data specified by the PAGE OR OPERATION CODE field */
+#define SCSI_INQ_REQ_CMDT 0x02
+
+_Pragma("pack(1)")
+
+/**
+ * \brief SCSI Standard Inquiry data structure
+ */
+struct scsi_inquiry_data {
+	uint8_t pq_pdt;                      /**< Peripheral Qual / Peripheral Dev Type */
+#define SCSI_INQ_PQ_CONNECTED 0x00       /**< Peripheral connected */
+#define SCSI_INQ_PQ_NOT_CONN 0x20        /**< Peripheral not connected */
+#define SCSI_INQ_PQ_NOT_SUPP 0x60        /**< Peripheral not supported */
+#define SCSI_INQ_DT_DIR_ACCESS 0x00      /**< Direct Access (SBC) */
+#define SCSI_INQ_DT_SEQ_ACCESS 0x01      /**< Sequential Access */
+#define SCSI_INQ_DT_PRINTER 0x02         /**< Printer */
+#define SCSI_INQ_DT_PROCESSOR 0x03       /**< Processor device */
+#define SCSI_INQ_DT_WRITE_ONCE 0x04      /**< Write-once device */
+#define SCSI_INQ_DT_CD_DVD 0x05          /**< CD/DVD device */
+#define SCSI_INQ_DT_OPTICAL 0x07         /**< Optical Memory */
+#define SCSI_INQ_DT_MC 0x08              /**< Medium Changer */
+#define SCSI_INQ_DT_ARRAY 0x0c           /**< Storage Array Controller */
+#define SCSI_INQ_DT_ENCLOSURE 0x0d       /**< Enclosure Services */
+#define SCSI_INQ_DT_RBC 0x0e             /**< Simplified Direct Access */
+#define SCSI_INQ_DT_OCRW 0x0f            /**< Optical card reader/writer */
+#define SCSI_INQ_DT_BCC 0x10             /**< Bridge Controller Commands */
+#define SCSI_INQ_DT_OSD 0x11             /**< Object-based Storage */
+#define SCSI_INQ_DT_NONE 0x1f            /**< No Peripheral */
+	uint8_t flags1;                      /**< Flags (byte 1) */
+#define SCSI_INQ_RMB 0x80                /**< Removable Medium */
+	uint8_t version;                     /**< Version */
+#define SCSI_INQ_VER_NONE 0x00           /**< No standards conformance */
+#define SCSI_INQ_VER_SPC 0x03            /**< SCSI Primary Commands     (link to SBC) */
+#define SCSI_INQ_VER_SPC2 0x04           /**< SCSI Primary Commands - 2 (link to SBC-2) */
+#define SCSI_INQ_VER_SPC3 0x05           /**< SCSI Primary Commands - 3 (link to SBC-2) */
+#define SCSI_INQ_VER_SPC4 0x06           /**< SCSI Primary Commands - 4 (link to SBC-3) */
+	uint8_t flags3;                      /**< Flags (byte 3) */
+#define SCSI_INQ_NORMACA 0x20            /**< Normal ACA Supported */
+#define SCSI_INQ_HISUP 0x10              /**< Hierarchal LUN addressing */
+#define SCSI_INQ_RSP_SPC2 0x02           /**< SPC-2 / SPC-3 response format */
+	uint8_t addl_len;                    /**< Additional Length (n-4) */
+#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) /**< Total length is \a tot */
+	uint8_t flags5;                      /**< Flags (byte 5) */
+#define SCSI_INQ_SCCS 0x80
+	uint8_t flags6; /**< Flags (byte 6) */
+#define SCSI_INQ_BQUE 0x80
+#define SCSI_INQ_ENCSERV 0x40
+#define SCSI_INQ_MULTIP 0x10
+#define SCSI_INQ_MCHGR 0x08
+#define SCSI_INQ_ADDR16 0x01
+	uint8_t flags7; /**< Flags (byte 7) */
+#define SCSI_INQ_WBUS16 0x20
+#define SCSI_INQ_SYNC 0x10
+#define SCSI_INQ_LINKED 0x08
+#define SCSI_INQ_CMDQUE 0x02
+	uint8_t vendor_id[8];   /**< T10 Vendor Identification */
+	uint8_t product_id[16]; /**< Product Identification */
+	uint8_t product_rev[4]; /**< Product Revision Level */
+};
+
+/**
+ * \brief SCSI Standard Request sense data structure
+ */
+#define SCSI_SENSE_VALID 0x80 /**< Indicates the INFORMATION field contains valid information */
+#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F
+#define SCSI_SENSE_CURRENT 0x70 /**< Response code 70h (current errors) */
+#define SCSI_SENSE_DEFERRED 0x71
+
+#define SCSI_SENSE_FILEMARK 0x80 /**< Indicates that the current command has read a filemark or setmark. */
+#define SCSI_SENSE_EOM 0x40      /**< Indicates that an end-of-medium condition exists. */
+#define SCSI_SENSE_ILI                                                                                                 \
+	0x20 /**< Indicates that the requested logical block length did not match the logical block length of the data on  \
+	        the medium. */
+#define SCSI_SENSE_RESERVED 0x10     /**< Reserved */
+#define SCSI_SENSE_KEY(x) (x & 0x0F) /**< Sense Key */
+
+#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len)-8)
+
+#define SCSI_SENSE_SKSV 0x80 /**< Indicates the SENSE-KEY SPECIFIC field contains valid information */
+
+struct scsi_request_sense_data {
+	/** 1st byte: REQUEST SENSE response flags*/
+	uint8_t valid_reponse_code;
+	/** 2nd byte */
+	uint8_t obsolete;
+	/** 3rd byte */
+	uint8_t sense_flag_key;
+	/** 4th to 7th bytes - INFORMATION field */
+	uint8_t information[4];
+	/** 8th byte  - ADDITIONAL SENSE LENGTH field */
+	uint8_t AddSenseLen;
+	/** 9th to 12th byte  - COMMAND-SPECIFIC INFORMATION field */
+	uint8_t CmdSpecINFO[4];
+	/** 13th to 14th byte  - ADDITIONAL SENSE CODE and QUALIFIER field */
+	union {
+		struct {
+			uint8_t code;      /**< ADDITIONAL SENSE CODE (ASC) */
+			uint8_t qualifier; /**< ADDITIONAL SENSE CODE QUALIFIER (ASCQ) */
+		} add_sense;
+		be16_t AddSense; /**< ASC | ASCQ */
+	};
+	/** 15th byte  - FIELD REPLACEABLE UNIT CODE field */
+	uint8_t FldReplUnitCode;
+	/** 16th byte */
+	uint8_t SenseKeySpec[3];
+};
+
+_Pragma("pack()")
+
+/**< Vital Product Data page codes */
+enum scsi_vpd_page_code {
+	SCSI_VPD_SUPPORTED_PAGES       = 0x00,
+	SCSI_VPD_UNIT_SERIAL_NUMBER    = 0x80,
+	SCSI_VPD_DEVICE_IDENTIFICATION = 0x83
+};
+#define SCSI_VPD_HEADER_SIZE 4
+
+/**< Constants associated with the Device Identification VPD page */
+#define SCSI_VPD_ID_HEADER_SIZE 4
+
+#define SCSI_VPD_CODE_SET_BINARY 1
+#define SCSI_VPD_CODE_SET_ASCII 2
+#define SCSI_VPD_CODE_SET_UTF8 3
+
+#define SCSI_VPD_ID_TYPE_T10 1
+
+/**< Sense keys */
+enum scsi_sense_key {
+	SCSI_SK_NO_SENSE        = 0x0,
+	SCSI_SK_RECOVERED_ERROR = 0x1,
+	SCSI_SK_NOT_READY       = 0x2,
+	SCSI_SK_MEDIUM_ERROR    = 0x3,
+	SCSI_SK_HARDWARE_ERROR  = 0x4,
+	SCSI_SK_ILLEGAL_REQUEST = 0x5,
+	SCSI_SK_UNIT_ATTENTION  = 0x6,
+	SCSI_SK_DATA_PROTECT    = 0x7,
+	SCSI_SK_BLANK_CHECK     = 0x8,
+	SCSI_SK_VENDOR_SPECIFIC = 0x9,
+	SCSI_SK_COPY_ABORTED    = 0xa,
+	SCSI_SK_ABORTED_COMMAND = 0xb,
+	SCSI_SK_VOLUME_OVERFLOW = 0xd,
+	SCSI_SK_MISCOMPARE      = 0xe
+};
+
+/**< Additional Sense Code | Additional Sense Code Qualifier pairs (BE16) */
+enum scsi_asc_ascq {
+	SCSI_ASC_NO_ADDITIONAL_SENSE_INFO         = 0x0000,
+	SCSI_ASC_LU_NOT_READY_REBUILD_IN_PROGRESS = 0x0405,
+	SCSI_ASC_WRITE_ERROR                      = 0x0c00,
+	SCSI_ASC_UNRECOVERED_READ_ERROR           = 0x1100,
+	SCSI_ASC_INVALID_COMMAND_OPERATION_CODE   = 0x2000,
+	SCSI_ASC_INVALID_FIELD_IN_CDB             = 0x2400,
+	SCSI_ASC_WRITE_PROTECTED                  = 0x2700,
+	SCSI_ASC_NOT_READY_TO_READY_CHANGE        = 0x2800,
+	SCSI_ASC_MEDIUM_NOT_PRESENT               = 0x3A00,
+	SCSI_ASC_INTERNAL_TARGET_FAILURE          = 0x4400
+};
+
+/**
+ * \brief SPC-2 Mode parameter
+ * This subclauses describes the block descriptors and the pages
+ * used with MODE SELECT and MODE SENSE commands
+ * that are applicable to all SCSI devices.
+ */
+enum scsi_spc_mode {
+	SCSI_MS_MODE_VENDOR_SPEC = 0x00,
+	SCSI_MS_MODE_INFEXP      = 0x1C, /**< Informational exceptions control page */
+	SCSI_MS_MODE_ALL         = 0x3f
+};
+
+/**
+ * \brief SPC-2 Informational exceptions control page
+ * See chapter 8.3.8
+ * \note Fields are MSB first (BE)
+ */
+struct spc_control_page_info_execpt {
+	uint8_t page_code;
+	uint8_t page_length;
+#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A
+	uint8_t flags1;
+#define SPC_MP_INFEXP_PERF (1 << 7)   /**< Initiator Control */
+#define SPC_MP_INFEXP_EBF (1 << 5)    /**< Caching Analysis Permitted */
+#define SPC_MP_INFEXP_EWASC (1 << 4)  /**< Discontinuity */
+#define SPC_MP_INFEXP_DEXCPT (1 << 3) /**< Size enable */
+#define SPC_MP_INFEXP_TEST (1 << 2)   /**< Write-back Cache Enable */
+#define SPC_MP_INFEXP_LOGERR (1 << 0) /**< Log errors bit */
+	uint8_t mrie;
+#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00
+#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01
+#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02
+#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03
+#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04
+#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05
+#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06
+	be32_t interval_timer;
+	be32_t report_count;
+};
+
+enum scsi_spc_mode_sense_pc {
+	SCSI_MS_SENSE_PC_CURRENT    = 0,
+	SCSI_MS_SENSE_PC_CHANGEABLE = 1,
+	SCSI_MS_SENSE_PC_DEFAULT    = 2,
+	SCSI_MS_SENSE_PC_SAVED      = 3
+};
+
+/**
+ * \brief Check whether dbd field is set in sense code
+ * \param[in] cdb pointer to the sense code block
+ * \return Operation status.
+ */
+static inline bool scsi_mode_sense_dbd_is_set(const uint8_t *cdb)
+{
+	return (cdb[1] >> 3) & 1;
+}
+
+/**
+ * \brief Get page code from mode sense code
+ * \param[in] cdb pointer to the sense code block
+ * \return Operation status.
+ */
+static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t *cdb)
+{
+	return cdb[2] & 0x3f;
+}
+
+/**
+ * \brief Get pc from mode sense code
+ * \param[in] cdb pointer to the sense code block
+ * \return Operation status.
+ */
+static inline uint8_t scsi_mode_sense_get_pc(const uint8_t *cdb)
+{
+	return cdb[2] >> 6;
+}
+
+/**
+ * \brief SCSI Mode Parameter Header used by MODE SELECT(6) and MODE SENSE(6)
+ * \note Fields are MSB first (BE)
+ */
+struct scsi_mode_param_header6 {
+	uint8_t mode_data_length;          /**< Number of bytes after this */
+	uint8_t medium_type;               /**< Medium Type */
+	uint8_t device_specific_parameter; /**< Defined by command set */
+	uint8_t block_descriptor_length;   /**< Length of block descriptors */
+};
+
+/**
+ * \brief SCSI Mode Parameter Header used by MODE SELECT(10) and MODE SENSE(10)
+ * \note Fields are MSB first (BE)
+ */
+struct scsi_mode_param_header10 {
+	le16_t  mode_data_length;          /**< Number of bytes after this */
+	uint8_t medium_type;               /**< Medium Type */
+	uint8_t device_specific_parameter; /**< Defined by command set */
+	uint8_t flags4;                    /**< LONGLBA in bit 0 */
+	uint8_t reserved;
+	le16_t  block_descriptor_length; /**< Length of block descriptors */
+};
+
+/**
+ * \brief SCSI Page_0 Mode Page header (SPF not set)
+ */
+struct scsi_mode_page_0_header {
+	uint8_t page_code;
+#define SCSI_PAGE_CODE_PS (1 << 7)  /**< Parameters Savable */
+#define SCSI_PAGE_CODE_SPF (1 << 6) /**< SubPage Format */
+	uint8_t page_length;            /**< Number of bytes after this */
+#define SCSI_MS_PAGE_LEN(total) ((total)-2)
+};
+
+#endif /**< SPC_PROTOCOL_H_ */
diff --git a/uf2-samdx1/lib/usb_msc/usb_includes.h b/uf2-samdx1/lib/usb_msc/usb_includes.h
new file mode 100644
index 00000000..b41cd69c
--- /dev/null
+++ b/uf2-samdx1/lib/usb_msc/usb_includes.h
@@ -0,0 +1,137 @@
+/**
+ * \file
+ *
+ * \brief USB Include Header Files.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved.
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+#ifndef _USB_INCLUDES_H_
+#define _USB_INCLUDES_H_
+
+#ifdef USB_USER_INCLUDES
+
+//#include "usb_user_includes.h"
+
+#else
+/* Include START headers */
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+//#include <utils.h>
+//#include <utils_list.h>
+//#include <utils_assert.h>
+//#include <hal_atomic.h>
+
+typedef uint16_t le16_t;
+typedef uint32_t le32_t;
+typedef uint16_t be16_t;
+typedef uint32_t be32_t;
+
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define is_constant(exp) __builtin_constant_p(exp)
+#else
+#define is_constant(exp) (0)
+#endif
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define swap_u16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) | ((uint16_t)(u16) << 8)))
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#if (defined __GNUC__)
+#define swap_u32(u32)                                                                                                  \
+	(is_constant(u32)                                                                                                  \
+	     ? ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16)))     \
+	     : ((uint32_t)__builtin_bswap32((uint32_t)(u32))))
+#else
+#define swap_u32(u32)                                                                                                  \
+	((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16)))
+#endif
+
+/** Get a value from/to LE16 data */
+#define LE16(x) (x)
+/** Get a value from/to LE32 data */
+#define LE32(x) (x)
+/** Get a value from/to BE16 data */
+#define BE16(x) swap_u16(x)
+/** Get a value from/to BE32 data */
+#define BE32(x) swap_u32(x)
+
+/** Get byte 0 for BE 16-bit value */
+#define BE16B0(a) ((uint8_t)((a) >> 8))
+/** Get byte 1 for BE 16-bit value */
+#define BE16B1(a) ((uint8_t)((a) >> 0))
+
+/** Get byte 0 for BE 32-bit value */
+#define BE32B0(a) ((uint8_t)((a) >> 24))
+/** Get byte 1 for BE 32-bit value */
+#define BE32B1(a) ((uint8_t)((a) >> 16))
+/** Get byte 2 for BE 32-bit value */
+#define BE32B2(a) ((uint8_t)((a) >> 8))
+/** Get byte 3 for BE 32-bit value */
+#define BE32B3(a) ((uint8_t)((a) >> 0))
+
+/** Get byte 0 for LE 16-bit value */
+#define LE16B0(a) ((uint8_t)((a) >> 0))
+/** Get byte 1 for LE 16-bit value */
+#define LE16B1(a) ((uint8_t)((a) >> 8))
+
+/** Get byte 0 for LE 32-bit value */
+#define LE32B0(a) ((uint8_t)((a) >> 0))
+/** Get byte 1 for LE 32-bit value */
+#define LE32B1(a) ((uint8_t)((a) >> 8))
+/** Get byte 2 for LE 32-bit value */
+#define LE32B2(a) ((uint8_t)((a) >> 16))
+/** Get byte 3 for LE 32-bit value */
+#define LE32B3(a) ((uint8_t)((a) >> 24))
+
+#endif /* USB_USER_INCLUDES */
+
+#endif /* _USB_INCLUDES_H_ */
diff --git a/uf2-samdx1/lib/usb_msc/usb_protocol.h b/uf2-samdx1/lib/usb_msc/usb_protocol.h
new file mode 100644
index 00000000..2ffa70a5
--- /dev/null
+++ b/uf2-samdx1/lib/usb_msc/usb_protocol.h
@@ -0,0 +1,765 @@
+/**
+ * \file
+ *
+ * \brief USB protocol definitions.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+#ifndef _USB_PROTOCOL_H_
+#define _USB_PROTOCOL_H_
+
+#include "usb_includes.h"
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_protocol_group USB Protocol Definitions
+ *
+ * This module defines constants and data structures provided by the USB
+ * 2.0 specification.
+ *
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __CC_ARM
+#pragma anon_unions
+#endif
+
+/*! Value for field bcdUSB */
+#define USB_V2_0 (0x0200) /*!< USB Specification version 2.00 */
+#define USB_V2_1 (0x0201) /*!< USB Specification version 2.01 (support BOS) */
+
+/*! \name Generic definitions (Class, subclass and protocol)
+ */
+/*! @{ */
+#define USB_CLASS_NO (0x00)
+#define USB_SUBCLASS_NO (0x00)
+#define USB_PROTOCOL_NO (0x00)
+/*! @} */
+
+/*! \name IAD (Interface Association Descriptor) constants */
+/*! @{ */
+#define USB_CLASS_IAD (0xEF)
+#define USB_SUBCLASS_IAD (0x02)
+#define USB_PROTOCOL_IAD (0x01)
+/*! @} */
+
+/**
+ * \brief USB request data transfer direction (bmRequestType)
+ */
+#define USB_REQT_DIR_OUT (0 << 7)  /*!< Host to device */
+#define USB_REQT_DIR_H2D (0 << 7)  /*!< Host to device */
+#define USB_REQT_DIR_IN (1 << 7)   /*!< Device to host */
+#define USB_REQT_DIR_D2H (1 << 7)  /*!< Device to host */
+#define USB_REQT_DIR_MASK (1 << 7) /*!< Mask */
+
+/**
+ * \brief USB request types (bmRequestType)
+ */
+#define USB_REQT_TYPE_STANDARD (0 << 5) /*!< Standard request */
+#define USB_REQT_TYPE_CLASS (1 << 5)    /*!< Class-specific request */
+#define USB_REQT_TYPE_VENDOR (2 << 5)   /*!< Vendor-specific request */
+#define USB_REQT_TYPE_MASK (3 << 5)     /*!< Mask */
+
+/**
+ * \brief USB recipient codes (bmRequestType)
+ */
+#define USB_REQT_RECIP_DEVICE (0 << 0)    /*!< Recipient device */
+#define USB_REQT_RECIP_INTERFACE (1 << 0) /*!< Recipient interface */
+#define USB_REQT_RECIP_ENDPOINT (2 << 0)  /*!< Recipient endpoint */
+#define USB_REQT_RECIP_OTHER (3 << 0)     /*!< Recipient other */
+#define USB_REQT_RECIP_MASK (0x1F)        /*!< Mask */
+
+/**
+ * \brief Standard USB control transfer stages.
+ */
+enum usb_ctrl_stage { USB_SETUP_STAGE = 0, USB_DATA_STAGE = 1, USB_STATUS_STAGE = 2 };
+
+/**
+ * \brief Standard USB requests (bRequest)
+ */
+enum usb_req_code {
+	USB_REQ_GET_STATUS    = 0,
+	USB_REQ_CLEAR_FTR     = 1,
+	USB_REQ_SET_FTR       = 3,
+	USB_REQ_SET_ADDRESS   = 5,
+	USB_REQ_GET_DESC      = 6,
+	USB_REQ_SET_DESC      = 7,
+	USB_REQ_GET_CONFIG    = 8,
+	USB_REQ_SET_CONFIG    = 9,
+	USB_REQ_GET_INTERFACE = 10,
+	USB_REQ_SET_INTERFACE = 11,
+	USB_REQ_SYNCH_FRAME   = 12,
+	USB_REQ_SET_SEL       = 48,
+	USB_REQ_ISOCH_DELAY   = 49
+};
+
+/**
+ * \brief Standard USB device status flags
+ *
+ */
+enum usb_dev_status {
+	USB_DEV_STAT_BUS_POWERED  = 0,
+	USB_DEV_STAT_SELF_POWERED = 1,
+	USB_DEV_STAT_REMOTEWAKEUP = 2,
+	USB_DEV_STAT_U1_ENABLE    = 4,
+	USB_DEV_STAT_U2_ENABLE    = 8,
+	USB_DEV_STAT_LTM_ENABLE   = 16
+};
+
+/**
+ * \brief Standard USB Interface status flags
+ *
+ */
+enum usb_interface_status {
+	USB_IFACE_STAT_RESERVED       = 0,
+	USB_IFACE_STAT_REMOTEWAKE_CAP = 1,
+	USB_IFACE_STAT_REMOTEWAKE     = 2
+};
+
+/**
+ * \brief Standard USB endpoint status flags
+ *
+ */
+enum usb_endpoint_status { USB_EP_STAT_HALT = 1 };
+
+/**
+ * \brief Standard USB device feature flags
+ *
+ * \note valid for SetFeature request.
+ */
+enum usb_device_feature {
+	USB_DEV_FTR_REMOTE_WAKEUP    = 1, /*!< Remote wakeup enabled */
+	USB_DEV_FTR_TEST_MODE        = 2, /*!< USB test mode */
+	USB_DEV_FTR_OTG_B_HNP_ENABLE = 3,
+	USB_DEV_FTR_OTG_A_HNP_SP     = 4,
+	USB_DEV_FTR_OTG_A_ALT_HNP_SP = 5,
+	USB_DEV_FTR_U1_ENABLE        = 48,
+	USB_DEV_FTR_U2_ENABLE        = 49,
+	USB_DEV_FTR_LTM_ENABLE       = 50
+};
+
+/**
+ * \brief Test Mode possible on HS USB device
+ *
+ * \note valid for USB_DEV_FTR_TEST_MODE request.
+ */
+enum usb_device_hs_test_mode {
+	USB_DEV_TEST_MODE_J            = 1,
+	USB_DEV_TEST_MODE_K            = 2,
+	USB_DEV_TEST_MODE_SE0_NAK      = 3,
+	USB_DEV_TEST_MODE_PACKET       = 4,
+	USB_DEV_TEST_MODE_FORCE_ENABLE = 5
+};
+
+/**
+ * \brief Standard Feature Selectors for Interface
+ */
+enum usb_iface_feature { USB_IFACE_FTR_FUNC_SUSP = 0 };
+
+/**
+ * \brief Standard USB endpoint feature/status flags
+ */
+enum usb_endpoint_feature { USB_EP_FTR_HALT = 0 };
+
+/**
+ * \brief Standard USB Test Mode Selectors
+ */
+enum usb_test_mode_selector {
+	USB_TEST_J            = 0x01,
+	USB_TEST_K            = 0x02,
+	USB_TEST_SE0_NAK      = 0x03,
+	USB_TEST_PACKET       = 0x04,
+	USB_TEST_FORCE_ENABLE = 0x05
+};
+
+/**
+ * \brief Standard USB descriptor types
+ */
+enum usb_descriptor_type {
+	USB_DT_DEVICE             = 1,
+	USB_DT_CONFIG             = 2,
+	USB_DT_STRING             = 3,
+	USB_DT_INTERFACE          = 4,
+	USB_DT_ENDPOINT           = 5,
+	USB_DT_DEVICE_QUALIFIER   = 6,
+	USB_DT_OTHER_SPEED_CONFIG = 7,
+	USB_DT_INTERFACE_POWER    = 8,
+	USB_DT_OTG                = 9,
+	USB_DT_DEBUG              = 10,
+	USB_DT_IAD                = 11,
+	USB_DT_BOS                = 15,
+	USB_DT_DEV_CAP            = 16,
+	USB_DT_SS_EP_COMPANION    = 48
+};
+
+/**
+ * \brief Capability types
+ */
+enum usb_capability_type {
+	USB_CAPT_WIRELESS     = 1,
+	USB_CAPT_2_0_EXT      = 2,
+	USB_CAPT_SUPER_SPEED  = 3,
+	USB_CAPT_CONTAINER_ID = 4
+};
+
+/**
+ * \brief USB 2.0 Extension attributes
+ */
+enum usb_2_0_ext_attr { USB_2_0_EXT_LPM_SP = 1 };
+
+/**
+ * \brief USB SuperSpeed Capability attributes
+ */
+enum usb_ss_cap_attr { USB_SS_LTM_SP };
+
+/**
+ * \brief USB Speed Supports
+ */
+enum usb_speed_sp {
+	USB_SPEED_LOW_SP   = 1,
+	USB_SPEED_LS_SP    = 1,
+	USB_SPEED_FULL_SP  = 2,
+	USB_SPEED_FS_SP    = 2,
+	USB_SPEED_HIGH_SP  = 4,
+	USB_SPEED_HS_SP    = 4,
+	USB_SPEED_SUPER_SP = 8,
+	USB_SPEED_SS_SP    = 8
+};
+
+/**
+ * \brief Standard USB endpoint transfer types
+ */
+enum usb_ep_type {
+	USB_EP_TYPE_CONTROL     = 0x00,
+	USB_EP_TYPE_ISOCHRONOUS = 0x01,
+	USB_EP_TYPE_BULK        = 0x02,
+	USB_EP_TYPE_INTERRUPT   = 0x03,
+	USB_EP_TYPE_MASK        = 0x03u
+};
+
+/**
+ * \brief USB endpoint interrupt types
+ */
+enum usb_ep_int_type { USB_EP_INT_T_PERIODIC = 0x00u, USB_EP_INT_T_NOTIFICATION = 0x01u, USB_EP_INT_T_MASK = 0x03u };
+
+/**
+ * \brief Standard USB endpoint synchronization types
+ */
+enum usb_ep_sync_type {
+	USB_EP_SYNC_T_NO       = 0x00u,
+	USB_EP_SYNC_T_ASYNC    = 0x02u,
+	USB_EP_SYNC_T_ADAPTIVE = 0x02u,
+	USB_EP_SYNC_T_SYNC     = 0x03u,
+	USB_EP_SYNC_T_MASK     = 0x03u
+};
+
+/**
+ * \brief Standard USB endpoint usage types
+ */
+enum usb_ep_usage_type {
+	USB_EP_USAGE_T_DATA          = 0x00u,
+	USB_EP_USAGE_T_FEEDBACK      = 0x01u,
+	USB_EP_USAGE_T_FEEDBACK_DATA = 0x02u,
+	USB_EP_USAGE_T_MASK          = 0x03u
+};
+
+/**
+ * \brief Standard USB language IDs for string descriptors
+ */
+enum usb_langid {
+	USB_LANGID_EN_US = 0x0409 /*!< English (United States) */
+};
+
+/**
+ * \brief Mask selecting the index part of an endpoint address
+ */
+#define USB_EP_ADDR_MASK 0x0f
+/**
+ * \brief Endpoint transfer direction is IN
+ */
+#define USB_EP_DIR_IN 0x80
+/**
+ * \brief Endpoint transfer direction is OUT
+ */
+#define USB_EP_DIR_OUT 0x00
+
+/**
+ * \brief Maximum length in bytes of a USB descriptor
+ *
+ * The maximum length of a USB descriptor is limited by the 8-bit
+ * bLength field.
+ */
+#define USB_DESC_LEN_MAX 255
+
+/*
+ * 2-byte alignment requested for all USB structures.
+ */
+_Pragma("pack(1)")
+
+/**
+ * \brief A USB Device SETUP request
+ *
+ * The data payload of SETUP packets always follows this structure.
+ */
+typedef struct usb_req {
+	uint8_t bmRequestType;
+	uint8_t bRequest;
+	union {
+		le16_t wValue;
+		struct {
+			uint8_t l;
+			uint8_t h;
+		} wValueBytes;
+	};
+	union {
+		le16_t wIndex;
+		struct {
+			uint8_t l;
+			uint8_t h;
+		} wIndexBytes;
+	};
+	union {
+		le16_t wLength;
+		struct {
+			uint8_t l;
+			uint8_t h;
+		} wLengthBytes;
+	};
+} usb_req_t;
+
+/**
+ * \brief Standard USB device descriptor structure
+ */
+typedef struct usb_dev_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t  bcdUSB;
+	uint8_t bDeviceClass;
+	uint8_t bDeviceSubClass;
+	uint8_t bDeviceProtocol;
+	uint8_t bMaxPacketSize0;
+	le16_t  idVendor;
+	le16_t  idProduct;
+	le16_t  bcdDevice;
+	uint8_t iManufacturer;
+	uint8_t iProduct;
+	uint8_t iSerialNumber;
+	uint8_t bNumConfigurations;
+} usb_dev_desc_t;
+
+/**
+ * \brief Binary device Object Store (BOS) descriptor structure
+ */
+typedef struct usb_bos_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t  wTotalLength;
+	uint8_t bNumDeviceCaps;
+} usb_bos_desc_t;
+
+/**
+ * \brief Device Capability Descriptor structure
+ */
+typedef struct usb_cap_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDevCapabilityType;
+	uint8_t Vars[1];
+} usb_cap_desc_t;
+
+/**
+ * \brief USB 2.0 Extension Descriptor structure
+ */
+typedef struct usb_2_0_ext {
+	uint8_t  bLength;
+	uint8_t  bDescriptorType;
+	uint8_t  bDevCapabilityType;
+	uint32_t bmAttributes;
+} usb_2_0_ext_t;
+
+/**
+ * \brief LPM Device Capabilities descriptor structure
+ */
+typedef struct usb_2_0_ext usb_lpm_cap_desc_t;
+
+/**
+ * \brief SuperSpeed USB Device Capability structure
+ */
+typedef struct usb_ss_cap_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDevCapabilityType;
+	uint8_t bmAttributes;
+	le16_t  wSpeedsSupported;
+	uint8_t bFunctionalitySupport;
+	uint8_t bU1DevExitLat;
+	uint8_t bU2DevExitLat;
+} usb_ss_cap_desc_t;
+
+/**
+ * \brief USB Container ID Descriptor structure
+ */
+typedef struct usb_container_id_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDevCapabilityType;
+	uint8_t bReserved;
+	uint8_t ContainerID[16];
+} usb_container_id_desc_t;
+
+/**
+ * \brief Standard USB device qualifier descriptor structure
+ *
+ * This descriptor contains information about the device when running at
+ * the "other" speed (i.e. if the device is currently operating at high
+ * speed, this descriptor can be used to determine what would change if
+ * the device was operating at full speed.)
+ */
+typedef struct usb_dev_qual_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t  bcdUSB;
+	uint8_t bDeviceClass;
+	uint8_t bDeviceSubClass;
+	uint8_t bDeviceProtocol;
+	uint8_t bMaxPacketSize0;
+	uint8_t bNumConfigurations;
+	uint8_t bReserved;
+} usb_dev_qual_desc_t;
+
+/**
+ * \brief Standard USB configuration descriptor structure
+ */
+typedef struct usb_config_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t  wTotalLength;
+	uint8_t bNumInterfaces;
+	uint8_t bConfigurationValue;
+	uint8_t iConfiguration;
+	uint8_t bmAttributes;
+	uint8_t bMaxPower;
+} usb_config_desc_t;
+
+#define USB_CONFIG_ATTR_MUST_SET (1 << 7)      /*!< Must always be set */
+#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6)   /*!< Bus-powered */
+#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6)  /*!< Self-powered */
+#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) /*!< remote wakeup supported */
+
+#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) /*!< Max power in mA */
+
+/**
+ * \brief Standard USB association descriptor structure
+ */
+typedef struct usb_iad_desc {
+	uint8_t bLength;           /*!< Size of this descriptor in bytes */
+	uint8_t bDescriptorType;   /*!< Interface descriptor type */
+	uint8_t bFirstInterface;   /*!< Number of interface */
+	uint8_t bInterfaceCount;   /*!< value to select alternate setting */
+	uint8_t bFunctionClass;    /*!< Class code assigned by the USB */
+	uint8_t bFunctionSubClass; /*!< Sub-class code assigned by the USB */
+	uint8_t bFunctionProtocol; /*!< Protocol code assigned by the USB */
+	uint8_t iFunction;         /*!< Index of string descriptor */
+} usb_iad_desc_t;
+
+/**
+ * \brief Standard USB interface descriptor structure
+ */
+typedef struct usb_iface_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bInterfaceNumber;
+	uint8_t bAlternateSetting;
+	uint8_t bNumEndpoints;
+	uint8_t bInterfaceClass;
+	uint8_t bInterfaceSubClass;
+	uint8_t bInterfaceProtocol;
+	uint8_t iInterface;
+} usb_iface_desc_t;
+
+/**
+ * \brief Standard USB endpoint descriptor structure
+ */
+typedef struct usb_ep_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bEndpointAddress;
+	uint8_t bmAttributes;
+	le16_t  wMaxPacketSize;
+	uint8_t bInterval;
+} usb_ep_desc_t;
+
+/**
+ * \brief SuperSpeed Endpoint Companion descriptor structure
+ */
+typedef struct usb_ss_ep_comp_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bMaxBurst;
+	uint8_t bmAttributes;
+	le16_t  wBytesPerInterval;
+} usb_ss_ep_comp_desc_t;
+
+/**
+ * \brief LPM Token bmAttributes structure
+ */
+typedef struct usb_lpm_attributes {
+	uint8_t bLinkState : 4;
+	uint8_t HIRD : 4;
+	uint8_t bRemoteWake : 1;
+	uint8_t Reserved : 2;
+} usb_lpm_attributes_t;
+
+/**
+ * \brief A standard USB string descriptor structure
+ */
+typedef struct usb_str_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+} usb_str_desc_t;
+
+typedef struct usb_str_langid_desc {
+	usb_str_desc_t desc;
+	le16_t         string[1];
+} usb_str_langid_desc_t;
+
+_Pragma("pack()")
+
+/** \name Macros to build USB standard descriptors */
+/*@{*/
+
+/** Build bytes for USB device descriptor. */
+#define USB_DEV_DESC_BYTES(bcdUSB,                                                                                     \
+                           bDeviceClass,                                                                               \
+                           bDeviceSubClass,                                                                            \
+                           bDeviceProtocol,                                                                            \
+                           bMaxPacketSize0,                                                                            \
+                           idVendor,                                                                                   \
+                           idProduct,                                                                                  \
+                           bcdDevice,                                                                                  \
+                           iManufacturer,                                                                              \
+                           iProduct,                                                                                   \
+                           iSerialNumber,                                                                              \
+                           bNumConfigurations)                                                                         \
+	18,       /* bLength */                                                                                            \
+	    0x01, /* bDescriptorType: DEVICE */                                                                            \
+	    LE_BYTE0(bcdUSB), LE_BYTE1(bcdUSB), bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0,           \
+	    LE_BYTE0(idVendor), LE_BYTE1(idVendor), LE_BYTE0(idProduct), LE_BYTE1(idProduct), LE_BYTE0(bcdDevice),         \
+	    LE_BYTE1(bcdDevice), iManufacturer, iProduct, iSerialNumber, bNumConfigurations
+
+#define USB_DEV_DESC_LEN 18
+
+/** Build bytes for USB configuration descriptor. */
+#define USB_CONFIG_DESC_BYTES(                                                                                         \
+    wTotalLength, bNumInterfaces, bConfigurationValue, iConfiguration, bmAttributes, bMaxPower)                        \
+	9,        /* bLength */                                                                                            \
+	    0x02, /* bDescriptorType: CONFIGURATION */                                                                     \
+	    LE_BYTE0(wTotalLength), LE_BYTE1(wTotalLength), bNumInterfaces, bConfigurationValue, iConfiguration,           \
+	    bmAttributes, bMaxPower
+
+#define USB_CONFIG_DESC_LEN 9
+
+/** Build bytes for USB IAD descriptor. */
+#define USB_IAD_DESC_BYTES(                                                                                            \
+    bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction)                 \
+	8,              /* bLength */                                                                                      \
+	    USB_DT_IAD, /* bDescriptorType */                                                                              \
+	    bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction
+
+#define USB_IAD_DESC_LEN 8
+
+/** Build bytes for USB interface descriptor. */
+#define USB_IFACE_DESC_BYTES(bInterfaceNumber,                                                                         \
+                             bAlternateSetting,                                                                        \
+                             bNumEndpoints,                                                                            \
+                             bInterfaceClass,                                                                          \
+                             bInterfaceSubClass,                                                                       \
+                             bInterfaceProtocol,                                                                       \
+                             iInterface)                                                                               \
+	9,        /* bLength */                                                                                            \
+	    0x04, /* bDescriptorType: INTERFACE */                                                                         \
+	    bInterfaceNumber, bAlternateSetting, bNumEndpoints, bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol,   \
+	    iInterface
+
+#define USB_IFACE_DESC_LEN 9
+
+/** Build bytes for USB endpoint descriptor. */
+#define USB_ENDP_DESC_BYTES(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval)                                 \
+	7,        /* bLength */                                                                                            \
+	    0x05, /* bDescriptorType: ENDPOINT */                                                                          \
+	    bEndpointAddress, bmAttributes, LE_BYTE0(wMaxPacketSize), LE_BYTE1(wMaxPacketSize), bInterval
+
+#define USB_ENDP_DESC_LEN 7
+
+/*@}*/
+
+/** \brief Get a word (calculate by little endian 16-bit data)
+ *  \param[in] ptr Byte pointer to the address to get data
+ *  \return a 16-bit word
+ */
+static inline uint16_t usb_get_u16(const uint8_t *ptr)
+{
+	return (ptr[0] + (ptr[1] << 8));
+}
+
+/** \brief Get a double word (calculate by little endian 32-bit data)
+ *  \param[in] ptr Byte pointer to the address to get data
+ *  \return a 32-bit word
+ */
+static inline uint32_t usb_get_u32(const uint8_t *ptr)
+{
+	return (ptr[0] + (ptr[1] << 8) + (ptr[2] << 16) + (ptr[3] << 24));
+}
+
+/** \brief Get descriptor length
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \return descriptor length
+ */
+static inline uint8_t usb_desc_len(const uint8_t *desc)
+{
+	return desc[0];
+}
+
+/** \brief Get descriptor type
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \return descriptor type
+ */
+static inline uint8_t usb_desc_type(const uint8_t *desc)
+{
+	return desc[1];
+}
+
+/** \brief Get next USB descriptor
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \return Byte pointer to the next descriptor
+ */
+static inline uint8_t *usb_desc_next(uint8_t *desc)
+{
+	return (desc + usb_desc_len(desc));
+}
+
+/** \brief Get idVendor of USB Device Descriptor
+ *  \param[in] dev_desc Byte pointer to the descriptor start address
+ *  \return 16-bit idVendor value
+ */
+static inline uint16_t usb_dev_desc_vid(const uint8_t *dev_desc)
+{
+	return usb_get_u16(dev_desc + 8);
+}
+
+/** \brief Get idProduct of USB Device Descriptor
+ *  \param[in] dev_desc Byte pointer to the descriptor start address
+ *  \return 16-bit idProduct value
+ */
+static inline uint16_t usb_dev_desc_pid(const uint8_t *dev_desc)
+{
+	return usb_get_u16(dev_desc + 10);
+}
+
+/** \brief Get wTotalLength of USB Configuration Descriptor
+ *  \param[in] cfg_desc Byte pointer to the descriptor start address
+ *  \return 16-bit total length of configuration list
+ */
+static inline uint16_t usb_cfg_desc_total_len(const uint8_t *cfg_desc)
+{
+	return usb_get_u16(cfg_desc + 2);
+}
+
+/** \brief Get Next USB Descriptor After the Configuration Descriptors list
+ *  \param[in] cfg_desc Byte pointer to the descriptor start address
+ *  \return Byte pointer to descriptor after configuration end
+ */
+static inline uint8_t *usb_cfg_desc_next(uint8_t *cfg_desc)
+{
+	return (cfg_desc + usb_cfg_desc_total_len(cfg_desc));
+}
+
+/** \brief Find specific USB Descriptor by its type
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \param[in] type The descriptor type expected
+ *  \return Pointer to the descriptor
+ *  \retval NULL if not found
+ */
+uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type);
+
+/** Get interface descriptor next to the specified one (by interface number)
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \param[in] iface_n The interface number to check
+ *  \return Pointer to the descriptor
+ *  \retval >= eof if not found
+ */
+uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n);
+
+/** Find endpoint descriptor, breaks if interface descriptor detected
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \return Pointer to the descriptor
+ *  \retval NULL if not found
+ */
+uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof);
+
+/** Find configuration descriptor by its configuration number
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \param[in] cfg_value The configure value expected
+ *  \return Pointer to the descriptor
+ *  \retval NULL if not found
+ */
+uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value);
+
+/** Find string descriptor by its index
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \param[in] str_index The string index expected
+ *  \return Pointer to the descriptor
+ *  \retval NULL if not found
+ */
+uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @} */
+
+#endif /* _USB_PROTOCOL_H_ */
diff --git a/uf2-samdx1/lib/usb_msc/usb_protocol_msc.h b/uf2-samdx1/lib/usb_msc/usb_protocol_msc.h
new file mode 100644
index 00000000..ce304bf4
--- /dev/null
+++ b/uf2-samdx1/lib/usb_msc/usb_protocol_msc.h
@@ -0,0 +1,177 @@
+/**
+ * \file
+ *
+ * \brief USB Mass Storage Class (MSC) protocol definitions.
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _USB_PROTOCOL_MSC_H_
+#define _USB_PROTOCOL_MSC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_protocol_group
+ * \defgroup usb_msc_protocol USB Mass Storage Class (MSC) protocol definitions
+ *
+ * @{
+ */
+
+/**
+ * \name Possible Class value
+ */
+//@{
+#define MSC_CLASS 0x08
+//@}
+
+/**
+ * \name Possible SubClass value
+ * \note In practice, most devices should use
+ * #MSC_SUBCLASS_TRANSPARENT and specify the actual command set in
+ * the standard INQUIRY data block, even if the MSC spec indicates
+ * otherwise. In particular, RBC is not supported by certain major
+ * operating systems like Windows XP.
+ */
+//@{
+#define MSC_SUBCLASS_RBC 0x01         /**< Reduced Block Commands */
+#define MSC_SUBCLASS_ATAPI 0x02       /**< CD/DVD devices */
+#define MSC_SUBCLASS_QIC_157 0x03     /**< Tape devices */
+#define MSC_SUBCLASS_UFI 0x04         /**< Floppy disk drives */
+#define MSC_SUBCLASS_SFF_8070I 0x05   /**< Floppy disk drives */
+#define MSC_SUBCLASS_TRANSPARENT 0x06 /**< Determined by INQUIRY */
+                                      //@}
+
+/**
+ * \name Possible protocol value
+ * \note Only the BULK protocol should be used in new designs.
+ */
+//@{
+#define MSC_PROTOCOL_CBI 0x00     /**< Command/Bulk/Interrupt */
+#define MSC_PROTOCOL_CBI_ALT 0x01 /**< W/o command completion */
+#define MSC_PROTOCOL_BULK 0x50    /**< Bulk-only */
+                                  //@}
+
+/**
+ * \brief MSC USB requests (bRequest)
+ */
+
+#define USB_REQ_MSC_BULK_RESET 0xFF  /**< Mass Storage Reset */
+#define USB_REQ_MSC_GET_MAX_LUN 0xFE /**< Get Max LUN */
+
+_Pragma("pack(1)")
+
+/**
+ * \name A Command Block Wrapper (CBW)
+ * \note Fields are LSB first (LE)
+ */
+//@{
+struct usb_msc_cbw {
+	le32_t  dCBWSignature;          /**< Must contain 'USBC' (0x43425355, LE32) */
+	le32_t  dCBWTag;                /**< Unique command ID (LE32) */
+	le32_t  dCBWDataTransferLength; /**< Number of bytes to transfer (LE32) */
+	uint8_t bmCBWFlags;             /**< Direction in bit 7 */
+	uint8_t bCBWLUN;                /**< Logical Unit Number */
+	uint8_t bCBWCBLength;           /**< Number of valid CDB bytes */
+	uint8_t CDB[16];                /**< SCSI Command Descriptor Block */
+};
+
+#define USB_CBW_SIGNATURE 0x43425355   /**< dCBWSignature value */
+#define USB_CBW_DIRECTION_IN (1 << 7)  /**< Data from device to host */
+#define USB_CBW_DIRECTION_OUT (0 << 7) /**< Data from host to device */
+#define USB_CBW_LUN_MASK 0x0F          /**< Valid bits in bCBWLUN */
+#define USB_CBW_LEN_MASK 0x1F          /**< Valid bits in bCBWCBLength */
+                                       //@}
+
+/**
+ * \name A Command Status Wrapper (CSW)
+ * \note Fields are LSB first (LE)
+ */
+//@{
+struct usb_msc_csw {
+	le32_t  dCSWSignature;   /**< Must contain 'USBS' */
+	le32_t  dCSWTag;         /**< Same as dCBWTag */
+	le32_t  dCSWDataResidue; /**< Number of bytes not transfered */
+	uint8_t bCSWStatus;      /**< Status code */
+};
+
+#define USB_CSW_SIGNATURE 0x53425355 /**< dCSWSignature value */
+#define USB_CSW_STATUS_PASS 0x00     /**< Command Passed */
+#define USB_CSW_STATUS_FAIL 0x01     /**< Command Failed */
+#define USB_CSW_STATUS_PE 0x02       /**< Phase Error */
+//@}
+
+_Pragma("pack()")
+
+//@}
+
+/**
+ * \brief Fill a Bulk-Only Mass Storage Reset request
+ * \param[out] req   Pointer to the request to fill
+ * \param[in]  iface Interface Number
+ */
+static inline void usb_fill_BOMSReset_req(struct usb_req *req, uint8_t iface)
+{
+	req->bmRequestType = 0x21;
+	req->bRequest      = USB_REQ_MSC_BULK_RESET;
+	req->wValue        = 0;
+	req->wIndex        = iface;
+	req->wLength       = 0;
+}
+
+/**
+ * \brief Fill a GetMaxLUN request
+ * \param[out] req   Pointer to the request to fill
+ * \param[in]  iface Interface Number
+ */
+static inline void usb_fill_GetMaxLUN_req(struct usb_req *req, uint8_t iface)
+{
+	req->bmRequestType = 0xA1;
+	req->bRequest      = USB_REQ_MSC_GET_MAX_LUN;
+	req->wValue        = 0;
+	req->wIndex        = iface;
+	req->wLength       = 1;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _USB_PROTOCOL_MSC_H_
diff --git a/uf2-samdx1/scripts/bin2uf2.js b/uf2-samdx1/scripts/bin2uf2.js
new file mode 100644
index 00000000..69acc840
--- /dev/null
+++ b/uf2-samdx1/scripts/bin2uf2.js
@@ -0,0 +1,37 @@
+#!/usr/bin/env node
+"use strict";
+
+let fs = require("fs")
+let buf = fs.readFileSync(process.argv[2])
+
+const APP_START_ADDRESS = 0x00002000
+
+const UF2_MAGIC_START0 = 0x0A324655 // "UF2\n"
+const UF2_MAGIC_START1 = 0x9E5D5157 // Randomly selected
+const UF2_MAGIC_END = 0x0AB16F30   // Ditto
+
+let numBlocks = (buf.length + 255) >> 8
+let outp = []
+for (let pos = 0; pos < buf.length; pos += 256) {
+    let bl = new Buffer(512)
+    for (let i = 0; i < 512; ++i)
+        bl[i] = 0 // just in case
+    bl.writeUInt32LE(UF2_MAGIC_START0, 0)
+    bl.writeUInt32LE(UF2_MAGIC_START1, 4)
+    bl.writeUInt32LE(0, 8) // flags
+    bl.writeUInt32LE(APP_START_ADDRESS + pos, 12)
+    bl.writeUInt32LE(256, 16)
+    bl.writeUInt32LE(outp.length, 20)
+    bl.writeUInt32LE(numBlocks, 24)
+    bl.writeUInt32LE(0, 28) // reserved
+    for (let i = 0; i < 256; ++i)
+        bl[i + 32] = buf[pos + i]
+    bl.writeUInt32LE(UF2_MAGIC_END, 512 - 4)
+    outp.push(bl)
+}
+
+if (numBlocks != outp.length) throw "oops";
+
+let outn = process.argv[3] || "flash.uf2"
+fs.writeFileSync(outn, Buffer.concat(outp))
+console.log(`Wrote ${numBlocks} blocks to ${outn}`)
\ No newline at end of file
diff --git a/uf2-samdx1/scripts/bossac.sh b/uf2-samdx1/scripts/bossac.sh
new file mode 100644
index 00000000..b22e0e3d
--- /dev/null
+++ b/uf2-samdx1/scripts/bossac.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+$HOME/Library/Arduino15/packages/arduino/tools/bossac/1.7.0/bossac \
+	-i -d --port=cu.usbmodem1411 -U true -i -e -w -v tmp/mpok.bin -R
diff --git a/uf2-samdx1/scripts/clean-ifaces/README.md b/uf2-samdx1/scripts/clean-ifaces/README.md
new file mode 100644
index 00000000..5cf7a892
--- /dev/null
+++ b/uf2-samdx1/scripts/clean-ifaces/README.md
@@ -0,0 +1,12 @@
+# Remove all usbmodem network interfaces on macOS
+
+Run:
+```
+node clean
+sudo cp preferences.plist /Library/Preferences/SystemConfiguration/preferences.plist
+```
+
+In case of problems, recover by running:
+```
+sudo cp old-preferences.plist /Library/Preferences/SystemConfiguration/preferences.plist
+```
diff --git a/uf2-samdx1/scripts/clean-ifaces/clean.js b/uf2-samdx1/scripts/clean-ifaces/clean.js
new file mode 100644
index 00000000..bd04b71e
--- /dev/null
+++ b/uf2-samdx1/scripts/clean-ifaces/clean.js
@@ -0,0 +1,39 @@
+let fs = require("fs")
+let plist = require("plist")
+let bkp = fs.readFileSync("/Library/Preferences/SystemConfiguration/preferences.plist", "utf8")
+let obj = plist.parse(bkp)
+
+let rem = {}
+for (let k of Object.keys(obj.NetworkServices)) {
+  let o = obj.NetworkServices[k]
+  if (/usbmodem/.test(o.Interface.DeviceName)) {
+    console.log("REMOVE", k, o.UserDefinedName)
+    rem[k] = 1
+  }
+}
+
+rec(obj)
+
+
+let fn = "preferences.plist"
+fs.writeFileSync(fn, plist.build(obj))
+console.log("wrote", fn)
+fs.writeFileSync("old-" + fn, bkp)
+
+function rec(o) {
+  if (Array.isArray(o)) {
+    for (let i = 0; i < o.length; ++i) {
+      while (rem.hasOwnProperty(o[i]))
+        o.splice(i, 1)
+    }
+    o.forEach(rec)
+  } else if (typeof o == "object") {
+    for (let k of Object.keys(o)) {
+      if (rem.hasOwnProperty(k)) {
+        delete o[k]
+      } else {
+        rec(o[k])
+      }
+    }
+  }
+}
diff --git a/uf2-samdx1/scripts/clean-ifaces/package.json b/uf2-samdx1/scripts/clean-ifaces/package.json
new file mode 100644
index 00000000..024a0e72
--- /dev/null
+++ b/uf2-samdx1/scripts/clean-ifaces/package.json
@@ -0,0 +1,11 @@
+{
+  "name": "clean-ifaces",
+  "version": "1.0.0",
+  "description": "Remove usbmodem interfaces",
+  "main": "clean.js",
+  "dependencies": {
+    "plist": "^2.1.0"
+  },
+  "author": "",
+  "license": "MIT"
+}
diff --git a/uf2-samdx1/scripts/dbgtool.js b/uf2-samdx1/scripts/dbgtool.js
new file mode 100644
index 00000000..f0c25130
--- /dev/null
+++ b/uf2-samdx1/scripts/dbgtool.js
@@ -0,0 +1,131 @@
+#!/usr/bin/env node
+"use strict";
+
+let logSym = "logStoreUF2"
+
+let fs = require("fs")
+let child_process = require("child_process")
+
+function fatal(msg) {
+    console.log("Fatal error:", msg)
+    process.exit(1)
+}
+
+function main() {
+    let fileName = process.argv[2]
+    if (!fileName) {
+    }
+
+    let mode = ""
+
+    if (/\.map$/.test(fileName)) mode = "map"
+    else if (/\.bin$/.test(fileName)) mode = "bin"
+    else if (/^server?$/.test(fileName)) mode = "server"
+    else if (/^fuses?$/.test(fileName)) mode = "fuses"
+    else {
+        console.log("usage: node " + process.argv[1] + " file.bin    # to burn")
+        console.log("usage: node " + process.argv[1] + " file.map    # to dump logs")
+        console.log("usage: node " + process.argv[1] + " server      # to run gdb server")
+        return
+    }
+
+
+    console.log("File: " + fileName)
+
+    let addr = 0
+    let logSize = 1024 * 4 + 4
+
+    if (mode == "map") {
+        let mapFile = fs.readFileSync(fileName, "utf8")
+        for (let ln of mapFile.split(/\r?\n/)) {
+            let m = /^\s*0x00000([0-9a-f]+)\s+(\S+)/.exec(ln)
+            if (m && m[2] == logSym) {
+                addr = parseInt(m[1], 16)
+                break
+            }
+        }
+        if (!addr) fatal(`Cannot find ${logSym} symbol in map file`)
+    }
+
+    let dirs = [
+        process.env["HOME"] + "/Library/Arduino15",
+        process.env["USERPROFILE"] + "/AppData/Local/Arduino15",
+        process.env["HOME"] + "/.arduino15",
+    ]
+
+    let pkgDir = ""
+
+    for (let d of dirs) {
+        pkgDir = d + "/packages/arduino/"
+        if (fs.existsSync(pkgDir)) break
+        pkgDir = ""
+    }
+
+    if (!pkgDir) fatal("cannot find Arduino packages directory")
+
+    let openocdPath = pkgDir + "tools/openocd/0.10.0-arduino1-static/"
+    if (!fs.existsSync(openocdPath)) fatal("openocd not installed in Arduino")
+
+    let openocdBin = openocdPath + "bin/openocd"
+
+    if (process.platform == "win32")
+        openocdBin += ".exe"
+
+    let cmd = `telnet_port disabled; init; halt; `
+    if (mode == "map")
+        cmd += `set M(0) 0; mem2array M 8 ${addr} ${logSize}; resume; parray M; shutdown`
+    else
+        cmd += `program ${fileName} verify reset; shutdown`
+
+    let args = ["-d2",
+        "-s", openocdPath + "/share/openocd/scripts/",
+        "-f", "interface/cmsis-dap.cfg",
+        "-f", "target/at91samdXX.cfg",
+        "-c", cmd]
+
+    if (mode == "server") {
+        args.pop()
+        args.pop()
+    }
+
+    if (mode == "fuses") {
+        args.pop()
+        args.pop()
+        args.push("-f")
+        args.push("scripts/fuses.tcl")
+    }
+
+    console.log("Starting " + openocdBin + " " + args.join(" "))
+    if (mode == "map")
+        child_process.execFile(openocdBin, args, {
+            maxBuffer: 1 * 1024 * 1024,
+        }, (err, stdout, stderr) => {
+            if (err) {
+                fatal("error: " + err.message)
+            }
+            let buf = new Buffer(logSize)
+            for (let l of stdout.split(/\r?\n/)) {
+                let m = /^M\((\d+)\)\s*=\s*(\d+)/.exec(l)
+                if (m) {
+                    buf[parseInt(m[1])] = parseInt(m[2])
+                }
+            }
+            let len = buf.readUInt32LE(0)
+            if (len == 0 || len > buf.length) {
+                console.log(stderr)
+                console.log("No logs.")
+            } else {
+                console.log("*\n* Logs\n*\n")
+                console.log(buf.slice(4, 4 + len).toString("binary"))
+            }
+        })
+    else {
+        let proc = child_process.spawn(openocdBin, args, {
+            stdio: "inherit"
+        })
+        proc.on("error", err => { throw err })
+        proc.on("close", () => { })
+    }
+}
+
+main()
diff --git a/uf2-samdx1/scripts/fuses.tcl b/uf2-samdx1/scripts/fuses.tcl
new file mode 100644
index 00000000..ea2e14b2
--- /dev/null
+++ b/uf2-samdx1/scripts/fuses.tcl
@@ -0,0 +1,61 @@
+# change forceupdate to 1 to update the fuses to values specified below
+set forceupdate 0
+set v0 0xD8E0C7FF
+set v1 0xFFFFFC5D
+
+init
+
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+source [find bitsbytes.tcl]
+source [find memory.tcl]
+
+set fuse0 0x00804000
+set fuse1 0x00804004
+set nvmctrl 0x41004000
+
+set cmd_ear 0x5
+set cmd_pbc 0x44
+set cmd_wap 0x6
+
+proc cmd {C} {
+  global nvmctrl
+  global fuse0
+  memwrite32 [expr $nvmctrl + 0x1C] [expr $fuse0 / 2]
+  memwrite16 $nvmctrl [expr 0xA500 | $C]
+}
+
+set f0 [memread32 $fuse0]
+set f1 [memread32 $fuse1]
+
+puts "Fuses:"
+puts [format %x $f0]
+puts [format %x $f1]
+
+set updatefuses 0
+
+if { $forceupdate } then {
+  set updatefuses 1
+} else {
+  if { ($f0 & 0x7) != 0x7 } then {
+    set updatefuses 1
+    set v0 [expr $f0 | 0x7]
+    set v1 $f1
+  }
+}
+
+if { $updatefuses } then {
+  puts "*** Updating fuses! ***"
+  puts [format %x $v0]
+  puts [format %x $v1]
+  cmd $cmd_pbc
+  cmd $cmd_ear
+
+  memwrite32 $fuse0 $v0
+  memwrite32 $fuse1 $v1
+
+  cmd $cmd_wap
+
+  reset
+}
+
+shutdown
diff --git a/uf2-samdx1/scripts/genapplet.js b/uf2-samdx1/scripts/genapplet.js
new file mode 100644
index 00000000..89fd3bee
--- /dev/null
+++ b/uf2-samdx1/scripts/genapplet.js
@@ -0,0 +1,48 @@
+let fs = require("fs")
+let s = fs.readFileSync(process.argv[2], "utf8")
+let infun = false
+let words = []
+for (let l of s.split(/\n/)) {
+    let m = /^00000000 <(.*)>:/.exec(l)
+    if (m && m[1] == process.argv[3]) infun = true
+    if (/^Disassembly/.test(l)) infun = false
+    if (!infun) continue
+    m = /^\s*[0-9a-f]+:\s+([0-9a-f]+)( ([0-9a-f]{4}))?\s+/.exec(l)
+    if (m) {
+        let n = m[1]
+        words.push(n)
+        if (m[3])
+            words.push(m[3])
+        if (n.length == 4 || n.length == 8) {
+            // ok
+        } else {
+            throw new Error()
+        }
+    }
+}
+
+let ww = []
+let pref = ""
+for (let w of words) {
+    if (w.length == 8) {
+        if (pref) throw new Error()
+        ww.push("0x" + w)
+    } else {
+        if (pref) {
+            ww.push("0x" + w + pref)
+            pref = ""
+        } else {
+            pref = w
+        }
+    }
+}
+
+words = ww
+
+let r = ""
+for (let i = 0; i < words.length; i++) {
+    if (i % 6 == 0) r += "\n"
+    r += words[i] + ", "
+}
+
+console.log(r)
\ No newline at end of file
diff --git a/uf2-samdx1/scripts/gendata.js b/uf2-samdx1/scripts/gendata.js
new file mode 100644
index 00000000..b814b787
--- /dev/null
+++ b/uf2-samdx1/scripts/gendata.js
@@ -0,0 +1,67 @@
+"use strict"
+let fs = require("fs")
+let buildPath = process.argv[2]
+let binName = buildPath + "/" + process.argv[3]
+let buf = fs.readFileSync(binName)
+let tail = new Buffer(8192 - buf.length)
+if (buf.length > 8192) {
+  console.error("Bootloader too big!")
+  process.exit(1)
+}
+tail.fill(0)
+buf = Buffer.concat([buf, tail]) // pad with zeros
+
+function addCrc(ptr, crc) {
+  crc = crc ^ ptr << 8;
+  for (var cmpt = 0; cmpt < 8; cmpt++) {
+    if (crc & 0x8000)
+      crc = crc << 1 ^ 0x1021;
+    else
+      crc = crc << 1;
+    crc &= 0xffff;
+  }
+  return crc
+}
+
+let strpos = buf.readUInt32LE(buf.length - 4)
+let strend = strpos
+while (buf[strend])
+  strend++;
+let infostr = buf.slice(strpos, strend).toString("utf8").trim()
+infostr = infostr.split(/\r?\n/).map(l => "// " + l + "\n").join("")
+
+let size = buf.length
+let s = infostr + "\n"
+s += "const uint8_t bootloader[" + size + "] "
+s += "__attribute__ ((section(\".vectors.needs.to.go.first\"))) "
+s += "__attribute__ ((aligned (4))) = {"
+function tohex(v) {
+  return "0x" + ("00" + v.toString(16)).slice(-2) + ", "
+}
+let crc = 0
+let crcs = ""
+for (let i = 0; i < size; ++i) {
+  if (i % 16 == 0) {
+    s += "\n"
+  }
+  s += tohex(buf[i])
+  crc = addCrc(buf[i], crc)
+  if (i % 1024 == 1023) {
+    crcs += crc + ", "
+    crc = 0
+  }
+}
+s += "\n};\n"
+s += "const uint16_t bootloader_crcs[] = {" + crcs + "};\n"
+
+let selfdata = "#include <stdint.h>\n" + s
+fs.writeFileSync(buildPath + "/selfdata.c", selfdata)
+
+// let sketch = fs.readFileSync("src/sketch.cpp", "utf8")
+// let instr =`//
+// // Bootloader update sketch. Paste into Arduino IDE and upload to the device
+// // to update bootloader. It will blink a few times and then start pulsing.
+// // Your OS will then detect a USB mass storage device.
+// //
+// `;
+// fs.writeFileSync(buildPath + "/update-bootloader.ino", instr + s + "\n" + sketch)
diff --git a/uf2-samdx1/scripts/gendata.py b/uf2-samdx1/scripts/gendata.py
new file mode 100644
index 00000000..6a5dbaa3
--- /dev/null
+++ b/uf2-samdx1/scripts/gendata.py
@@ -0,0 +1,65 @@
+import sys
+import os
+
+
+def update_crc(new_byte, current_crc):
+    crc = current_crc ^ new_byte << 8
+    for cmpt in range(8):
+        if crc & 0x8000:
+            crc = crc << 1 ^ 0x1021
+        else:
+            crc = crc << 1
+        crc &= 0xffff
+    return crc
+
+
+# Load the bootloader file
+bootloader_size = int(sys.argv[1])
+bin_name = sys.argv[2]
+bootloader = bytearray()
+with open(bin_name, "rb") as bootloader_bin:
+    bootloader.extend(bootloader_bin.read())
+
+# Fill the remaining space with 0xff.
+bootloader.extend([0xff] * (bootloader_size - len(bootloader)))
+
+# Output the bootloader binary data into C code to use in the self updater.
+selfdata_c_path = os.path.join(os.path.dirname(bin_name), "selfdata.c")
+with open(selfdata_c_path, "w") as output:
+    output.write("#include <stdint.h>\n")
+    output.write("const uint8_t bootloader[{}] ".format(bootloader_size) +
+                 "__attribute__ ((aligned (4))) = {\n")
+    crcs = []
+    crc = 0
+    for row in range(bootloader_size // 16):
+        # Save the crc every 1k.
+        if row % (1024 / 16) == 0 and row > 0:
+            crcs.append(crc)
+            crc = 0
+        start_index = row * 16
+        row_bytes = bootloader[start_index:start_index+16]
+        formatted_bytes = ["0x{:02x}".format(x) for x in row_bytes]
+        output.write(", ".join(formatted_bytes) + ",\n")
+
+        # Update the crc
+        for b in row_bytes:
+            crc = update_crc(b, crc)
+    crcs.append(crc)  # Add the last crc
+    output.write("\n};\n")
+
+    crcs = ["0x{:04x}".format(x) for x in crcs]
+    output.write("const uint16_t bootloader_crcs[] = {" +
+                 " ,".join(crcs) + "};\n")
+
+bin_dirname = os.path.dirname(bin_name)
+bin_basename_no_ext = os.path.basename(os.path.splitext(bin_name)[0])
+with open(os.path.join(bin_dirname, "update-" + bin_basename_no_ext + ".ino"), "w") as output:
+    output.write("""\
+// Bootloader update sketch. Paste into Arduino IDE and upload to the device
+// to update bootloader. It will blink a few times and then start pulsing.
+// Your OS will then detect a USB mass storage device.
+""")
+    with open(selfdata_c_path) as input:
+        output.write(input.read())
+    with open("src/sketch.cpp") as input:
+        output.write(input.read())
diff --git a/uf2-samdx1/scripts/samd21j18a.ld b/uf2-samdx1/scripts/samd21j18a.ld
new file mode 100644
index 00000000..c3e44657
--- /dev/null
+++ b/uf2-samdx1/scripts/samd21j18a.ld
@@ -0,0 +1,165 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00002000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        /*
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+        */
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+
+    _binfo_start = 0x00002000 - 4 * 4;
+    .binfo _binfo_start : {
+      KEEP(*(.binfo)) ;
+    } > rom
+}
diff --git a/uf2-samdx1/scripts/samd21j18a_self.ld b/uf2-samdx1/scripts/samd21j18a_self.ld
new file mode 100644
index 00000000..4c3e9ef9
--- /dev/null
+++ b/uf2-samdx1/scripts/samd21j18a_self.ld
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J18A
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00002000, LENGTH = 0x00020000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+	/*
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+	*/
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/uf2-samdx1/scripts/samd51j19a.ld b/uf2-samdx1/scripts/samd51j19a.ld
new file mode 100644
index 00000000..0f7ecbde
--- /dev/null
+++ b/uf2-samdx1/scripts/samd51j19a.ld
@@ -0,0 +1,151 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD51J19A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 16K
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 48K;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        /*
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+        */
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+
+    _binfo_start = 16K - 4 * 4;
+    .binfo _binfo_start : {
+      KEEP(*(.binfo)) ;
+    } > rom
+}
diff --git a/uf2-samdx1/scripts/samd51j19a_self.ld b/uf2-samdx1/scripts/samd51j19a_self.ld
new file mode 100644
index 00000000..977c4027
--- /dev/null
+++ b/uf2-samdx1/scripts/samd51j19a_self.ld
@@ -0,0 +1,163 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD51J19A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00004000, LENGTH = 0x00080000 - 0x4000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
+  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
+  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    .bkupram (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sbkupram = .;
+        *(.bkupram .bkupram.*);
+        . = ALIGN(8);
+        _ebkupram = .;
+    } > bkupram
+
+    .qspi (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sqspi = .;
+        *(.qspi .qspi.*);
+        . = ALIGN(8);
+        _eqspi = .;
+    } > qspi
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/uf2-samdx1/src/cdc_enumerate.c b/uf2-samdx1/src/cdc_enumerate.c
new file mode 100644
index 00000000..06654d06
--- /dev/null
+++ b/uf2-samdx1/src/cdc_enumerate.c
@@ -0,0 +1,1150 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "uf2.h"
+
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+PacketBuffer ctrlOutCache;
+PacketBuffer endpointCache[MAX_EP];
+
+__attribute__((__aligned__(4))) UsbDeviceDescriptor usb_endpoint_table[MAX_EP];
+
+__attribute__((__aligned__(4)))
+const char devDescriptor[] = {
+    /* Device descriptor */
+    0x12, // bLength
+    0x01, // bDescriptorType
+// bcdUSBL - v2.00; v2.10 is needed for WebUSB; there were issues with newer laptops running Win10
+// but it seems to be resolved
+#if USE_WEBUSB
+    0x10,
+#else
+    0x00,
+#endif
+    0x02,           //
+    0xEF,           // bDeviceClass:    Misc
+    0x02,           // bDeviceSubclass:
+    0x01,           // bDeviceProtocol:
+    0x40,           // bMaxPacketSize0
+    USB_VID & 0xff, // vendor ID
+    USB_VID >> 8,   //
+    USB_PID & 0xff, // product ID
+    USB_PID >> 8,   //
+    0x01,           // bcdDeviceL
+    0x42,           //
+    0x01,           // iManufacturer    // 0x01
+    0x02,           // iProduct
+    0x03,           // SerialNumber (required (!) for WebUSB)
+    0x01            // bNumConfigs
+};
+
+#define CFG_DESC_SIZE (32 + USE_CDC * (58 + 8) + USE_HID * 32 + USE_WEBUSB * 23)
+#define HID_IF_NUM (USE_CDC ? 3 : 1)
+#define WEB_IF_NUM (HID_IF_NUM + 1)
+
+#if USE_HID
+// can be requested separately from the entire config desc
+__attribute__((__aligned__(4)))
+char hidCfgDescriptor[] = {
+    9,          // size
+    4,          // interface
+    HID_IF_NUM, // interface number
+    0,          // alternate
+    2,          // num. endpoints
+    0x03,       // HID
+    0,          // sub
+    0,          // sub
+    3,          // stringID
+};
+
+__attribute__((__aligned__(4)))
+const char hidDescriptor[] = {
+    0x06, 0x97, 0xFF, // usage page vendor 0x97 (usage 0xff97 0x0001)
+    0x09, 0x01,       // usage 1
+    0xA1, 0x01,       // collection - application
+    0x15, 0x00,       // logical min 0
+    0x26, 0xFF, 0x00, // logical max 255
+    0x75, 8,          // report size 8
+    0x95, 64,         // report count 64
+    0x09, 0x01,       // usage 1
+    0x81, 0x02,       // input: data, variable, absolute
+    0x95, 64,         // report count 64
+    0x09, 0x01,       // usage 1
+    0x91, 0x02,       // output: data, variable, absolute
+    0x95, 1,          // report count 1
+    0x09, 0x01,       // usage 1
+    0xB1, 0x02,       // feature: data, variable, absolute
+    0xC0,             // end
+};
+#endif
+
+#ifndef USB_POWER_MA
+#define USB_POWER_MA 100
+#endif
+__attribute__((__aligned__(4)))
+char cfgDescriptor[] = {
+    /* ============== CONFIGURATION 1 =========== */
+    /* Configuration 1 descriptor */
+    0x09,          // CbLength
+    0x02,          // CbDescriptorType
+    CFG_DESC_SIZE, // CwTotalLength 2 EP + Control
+    0x00,
+    1 + 2 * USE_CDC + USE_HID + USE_WEBUSB, // CbNumInterfaces
+    0x01,                                   // CbConfigurationValue
+    0x00,                                   // CiConfiguration
+    0x80,                                   // CbmAttributes 0x80 - bus-powered
+    USB_POWER_MA/2,                         // MaxPower (*2mA)
+
+#if USE_CDC
+    // IAD for CDC
+    0x08, // bLength;
+    0x0B, // bDescriptorType;
+    0x00, // bFirstInterface;
+    0x02, // bInterfaceCount;
+    0x02, // bFunctionClass;
+    0x02, // bFunctionSubclass;
+    0x01, // bFunctionProtocol;
+    0x00, // iFunction; string
+
+    /* Communication Class Interface Descriptor Requirement */
+    0x09, // bLength
+    0x04, // bDescriptorType
+    0x00, // bInterfaceNumber
+    0x00, // bAlternateSetting
+    0x01, // bNumEndpoints
+    0x02, // bInterfaceClass
+    0x02, // bInterfaceSubclass
+    0x01, // bInterfaceProtocol
+    0x00, // iInterface
+
+    /* Header Functional Descriptor */
+    0x05, // bFunction Length
+    0x24, // bDescriptor type: CS_INTERFACE
+    0x00, // bDescriptor subtype: Header Func Desc
+    0x10, // bcdCDC:1.1
+    0x01,
+
+    /* ACM Functional Descriptor */
+    0x04, // bFunctionLength
+    0x24, // bDescriptor Type: CS_INTERFACE
+    0x02, // bDescriptor Subtype: ACM Func Desc
+    0x06, // bmCapabilities
+
+    /* Union Functional Descriptor */
+    0x05, // bFunctionLength
+    0x24, // bDescriptorType: CS_INTERFACE
+    0x06, // bDescriptor Subtype: Union Func Desc
+    0x00, // bMasterInterface: Communication Class Interface
+    0x01, // bSlaveInterface0: Data Class Interface
+
+    /* Call Management Functional Descriptor */
+    0x05, // bFunctionLength
+    0x24, // bDescriptor Type: CS_INTERFACE
+    0x01, // bDescriptor Subtype: Call Management Func Desc
+    0x03, // bmCapabilities: D1 + D0
+    0x01, // bDataInterface: Data Class Interface 1
+
+    /* Endpoint 1 descriptor */
+    0x07, // bLength
+    0x05, // bDescriptorType
+    USB_EP_COMM | 0x80, // bEndpointAddress, Endpoint 03 - IN
+    0x03, // bmAttributes      INT
+    0x08, // wMaxPacketSize
+    0x00,
+    0xFF, // bInterval
+
+    /* Data Class Interface Descriptor Requirement */
+    0x09, // bLength
+    0x04, // bDescriptorType
+    0x01, // bInterfaceNumber
+    0x00, // bAlternateSetting
+    0x02, // bNumEndpoints
+    0x0A, // bInterfaceClass
+    0x00, // bInterfaceSubclass
+    0x00, // bInterfaceProtocol
+    0x00, // iInterface
+
+    /* First alternate setting */
+    /* Endpoint 1 descriptor */
+    0x07,     // bLength
+    0x05,     // bDescriptorType
+    USB_EP_IN | 0x80, // bEndpointAddress, Endpoint 01 - IN
+    0x02,     // bmAttributes      BULK
+    PKT_SIZE, // wMaxPacketSize
+    0x00,
+    0x00, // bInterval
+
+    /* Endpoint 2 descriptor */
+    0x07,     // bLength
+    0x05,     // bDescriptorType
+    USB_EP_OUT, // bEndpointAddress, Endpoint 02 - OUT
+    0x02,     // bmAttributes      BULK
+    PKT_SIZE, // wMaxPacketSize
+    0x00,
+    0x00, // bInterval
+#endif
+
+    // MSC
+
+    9,               /// descriptor size in bytes
+    4,               /// descriptor type - interface
+    USE_CDC ? 2 : 0, /// interface number
+    0,               /// alternate setting number
+    2,               /// number of endpoints
+    USE_MSC * 8,     /// class code - mass storage
+    6,               /// subclass code - SCSI transparent command set
+    80,              /// protocol code - bulk only transport
+    0,               /// interface string index
+
+    7,                    /// descriptor size in bytes
+    5,                    /// descriptor type - endpoint
+    USB_EP_MSC_IN | 0x80, /// endpoint direction and number - in, 2
+    2,                    /// transfer type - bulk
+    PKT_SIZE,             /// maximum packet size
+    0,
+    0, /// not used
+
+    7,              /// descriptor size in bytes
+    5,              /// descriptor type - endpoint
+    USB_EP_MSC_OUT, /// endpoint direction and number - out, 1
+    2,              /// transfer type - bulk
+    PKT_SIZE,       /// maximum packet size
+    0,
+    0, /// maximum NAK rate
+
+#if USE_HID
+    // HID
+    9,          // size
+    4,          // interface
+    HID_IF_NUM, // interface number
+    0,          // alternate
+    2,          // num. endpoints
+    0x03,       // HID
+    0,          // sub
+    0,          // sub
+    0,          // stringID
+
+    9,
+    0x21,                     // HID
+    0x00, 0x01,               // hidbcd 1.00
+    0x00,                     // country code
+    0x01,                     // num desc
+    0x22,                     // report desc type
+    sizeof(hidDescriptor), 0, // size of report
+
+    // interrupt endpoints with interval=1
+    7, 5, 0x80 | USB_EP_HID, 3, PKT_SIZE, 0, 1, // in
+    7, 5, USB_EP_HID, 3, PKT_SIZE, 0, 1,        // out
+#endif
+
+#if USE_WEBUSB
+    9,          // size
+    4,          // interface
+    WEB_IF_NUM, // interface number
+    0,          // alternate
+    2,          // num. endpoints
+    0xFF,       // Vendor
+    42,         // sub
+    1,          // sub
+    0,          // stringID
+
+    // interrupt endpoints with interval=1
+    7, 5, 0x80 | USB_EP_WEB, 3, PKT_SIZE, 0, 1, // in
+    7, 5, USB_EP_WEB, 3, PKT_SIZE, 0, 1,        // out
+#endif
+};
+
+#define WINUSB_SIZE 170
+
+__attribute__((__aligned__(4)))
+static char bosDescriptor[] = {
+    0x05, // Length
+    0x0F, // Binary Object Store descriptor
+#if USE_WEBUSB
+    0x39, 0x00, // Total length
+    0x02,       // Number of device capabilities
+#else
+    0x05, 0x00, // Length
+    0x00        // num caps
+#endif
+
+#if USE_WEBUSB
+    // WebUSB Platform Capability descriptor (bVendorCode == 0x01).
+    0x18,                                           // Length
+    0x10,                                           // Device Capability descriptor
+    0x05,                                           // Platform Capability descriptor
+    0x00,                                           // Reserved
+    0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, // WebUSB GUID
+    0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65, // WebUSB GUID
+    0x00, 0x01,                                     // Version 1.0
+    0x01,                                           // Vendor request code
+    0x00,                                           // landing page
+
+    0x1C,                                           // Length
+    0x10,                                           // Device Capability descriptor
+    0x05,                                           // Platform Capability descriptor
+    0x00,                                           // Reserved
+    0xDF, 0x60, 0xDD, 0xD8, 0x89, 0x45, 0xC7, 0x4C, // MS OS 2.0 GUID
+    0x9C, 0xD2, 0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F, // MS OS 2.0 GUID
+    0x00, 0x00, 0x03, 0x06,                         // Windows version
+    WINUSB_SIZE, 0x00,                              // Descriptor set length
+    0x02,                                           // Vendor request code
+    0x00                                            // Alternate enumeration code
+#endif
+};
+
+#if USE_WEBUSB
+__attribute__((__aligned__(4)))
+static char msOS20Descriptor[] = {
+    // Microsoft OS 2.0 descriptor set header (table 10)
+    0x0A, 0x00,             // Descriptor size (10 bytes)
+    0x00, 0x00,             // MS OS 2.0 descriptor set header
+    0x00, 0x00, 0x03, 0x06, // Windows version (8.1) (0x06030000)
+    WINUSB_SIZE, 0x00,      // Size, MS OS 2.0 descriptor set
+
+    // Microsoft OS 2.0 function subset header
+    0x08, 0x00,             // Descriptor size (8 bytes)
+    0x02, 0x00,             // MS OS 2.0 function subset header
+    WEB_IF_NUM,             // first interface no
+    0x00,                   // Reserved
+    WINUSB_SIZE - 10, 0x00, // Size, MS OS 2.0 function subset
+
+    // Microsoft OS 2.0 compatible ID descriptor (table 13)
+    20, 0x00,                     // wLength
+    0x03, 0x00,                   // MS_OS_20_FEATURE_COMPATIBLE_ID
+    'W', 'I', 'N', 'U', 'S', 'B', //
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+    // interface guids
+    132, 0, 4, 0, 7, 0,
+    //
+    42, 0,
+    //
+    'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0,
+    'a', 0, 'c', 0, 'e', 0, 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0,
+    //
+    80, 0,
+    //
+    '{', 0, '9', 0, '2', 0, 'C', 0, 'E', 0, '6', 0, '4', 0, '6', 0, '2', 0, '-', 0, '9', 0, 'C', 0,
+    '7', 0, '7', 0, '-', 0, '4', 0, '6', 0, 'F', 0, 'E', 0, '-', 0, '9', 0, '3', 0, '3', 0, 'B', 0,
+    '-', 0, '3', 0, '1', 0, 'C', 0, 'B', 0, '9', 0, 'C', 0, '5', 0, 'B', 0, 'B', 0, '3', 0, 'B', 0,
+    '9', 0, '}', 0, 0, 0, 0, 0};
+
+STATIC_ASSERT(sizeof(msOS20Descriptor) == WINUSB_SIZE);
+
+#endif
+
+static uint8_t currentConfiguration;
+
+typedef struct {
+    uint8_t len;
+    uint8_t type;
+    uint8_t data[70];
+} StringDescriptor;
+
+
+// Serial numbers are derived from four 32-bit words. Add one character for null terminator
+#define SERIAL_NUMBER_LENGTH (4 * 8 + 1)
+// serial_number will be filled in when needed.
+static char serial_number[SERIAL_NUMBER_LENGTH];
+
+static const char *string_descriptors[] = {0, VENDOR_NAME, PRODUCT_NAME, serial_number};
+#define STRING_DESCRIPTOR_COUNT (sizeof(string_descriptors) / sizeof(string_descriptors[0]))
+
+static void load_serial_number(char serial_number[SERIAL_NUMBER_LENGTH]) {
+    // These are locations that taken together make up a unique serial number.
+    #ifdef SAMD21
+    uint32_t* addresses[4] = {(uint32_t *) 0x0080A00C, (uint32_t *) 0x0080A040,
+                              (uint32_t *) 0x0080A044, (uint32_t *) 0x0080A048};
+    #endif
+    #ifdef SAMD51
+    uint32_t* addresses[4] = {(uint32_t *) 0x008061FC, (uint32_t *) 0x00806010,
+                              (uint32_t *) 0x00806014, (uint32_t *) 0x00806018};
+    #endif
+    uint32_t serial_number_idx = 0;
+    for (int i = 0; i < 4; i++) {
+        serial_number_idx += writeNum(&(serial_number[serial_number_idx]), *(addresses[i]), true);
+    }
+    serial_number[serial_number_idx] = '\0';
+}
+
+#if USE_CDC
+static usb_cdc_line_coding_t line_coding = {
+    115200, // baudrate
+    0,      // 1 Stop Bit
+    0,      // None Parity
+    8       // 8 Data bits
+};
+
+static USB_CDC pCdc;
+#endif
+
+/* USB standard request code */
+#define STD_GET_STATUS_ZERO 0x0080
+#define STD_GET_STATUS_INTERFACE 0x0081
+#define STD_GET_STATUS_ENDPOINT 0x0082
+
+#define STD_CLEAR_FEATURE_ZERO 0x0100
+#define STD_CLEAR_FEATURE_INTERFACE 0x0101
+#define STD_CLEAR_FEATURE_ENDPOINT 0x0102
+#define STD_VENDOR_CTRL1 0x01C0
+#define STD_VENDOR_CTRL2 0x02C0
+
+#define STD_SET_FEATURE_ZERO 0x0300
+#define STD_SET_FEATURE_INTERFACE 0x0301
+#define STD_SET_FEATURE_ENDPOINT 0x0302
+
+#define STD_SET_ADDRESS 0x0500
+#define STD_GET_DESCRIPTOR 0x0680
+#define STD_GET_DESCRIPTOR1 0x0681
+#define STD_SET_DESCRIPTOR 0x0700
+#define STD_GET_CONFIGURATION 0x0880
+#define STD_SET_CONFIGURATION 0x0900
+#define STD_GET_INTERFACE 0x0A81
+#define STD_SET_INTERFACE 0x0B01
+#define STD_SYNCH_FRAME 0x0C82
+
+/* CDC Class Specific Request Code */
+#define GET_LINE_CODING 0x21A1
+#define SET_LINE_CODING 0x2021
+#define SET_CONTROL_LINE_STATE 0x2221
+
+// MSC
+#define MSC_RESET 0xFF21
+#define MSC_GET_MAX_LUN 0xFEA1
+
+// HID
+#define HID_REQUEST_GET_REPORT 0x01A1
+#define HID_REQUEST_GET_IDLE 0x02A1
+#define HID_REQUEST_GET_PROTOCOL 0x03A1
+#define HID_REQUEST_SET_REPORT 0x0921
+#define HID_REQUEST_SET_IDLE 0x0A21
+#define HID_REQUEST_SET_PROTOCOL 0x0B21
+
+static void AT91F_CDC_Enumerate(void);
+
+STATIC_ASSERT(sizeof(cfgDescriptor) == CFG_DESC_SIZE);
+
+/**
+ * \fn AT91F_InitUSB
+ *
+ * \brief Initializes USB
+ */
+void AT91F_InitUSB(void) {
+    uint32_t pad_transn, pad_transp, pad_trim;
+
+    /* Enable USB clock */
+    #ifdef SAMD21
+    PM->APBBMASK.reg |= PM_APBBMASK_USB;
+    #define DM_PIN PIN_PA24G_USB_DM
+    #define DM_MUX MUX_PA24G_USB_DM
+    #define DP_PIN PIN_PA25G_USB_DP
+    #define DP_MUX MUX_PA25G_USB_DP
+    #endif
+    #ifdef SAMD51
+    #define DM_PIN PIN_PA24H_USB_DM
+    #define DM_MUX MUX_PA24H_USB_DM
+    #define DP_PIN PIN_PA25H_USB_DP
+    #define DP_MUX MUX_PA25H_USB_DP
+    #endif
+
+    /* Set up the USB DP/DN pins */
+    PORT->Group[0].PINCFG[DM_PIN].bit.PMUXEN = 1;
+    PORT->Group[0].PMUX[DM_PIN / 2].reg &= ~(0xF << (4 * (DM_PIN & 0x01u)));
+    PORT->Group[0].PMUX[DM_PIN / 2].reg |= DM_MUX << (4 * (DM_PIN & 0x01u));
+    PORT->Group[0].PINCFG[DP_PIN].bit.PMUXEN = 1;
+    PORT->Group[0].PMUX[DP_PIN / 2].reg &= ~(0xF << (4 * (DP_PIN & 0x01u)));
+    PORT->Group[0].PMUX[DP_PIN / 2].reg |= DP_MUX << (4 * (DP_PIN & 0x01u));
+
+    #ifdef SAMD21
+    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(6) | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+    while (GCLK->STATUS.bit.SYNCBUSY) {}
+    #endif
+    #ifdef SAMD51
+    GCLK->PCHCTRL[USB_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+    MCLK->AHBMASK.bit.USB_ = true;
+    MCLK->APBBMASK.bit.USB_ = true;
+
+    while(GCLK->SYNCBUSY.bit.GENCTRL0) {}
+    #endif
+
+    /* Reset */
+    USB->HOST.CTRLA.bit.SWRST = 1;
+    while (USB->HOST.SYNCBUSY.bit.SWRST) {
+        /* Sync wait */
+    }
+
+    /* Load Pad Calibration */
+    pad_transn = ((*((uint32_t*) USB_FUSES_TRANSN_ADDR)) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
+
+    if (pad_transn == 0x1F) {
+        pad_transn = 5;
+    }
+
+    USB->HOST.PADCAL.bit.TRANSN = pad_transn;
+
+    pad_transp = ((*((uint32_t*) USB_FUSES_TRANSP_ADDR)) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
+
+    if (pad_transp == 0x1F) {
+        pad_transp = 29;
+    }
+
+    USB->HOST.PADCAL.bit.TRANSP = pad_transp;
+    pad_trim = ((*((uint32_t*) USB_FUSES_TRIM_ADDR)) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
+
+    if (pad_trim == 0x7) {
+        pad_trim = 3;
+    }
+
+    USB->HOST.PADCAL.bit.TRIM = pad_trim;
+
+    /* Set the configuration */
+    /* Set mode to Device mode */
+    USB->HOST.CTRLA.bit.MODE = 0;
+    /* Enable Run in Standby */
+    USB->HOST.CTRLA.bit.RUNSTDBY = true;
+    /* Set the descriptor address */
+    USB->HOST.DESCADD.reg = (uint32_t)(&usb_endpoint_table[0]);
+    /* Set speed configuration to Full speed */
+    USB->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val;
+    /* Attach to the USB host */
+    USB->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+
+    /* Initialize endpoint table RAM location to a known value 0 */
+    memset((uint8_t *)(&usb_endpoint_table[0]), 0, sizeof(usb_endpoint_table));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    USB_IsConfigured
+//* \brief Test if the device is configured and handle
+// enumerationDEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1
+//*----------------------------------------------------------------------------
+bool USB_Ok() {
+    timerTick();
+
+    /* Check for End of Reset flag */
+    if (USB->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) {
+        /* Clear the flag */
+        USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+        /* Set Device address as 0 */
+        USB->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | 0;
+        /* Configure endpoint 0 */
+        /* Configure Endpoint 0 for Control IN and Control OUT */
+        USB->DEVICE.DeviceEndpoint[0].EPCFG.reg =
+            USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
+        USB->DEVICE.DeviceEndpoint[0].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+        USB->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+        /* Configure control OUT Packet size to 64 bytes */
+        usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.SIZE = 3;
+        /* Configure control IN Packet size to 64 bytes */
+        usb_endpoint_table[0].DeviceDescBank[1].PCKSIZE.bit.SIZE = 3;
+        /* Configure the data buffer address for control OUT */
+        usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)&ctrlOutCache.buf;
+        /* Configure the data buffer address for control IN */
+        usb_endpoint_table[0].DeviceDescBank[1].ADDR.reg = (uint32_t)&endpointCache[0].buf;
+        /* Set Multipacket size to 8 for control OUT and byte count to 0*/
+        usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
+        usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+        USB->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+        // Reset current configuration value to 0
+        currentConfiguration = 0;
+    } else if (USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) {
+        AT91F_CDC_Enumerate();
+    }
+
+    return currentConfiguration != 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    USB_Read
+//* \brief Read available data from Endpoint OUT
+//*----------------------------------------------------------------------------
+uint32_t USB_ReadCore(void *pData, uint32_t length, uint32_t ep, PacketBuffer *cache) {
+    uint32_t packetSize = 0;
+    UsbDeviceDescriptor *epdesc = (UsbDeviceDescriptor *)USB->HOST.DESCADD.reg + ep;
+
+    if (!cache) {
+        cache = &endpointCache[ep];
+#if USE_HID || USE_WEBUSB
+        assert(ep != USB_EP_HID && ep != USB_EP_WEB);
+#endif
+        timerTick();
+    }
+
+    if (cache->ptr < cache->size) {
+        packetSize = MIN(cache->size - cache->ptr, length);
+        if (pData) {
+            memcpy(pData, cache->buf + cache->ptr, packetSize);
+            cache->ptr += packetSize;
+        }
+        return packetSize;
+    }
+
+    if (!cache->read_job) {
+        /* Set the buffer address for ep data */
+        epdesc->DeviceDescBank[0].ADDR.reg = (uint32_t)&cache->buf;
+        /* Set the byte count as zero */
+        epdesc->DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+        /* Set the byte count as zero */
+        epdesc->DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+        /* Start the reception by clearing the bank 0 ready bit */
+        USB->DEVICE.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = true;
+        /* set the user flag */
+        cache->read_job = true;
+    }
+
+    /* Check for Transfer Complete 0 flag */
+    if (USB->DEVICE.DeviceEndpoint[ep].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
+        /* Set packet size */
+        cache->size = epdesc->DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+
+        // this is when processing a hand-over
+        if (cache->read_job == 2) {
+            memcpy(&cache->buf, (void *)epdesc->DeviceDescBank[0].ADDR.reg, cache->size);
+        }
+
+        packetSize = MIN(cache->size, length);
+        if (pData) {
+            cache->ptr = packetSize;
+            /* Copy read data to user buffer */
+            memcpy(pData, cache->buf, packetSize);
+        } else {
+            cache->ptr = 0;
+        }
+        /* Clear the Transfer Complete 0 flag */
+        USB->DEVICE.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+        /* Clear the user flag */
+        cache->read_job = false;
+    }
+
+    // if (packetSize)
+    //    logval("read", packetSize);
+
+    return packetSize;
+}
+
+uint32_t USB_Read(void *pData, uint32_t length, uint32_t ep) {
+    return USB_ReadCore(pData, length, ep, 0);
+}
+
+void USB_ReadBlocking(void *dst, uint32_t length, uint32_t ep, PacketBuffer *cache) {
+    /* Blocking read till specified number of bytes is received */
+    while (length) {
+        uint32_t curr = USB_ReadCore(dst, length, ep, cache);
+        // if (curr > 0)
+        //    logval("readbl", length);
+        length -= curr;
+        dst = (char *)dst + curr;
+    }
+}
+
+uint32_t USB_Write(const void *pData, uint32_t length, uint8_t ep_num) {
+    return USB_WriteCore(pData, length, ep_num, false);
+}
+
+uint32_t USB_WriteCore(const void *pData, uint32_t length, uint8_t ep_num, bool handoverMode) {
+    uint32_t data_address;
+
+    UsbDeviceDescriptor *epdesc = (UsbDeviceDescriptor *)USB->HOST.DESCADD.reg + ep_num;
+
+    if (handoverMode) {
+        data_address = (uint32_t)pData;
+        epdesc->DeviceDescBank[1].PCKSIZE.bit.AUTO_ZLP = false;
+    }
+    /* Check for requirement for multi-packet or auto zlp */
+    else if (length >= (1 << (epdesc->DeviceDescBank[1].PCKSIZE.bit.SIZE + 3))) {
+        /* Update the EP data address */
+        data_address = (uint32_t)pData;
+        // data must be in RAM!
+        assert(data_address >= HMCRAMC0_ADDR);
+
+        // always disable AUTO_ZLP on MSC channel, otherwise enable
+        epdesc->DeviceDescBank[1].PCKSIZE.bit.AUTO_ZLP = ep_num == USB_EP_MSC_IN ? false : true;
+    } else {
+        /* Copy to local buffer */
+        memcpy(endpointCache[ep_num].buf, pData, length);
+        /* Update the EP data address */
+        data_address = (uint32_t)&endpointCache[ep_num].buf;
+    }
+
+    /* Set the buffer address for ep data */
+    epdesc->DeviceDescBank[1].ADDR.reg = data_address;
+    /* Set the byte count as zero */
+    epdesc->DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = length;
+    /* Set the multi packet size as zero for multi-packet transfers where length
+     * > ep size */
+    epdesc->DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+    /* Clear the transfer complete flag  */
+    USB->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+    /* Set the bank as ready */
+    USB->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
+
+    /* Wait for transfer to complete */
+    while (!(USB->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)) {
+        // if (ep_num && !USB_Ok())
+        //    return -1;
+    }
+
+    return length;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_USB_SendZlp
+//* \brief Send zero length packet through the control endpoint
+//*----------------------------------------------------------------------------
+void AT91F_USB_SendZlp(void) {
+    uint8_t c = 0;
+    USB_Write(&c, 0, 0);
+}
+
+static void configureInOut(uint8_t in_ep) {
+    /* Configure BULK OUT endpoint for CDC Data interface*/
+    USB->DEVICE.DeviceEndpoint[in_ep + 1].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(3);
+    /* Set maximum packet size as 64 bytes */
+    usb_endpoint_table[in_ep + 1].DeviceDescBank[0].PCKSIZE.bit.SIZE = 3;
+    USB->DEVICE.DeviceEndpoint[in_ep + 1].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+    /* Configure the data buffer */
+    usb_endpoint_table[in_ep + 1].DeviceDescBank[0].ADDR.reg =
+        (uint32_t)&endpointCache[in_ep + 1].buf;
+
+    /* Configure BULK IN endpoint for CDC Data interface */
+    USB->DEVICE.DeviceEndpoint[in_ep].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE1(3);
+    /* Set maximum packet size as 64 bytes */
+    usb_endpoint_table[in_ep].DeviceDescBank[1].PCKSIZE.bit.SIZE = 3;
+    USB->DEVICE.DeviceEndpoint[in_ep].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+    /* Configure the data buffer */
+    usb_endpoint_table[in_ep].DeviceDescBank[1].ADDR.reg = (uint32_t)&endpointCache[in_ep].buf;
+}
+
+#if USE_HID || USE_WEBUSB
+__attribute__((noinline))
+static void configureInterruptInOut(uint8_t ep) {
+    USB->DEVICE.DeviceEndpoint[ep].EPCFG.reg =
+        USB_DEVICE_EPCFG_EPTYPE0(4) | USB_DEVICE_EPCFG_EPTYPE1(4);
+    USB->DEVICE.DeviceEndpoint[ep].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+    USB->DEVICE.DeviceEndpoint[ep].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+    usb_endpoint_table[ep].DeviceDescBank[0].PCKSIZE.bit.SIZE = 3;
+    usb_endpoint_table[ep].DeviceDescBank[1].PCKSIZE.bit.SIZE = 3;
+}
+#endif
+
+static uint16_t wLength;
+
+static void sendCtrl(const void *data, uint32_t len) { USB_Write(data, MIN(len, wLength), 0); }
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CDC_Enumerate
+//* \brief This function is a callback invoked when a SETUP packet is received
+//*----------------------------------------------------------------------------
+void AT91F_CDC_Enumerate() {
+    uint8_t bmRequestType, bRequest, dir;
+    uint16_t wValue, wIndex, wStatus;
+
+    /* Clear the Received Setup flag */
+    USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+
+    /* Read the USB request parameters */
+    bmRequestType = ctrlOutCache.buf[0];
+    bRequest = ctrlOutCache.buf[1];
+    wValue = (ctrlOutCache.buf[2] & 0xFF);
+    wValue |= (ctrlOutCache.buf[3] << 8);
+    wIndex = (ctrlOutCache.buf[4] & 0xFF);
+    wIndex |= (ctrlOutCache.buf[5] << 8);
+    wLength = (ctrlOutCache.buf[6] & 0xFF);
+    wLength |= (ctrlOutCache.buf[7] << 8);
+
+    /* Clear the Bank 0 ready flag on Control OUT */
+    USB->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+    uint32_t reqId = (bRequest << 8) | bmRequestType;
+
+    logwrite("USBReq: ");
+    logwritenum(reqId);
+    logwrite(" wValue: ");
+    logwritenum(wValue);
+    logwrite(" wIndex: ");
+    logwritenum(wIndex);
+    logval(" wLen", wLength);
+
+    /* Handle supported standard device request Cf Table 9-3 in USB
+     * specification Rev 1.1 */
+    switch (reqId) {
+    case STD_GET_DESCRIPTOR1:
+    case STD_GET_DESCRIPTOR:
+        if (wValue == 0x100)
+            /* Return Device Descriptor */
+            sendCtrl(devDescriptor, sizeof(devDescriptor));
+        else if (wValue == 0x200)
+            /* Return Configuration Descriptor */
+            sendCtrl(cfgDescriptor, sizeof(cfgDescriptor));
+        else if (ctrlOutCache.buf[3] == 3) {
+            if (ctrlOutCache.buf[2] >= STRING_DESCRIPTOR_COUNT)
+            {
+                stall_ep(0);
+            } else {
+                StringDescriptor desc = {0};
+                desc.type = 3;
+                if (ctrlOutCache.buf[2] == 0) {
+                    desc.len = 4;
+                    desc.data[0] = 0x09;
+                    desc.data[1] = 0x04;
+                } else {
+                load_serial_number(serial_number);
+                    const char *ptr = string_descriptors[ctrlOutCache.buf[2]];
+                    desc.len = strlen(ptr) * 2 + 2;
+                    for (int i = 0; ptr[i]; i++) {
+                        desc.data[i * 2] = ptr[i];
+                    }
+                }
+                sendCtrl(&desc, desc.len);
+            }
+        } else if (ctrlOutCache.buf[3] == 0x0F) {
+            sendCtrl(bosDescriptor, sizeof(bosDescriptor));
+        }
+#if USE_HID
+        else if (ctrlOutCache.buf[3] == 0x21) {
+            sendCtrl(hidCfgDescriptor, sizeof(hidCfgDescriptor));
+        } else if (ctrlOutCache.buf[3] == 0x22) {
+            sendCtrl(hidDescriptor, sizeof(hidDescriptor));
+        }
+#endif
+        else {
+            /* Stall the request */
+            stall_ep(0);
+        }
+        break;
+#if USE_WEBUSB
+    case STD_VENDOR_CTRL1:
+        stall_ep(0);
+        break;
+    case STD_VENDOR_CTRL2:
+        if (wIndex == 0x07)
+            sendCtrl(msOS20Descriptor, sizeof(msOS20Descriptor));
+        else
+            stall_ep(0);
+        break;
+#endif
+    case STD_SET_ADDRESS:
+        /* Send ZLP */
+        AT91F_USB_SendZlp();
+        /* Set device address to the newly received address from host */
+        USB->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | wValue;
+        break;
+    case STD_SET_CONFIGURATION:
+        /* Store configuration */
+        currentConfiguration = (uint8_t)wValue;
+        /* Send ZLP */
+        AT91F_USB_SendZlp();
+
+#if USE_CDC
+        configureInOut(USB_EP_IN);
+
+        /* Configure INTERRUPT IN endpoint for CDC COMM interface*/
+        USB->DEVICE.DeviceEndpoint[USB_EP_COMM].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE1(4);
+        /* Set maximum packet size as 64 bytes */
+        usb_endpoint_table[USB_EP_COMM].DeviceDescBank[1].PCKSIZE.bit.SIZE = 0;
+        USB->DEVICE.DeviceEndpoint[USB_EP_COMM].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+#endif
+
+        configureInOut(USB_EP_MSC_IN);
+
+#if USE_HID
+        configureInterruptInOut(USB_EP_HID);
+#endif
+
+#if USE_WEBUSB
+        configureInterruptInOut(USB_EP_WEB);
+#endif
+
+        break;
+
+    case STD_GET_CONFIGURATION:
+        /* Return current configuration value */
+        sendCtrl(&(currentConfiguration), sizeof(currentConfiguration));
+        break;
+
+    case STD_GET_STATUS_ZERO:
+        wStatus = 0;
+        sendCtrl(&wStatus, sizeof(wStatus));
+        break;
+    case STD_GET_STATUS_INTERFACE:
+        wStatus = 0;
+        sendCtrl(&wStatus, sizeof(wStatus));
+        break;
+    case STD_GET_STATUS_ENDPOINT:
+        wStatus = 0;
+        dir = wIndex & 80;
+        wIndex &= 0x0F;
+        if (wIndex < MAX_EP) {
+            if (dir) {
+                wStatus = (USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUS.reg &
+                           USB_DEVICE_EPSTATUSSET_STALLRQ1)
+                              ? 1
+                              : 0;
+            } else {
+                wStatus = (USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUS.reg &
+                           USB_DEVICE_EPSTATUSSET_STALLRQ0)
+                              ? 1
+                              : 0;
+            }
+            /* Return current status of endpoint */
+            sendCtrl(&wStatus, sizeof(wStatus));
+        } else
+            /* Stall the request */
+            stall_ep(0);
+        break;
+    case STD_SET_FEATURE_ZERO:
+        /* Stall the request */
+        stall_ep(0);
+        break;
+    case STD_SET_FEATURE_INTERFACE:
+        /* Send ZLP */
+        AT91F_USB_SendZlp();
+        break;
+    case STD_SET_FEATURE_ENDPOINT:
+        dir = wIndex & 0x80;
+        wIndex &= 0x0F;
+        if ((wValue == 0) && wIndex && (wIndex < MAX_EP)) {
+            /* Set STALL request for the endpoint */
+            if (dir) {
+                USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSSET.reg =
+                    USB_DEVICE_EPSTATUSSET_STALLRQ1;
+            } else {
+                USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSSET.reg =
+                    USB_DEVICE_EPSTATUSSET_STALLRQ0;
+            }
+            /* Send ZLP */
+            AT91F_USB_SendZlp();
+        } else
+            /* Stall the request */
+            stall_ep(0);
+        break;
+    case STD_CLEAR_FEATURE_ZERO:
+        /* Stall the request */
+        stall_ep(0);
+        break;
+    case STD_CLEAR_FEATURE_INTERFACE:
+        /* Send ZLP */
+        AT91F_USB_SendZlp();
+        break;
+    case STD_CLEAR_FEATURE_ENDPOINT:
+        dir = wIndex & 0x80;
+        wIndex &= 0x0F;
+        if ((wValue == 0) && wIndex && (wIndex < MAX_EP)) {
+            if (dir) {
+                if (USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUS.reg &
+                    USB_DEVICE_EPSTATUSSET_STALLRQ1) {
+                    // Remove stall request
+                    USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSCLR.reg =
+                        USB_DEVICE_EPSTATUSCLR_STALLRQ1;
+                    if (USB->DEVICE.DeviceEndpoint[wIndex].EPINTFLAG.reg &
+                        USB_DEVICE_EPINTFLAG_STALL1) {
+                        USB->DEVICE.DeviceEndpoint[wIndex].EPINTFLAG.reg =
+                            USB_DEVICE_EPINTFLAG_STALL1;
+                        // The Stall has occurred, then reset data toggle
+                        USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSCLR.reg =
+                            USB_DEVICE_EPSTATUSSET_DTGLIN;
+                    }
+                }
+            } else {
+                if (USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUS.reg &
+                    USB_DEVICE_EPSTATUSSET_STALLRQ0) {
+                    // Remove stall request
+                    USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSCLR.reg =
+                        USB_DEVICE_EPSTATUSCLR_STALLRQ0;
+                    if (USB->DEVICE.DeviceEndpoint[wIndex].EPINTFLAG.reg &
+                        USB_DEVICE_EPINTFLAG_STALL0) {
+                        USB->DEVICE.DeviceEndpoint[wIndex].EPINTFLAG.reg =
+                            USB_DEVICE_EPINTFLAG_STALL0;
+                        // The Stall has occurred, then reset data toggle
+                        USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSCLR.reg =
+                            USB_DEVICE_EPSTATUSSET_DTGLOUT;
+                    }
+                }
+            }
+            /* Send ZLP */
+            AT91F_USB_SendZlp();
+        } else {
+            stall_ep(0);
+        }
+        break;
+
+#if USE_CDC
+    // handle CDC class requests
+    case SET_LINE_CODING:
+        /* Send ZLP */
+        AT91F_USB_SendZlp();
+        break;
+    case GET_LINE_CODING:
+        /* Send current line coding */
+        sendCtrl(&line_coding, sizeof(usb_cdc_line_coding_t));
+        break;
+    case SET_CONTROL_LINE_STATE:
+        /* Store the current connection */
+        pCdc.currentConnection = wValue;
+        /* Send ZLP */
+        AT91F_USB_SendZlp();
+        break;
+#endif
+
+#if USE_MSC_CHECKS
+    // MSC
+    case MSC_RESET:
+        DBG_MSC(logmsg("MSC reset"));
+        msc_reset();
+        break;
+#endif
+
+    case MSC_GET_MAX_LUN:
+        DBG_MSC(logmsg("MSC maxlun"));
+        wStatus = MAX_LUN;
+        sendCtrl(&wStatus, 1);
+        break;
+
+#if USE_HID
+    case HID_REQUEST_GET_PROTOCOL:
+    case HID_REQUEST_GET_IDLE:
+    case HID_REQUEST_GET_REPORT: {
+        uint8_t buf[8] = {0};
+        sendCtrl(buf, 8);
+    } break;
+
+    case HID_REQUEST_SET_IDLE:
+    case HID_REQUEST_SET_REPORT:
+    case HID_REQUEST_SET_PROTOCOL:
+        AT91F_USB_SendZlp();
+        break;
+#endif
+
+    default:
+        logval("Invalid CTRL command", reqId);
+        /* Stall the request */
+        stall_ep(0);
+        break;
+    }
+}
+
+static bool isInEP(uint8_t ep) { return ep == USB_EP_IN || ep == USB_EP_MSC_IN; }
+
+void reset_ep(uint8_t ep) {
+    assert(ep != 0);
+
+    // Stop transfer
+    if (isInEP(ep)) {
+        USB->DEVICE.DeviceEndpoint[ep].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+        // Eventually ack a transfer occur during abort
+        USB->DEVICE.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+    } else {
+        USB->DEVICE.DeviceEndpoint[ep].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+        // Eventually ack a transfer occur during abort
+        USB->DEVICE.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+    }
+}
+
+void stall_ep(uint8_t ep) {
+    logval("Stall EP", ep);
+    /* Check the direction */
+    if (ep == 0 || isInEP(ep)) {
+        /* Set STALL request on IN direction */
+        USB->DEVICE.DeviceEndpoint[ep].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
+    } else {
+        /* Set STALL request on OUT direction */
+        USB->DEVICE.DeviceEndpoint[ep].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
+    }
+}
+
+void usb_init(void) {
+    /* Initialize USB */
+    AT91F_InitUSB();
+    currentConfiguration = 0;
+#if USE_CDC
+    pCdc.currentConnection = 0;
+#endif
+    USB->HOST.CTRLA.bit.ENABLE = true;
+}
+
+#include "usart_sam_ba.h"
+
+#if USE_UART
+#define UART(e)                                                                                    \
+    if (b_sam_ba_interface_usart)                                                                  \
+        return e;
+#else
+#define UART(e)
+#endif
+
+bool cdc_is_rx_ready(void) {
+    UART(usart_is_rx_ready())
+
+    /* Check whether the device is configured */
+    if (!USB_Ok())
+        return 0;
+
+    /* Return transfer complete 0 flag status */
+    return (USB->DEVICE.DeviceEndpoint[USB_EP_OUT].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0);
+}
+
+uint32_t cdc_write_buf(void const *data, uint32_t length) {
+    UART(usart_putdata(data, length))
+    /* Send the specified number of bytes on USB CDC */
+    USB_Write((const char *)data, length, USB_EP_IN);
+    return length;
+}
+
+uint32_t cdc_write_buf_xmd(void const *data, uint32_t length) {
+    UART(usart_putdata_xmd(data, length))
+    /* Send the specified number of bytes on USB CDC */
+    USB_Write((const char *)data, length, USB_EP_IN);
+    return length;
+}
+
+uint32_t cdc_read_buf(void *data, uint32_t length) {
+    UART(usart_getdata(data, length))
+
+    /* Check whether the device is configured */
+    if (!USB_Ok())
+        return 0;
+
+    /* Read from USB CDC */
+    return USB_Read((char *)data, length, USB_EP_OUT);
+}
+
+uint32_t cdc_read_buf_xmd(void *data, uint32_t length) {
+    UART(usart_getdata_xmd(data, length))
+    /* Check whether the device is configured */
+    if (!USB_Ok())
+        return 0;
+
+    /* Blocking read till specified number of bytes is received */
+    USB_ReadBlocking((char *)data, length, USB_EP_OUT, 0);
+
+    return length;
+}
diff --git a/uf2-samdx1/src/fat.c b/uf2-samdx1/src/fat.c
new file mode 100644
index 00000000..6f63a43d
--- /dev/null
+++ b/uf2-samdx1/src/fat.c
@@ -0,0 +1,266 @@
+
+#include "uf2.h"
+
+#define SERIAL0 (*(uint32_t *)0x0080A00C)
+#define SERIAL1 (*(uint32_t *)0x0080A040)
+#define SERIAL2 (*(uint32_t *)0x0080A044)
+#define SERIAL3 (*(uint32_t *)0x0080A048)
+
+typedef struct {
+    uint8_t JumpInstruction[3];
+    uint8_t OEMInfo[8];
+    uint16_t SectorSize;
+    uint8_t SectorsPerCluster;
+    uint16_t ReservedSectors;
+    uint8_t FATCopies;
+    uint16_t RootDirectoryEntries;
+    uint16_t TotalSectors16;
+    uint8_t MediaDescriptor;
+    uint16_t SectorsPerFAT;
+    uint16_t SectorsPerTrack;
+    uint16_t Heads;
+    uint32_t HiddenSectors;
+    uint32_t TotalSectors32;
+    uint8_t PhysicalDriveNum;
+    uint8_t Reserved;
+    uint8_t ExtendedBootSig;
+    uint32_t VolumeSerialNumber;
+    uint8_t VolumeLabel[11];
+    uint8_t FilesystemIdentifier[8];
+} __attribute__((packed)) FAT_BootBlock;
+
+typedef struct {
+    char name[8];
+    char ext[3];
+    uint8_t attrs;
+    uint8_t reserved;
+    uint8_t createTimeFine;
+    uint16_t createTime;
+    uint16_t createDate;
+    uint16_t lastAccessDate;
+    uint16_t highStartCluster;
+    uint16_t updateTime;
+    uint16_t updateDate;
+    uint16_t startCluster;
+    uint32_t size;
+} __attribute__((packed)) DirEntry;
+
+STATIC_ASSERT(sizeof(DirEntry) == 32);
+
+struct TextFile {
+    const char name[11];
+    const char *content;
+};
+
+#define STR0(x) #x
+#define STR(x) STR0(x)
+const char infoUf2File[] = //
+    "UF2 Bootloader " UF2_VERSION "\r\n"
+    "Model: " PRODUCT_NAME "\r\n"
+    "Board-ID: " BOARD_ID "\r\n"
+    #if USE_URL_IN_INFO
+    INDEX_URL "\r\n"
+    #endif
+    ;
+
+#if USE_FAT
+#if USE_INDEX_HTM
+const char indexFile[] = //
+    "<!doctype html>\n"
+    "<html>"
+    "<body>"
+    "<script>\n"
+    "location.replace(\"" INDEX_URL "\");\n"
+    "</script>"
+    "</body>"
+    "</html>\n";
+#endif
+
+// WARNING -- code presumes only one NULL .content for .UF2 file
+//            and requires it be the last element of the array
+static const struct TextFile info[] = {
+    {.name = "INFO_UF2TXT", .content = infoUf2File},
+#if USE_INDEX_HTM
+    {.name = "INDEX   HTM", .content = indexFile},
+#endif
+    {.name = "CURRENT UF2"},
+};
+#define NUM_FILES (sizeof(info) / sizeof(info[0]))
+#define NUM_DIRENTRIES (NUM_FILES + 1) // Code adds volume label as first root directory entry
+
+#define UF2_SIZE (FLASH_SIZE * 2)
+#define UF2_SECTORS (UF2_SIZE / 512)
+#define UF2_FIRST_SECTOR (NUM_FILES + 1) // WARNING -- code presumes each non-UF2 file content fits in single sector
+#define UF2_LAST_SECTOR (UF2_FIRST_SECTOR + UF2_SECTORS - 1)
+#endif
+
+#define RESERVED_SECTORS 1
+#define ROOT_DIR_SECTORS 4
+#define SECTORS_PER_FAT ((NUM_FAT_BLOCKS * 2 + 511) / 512)
+
+#define START_FAT0 RESERVED_SECTORS
+#define START_FAT1 (START_FAT0 + SECTORS_PER_FAT)
+#define START_ROOTDIR (START_FAT1 + SECTORS_PER_FAT)
+#define START_CLUSTERS (START_ROOTDIR + ROOT_DIR_SECTORS)
+
+// all directory entries must fit in a single sector
+// because otherwise current code overflows buffer
+#define DIRENTRIES_PER_SECTOR (512/sizeof(DirEntry))
+#if USE_FAT
+STATIC_ASSERT(NUM_DIRENTRIES < DIRENTRIES_PER_SECTOR * ROOT_DIR_SECTORS);
+#endif
+
+static const FAT_BootBlock BootBlock = {
+    .JumpInstruction = {0xeb, 0x3c, 0x90},
+    .OEMInfo = "UF2 UF2 ",
+    .SectorSize = 512,
+    .SectorsPerCluster = 1,
+    .ReservedSectors = RESERVED_SECTORS,
+    .FATCopies = 2,
+    .RootDirectoryEntries = (ROOT_DIR_SECTORS * DIRENTRIES_PER_SECTOR),
+    .TotalSectors16 = NUM_FAT_BLOCKS - 2,
+    .MediaDescriptor = 0xF8,
+    .SectorsPerFAT = SECTORS_PER_FAT,
+    .SectorsPerTrack = 1,
+    .Heads = 1,
+    .PhysicalDriveNum = 0x80, // to match MediaDescriptor of 0xF8
+    .ExtendedBootSig = 0x29,
+    .VolumeSerialNumber = 0x00420042,
+    .VolumeLabel = VOLUME_LABEL,
+    .FilesystemIdentifier = "FAT16   ",
+};
+
+void padded_memcpy(char *dst, const char *src, int len) {
+    for (int i = 0; i < len; ++i) {
+        if (*src)
+            *dst = *src++;
+        else
+            *dst = ' ';
+        dst++;
+    }
+}
+
+void read_block(uint32_t block_no, uint8_t *data) {
+    memset(data, 0, 512);
+    uint32_t sectionIdx = block_no;
+
+    if (block_no == 0) { // Requested boot block
+        memcpy(data, &BootBlock, sizeof(BootBlock));
+        data[510] = 0x55;
+        data[511] = 0xaa;
+        // logval("data[0]", data[0]);
+    } else if (block_no < START_ROOTDIR) {  // Requested FAT table sector
+        sectionIdx -= START_FAT0;
+        // logval("sidx", sectionIdx);
+        if (sectionIdx >= SECTORS_PER_FAT)
+            sectionIdx -= SECTORS_PER_FAT; // second FAT is same as the first...
+#if USE_FAT
+        if (sectionIdx == 0) {
+            data[0] = 0xf0;
+            // WARNING -- code presumes only one NULL .content for .UF2 file
+            //            and all non-NULL .content fit in one sector
+            //            and requires it be the last element of the array
+            for (int i = 1; i < NUM_FILES * 2 + 4; ++i) {
+                data[i] = 0xff;
+            }
+        }
+        for (int i = 0; i < 256; ++i) { // Generate the FAT chain for the firmware "file"
+            uint32_t v = sectionIdx * 256 + i;
+            if (UF2_FIRST_SECTOR <= v && v <= UF2_LAST_SECTOR)
+                ((uint16_t *)(void *)data)[i] = v == UF2_LAST_SECTOR ? 0xffff : v + 1;
+        }
+#else
+        if (sectionIdx == 0)
+            memcpy(data, "\xf0\xff\xff\xff", 4);
+#endif
+    }
+#if USE_FAT
+    else if (block_no < START_CLUSTERS) { // Requested sector of the root directory
+        sectionIdx -= START_ROOTDIR;
+        if (sectionIdx == 0) {
+            DirEntry *d = (void *)data;
+            padded_memcpy(d->name, BootBlock.VolumeLabel, 11);
+            d->attrs = 0x28;
+            for (int i = 0; i < NUM_FILES; ++i) {
+                d++;
+                const struct TextFile *inf = &info[i];
+                d->size = inf->content ? strlen(inf->content) : UF2_SIZE;
+                d->startCluster = i + 2;
+                padded_memcpy(d->name, inf->name, 11);
+                d->createDate = 0x4d99;
+                d->updateDate = 0x4d99;
+            }
+        }
+    } else { // Requested sector from file space
+        sectionIdx -= START_CLUSTERS;
+        // WARNING -- code presumes all but last file take exactly one sector
+        if (sectionIdx < NUM_FILES - 1) {
+            memcpy(data, info[sectionIdx].content, strlen(info[sectionIdx].content));
+        } else {
+            sectionIdx -= NUM_FILES - 1;
+            uint32_t addr = sectionIdx * 256;
+            if (addr < FLASH_SIZE) {
+                UF2_Block *bl = (void *)data;
+                bl->magicStart0 = UF2_MAGIC_START0;
+                bl->magicStart1 = UF2_MAGIC_START1;
+                bl->magicEnd = UF2_MAGIC_END;
+                bl->blockNo = sectionIdx;
+                bl->numBlocks = FLASH_SIZE / 256;
+                bl->targetAddr = addr;
+                bl->payloadSize = 256;
+                bl->flags |= UF2_FLAG_FAMILYID_PRESENT;
+                bl->familyID = UF2_FAMILY;
+                memcpy(bl->data, (void *)addr, bl->payloadSize);
+            }
+        }
+    }
+#endif
+}
+
+void write_block(uint32_t block_no, uint8_t *data, bool quiet, WriteState *state) {
+    UF2_Block *bl = (void *)data;
+    if (!is_uf2_block(bl) || !UF2_IS_MY_FAMILY(bl)) {
+        return;
+    }
+
+    if ((bl->flags & UF2_FLAG_NOFLASH) || bl->payloadSize != 256 || (bl->targetAddr & 0xff) ||
+        bl->targetAddr < APP_START_ADDRESS || bl->targetAddr >= FLASH_SIZE) {
+#if USE_DBG_MSC
+        if (!quiet)
+            logval("invalid target addr", bl->targetAddr);
+#endif
+        // this happens when we're trying to re-flash CURRENT.UF2 file previously
+        // copied from a device; we still want to count these blocks to reset properly
+    } else {
+        // logval("write block at", bl->targetAddr);
+        flash_write_row((void *)bl->targetAddr, (void *)bl->data);
+    }
+
+    if (state && bl->numBlocks) {
+        if (state->numBlocks != bl->numBlocks) {
+            if (bl->numBlocks >= MAX_BLOCKS || state->numBlocks)
+                state->numBlocks = 0xffffffff;
+            else
+                state->numBlocks = bl->numBlocks;
+        }
+        if (bl->blockNo < MAX_BLOCKS) {
+            uint8_t mask = 1 << (bl->blockNo % 8);
+            uint32_t pos = bl->blockNo / 8;
+            if (!(state->writtenMask[pos] & mask)) {
+                // logval("incr", state->numWritten);
+                state->writtenMask[pos] |= mask;
+                state->numWritten++;
+            }
+            if (state->numWritten >= state->numBlocks) {
+                // wait a little bit before resetting, to avoid Windows transmit error
+                // https://github.com/Microsoft/uf2-samd21/issues/11
+                if (!quiet)
+                    resetHorizon = timerHigh + 30;
+                // resetIntoApp();
+            }
+        }
+    } else {
+        if (!quiet)
+            resetHorizon = timerHigh + 300;
+    }
+}
diff --git a/uf2-samdx1/src/flash_samd21.c b/uf2-samdx1/src/flash_samd21.c
new file mode 100644
index 00000000..04348ace
--- /dev/null
+++ b/uf2-samdx1/src/flash_samd21.c
@@ -0,0 +1,115 @@
+#include "uf2.h"
+
+// this actually generates less code than a function
+#define wait_ready()                                                                               \
+    while (NVMCTRL->INTFLAG.bit.READY == 0)                                                        \
+        ;
+
+void flash_erase_row(uint32_t *dst) {
+    wait_ready();
+    NVMCTRL->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+    // Execute "ER" Erase Row
+    NVMCTRL->ADDR.reg = (uint32_t)dst / 2;
+    NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
+    wait_ready();
+}
+
+void flash_erase_to_end(uint32_t *start_address) {
+    // Note: the flash memory is erased in ROWS, that is in
+    // block of 4 pages.
+    //       Even if the starting address is the last byte
+    //       of a ROW the entire
+    //       ROW is erased anyway.
+
+    uint32_t dst_addr = (uint32_t) start_address; // starting address
+
+    while (dst_addr < FLASH_SIZE) {
+        flash_erase_row((void *)dst_addr);
+        dst_addr += FLASH_ROW_SIZE;
+    }
+}
+
+void copy_words(uint32_t *dst, uint32_t *src, uint32_t n_words) {
+    while (n_words--)
+        *dst++ = *src++;
+}
+
+void flash_write_words(uint32_t *dst, uint32_t *src, uint32_t n_words) {
+    // Set automatic page write
+    NVMCTRL->CTRLB.bit.MANW = 0;
+
+    while (n_words > 0) {
+        uint32_t len = (FLASH_PAGE_SIZE >> 2) < n_words ? (FLASH_PAGE_SIZE >> 2) : n_words;
+        n_words -= len;
+
+        // Execute "PBC" Page Buffer Clear
+        NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC;
+        wait_ready();
+
+        // make sure there are no other memory writes here
+        // otherwise we get lock-ups
+
+        while (len--)
+            *dst++ = *src++;
+
+        // Execute "WP" Write Page
+        NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP;
+        wait_ready();
+    }
+}
+
+void flash_write(void) {
+    uint32_t *src = (void *)0x20006000;
+    uint32_t *dst = (void *)*src++;
+    uint32_t n_rows = *src++;
+
+    NVMCTRL->CTRLB.bit.MANW = 1;
+    while (n_rows--) {
+        wait_ready();
+        NVMCTRL->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+        // Execute "ER" Erase Row
+        NVMCTRL->ADDR.reg = (uint32_t)dst / 2;
+        NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
+        wait_ready();
+
+        // there are 4 pages to a row
+        for (int i = 0; i < 4; ++i) {
+            // Execute "PBC" Page Buffer Clear
+            NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC;
+            wait_ready();
+
+            uint32_t len = FLASH_PAGE_SIZE >> 2;
+            while (len--)
+                *dst++ = *src++;
+
+            // Execute "WP" Write Page
+            NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP;
+            wait_ready();
+        }
+    }
+}
+
+// Skip writing blocks that are identical to the existing block.
+// only disable for debugging/timing
+#define QUICK_FLASH 1
+
+void flash_write_row(uint32_t *dst, uint32_t *src) {
+#if QUICK_FLASH
+    bool src_different = false;
+    for (int i = 0; i < FLASH_ROW_SIZE / 4; ++i) {
+        if (src[i] != dst[i]) {
+            src_different = true;
+            break;
+        }
+    }
+
+    if (!src_different) {
+        return;
+    }
+#endif
+
+    flash_erase_row(dst);
+    flash_write_words(dst, src, FLASH_ROW_SIZE / 4);
+}
diff --git a/uf2-samdx1/src/flash_samd51.c b/uf2-samdx1/src/flash_samd51.c
new file mode 100644
index 00000000..ce508276
--- /dev/null
+++ b/uf2-samdx1/src/flash_samd51.c
@@ -0,0 +1,139 @@
+#include "uf2.h"
+
+// this actually generates less code than a function
+#define wait_ready()                                                                               \
+    while (NVMCTRL->STATUS.bit.READY == 0)                                                        \
+        ;
+
+void flash_erase_block(uint32_t *dst) {
+    wait_ready();
+
+    // Execute "ER" Erase Row
+    NVMCTRL->ADDR.reg = (uint32_t)dst;
+    NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_EB;
+    wait_ready();
+}
+
+void flash_erase_to_end(uint32_t *dst) {
+    for (uint32_t i = ((uint32_t) dst); i < FLASH_SIZE; i += NVMCTRL_BLOCK_SIZE) {
+        flash_erase_block((uint32_t *)i);
+    }
+}
+
+void copy_words(uint32_t *dst, uint32_t *src, uint32_t n_words) {
+    while (n_words--)
+        *dst++ = *src++;
+}
+
+#define QUAD_WORD (4 * 4)
+void flash_write_words(uint32_t *dst, uint32_t *src, uint32_t n_words) {
+    // Set manual page write
+    NVMCTRL->CTRLA.bit.WMODE = NVMCTRL_CTRLA_WMODE_MAN;
+
+    // Execute "PBC" Page Buffer Clear
+    wait_ready();
+    NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_PBC;
+    wait_ready();
+
+    while (n_words > 0) {
+        // We write quad words so that we can write 256 byte blocks like UF2
+        // provides. Pages are 512 bytes and would require loading data back out
+        // of flash for the neighboring row.
+        uint32_t len = 4 < n_words ? 4 : n_words;
+
+        wait_ready();
+        for (uint32_t i = 0; i < 4; i++) {
+            if (i < len) {
+                dst[i] = src[i];
+            } else {
+                dst[i] = 0xffffffff;
+            }
+        }
+
+        // Trigger the quad word write.
+        NVMCTRL->ADDR.reg = (uint32_t)dst;
+        NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_WQW;
+
+        // Advance to quad word
+        dst += len;
+        src += len;
+        n_words -= len;
+    }
+}
+
+// On the SAMD51 we can only erase 4KiB blocks of 512 byte pages. To reduce wear
+// and increase flash speed we only want to erase a block at most once per
+// flash. Each 256 byte row from the UF2 comes in an unknown order. So, we wait
+// to erase until we see a row that varies with current memory. Before erasing,
+// we cache the rows that were the same up to this point, perform the erase and
+// flush the previously seen rows. Every row after will get written without
+// another erase.
+
+bool block_erased[FLASH_SIZE / NVMCTRL_BLOCK_SIZE];
+bool row_same[FLASH_SIZE / NVMCTRL_BLOCK_SIZE][NVMCTRL_BLOCK_SIZE / FLASH_ROW_SIZE];
+
+// Skip writing blocks that are identical to the existing block.
+// only disable for debugging/timing
+#define QUICK_FLASH 1
+
+void flash_write_row(uint32_t *dst, uint32_t *src) {
+    const uint32_t FLASH_ROW_SIZE_WORDS = FLASH_ROW_SIZE / 4;
+
+    // The cache in Rev A isn't reliable when reading and writing to the NVM.
+    NVMCTRL->CTRLA.bit.CACHEDIS0 = true;
+    NVMCTRL->CTRLA.bit.CACHEDIS1 = true;
+
+    uint32_t block = ((uint32_t) dst) / NVMCTRL_BLOCK_SIZE;
+    uint8_t row = (((uint32_t) dst) % NVMCTRL_BLOCK_SIZE) / FLASH_ROW_SIZE;
+#if QUICK_FLASH
+    bool src_different = false;
+    for (uint32_t i = 0; i < FLASH_ROW_SIZE_WORDS; ++i) {
+        if (src[i] != dst[i]) {
+            src_different = true;
+            break;
+        }
+    }
+
+    // Row is the same, quit early but keep track in case we need to erase its
+    // block. This is ok after an erase because the destination will be all 1s.
+    if (!src_different) {
+        row_same[block][row] = true;
+        return;
+    }
+#endif
+
+    if (!block_erased[block]) {
+        uint8_t rows_per_block = NVMCTRL_BLOCK_SIZE / FLASH_ROW_SIZE;
+        uint32_t* block_address = (uint32_t *) (block * NVMCTRL_BLOCK_SIZE);
+
+        bool some_rows_same = false;
+        for (uint8_t i = 0; i < rows_per_block; i++) {
+            some_rows_same = some_rows_same || row_same[block][i];
+        }
+        uint32_t row_cache[rows_per_block][FLASH_ROW_SIZE_WORDS];
+        if (some_rows_same) {
+            for (uint8_t i = 0; i < rows_per_block; i++) {
+                if(row_same[block][i]) {
+                    memcpy(row_cache[i], block_address + i * FLASH_ROW_SIZE_WORDS, FLASH_ROW_SIZE);
+                }
+            }
+        }
+        flash_erase_block(dst);
+        block_erased[block] = true;
+        if (some_rows_same) {
+            for (uint8_t i = 0; i < rows_per_block; i++) {
+                if(row_same[block][i]) {
+                    // dst is a uint32_t pointer so we add the number of words,
+                    // not bytes.
+                    flash_write_words(block_address + i * FLASH_ROW_SIZE_WORDS, row_cache[i], FLASH_ROW_SIZE_WORDS);
+                }
+            }
+        }
+    }
+
+    flash_write_words(dst, src, FLASH_ROW_SIZE_WORDS);
+
+    // Don't return until we're done writing in case something after us causes
+    // a reset.
+    wait_ready();
+}
diff --git a/uf2-samdx1/src/hid.c b/uf2-samdx1/src/hid.c
new file mode 100644
index 00000000..9ba8c53b
--- /dev/null
+++ b/uf2-samdx1/src/hid.c
@@ -0,0 +1,220 @@
+#include "uf2.h"
+
+#if USE_HID || USE_WEBUSB
+
+typedef struct {
+    PacketBuffer pbuf;
+    uint16_t size;
+    uint8_t serial;
+    uint8_t ep;
+    union {
+        uint8_t buf[FLASH_ROW_SIZE + 64];
+        uint32_t buf32[(FLASH_ROW_SIZE + 64) / 4];
+        uint16_t buf16[(FLASH_ROW_SIZE + 64) / 2];
+        HF2_Command cmd;
+        HF2_Response resp;
+    };
+} HID_InBuffer;
+
+// Recieve HF2 message
+// Does not block. Will store intermediate data in pkt.
+// `serial` flag is cleared if we got a command message.
+int recv_hf2(HID_InBuffer *pkt) {
+    if (!USB_ReadCore(NULL, 64, pkt->ep, &pkt->pbuf))
+        return 0; // no data
+
+    // logval("rhf2", pkt->pbuf.size);
+    assert(pkt->pbuf.ptr == 0 && pkt->pbuf.size > 0);
+    pkt->pbuf.size = 0;
+    uint8_t tag = pkt->pbuf.buf[0];
+#if !USE_HID_SERIAL
+    if (tag & 0x80) {
+        return 0;
+    }
+#endif
+    // serial packets not allowed when in middle of command packet
+    assert(pkt->size == 0 || !(tag & HF2_FLAG_SERIAL_OUT));
+    memcpy(pkt->buf + pkt->size, pkt->pbuf.buf + 1, tag & HF2_SIZE_MASK);
+    pkt->size += tag & HF2_SIZE_MASK;
+    assert(pkt->size <= sizeof(pkt->buf));
+    tag &= HF2_FLAG_MASK;
+    if (tag != HF2_FLAG_CMDPKT_BODY) {
+#if USE_HID_SERIAL
+        pkt->serial = tag - 0x40;
+#endif
+        int sz = pkt->size;
+        pkt->size = 0;
+        return sz;
+    }
+    return 0;
+}
+
+// Send HF2 message.
+// Use command message when flag == HF2_FLAG_CMDPKT_BODY
+// Use serial stdout for HF2_FLAG_SERIAL_OUT and stderr for HF2_FLAG_SERIAL_ERR.
+void send_hf2(const void *data, int size, int ep, int flag) {
+    uint8_t buf[64];
+    const uint8_t *ptr = data;
+
+    for (;;) {
+        int s = 63;
+        if (size <= 63) {
+            s = size;
+            if (flag == HF2_FLAG_CMDPKT_BODY)
+                flag = HF2_FLAG_CMDPKT_LAST;
+        }
+        buf[0] = flag | s;
+        memcpy(buf + 1, ptr, s);
+        USB_WriteCore(buf, sizeof(buf), ep, true);
+        ptr += s;
+        size -= s;
+        if (!size)
+            break;
+    }
+}
+
+void send_hf2_response(HID_InBuffer *pkt, int size) {
+    logval("sendresp", size);
+    send_hf2(pkt->buf, 4 + size, pkt->ep, HF2_FLAG_CMDPKT_BODY);
+}
+
+static void checksum_pages(HID_InBuffer *pkt, int start, int num) {
+    for (int i = 0; i < num; ++i) {
+        uint8_t *data = (uint8_t *)start + i * FLASH_ROW_SIZE;
+        uint16_t crc = 0;
+        for (int j = 0; j < FLASH_ROW_SIZE; ++j) {
+            crc = add_crc(*data++, crc);
+        }
+        pkt->resp.data16[i] = crc;
+    }
+    send_hf2_response(pkt, num * 2);
+}
+
+void process_core(HID_InBuffer *pkt) {
+    int sz = recv_hf2(pkt);
+
+    if (!sz)
+        return;
+
+    uint32_t tmp;
+
+#if USE_HID_SERIAL
+    if (pkt->serial) {
+#if USE_LOGS
+        if (pkt->buf[0] == 'L') {
+            send_hf2(logStoreUF2.buffer, logStoreUF2.ptr, pkt->ep, HF2_FLAG_SERIAL_OUT);
+        } else
+#endif
+        {
+            send_hf2("OK\n", 3, pkt->ep, HF2_FLAG_SERIAL_ERR);
+        }
+        return;
+    }
+#endif
+
+    logwrite("HID sz=");
+    logwritenum(sz);
+    logval(" CMD", pkt->buf32[0]);
+
+    // one has to be careful dealing with these, as they share memory
+    HF2_Command *cmd = &pkt->cmd;
+    HF2_Response *resp = &pkt->resp;
+
+    uint32_t cmdId = cmd->command_id;
+    resp->tag = cmd->tag;
+    resp->status16 = HF2_STATUS_OK;
+
+#define checkDataSize(str, add) assert(sz == 8 + sizeof(cmd->str) + (add))
+
+    switch (cmdId) {
+    case HF2_CMD_INFO:
+        tmp = strlen(infoUf2File);
+        memcpy(pkt->resp.data8, infoUf2File, tmp);
+        send_hf2_response(pkt, tmp);
+        return;
+
+    case HF2_CMD_BININFO:
+        resp->bininfo.mode = HF2_MODE_BOOTLOADER;
+        resp->bininfo.flash_page_size = FLASH_ROW_SIZE;
+        resp->bininfo.flash_num_pages = FLASH_SIZE / FLASH_ROW_SIZE;
+        resp->bininfo.max_message_size = sizeof(pkt->buf);
+        resp->bininfo.uf2_family = UF2_FAMILY;
+        send_hf2_response(pkt, sizeof(resp->bininfo));
+        return;
+
+    case HF2_CMD_RESET_INTO_APP:
+        resetIntoApp();
+        break;
+    case HF2_CMD_RESET_INTO_BOOTLOADER:
+        resetIntoBootloader();
+        break;
+    case HF2_CMD_START_FLASH:
+        // userspace app should reboot into bootloader on this command; we just ignore it
+        // userspace can also call hf2_handover() here
+        break;
+    case HF2_CMD_WRITE_FLASH_PAGE:
+        checkDataSize(write_flash_page, FLASH_ROW_SIZE);
+        // first send ACK and then start writing, while getting the next packet
+        send_hf2_response(pkt, 0);
+        if (cmd->write_flash_page.target_addr >= APP_START_ADDRESS) {
+            flash_write_row((void *)cmd->write_flash_page.target_addr, cmd->write_flash_page.data);
+        }
+        return;
+#if USE_HID_EXT
+    case HF2_CMD_WRITE_WORDS:
+        checkDataSize(write_words, cmd->write_words.num_words << 2);
+        copy_words((void *)cmd->write_words.target_addr, cmd->write_words.words,
+                   cmd->write_words.num_words);
+        break;
+    case HF2_CMD_READ_WORDS:
+        checkDataSize(read_words, 0);
+        tmp = cmd->read_words.num_words;
+        copy_words(resp->data32, (void *)cmd->read_words.target_addr, tmp);
+        send_hf2_response(pkt, tmp << 2);
+        return;
+#endif
+    case HF2_CMD_CHKSUM_PAGES:
+        checkDataSize(chksum_pages, 0);
+        checksum_pages(pkt, cmd->chksum_pages.target_addr, cmd->chksum_pages.num_pages);
+        return;
+
+    default:
+        // command not understood
+        resp->status16 = HF2_STATUS_INVALID_CMD;
+        break;
+    }
+
+    send_hf2_response(pkt, 0);
+}
+
+#if USE_HID
+static HID_InBuffer hidbufData;
+#endif
+
+#if USE_WEBUSB
+static HID_InBuffer webbufData;
+#endif
+
+void process_hid() {
+#if USE_HID
+    hidbufData.ep = USB_EP_HID;
+    process_core(&hidbufData);
+#endif
+#if USE_WEBUSB
+    webbufData.ep = USB_EP_WEB;
+    process_core(&webbufData);
+#endif
+}
+
+#if USE_HID_HANDOVER
+void hidHandoverLoop(int ep) {
+    handoverPrep();
+    HID_InBuffer buf = {0};
+    buf.ep = ep;
+    while (1) {
+        process_core(&buf);
+    }
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/uf2-samdx1/src/images.c b/uf2-samdx1/src/images.c
new file mode 100644
index 00000000..ad25a816
--- /dev/null
+++ b/uf2-samdx1/src/images.c
@@ -0,0 +1,118 @@
+#include <stdint.h>
+
+// all https://makecode.com/_VrfEKzV4xfvq
+
+// https://makecode.com/_7VxXm3JMPXfM - file
+// https://makecode.com/_LuEUCsPEKUbs - download
+const uint8_t fileLogo[] = {
+32, 32, 71, 140, 201, 151, 1, 2, 146, 1, 2, 146, 63, 2, 151, 9, 153, 9, 153, 9, 146, 1, 9, 146, 3, 9, 146, 7, 9, 137, 205, 72, 140, 206, 36, 139, 207, 18, 138, 206, 36, 139, 205, 72, 149, 7, 9, 146, 3, 9, 146, 1, 9, 153, 9, 153, 9, 153, 9, 148, 63, 2, 146, 1, 2, 146, 1, 2, 146, 201, 191, 191, 191, 174
+};
+
+// https://makecode.com/_9b0RcK5yRa12
+const uint8_t pendriveLogo[] = {
+32, 32, 59, 137, 215, 137, 1, 143, 1, 8, 146, 203, 149, 3, 8, 146, 3, 8, 146, 115, 8, 146, 115, 8, 146, 3, 8, 146, 3, 8, 146, 115, 8, 146, 115, 8, 146, 3, 8, 146, 3, 8, 146, 203, 149, 1, 8, 146, 1, 8, 146, 1, 120, 211, 191, 191, 191, 191, 191, 191, 191, 135
+};
+
+// https://makecode.com/_TTqbj705L4mr
+const uint8_t arrowLogo[] = {
+32, 32, 54, 137, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 146, 211, 142, 209, 144, 207, 146, 205, 148, 203, 150, 201, 152, 199, 154, 31, 154, 7, 154, 1, 191, 191, 191, 175
+};
+
+const uint8_t font8[] = {
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x5e, 0x00, 0x00, 0x00, 
+0x00, 0x0e, 0x00, 0x0e, 0x00, 0x00, 
+0x28, 0xfe, 0x28, 0xfe, 0x28, 0x00, 
+0x4c, 0x92, 0xff, 0x92, 0x64, 0x00, 
+0x02, 0x65, 0x12, 0x48, 0xa6, 0x40, 
+0x6c, 0x92, 0x92, 0x6c, 0xa0, 0x00, 
+0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x7c, 0x82, 0x00, 0x00, 
+0x00, 0x00, 0x82, 0x7c, 0x00, 0x00, 
+0x54, 0x38, 0x10, 0x38, 0x54, 0x00, 
+0x10, 0x10, 0x7c, 0x10, 0x10, 0x00, 
+0x00, 0x00, 0x90, 0x70, 0x00, 0x00, 
+0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 
+0x00, 0x00, 0x60, 0x60, 0x00, 0x00, 
+0x00, 0x60, 0x10, 0x08, 0x06, 0x00, 
+0x00, 0x3c, 0x42, 0x42, 0x3c, 0x00, 
+0x00, 0x44, 0x7e, 0x40, 0x00, 0x00, 
+0x00, 0x44, 0x62, 0x52, 0x4c, 0x00, 
+0x00, 0x42, 0x4a, 0x4e, 0x32, 0x00, 
+0x30, 0x28, 0x24, 0x7e, 0x20, 0x00, 
+0x00, 0x4e, 0x4a, 0x4a, 0x32, 0x00, 
+0x00, 0x3c, 0x4a, 0x4a, 0x30, 0x00, 
+0x00, 0x02, 0x62, 0x12, 0x0e, 0x00, 
+0x00, 0x34, 0x4a, 0x4a, 0x34, 0x00, 
+0x00, 0x0c, 0x52, 0x52, 0x3c, 0x00, 
+0x00, 0x00, 0x6c, 0x6c, 0x00, 0x00, 
+0x00, 0x00, 0x96, 0x76, 0x00, 0x00, 
+0x10, 0x28, 0x28, 0x44, 0x44, 0x00, 
+0x28, 0x28, 0x28, 0x28, 0x28, 0x00, 
+0x44, 0x44, 0x28, 0x28, 0x10, 0x00, 
+0x00, 0x02, 0x59, 0x09, 0x06, 0x00, 
+0x3c, 0x42, 0x5a, 0x56, 0x08, 0x00, 
+0x78, 0x14, 0x12, 0x14, 0x78, 0x00, 
+0x7e, 0x4a, 0x4a, 0x4a, 0x34, 0x00, 
+0x00, 0x3c, 0x42, 0x42, 0x24, 0x00, 
+0x00, 0x7e, 0x42, 0x42, 0x3c, 0x00, 
+0x00, 0x7e, 0x4a, 0x4a, 0x42, 0x00, 
+0x00, 0x7e, 0x0a, 0x0a, 0x02, 0x00, 
+0x00, 0x3c, 0x42, 0x52, 0x34, 0x00, 
+0x00, 0x7e, 0x08, 0x08, 0x7e, 0x00, 
+0x00, 0x42, 0x7e, 0x42, 0x00, 0x00, 
+0x20, 0x40, 0x42, 0x3e, 0x02, 0x00, 
+0x00, 0x7e, 0x08, 0x14, 0x62, 0x00, 
+0x00, 0x7e, 0x40, 0x40, 0x40, 0x00, 
+0x7e, 0x04, 0x18, 0x04, 0x7e, 0x00, 
+0x00, 0x7e, 0x04, 0x08, 0x7e, 0x00, 
+0x3c, 0x42, 0x42, 0x42, 0x3c, 0x00, 
+0x00, 0x7e, 0x12, 0x12, 0x0c, 0x00, 
+0x00, 0x3c, 0x52, 0x62, 0xbc, 0x00, 
+0x00, 0x7e, 0x12, 0x12, 0x6c, 0x00, 
+0x00, 0x24, 0x4a, 0x52, 0x24, 0x00, 
+0x02, 0x02, 0x7e, 0x02, 0x02, 0x00, 
+0x00, 0x3e, 0x40, 0x40, 0x3e, 0x00, 
+0x00, 0x1e, 0x70, 0x70, 0x1e, 0x00, 
+0x7e, 0x20, 0x18, 0x20, 0x7e, 0x00, 
+0x42, 0x24, 0x18, 0x24, 0x42, 0x00, 
+0x06, 0x08, 0x70, 0x08, 0x06, 0x00, 
+0x00, 0x62, 0x52, 0x4a, 0x46, 0x00, 
+0x00, 0x7e, 0x42, 0x42, 0x00, 0x00, 
+0x00, 0x06, 0x08, 0x10, 0x60, 0x00, 
+0x00, 0x42, 0x42, 0x7e, 0x00, 0x00, 
+0x08, 0x04, 0x02, 0x04, 0x08, 0x00, 
+0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 
+0x00, 0x00, 0x02, 0x04, 0x00, 0x00, 
+0x00, 0x30, 0x48, 0x48, 0x78, 0x00, 
+0x00, 0x7e, 0x48, 0x48, 0x30, 0x00, 
+0x00, 0x30, 0x48, 0x48, 0x48, 0x00, 
+0x00, 0x30, 0x48, 0x48, 0x7e, 0x00, 
+0x00, 0x30, 0x68, 0x58, 0x50, 0x00, 
+0x00, 0x10, 0x7c, 0x12, 0x04, 0x00, 
+0x00, 0x18, 0xa4, 0xa4, 0x78, 0x00, 
+0x00, 0x7e, 0x08, 0x08, 0x70, 0x00, 
+0x00, 0x48, 0x7a, 0x40, 0x00, 0x00, 
+0x00, 0x40, 0x84, 0x7d, 0x00, 0x00, 
+0x00, 0x7e, 0x10, 0x28, 0x40, 0x00, 
+0x00, 0x42, 0x7e, 0x40, 0x00, 0x00, 
+0x78, 0x08, 0x30, 0x08, 0x70, 0x00, 
+0x00, 0x78, 0x08, 0x08, 0x70, 0x00, 
+0x00, 0x30, 0x48, 0x48, 0x30, 0x00, 
+0x00, 0xfc, 0x24, 0x24, 0x18, 0x00, 
+0x00, 0x18, 0x24, 0x24, 0xfc, 0x00, 
+0x00, 0x78, 0x10, 0x08, 0x10, 0x00, 
+0x00, 0x50, 0x58, 0x68, 0x28, 0x00, 
+0x00, 0x08, 0x3e, 0x48, 0x20, 0x00, 
+0x00, 0x38, 0x40, 0x40, 0x78, 0x00, 
+0x00, 0x18, 0x60, 0x60, 0x18, 0x00, 
+0x38, 0x40, 0x30, 0x40, 0x38, 0x00, 
+0x00, 0x48, 0x30, 0x30, 0x48, 0x00, 
+0x00, 0x5c, 0xa0, 0xa0, 0x7c, 0x00, 
+0x00, 0x48, 0x68, 0x58, 0x48, 0x00, 
+0x00, 0x08, 0x36, 0x41, 0x00, 0x00, 
+0x00, 0x00, 0xfe, 0x00, 0x00, 0x00, 
+0x00, 0x41, 0x36, 0x08, 0x00, 0x00, 
+0x00, 0x08, 0x04, 0x08, 0x04, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+};
diff --git a/uf2-samdx1/src/init_samd21.c b/uf2-samdx1/src/init_samd21.c
new file mode 100644
index 00000000..a77e7e99
--- /dev/null
+++ b/uf2-samdx1/src/init_samd21.c
@@ -0,0 +1,120 @@
+#include "uf2.h"
+#define SYSCTRL_FUSES_OSC32K_CAL_ADDR   (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_OSC32K_CAL_Pos   6
+#define 	SYSCTRL_FUSES_OSC32K_ADDR   SYSCTRL_FUSES_OSC32K_CAL_ADDR
+#define 	SYSCTRL_FUSES_OSC32K_Pos   SYSCTRL_FUSES_OSC32K_CAL_Pos
+#define 	SYSCTRL_FUSES_OSC32K_Msk   (0x7Fu << SYSCTRL_FUSES_OSC32K_Pos)
+
+volatile bool g_interrupt_enabled = true;
+
+// SAMD21 starts at 1MHz by default.
+uint32_t current_cpu_frequency_MHz = 1;
+
+static void gclk_sync(void) {
+    while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY)
+        ;
+}
+
+static void dfll_sync(void) {
+    while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0)
+        ;
+}
+
+#define NVM_SW_CALIB_DFLL48M_COARSE_VAL   58
+#define NVM_SW_CALIB_DFLL48M_FINE_VAL     64
+
+
+void system_init(void) {
+
+  NVMCTRL->CTRLB.bit.RWS = 1;
+
+#if defined(CRYSTALLESS)
+  // Turn on DFLL with USB correction and sync to internal 8 mhz oscillator
+  SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
+  dfll_sync();
+
+  SYSCTRL_DFLLVAL_Type dfllval_conf = {0};
+  uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+		       + (NVM_SW_CALIB_DFLL48M_COARSE_VAL / 32))
+		     >> (NVM_SW_CALIB_DFLL48M_COARSE_VAL % 32))
+    & ((1 << 6) - 1);
+  if (coarse == 0x3f) {
+    coarse = 0x1f;
+  }
+  dfllval_conf.bit.COARSE  = coarse;
+  // TODO(tannewt): Load this from a well known flash location so that it can be
+  // calibrated during testing.
+  dfllval_conf.bit.FINE    = 0x1ff;
+
+  SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 0x1f / 4 ) | // Coarse step is 31, half of the max value
+                         SYSCTRL_DFLLMUL_FSTEP( 10 ) |
+                         48000;
+  SYSCTRL->DFLLVAL.reg = dfllval_conf.reg;
+  SYSCTRL->DFLLCTRL.reg = 0;
+  dfll_sync();
+  SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_MODE |
+                          SYSCTRL_DFLLCTRL_CCDIS |
+                          SYSCTRL_DFLLCTRL_USBCRM | /* USB correction */
+                          SYSCTRL_DFLLCTRL_BPLCKC;
+  dfll_sync();
+  SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
+  dfll_sync();
+
+#else
+
+    SYSCTRL->XOSC32K.reg =
+        SYSCTRL_XOSC32K_STARTUP(6) | SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K;
+    SYSCTRL->XOSC32K.bit.ENABLE = 1;
+    while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) == 0)
+        ;
+
+    GCLK->GENDIV.reg = GCLK_GENDIV_ID(1);
+    gclk_sync();
+
+    GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(1) | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_GENEN;
+    gclk_sync();
+
+    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(0) | GCLK_CLKCTRL_GEN_GCLK1 | GCLK_CLKCTRL_CLKEN;
+    gclk_sync();
+
+    SYSCTRL->DFLLCTRL.bit.ONDEMAND = 0;
+    dfll_sync();
+
+    SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(31) | SYSCTRL_DFLLMUL_FSTEP(511) |
+                           SYSCTRL_DFLLMUL_MUL((CPU_FREQUENCY / (32 * 1024)));
+    dfll_sync();
+
+    SYSCTRL->DFLLCTRL.reg |=
+        SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_WAITLOCK | SYSCTRL_DFLLCTRL_QLDIS;
+    dfll_sync();
+
+    SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE;
+
+    while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
+           (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0)
+        ;
+    dfll_sync();
+
+#endif
+
+    // Configure DFLL48M as source for GCLK_GEN 0
+    GCLK->GENDIV.reg = GCLK_GENDIV_ID(0);
+    gclk_sync();
+
+    // Add GCLK_GENCTRL_OE below to output GCLK0 on the SWCLK pin.
+    GCLK->GENCTRL.reg =
+        GCLK_GENCTRL_ID(0) | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_IDC | GCLK_GENCTRL_GENEN;
+    gclk_sync();
+
+    SysTick_Config(1000);
+
+    // Uncomment these two lines to output GCLK0 on the SWCLK pin.
+    // PORT->Group[0].PINCFG[30].bit.PMUXEN = 1;
+    // Set the port mux mask for odd processor pin numbers, PA30 = 30 is even number, PMUXE = PMUX Even
+    // PORT->Group[0].PMUX[30 / 2].reg |= PORT_PMUX_PMUXE_H;
+
+    current_cpu_frequency_MHz = 48;
+
+}
+
+void SysTick_Handler(void) { LED_TICK(); }
diff --git a/uf2-samdx1/src/init_samd51.c b/uf2-samdx1/src/init_samd51.c
new file mode 100644
index 00000000..a4525ffc
--- /dev/null
+++ b/uf2-samdx1/src/init_samd51.c
@@ -0,0 +1,89 @@
+#include "uf2.h"
+
+// SAMD51 starts at 48MHz by default.
+uint32_t current_cpu_frequency_MHz = 48;
+
+void system_init(void) {
+    // Automatic wait states.
+    NVMCTRL->CTRLA.bit.AUTOWS = 1;
+
+    // Output GCLK0 to Metro M4 D5. This way we can see if/when we mess it up.
+    // PORT->Group[1].PINCFG[14].bit.PMUXEN = true;
+    // PORT->Group[1].PMUX[7].bit.PMUXE = 12;
+
+    /* Software reset the module to ensure it is re-initialized correctly */
+    /* Note: Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
+     * CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete
+     */
+    GCLK->CTRLA.bit.SWRST = 1;
+    while (GCLK->SYNCBUSY.bit.SWRST) {
+        /* wait for reset to complete */
+    }
+
+    // Temporarily switch the CPU to the internal 32k oscillator while we
+    // reconfigure the DFLL.
+    GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) |
+                           GCLK_GENCTRL_OE |
+                           GCLK_GENCTRL_GENEN;
+
+    while (GCLK->SYNCBUSY.bit.GENCTRL0) {
+        /* Wait for synchronization */
+    }
+
+    // Configure the DFLL for USB clock recovery.
+    OSCCTRL->DFLLCTRLA.reg = 0;
+
+    OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_CSTEP( 0x1 ) |
+                           OSCCTRL_DFLLMUL_FSTEP( 0x1 ) |
+                           OSCCTRL_DFLLMUL_MUL( 0xBB80 );
+
+    while (OSCCTRL->DFLLSYNC.bit.DFLLMUL) {
+        /* Wait for synchronization */
+    }
+
+    OSCCTRL->DFLLCTRLB.reg = 0;
+    while (OSCCTRL->DFLLSYNC.bit.DFLLCTRLB) {
+        /* Wait for synchronization */
+    }
+
+    OSCCTRL->DFLLCTRLA.bit.ENABLE = true;
+    while (OSCCTRL->DFLLSYNC.bit.ENABLE) {
+        /* Wait for synchronization */
+    }
+
+    OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg;
+    while(OSCCTRL->DFLLSYNC.bit.DFLLVAL ) {}
+
+    OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_WAITLOCK |
+    OSCCTRL_DFLLCTRLB_CCDIS | OSCCTRL_DFLLCTRLB_USBCRM ;
+
+    while (!OSCCTRL->STATUS.bit.DFLLRDY) {
+        /* Wait for synchronization */
+    }
+
+    // 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
+    GCLK->GENCTRL[0].reg =
+        GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL) |
+                         GCLK_GENCTRL_IDC |
+                         GCLK_GENCTRL_OE |
+                         GCLK_GENCTRL_GENEN;
+
+    while (GCLK->SYNCBUSY.bit.GENCTRL0) {
+      /* Wait for synchronization */
+    }
+
+    /* Turn on the digital interface clock */
+    //MCLK->APBAMASK.reg |= MCLK_APBAMASK_GCLK;
+
+    /*
+     * Now that all system clocks are configured, we can set CLKDIV .
+     * These values are normally the ones present after Reset.
+     */
+    MCLK->CPUDIV.reg = MCLK_CPUDIV_DIV_DIV1;
+
+    SysTick_Config(1000);
+    // No change from initial frequency.
+    // current_cpu_frequency_MHz = 48;
+}
+
+void SysTick_Handler(void) { LED_TICK(); }
diff --git a/uf2-samdx1/src/main.c b/uf2-samdx1/src/main.c
new file mode 100644
index 00000000..3721fdd9
--- /dev/null
+++ b/uf2-samdx1/src/main.c
@@ -0,0 +1,371 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * --------------------
+ * SAM-BA Implementation on SAMD21 and SAMD51
+ * --------------------
+ * Requirements to use SAM-BA :
+ *
+ * Supported communication interfaces (SAMD21):
+ * --------------------
+ *
+ * SERCOM5 : RX:PB23 TX:PB22
+ * Baudrate : 115200 8N1
+ *
+ * USB : D-:PA24 D+:PA25
+ *
+ * Pins Usage
+ * --------------------
+ * The following pins are used by the program :
+ * PA25 : input/output
+ * PA24 : input/output
+ * PB23 : input
+ * PB22 : output
+ * PA15 : input
+ *
+ * The application board shall avoid driving the PA25,PA24,PB23,PB22 and PA15
+ * signals
+ * while the boot program is running (after a POR for example)
+ *
+ * Clock system
+ * --------------------
+ * CPU clock source (GCLK_GEN_0) - 48MHz DFLL oscillator (DFLL48M)
+ * SERCOM5 core GCLK source (GCLK_ID_SERCOM5_CORE) - GCLK_GEN_0 (i.e., FDLL48M)
+ * USB GCLK source (GCLK_ID_USB) - GCLK_GEN_0 (i.e., DFLL in CRM or open loop mode)
+ *
+ * Crystalless mode:
+ * GCLK Generator 0 source (GCLK_GEN_0) - 48MHz DFLL in Clock Recovery mode
+ * (DFLL48M)
+ *
+ * Crytal mode:
+ * GCLK Generator 0 source (GCLK_GEN_0) - 48MHz DFLL in closed loop mode
+ * GCLK Generator 1 source (GCLK_GEN_1) - 32 kHz external cyrstal (XOSC32K)
+ * DFLL48M Refence clock (GCLK_DFLL48M_REF) - GCLK_GEN_1 (i.e., XOSC32K)
+ *
+ * Memory Mapping
+ * --------------------
+ * SAM-BA code will be located at 0x0 and executed before any applicative code.
+ *
+ * Applications compiled to be executed along with the bootloader will start at
+ * 0x2000 (samd21) or 0x4000 (samd51)
+ *
+ */
+
+#include "uf2.h"
+
+static void check_start_application(void);
+
+static volatile bool main_b_cdc_enable = false;
+extern int8_t led_tick_step;
+
+#if defined(SAMD21)
+    #define RESET_CONTROLLER PM
+#elif defined(SAMD51)
+    #define RESET_CONTROLLER RSTC
+#endif
+
+/**
+ * \brief Check the application startup condition
+ *
+ */
+static void check_start_application(void) {
+    uint32_t app_start_address;
+
+    /* Load the Reset Handler address of the application */
+    app_start_address = *(uint32_t *)(APP_START_ADDRESS + 4);
+
+    /**
+     * Test reset vector of application @APP_START_ADDRESS+4
+     * Sanity check on the Reset_Handler address
+     */
+    if (app_start_address < APP_START_ADDRESS || app_start_address > FLASH_SIZE) {
+        /* Stay in bootloader */
+        return;
+    }
+
+#if USE_SINGLE_RESET
+    if (SINGLE_RESET()) {
+        if (RESET_CONTROLLER->RCAUSE.bit.POR || *DBL_TAP_PTR != DBL_TAP_MAGIC_QUICK_BOOT) {
+            // the second tap on reset will go into app
+            *DBL_TAP_PTR = DBL_TAP_MAGIC_QUICK_BOOT;
+            // this will be cleared after successful USB enumeration
+            // this is around 1.5s
+            resetHorizon = timerHigh + 50;
+            return;
+        }
+    }
+#endif
+
+    if (RESET_CONTROLLER->RCAUSE.bit.POR) {
+        *DBL_TAP_PTR = 0;
+    }
+    else if (*DBL_TAP_PTR == DBL_TAP_MAGIC) {
+        *DBL_TAP_PTR = 0;
+        return; // stay in bootloader
+    }
+    else {
+        if (*DBL_TAP_PTR != DBL_TAP_MAGIC_QUICK_BOOT) {
+            *DBL_TAP_PTR = DBL_TAP_MAGIC;
+            delay(500);
+        }
+        *DBL_TAP_PTR = 0;
+    }
+
+    LED_MSC_OFF();
+
+#if defined(BOARD_RGBLED_CLOCK_PIN)
+    // This won't work for neopixel, because we're running at 1MHz or thereabouts...
+    RGBLED_set_color(COLOR_LEAVE);
+#endif
+
+    /* Rebase the Stack Pointer */
+    __set_MSP(*(uint32_t *)APP_START_ADDRESS);
+
+    /* Rebase the vector table base address */
+    SCB->VTOR = ((uint32_t)APP_START_ADDRESS & SCB_VTOR_TBLOFF_Msk);
+
+    /* Jump to application Reset Handler in the application */
+    asm("bx %0" ::"r"(app_start_address));
+}
+
+extern char _etext;
+extern char _end;
+
+/**
+ *  \brief  SAM-BA Main loop.
+ *  \return Unused (ANSI-C compatibility).
+ */
+int main(void) {
+    // if VTOR is set, we're not running in bootloader mode; halt
+    if (SCB->VTOR)
+        while (1) {
+        }
+
+#if defined(SAMD21)
+    // Check for voltage too low, and set up brownout protection.
+    // Code largely taken from https://blog.thea.codes/sam-d21-brown-out-detector/ (thanks!)
+
+    // Disable the brown-out detector during configuration, otherwise
+    // it might misbehave and reset the microcontroller.
+    SYSCTRL->BOD33.bit.ENABLE = 0;
+    while (!SYSCTRL->PCLKSR.bit.B33SRDY) {};
+
+    // Configure the brown-out detector so that the program can use it to watch the power supply voltage.
+    SYSCTRL->BOD33.reg = (
+        // This sets the minimum voltage level to about 2.9V. See datasheet table 37-21.
+        // Voltage threshold is about 1.5V + LEVEL * 34mV. See "Electrical Characteristics" in datasheet.
+        // 39 is about 2.8V, and is a standard measured value in the datasheet.
+        // External flash chips usually require at least 2.7V.
+        SYSCTRL_BOD33_LEVEL(39) |
+        // Since the program is waiting for the voltage to rise,
+        // don't reset the microcontroller if the voltage is too low.
+        SYSCTRL_BOD33_ACTION_NONE |
+        // Enable hysteresis to better deal with noisy power supplies and voltage transients.
+        SYSCTRL_BOD33_HYST);
+
+    // Enable the brown-out detector and then wait for the voltage level to settle.
+    SYSCTRL->BOD33.bit.ENABLE = 1;
+    while (!SYSCTRL->PCLKSR.bit.BOD33RDY) {}
+
+    // BOD33DET is set when the voltage is *too low*, so wait for it to be cleared.
+    while (SYSCTRL->PCLKSR.bit.BOD33DET) {}
+
+    // Let the brown-out detector automatically reset the microcontroller if the voltage drops too low.
+    SYSCTRL->BOD33.bit.ENABLE = 0;
+    while (!SYSCTRL->PCLKSR.bit.B33SRDY) {};
+
+    SYSCTRL->BOD33.reg |= SYSCTRL_BOD33_ACTION_RESET;
+    SYSCTRL->BOD33.bit.ENABLE = 1;
+
+    // If fuses have been reset to all ones, the watchdog ALWAYS-ON is
+    // set, so we can't turn off the watchdog.  Set the fuse to a
+    // reasonable value and reset. This is a mini version of the fuse
+    // reset code in selfmain.c.
+    if (((uint32_t *)NVMCTRL_AUX0_ADDRESS)[0] == 0xffffffff) {
+        // Clear any error flags.
+        NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+        // Turn off cache and put in manual mode.
+        NVMCTRL->CTRLB.reg = NVMCTRL->CTRLB.reg | NVMCTRL_CTRLB_CACHEDIS | NVMCTRL_CTRLB_MANW;
+        // Set address to write.
+        NVMCTRL->ADDR.reg = NVMCTRL_AUX0_ADDRESS / 2;
+        // Erase auxiliary row.
+        NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_EAR;
+	while (!(NVMCTRL->INTFLAG.bit.READY)) {}
+        // Clear page buffer.
+        NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC;
+	while (!(NVMCTRL->INTFLAG.bit.READY)) {}
+        // Reasonable fuse values, including 8k BOOTPROT.
+        ((uint32_t *)NVMCTRL_AUX0_ADDRESS)[0] = 0xD8E0C7FA;
+        ((uint32_t *)NVMCTRL_AUX0_ADDRESS)[1] = 0xFFFFFC5D;
+        // Write the fuses
+	NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WAP;
+	while (!(NVMCTRL->INTFLAG.bit.READY)) {}
+        resetIntoBootloader();
+    }
+
+    // Disable the watchdog, in case the application set it.
+    WDT->CTRL.reg = 0;
+    while(WDT->STATUS.bit.SYNCBUSY) {}
+
+#elif defined(SAMD51)
+    // Disable the watchdog, in case the application set it.
+    WDT->CTRLA.reg = 0;
+    while(WDT->SYNCBUSY.reg) {}
+
+    // Enable 2.7V brownout detection. The default fuse value is 1.7
+    // Set brownout detection to ~2.7V. Default from factory is 1.7V,
+    // which is too low for proper operation of external SPI flash chips (they are 2.7-3.6V).
+    // Also without this higher level, the SAMD51 will write zeros to flash intermittently.
+    // Disable while changing level.
+
+    SUPC->BOD33.bit.ENABLE = 0;
+    while (!SUPC->STATUS.bit.B33SRDY) {}  // Wait for BOD33 to synchronize.
+    SUPC->BOD33.bit.LEVEL = 200;  // 2.7V: 1.5V + LEVEL * 6mV.
+    // Don't reset right now.
+    SUPC->BOD33.bit.ACTION = SUPC_BOD33_ACTION_NONE_Val;
+    SUPC->BOD33.bit.RUNSTDBY = 1;
+    SUPC->BOD33.bit.ENABLE = 1; // enable brown-out detection
+
+    // Wait for BOD33 peripheral to be ready.
+    while (!SUPC->STATUS.bit.BOD33RDY) {}
+
+    // Wait for voltage to rise above BOD33 value.
+    while (SUPC->STATUS.bit.BOD33DET) {}
+
+    // If we are starting from a power-on or a brownout,
+    // wait for the voltage to stabilize. Don't do this on an
+    // external reset because it interferes with the timing of double-click.
+    // "BODVDD" means BOD33.
+    if (RSTC->RCAUSE.bit.POR || RSTC->RCAUSE.bit.BODVDD) {
+        do {
+            // Check again in 100ms.
+            delay(100);
+        } while (SUPC->STATUS.bit.BOD33DET);
+    }
+
+    // Now enable reset if voltage falls below minimum.
+    SUPC->BOD33.bit.ENABLE = 0;
+    while (!SUPC->STATUS.bit.B33SRDY) {}  // Wait for BOD33 to synchronize.
+    SUPC->BOD33.bit.ACTION = SUPC_BOD33_ACTION_RESET_Val;
+    SUPC->BOD33.bit.ENABLE = 1;
+#endif
+
+#if USB_VID == 0x239a && USB_PID == 0x0013     // Adafruit Metro M0
+    // Delay a bit so SWD programmer can have time to attach.
+    delay(15);
+#endif
+    led_init();
+
+    logmsg("Start");
+    assert((uint32_t)&_etext < APP_START_ADDRESS);
+    // bossac writes at 0x20005000
+    assert(!USE_MONITOR || (uint32_t)&_end < 0x20005000);
+
+    assert(8 << NVMCTRL->PARAM.bit.PSZ == FLASH_PAGE_SIZE);
+    assert(FLASH_PAGE_SIZE * NVMCTRL->PARAM.bit.NVMP == FLASH_SIZE);
+
+    /* Jump in application if condition is satisfied */
+    check_start_application();
+
+    /* We have determined we should stay in the monitor. */
+    /* System initialization */
+    system_init();
+
+    __DMB();
+    __enable_irq();
+
+#if USE_UART
+    /* UART is enabled in all cases */
+    usart_open();
+#endif
+
+    logmsg("Before main loop");
+
+    usb_init();
+
+    // not enumerated yet
+    RGBLED_set_color(COLOR_START);
+    led_tick_step = 10;
+
+    /* Wait for a complete enum on usb or a '#' char on serial line */
+    while (1) {
+        if (USB_Ok()) {
+            if (!main_b_cdc_enable) {
+#if USE_SINGLE_RESET
+                // this might have been set
+                resetHorizon = 0;
+#endif
+                RGBLED_set_color(COLOR_USB);
+                led_tick_step = 1;
+
+#if USE_SCREEN
+                screen_init();
+                draw_drag();
+#endif
+            }
+
+            main_b_cdc_enable = true;
+        }
+
+#if USE_MONITOR
+        // Check if a USB enumeration has succeeded
+        // And com port was opened
+        if (main_b_cdc_enable) {
+            logmsg("entering monitor loop");
+            // SAM-BA on USB loop
+            while (1) {
+                sam_ba_monitor_run();
+            }
+        }
+#if USE_UART
+        /* Check if a '#' has been received */
+        if (!main_b_cdc_enable && usart_sharp_received()) {
+            RGBLED_set_color(COLOR_UART);
+            sam_ba_monitor_init(SAM_BA_INTERFACE_USART);
+            /* SAM-BA on UART loop */
+            while (1) {
+                sam_ba_monitor_run();
+            }
+        }
+#endif
+#else // no monitor
+        if (main_b_cdc_enable) {
+            process_msc();
+        }
+#endif
+
+        if (!main_b_cdc_enable) {
+            // get more predictable timings before the USB is enumerated
+            for (int i = 1; i < 256; ++i) {
+                asm("nop");
+            }
+        }
+    }
+}
diff --git a/uf2-samdx1/src/msc.c b/uf2-samdx1/src/msc.c
new file mode 100644
index 00000000..36229788
--- /dev/null
+++ b/uf2-samdx1/src/msc.c
@@ -0,0 +1,897 @@
+/**
+ * \file
+ *
+ * \brief USB Device Mass Storage Class (MSC) interface.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+#define DEFINE_CONFIG_DATA 1
+
+#include "uf2.h"
+
+#include "lib/usb_msc/sbc_protocol.h"
+#include "lib/usb_msc/spc_protocol.h"
+#include "lib/usb_msc/usb_protocol.h"
+#include "lib/usb_msc/usb_protocol_msc.h"
+
+#if !USE_DBG_MSC
+#undef logmsg
+#undef logval
+#define logmsg(...) NOOP
+#define logval(...) NOOP
+#endif
+
+// From sam0/utils/compiler.h in ASF3
+#define  le32_to_cpu(x) (x)
+#define  cpu_to_le32(x) (x)
+#define  CPU_TO_BE32(x) ((uint32_t)__builtin_bswap32((uint32_t)(x)))
+#define  cpu_to_be16(x) ((uint16_t)(((uint16_t)(x) >> 8) |\
+                           ((uint16_t)(x) << 8)))
+
+#define MSB3(u32)   (((uint8_t  *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
+#define MSB2(u32)   (((uint8_t  *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB1(u32)   (((uint8_t  *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB0(u32)   (((uint8_t  *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
+
+#define  MSB(u16)   (((uint8_t  *)&(u16))[1]) //!< Most significant byte of \a u16.
+#define  LSB(u16)   (((uint8_t  *)&(u16))[0]) //!< Least significant byte of \a u16.
+
+bool mscReset = false;
+//! True when an invalid command with nonzero residue has stalled a bulk endpoint
+//! and the CSW must be sent later; the stall may be on Bulk-IN or Bulk-OUT
+//! depending on the CBW direction.
+static bool udi_msc_csw_pending;
+
+void msc_reset(void) {
+    mscReset = true;
+    udi_msc_csw_pending = false;
+    reset_ep(USB_EP_MSC_IN);
+    reset_ep(USB_EP_MSC_OUT);
+}
+
+//! Structure to receive a CBW packet
+static struct usb_msc_cbw udi_msc_cbw;
+//! Structure to send a CSW packet
+static struct usb_msc_csw udi_msc_csw = {.dCSWSignature = CPU_TO_BE32(USB_CSW_SIGNATURE)};
+//! Structure with current SCSI sense data
+static struct scsi_request_sense_data udi_msc_sense;
+
+#if USE_MSC_CHECKS
+/**
+ * \brief Stall CBW request
+ */
+static void udi_msc_cbw_invalid(void);
+
+/**
+ * \brief Stall CSW request
+ */
+static void udi_msc_csw_invalid(void);
+#endif
+
+/**
+ * \brief Function to check the CBW length and direction
+ * Call it after SCSI command decode to check integrity of command
+ *
+ * \param alloc_len  number of bytes that device want transfer
+ * \param dir_flag   Direction of transfer (USB_CBW_DIRECTION_IN/OUT)
+ *
+ * \retval true if the command can be processed
+ */
+static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag);
+//@}
+
+/**
+ * \name Routines to process small data packet
+ */
+//@{
+
+/**
+ * \brief Sends data on MSC IN endpoint
+ * Called by SCSI command which must send a data to host followed by a CSW
+ *
+ * \param buffer        Internal RAM buffer to send
+ * \param buf_size   Size of buffer to send
+ */
+static void udi_msc_data_send(uint8_t *buffer, uint8_t buf_size);
+
+/**
+ * \name Routines to process CSW packet
+ */
+//@{
+
+/**
+ * \brief Build CSW packet and send it
+ *
+ * Called at the end of SCSI command
+ */
+static void udi_msc_csw_process(void);
+
+/**
+ * \brief Sends CSW
+ *
+ * Called by #udi_msc_csw_process()
+ * or UDD callback when endpoint halt is cleared
+ */
+void udi_msc_csw_send(void);
+static bool udi_msc_csw_ready_to_send(void);
+static void udi_msc_command_invalid(void);
+
+/**
+ * \name Routines manage sense data
+ */
+//@{
+
+/**
+ * \brief Reinitialize sense data.
+ */
+static void udi_msc_clear_sense(void);
+
+/**
+ * \brief Update sense data with new value to signal a fail
+ *
+ * \param sense_key     Sense key
+ * \param add_sense     Additional Sense Code
+ * \param lba           LBA corresponding at error
+ */
+static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense, uint32_t lba);
+
+/**
+ * \brief Update sense data with new value to signal success
+ */
+static void udi_msc_sense_pass(void);
+
+/**
+ * \brief Update sense data to signal a hardware error on memory
+ */
+static void udi_msc_sense_fail_hardware(void);
+
+#if USE_MSC_CHECKS
+/**
+ * \brief Update sense data to signal that CDB fields are not valid
+ */
+static void udi_msc_sense_fail_cdb_invalid(void);
+#endif
+
+/**
+ * \brief Update sense data to signal that command is not supported
+ */
+static void udi_msc_sense_command_invalid(void);
+//@}
+
+/**
+ * \name Routines manage SCSI Commands
+ */
+//@{
+
+/**
+ * \brief Process SPC Request Sense command
+ * Returns error information about last command
+ */
+static void udi_msc_spc_requestsense(void);
+
+/**
+ * \brief Process SPC Inquiry command
+ * Returns information (name,version) about disk
+ */
+static void udi_msc_spc_inquiry(void);
+
+/**
+ * \brief Checks state of disk
+ *
+ * \retval true if disk is ready, otherwise false and updates sense data
+ */
+static bool udi_msc_spc_testunitready_global(void);
+
+/**
+ * \brief Process test unit ready command
+ * Returns state of logical unit
+ */
+static void udi_msc_spc_testunitready(void);
+
+/**
+ * \brief Process prevent allow medium removal command
+ */
+static void udi_msc_spc_prevent_allow_medium_removal(void);
+
+/**
+ * \brief Process mode sense command
+ *
+ * \param b_sense10     Sense10 SCSI command, if true
+ * \param b_sense10     Sense6  SCSI command, if false
+ */
+static void udi_msc_spc_mode_sense(bool b_sense10);
+
+/**
+ * \brief Process start stop command
+ */
+static void udi_msc_sbc_start_stop(void);
+
+/**
+ * \brief Process read capacity command
+ */
+static void udi_msc_sbc_read_capacity(void);
+
+/**
+ * \brief Process read10 or write10 command
+ *
+ * \param b_read     Read transfer, if true,
+ * \param b_read     Write transfer, if false
+ */
+static void udi_msc_sbc_trans(bool b_read);
+
+static void udi_msc_read_format_capacity(void);
+
+void udd_ep_set_halt(uint8_t ep) {
+    stall_ep(ep);
+    reset_ep(ep);
+}
+
+#if USE_MSC_CHECKS
+static void udi_msc_cbw_invalid(void) {
+    logmsg("MSC CBW Invalid; halt");
+    udd_ep_set_halt(USB_EP_MSC_OUT);
+
+    // TODO If stall cleared then re-stall it. Only Setup MSC Reset can clear it
+}
+
+static void udi_msc_csw_invalid(void) {
+    logmsg("MSC CSW Invalid; halt");
+    udd_ep_set_halt(USB_EP_MSC_IN);
+
+    // TODO If stall cleared then re-stall it. Only Setup MSC Reset can clear it
+}
+#endif
+
+bool try_read_cbw(struct usb_msc_cbw *cbw, uint8_t ep, PacketBuffer *handoverCache) {
+    if (!USB_ReadCore(NULL, 1, ep, handoverCache))
+        return false; // no data available
+
+    uint32_t nb_received = USB_ReadCore((void *)cbw, sizeof(*cbw), ep, handoverCache);
+
+#if USE_MSC_CHECKS
+    // Check CBW integrity:
+    // transfer status/CBW length/CBW signature
+    if ((sizeof(*cbw) != nb_received) || (cbw->dCBWSignature != CPU_TO_BE32(USB_CBW_SIGNATURE))) {
+        if (handoverCache)
+            resetIntoBootloader();
+        // (5.2.1) Devices receiving a CBW with an invalid signature should
+        // stall
+        // further traffic on the Bulk In pipe, and either stall further traffic
+        // or accept and discard further traffic on the Bulk Out pipe, until
+        // reset recovery.
+        udi_msc_cbw_invalid();
+        udi_msc_csw_invalid();
+        return false;
+    }
+
+    // in handover mode we don't care about LUN
+    if (handoverCache)
+        return true;
+
+    // Check LUN asked
+    cbw->bCBWLUN &= USB_CBW_LUN_MASK;
+    if (cbw->bCBWLUN > MAX_LUN) {
+        // Bad LUN, then stop command process
+        udi_msc_sense_fail_cdb_invalid();
+        udi_msc_csw_process();
+        return false;
+    }
+#else
+    (void)nb_received;
+#endif
+
+    return true;
+}
+
+void process_msc(void) {
+#if USE_HID || USE_WEBUSB
+    process_hid();
+#endif
+
+    if (udi_msc_csw_pending) {
+        if (!udi_msc_csw_ready_to_send())
+            return;
+        udi_msc_csw_pending = false;
+        udi_msc_csw_process();
+        return;
+    }
+
+    if (!try_read_cbw(&udi_msc_cbw, USB_EP_MSC_OUT, false))
+        return; // no data
+
+    // Prepare CSW residue field with the size requested
+    udi_msc_csw.dCSWDataResidue = le32_to_cpu(udi_msc_cbw.dCBWDataTransferLength);
+
+    // if (SBC_WRITE10 != udi_msc_cbw.CDB[0])
+    //    logval("MSC CMD", udi_msc_cbw.CDB[0]);
+
+    // Decode opcode
+    switch (udi_msc_cbw.CDB[0]) {
+    case SPC_REQUEST_SENSE:
+        udi_msc_spc_requestsense();
+        break;
+
+    case SPC_INQUIRY:
+        udi_msc_spc_inquiry();
+        break;
+
+    case SPC_MODE_SENSE6:
+        udi_msc_spc_mode_sense(false);
+        break;
+    case SPC_MODE_SENSE10:
+        udi_msc_spc_mode_sense(true);
+        break;
+
+    case SPC_TEST_UNIT_READY:
+        udi_msc_spc_testunitready();
+        break;
+
+    case SBC_READ_CAPACITY10:
+        udi_msc_sbc_read_capacity();
+        break;
+
+    case SBC_START_STOP_UNIT:
+        udi_msc_sbc_start_stop();
+        break;
+
+    // Accepts request to support plug/plug in case of card reader
+    case SPC_PREVENT_ALLOW_MEDIUM_REMOVAL:
+        udi_msc_spc_prevent_allow_medium_removal();
+        break;
+
+    // Accepts request to support full format from Windows
+    case SBC_VERIFY10:
+        udi_msc_sense_pass();
+        udi_msc_csw_process();
+        break;
+
+    case SBC_READ10:
+        udi_msc_sbc_trans(true);
+        break;
+
+    case SBC_WRITE10:
+        udi_msc_sbc_trans(false);
+        break;
+
+    case 0x23:
+        udi_msc_read_format_capacity();
+        break;
+
+    default:
+        logval("Invalid MSC command", udi_msc_cbw.CDB[0]);
+        udi_msc_command_invalid();
+        break;
+    }
+}
+
+static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag) {
+/*
+ * The following cases should result in a phase error:
+ *  - Case  2: Hn < Di
+ *  - Case  3: Hn < Do
+ *  - Case  7: Hi < Di
+ *  - Case  8: Hi <> Do
+ *  - Case 10: Ho <> Di
+ *  - Case 13: Ho < Do
+ */
+#if USE_MSC_CHECKS
+    if (((udi_msc_cbw.bmCBWFlags ^ dir_flag) & USB_CBW_DIRECTION_IN) ||
+        (udi_msc_csw.dCSWDataResidue < alloc_len)) {
+        udi_msc_sense_fail_cdb_invalid();
+        udi_msc_csw_process();
+        return false;
+    }
+#endif
+
+    /*
+     * The following cases should result in a stall and nonzero
+     * residue:
+     *  - Case  4: Hi > Dn
+     *  - Case  5: Hi > Di
+     *  - Case  9: Ho > Dn
+     *  - Case 11: Ho > Do
+     */
+    return true;
+}
+
+//---------------------------------------------
+//------- Routines to process small data packet
+
+static void udi_msc_data_send(uint8_t *buffer, uint8_t buf_size) {
+    if (USB_Write((void *)buffer, buf_size, USB_EP_MSC_IN) != buf_size) {
+        // If endpoint not available, then exit process command
+        udi_msc_sense_fail_hardware();
+        udi_msc_csw_process();
+    }
+
+    // Update sense data
+    udi_msc_sense_pass();
+    // Update CSW
+    udi_msc_csw.dCSWDataResidue -= buf_size;
+    udi_msc_csw_process();
+}
+
+//---------------------------------------------
+//------- Routines to process CSW packet
+
+static void udi_msc_csw_process(void) {
+    // Prepare and send CSW
+    udi_msc_csw.dCSWTag = udi_msc_cbw.dCBWTag;
+    udi_msc_csw.dCSWDataResidue = cpu_to_le32(udi_msc_csw.dCSWDataResidue);
+    udi_msc_csw_send();
+}
+
+void udi_msc_csw_send(void) { USB_Write((void *)&udi_msc_csw, sizeof(udi_msc_csw), USB_EP_MSC_IN); }
+
+// CSW is always sent on EP_MSC_IN, but USB_Write is blocking — so for both
+// Hi> and Ho> failures we must defer the CSW until the host has cleared
+// the relevant pipe halt. Otherwise, the main loop is stuck inside USB_Write
+// and we can't process the host's CLEAR_FEATURE SETUP, deadlocking recovery.
+// We check both directions: only one is stalled at a time, but checking both
+// means the predicate doesn't need to know which.
+static bool udi_msc_csw_ready_to_send(void) {
+    return !(USB->DEVICE.DeviceEndpoint[USB_EP_MSC_IN].EPSTATUS.reg &
+             USB_DEVICE_EPSTATUSSET_STALLRQ1) &&
+           !(USB->DEVICE.DeviceEndpoint[USB_EP_MSC_OUT].EPSTATUS.reg &
+             USB_DEVICE_EPSTATUSSET_STALLRQ0);
+}
+
+static void udi_msc_command_invalid(void) {
+    udi_msc_sense_command_invalid();
+
+    if (udi_msc_csw.dCSWDataResidue != 0) {
+        udi_msc_csw_pending = true;
+        udd_ep_set_halt((udi_msc_cbw.bmCBWFlags & USB_CBW_DIRECTION_IN)
+                        ? USB_EP_MSC_IN : USB_EP_MSC_OUT);
+        return;
+    }
+
+    udi_msc_csw_process();
+}
+
+//---------------------------------------------
+//------- Routines manage sense data
+
+static void udi_msc_clear_sense(void) {
+    memset((uint8_t *)&udi_msc_sense, 0, sizeof(struct scsi_request_sense_data));
+    udi_msc_sense.valid_reponse_code = SCSI_SENSE_VALID | SCSI_SENSE_CURRENT;
+    udi_msc_sense.AddSenseLen = SCSI_SENSE_ADDL_LEN(sizeof(udi_msc_sense));
+}
+
+static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense, uint32_t lba) {
+    logval("MSC sense fail", sense_key);
+    udi_msc_clear_sense();
+    udi_msc_csw.bCSWStatus = USB_CSW_STATUS_FAIL;
+    udi_msc_sense.sense_flag_key = sense_key;
+    udi_msc_sense.information[0] = lba >> 24;
+    udi_msc_sense.information[1] = lba >> 16;
+    udi_msc_sense.information[2] = lba >> 8;
+    udi_msc_sense.information[3] = lba;
+    udi_msc_sense.AddSense = add_sense;
+}
+
+static void udi_msc_sense_pass(void) {
+    udi_msc_clear_sense();
+    udi_msc_csw.bCSWStatus = USB_CSW_STATUS_PASS;
+}
+
+static void udi_msc_sense_fail_hardware(void) {
+    udi_msc_sense_fail(SCSI_SK_HARDWARE_ERROR, SCSI_ASC_NO_ADDITIONAL_SENSE_INFO, 0);
+}
+
+#if USE_MSC_CHECKS
+static void udi_msc_sense_fail_cdb_invalid(void) {
+    udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, SCSI_ASC_INVALID_FIELD_IN_CDB, 0);
+}
+#endif
+
+static void udi_msc_sense_command_invalid(void) {
+    udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, SCSI_ASC_INVALID_COMMAND_OPERATION_CODE, 0);
+}
+
+//---------------------------------------------
+//------- Routines manage SCSI Commands
+
+static void udi_msc_spc_requestsense(void) {
+    uint8_t length = udi_msc_cbw.CDB[4];
+
+    // Can't send more than sense data length
+    if (length > sizeof(udi_msc_sense))
+        length = sizeof(udi_msc_sense);
+
+    if (!udi_msc_cbw_validate(length, USB_CBW_DIRECTION_IN))
+        return;
+    // Send sense data
+    udi_msc_data_send((uint8_t *)&udi_msc_sense, length);
+}
+
+static void udi_msc_read_format_capacity(void) {
+    uint8_t buf[12] = {0,
+                       0,
+                       0,
+                       8, // length
+                       (NUM_FAT_BLOCKS >> 24) & 0xFF,
+                       (NUM_FAT_BLOCKS >> 16) & 0xFF,
+                       (NUM_FAT_BLOCKS >> 8) & 0xFF,
+                       (NUM_FAT_BLOCKS >> 0) & 0xFF,
+                       2, // Descriptor Code: Formatted Media
+                       0,
+                       (512 >> 8) & 0xff,
+                       0};
+
+    size_t length = 12;
+
+    if (udi_msc_csw.dCSWDataResidue > length)
+        udi_msc_csw.dCSWDataResidue = length;
+
+    if (!udi_msc_cbw_validate(length, USB_CBW_DIRECTION_IN))
+        return;
+    udi_msc_data_send(buf, length);
+}
+
+static void udi_msc_spc_inquiry(void) {
+    uint8_t length;
+    __attribute__((__aligned__(4)))
+    // Constant inquiry data for all LUNs
+    static struct scsi_inquiry_data udi_msc_inquiry_data = {
+        .pq_pdt = SCSI_INQ_PQ_CONNECTED | SCSI_INQ_DT_DIR_ACCESS,
+        .version = 2, // SCSI_INQ_VER_SPC,
+        .flags1 = SCSI_INQ_RMB,
+        .flags3 = SCSI_INQ_RSP_SPC2,
+        .addl_len = 36 - 4, // SCSI_INQ_ADDL_LEN(sizeof(struct scsi_inquiry_data)),
+        // Linux displays this; Windows shows it in Dev Mgr
+        .vendor_id = "",
+        .product_id = "",
+        .product_rev = {'1', '.', '0', '0'},
+    };
+
+    // we use both product_id and vendor_id fields and hope for the best
+    padded_memcpy(udi_msc_inquiry_data.vendor_id, PRODUCT_NAME, 8 + 16);
+
+    length = udi_msc_cbw.CDB[4];
+
+    // Can't send more than inquiry data length
+    if (length > sizeof(udi_msc_inquiry_data))
+        length = sizeof(udi_msc_inquiry_data);
+
+    if (!udi_msc_cbw_validate(length, USB_CBW_DIRECTION_IN))
+        return;
+
+    /*
+if ((0 != (udi_msc_cbw.CDB[1] & (SCSI_INQ_REQ_EVPD | SCSI_INQ_REQ_CMDT))) ||
+    (0 != udi_msc_cbw.CDB[2])) {
+    logval("unsupp", udi_msc_cbw.CDB[1]);
+    // CMDT and EPVD bits are not at 0
+    // PAGE or OPERATION CODE fields are not empty
+    //  = No standard inquiry asked
+    udi_msc_sense_fail_cdb_invalid(); // Command is unsupported
+    udi_msc_csw_process();
+    return;
+}
+*/
+
+    // logval("Sense Size", length);
+
+    // Send inquiry data
+    udi_msc_data_send((uint8_t *)&udi_msc_inquiry_data, length);
+}
+
+static bool udi_msc_spc_testunitready_global(void) { return true; }
+
+static void udi_msc_spc_testunitready(void) {
+    if (udi_msc_spc_testunitready_global()) {
+        // LUN ready, then update sense data with status pass
+        udi_msc_sense_pass();
+    }
+    // Send status in CSW packet
+    udi_msc_csw_process();
+}
+
+static void udi_msc_spc_mode_sense(bool b_sense10) {
+    // Union of all mode sense structures
+    union sense_6_10 {
+        struct {
+            struct scsi_mode_param_header6 header;
+            struct spc_control_page_info_execpt sense_data;
+        } s6;
+        struct {
+            struct scsi_mode_param_header10 header;
+            struct spc_control_page_info_execpt sense_data;
+        } s10;
+    };
+
+    uint8_t data_sense_lgt;
+    uint8_t mode;
+    uint8_t request_lgt;
+    struct spc_control_page_info_execpt *ptr_mode;
+    __attribute__((__aligned__(4))) static union sense_6_10 sense;
+
+    // Clear all fields
+    memset(&sense, 0, sizeof(sense));
+
+    // Initialize process
+    if (b_sense10) {
+        request_lgt = udi_msc_cbw.CDB[8];
+        ptr_mode = &sense.s10.sense_data;
+        data_sense_lgt = sizeof(struct scsi_mode_param_header10);
+    } else {
+        request_lgt = udi_msc_cbw.CDB[4];
+        ptr_mode = &sense.s6.sense_data;
+        data_sense_lgt = sizeof(struct scsi_mode_param_header6);
+    }
+
+    // No Block descriptor
+
+    // Fill page(s)
+    mode = udi_msc_cbw.CDB[2] & SCSI_MS_MODE_ALL;
+    if ((SCSI_MS_MODE_INFEXP == mode) || (SCSI_MS_MODE_ALL == mode)) {
+        // Informational exceptions control page (from SPC)
+        ptr_mode->page_code = SCSI_MS_MODE_INFEXP;
+        ptr_mode->page_length = SPC_MP_INFEXP_PAGE_LENGTH;
+        ptr_mode->mrie = SPC_MP_INFEXP_MRIE_NO_SENSE;
+        data_sense_lgt += sizeof(struct spc_control_page_info_execpt);
+    }
+    // Can't send more than mode sense data length
+    if (request_lgt > data_sense_lgt)
+        request_lgt = data_sense_lgt;
+    if (!udi_msc_cbw_validate(request_lgt, USB_CBW_DIRECTION_IN))
+        return;
+
+    // Fill mode parameter header length
+
+    if (b_sense10) {
+        sense.s10.header.mode_data_length = cpu_to_be16((data_sense_lgt - 2));
+    } else {
+        sense.s6.header.mode_data_length = data_sense_lgt - 1;
+    }
+
+    // Send mode sense data
+    udi_msc_data_send((uint8_t *)&sense, request_lgt);
+}
+
+static void udi_msc_spc_prevent_allow_medium_removal(void) {
+#if USE_MSC_CHECKS
+    uint8_t prevent = udi_msc_cbw.CDB[4];
+    if (0 == prevent) {
+        udi_msc_sense_pass();
+    } else {
+        udi_msc_sense_fail_cdb_invalid(); // Command is unsupported
+    }
+#else
+    udi_msc_sense_pass();
+#endif
+    udi_msc_csw_process();
+}
+
+static void udi_msc_sbc_start_stop(void) {
+#if 0
+	bool start = 0x1 & udi_msc_cbw.CDB[4];
+	bool loej = 0x2 & udi_msc_cbw.CDB[4];
+	if (loej) {
+		mem_unload(udi_msc_cbw.bCBWLUN, !start);
+	}
+#endif
+    udi_msc_sense_pass();
+    udi_msc_csw_process();
+}
+
+static void udi_msc_sbc_read_capacity(void) {
+    __attribute__((__aligned__(4))) static struct sbc_read_capacity10_data udi_msc_capacity;
+
+    if (!udi_msc_cbw_validate(sizeof(udi_msc_capacity), USB_CBW_DIRECTION_IN))
+        return;
+
+    udi_msc_capacity.max_lba = NUM_FAT_BLOCKS - 1;
+    // Format capacity data
+    udi_msc_capacity.block_len = CPU_TO_BE32(UDI_MSC_BLOCK_SIZE);
+    udi_msc_capacity.max_lba = CPU_TO_BE32(udi_msc_capacity.max_lba);
+    // Send the corresponding sense data
+    udi_msc_data_send((uint8_t *)&udi_msc_capacity, sizeof(udi_msc_capacity));
+}
+
+__attribute__((__aligned__(4))) static uint8_t block_buffer[UDI_MSC_BLOCK_SIZE];
+static WriteState usbWriteState;
+
+static void udi_msc_sbc_trans(bool b_read) {
+    uint32_t trans_size;
+
+    //! Memory address to execute the command
+    uint32_t udi_msc_addr;
+
+    //! Number of block to transfer
+    uint16_t udi_msc_nb_block;
+
+    // Read/Write command fields (address and number of block)
+    MSB0(udi_msc_addr) = udi_msc_cbw.CDB[2];
+    MSB1(udi_msc_addr) = udi_msc_cbw.CDB[3];
+    MSB2(udi_msc_addr) = udi_msc_cbw.CDB[4];
+    MSB3(udi_msc_addr) = udi_msc_cbw.CDB[5];
+    MSB(udi_msc_nb_block) = udi_msc_cbw.CDB[7];
+    LSB(udi_msc_nb_block) = udi_msc_cbw.CDB[8];
+
+    // Compute number of byte to transfer and valid it
+    trans_size = (uint32_t)udi_msc_nb_block * UDI_MSC_BLOCK_SIZE;
+    if (!udi_msc_cbw_validate(trans_size, (b_read) ? USB_CBW_DIRECTION_IN : USB_CBW_DIRECTION_OUT))
+        return;
+
+#if USE_DBG_MSC
+    logwrite(b_read ? "read @" : "write @");
+    logwritenum(udi_msc_addr);
+    logwrite(" sz:");
+    logwritenum(trans_size);
+    logwrite("\n");
+#endif
+
+    for (uint32_t i = 0; i < udi_msc_nb_block; ++i) {
+        if (!USB_Ok()) {
+            logmsg("Transfer aborted.");
+            return;
+        }
+
+        // logval("readblk", i);
+        if (b_read) {
+            read_block(udi_msc_addr + i, block_buffer);
+            USB_Write(block_buffer, UDI_MSC_BLOCK_SIZE, USB_EP_MSC_IN);
+        } else {
+            USB_ReadBlocking(block_buffer, UDI_MSC_BLOCK_SIZE, USB_EP_MSC_OUT, 0);
+
+#if 0
+            check_uf2_handover(block_buffer, udi_msc_nb_block - i - 1, USB_EP_MSC_IN,
+                               USB_EP_MSC_OUT, udi_msc_cbw.dCBWTag);
+#endif
+
+            write_block(udi_msc_addr + i, block_buffer, false, &usbWriteState);
+            led_signal();
+        }
+        udi_msc_csw.dCSWDataResidue -= UDI_MSC_BLOCK_SIZE;
+    }
+
+    udi_msc_sense_pass();
+
+    // Send status of transfer in CSW packet
+    udi_msc_csw_process();
+}
+
+#if USE_MSC_HANDOVER
+static void handover_flash(UF2_HandoverArgs *handover, PacketBuffer *handoverCache,
+                           WriteState *state) {
+    for (uint32_t i = 0; i < handover->blocks_remaining; ++i) {
+        USB_ReadBlocking(handover->buffer, UDI_MSC_BLOCK_SIZE, handover->ep_out, handoverCache);
+        write_block(0x1000 + i, handover->buffer, true, state);
+    }
+}
+
+static void process_handover_initial(UF2_HandoverArgs *handover, PacketBuffer *handoverCache,
+                                     WriteState *state) {
+    struct usb_msc_csw csw = {.dCSWTag = handover->cbw_tag,
+                              .dCSWSignature = CPU_TO_BE32(USB_CSW_SIGNATURE),
+                              .bCSWStatus = USB_CSW_STATUS_PASS,
+                              .dCSWDataResidue = 0};
+    // write out the block passed from user space
+    write_block(0xfff, handover->buffer, true, state);
+    // read-write remaining blocks
+    handover_flash(handover, handoverCache, state);
+    // send USB response, as the user space isn't gonna do it
+    USB_WriteCore((void *)&csw, sizeof(csw), handover->ep_in, true);
+}
+
+static void process_handover(UF2_HandoverArgs *handover, PacketBuffer *handoverCache,
+                             WriteState *state) {
+    struct usb_msc_cbw cbw;
+    int num = 0;
+
+    while (!try_read_cbw(&cbw, handover->ep_out, handoverCache)) {
+        // TODO is this the right value?
+        if (num++ > TIMER_STEP * 50) {
+            resetIntoApp();
+        }
+    }
+
+    struct usb_msc_csw csw = {.dCSWTag = cbw.dCBWTag,
+                              .dCSWSignature = CPU_TO_BE32(USB_CSW_SIGNATURE),
+                              .bCSWStatus = USB_CSW_STATUS_PASS,
+                              .dCSWDataResidue = le32_to_cpu(cbw.dCBWDataTransferLength)};
+
+    // if (SBC_WRITE10 != udi_msc_cbw.CDB[0])
+    //    logval("MSC CMD", udi_msc_cbw.CDB[0]);
+
+    uint16_t udi_msc_nb_block;
+
+    switch (cbw.CDB[0]) {
+    case SPC_TEST_UNIT_READY:
+        // ready, nothing to do
+        break;
+
+    case SBC_WRITE10:
+        MSB(udi_msc_nb_block) = cbw.CDB[7];
+        LSB(udi_msc_nb_block) = cbw.CDB[8];
+        handover->blocks_remaining = udi_msc_nb_block;
+        handover_flash(handover, handoverCache, state);
+        csw.dCSWDataResidue -= UDI_MSC_BLOCK_SIZE * udi_msc_nb_block;
+        break;
+
+    default:
+        resetIntoBootloader();
+        break;
+    }
+
+    USB_WriteCore((void *)&csw, sizeof(csw), handover->ep_in, true);
+}
+
+void handoverPrep() {
+    __disable_irq();
+    __DMB();
+
+    USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK;
+    USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK;
+
+    SCB->VTOR = 0;
+}
+
+static void handover(UF2_HandoverArgs *args) {
+    handoverPrep();
+
+    PacketBuffer cache = {0};
+    WriteState writeState = {0};
+    cache.read_job = 2;
+
+    // They may have 0x80 bit set
+    args->ep_in &= 0xf;
+    args->ep_out &= 0xf;
+
+    process_handover_initial(args, &cache, &writeState);
+    while (1) {
+        process_handover(args, &cache, &writeState);
+    }
+}
+#endif
+
+__attribute__((section(".binfo"))) __attribute__((__used__)) const UF2_BInfo binfo = {
+#ifdef HAS_CONFIG_DATA
+    .config_data = config_data,
+#endif
+#if USE_MSC_HANDOVER
+    .handoverMSC = handover,
+#endif
+#if USE_HID_HANDOVER
+    .handoverHID = hidHandoverLoop,
+#endif
+    .info_uf2 = infoUf2File,
+};
diff --git a/uf2-samdx1/src/sam_ba_monitor.c b/uf2-samdx1/src/sam_ba_monitor.c
new file mode 100644
index 00000000..2e7b2999
--- /dev/null
+++ b/uf2-samdx1/src/sam_ba_monitor.c
@@ -0,0 +1,300 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "uf2.h"
+
+static const char fullVersion[] = "v" SAM_BA_VERSION " [Arduino:XYZ] " __DATE__ " " __TIME__ "\n\r";
+
+/* b_terminal_mode mode (ascii) or hex mode */
+#if USE_CDC_TERMINAL
+volatile bool b_terminal_mode = false;
+#endif
+volatile bool b_sam_ba_interface_usart = false;
+
+void sam_ba_monitor_init(uint8_t com_interface) {
+#if USE_UART
+    // Selects the requested interface for future actions
+    if (com_interface == SAM_BA_INTERFACE_USART) {
+        b_sam_ba_interface_usart = true;
+    }
+#endif
+}
+
+/**
+ * \brief This function allows data rx by USART
+ *
+ * \param *data  Data pointer
+ * \param length Length of the data
+ */
+void sam_ba_putdata_term(uint8_t *data, uint32_t length) {
+#if USE_CDC_TERMINAL
+    uint8_t temp, buf[12], *data_ascii;
+    uint32_t i, int_value;
+
+    if (b_terminal_mode) {
+        if (length == 4)
+            int_value = *(uint32_t *)(void *)data;
+        else if (length == 2)
+            int_value = *(uint16_t *)(void *)data;
+        else
+            int_value = *(uint8_t *)(void *)data;
+
+        data_ascii = buf + 2;
+        data_ascii += length * 2 - 1;
+
+        for (i = 0; i < length * 2; i++) {
+            temp = (uint8_t)(int_value & 0xf);
+
+            if (temp <= 0x9)
+                *data_ascii = temp | 0x30;
+            else
+                *data_ascii = temp + 0x37;
+
+            int_value >>= 4;
+            data_ascii--;
+        }
+        buf[0] = '0';
+        buf[1] = 'x';
+        buf[length * 2 + 2] = '\n';
+        buf[length * 2 + 3] = '\r';
+        cdc_write_buf(buf, length * 2 + 4);
+    } else
+#endif
+        cdc_write_buf(data, length);
+    return;
+}
+
+volatile uint32_t sp;
+void call_applet(uint32_t address) {
+    uint32_t app_start_address;
+
+    /* Save current Stack Pointer */
+    sp = __get_MSP();
+
+    /* Rebase the Stack Pointer */
+    __set_MSP(*(uint32_t *)address);
+
+    /* Load the Reset Handler address of the application */
+    app_start_address = *(uint32_t *)(address + 4);
+
+    /* Jump to application Reset Handler in the application */
+    asm("blx %0" ::"r"(app_start_address):"r0","r1","r2","r3","lr");
+
+    /* Rebase the Stack Pointer */
+    __set_MSP(sp);
+}
+
+uint32_t current_number;
+uint32_t i, length;
+uint8_t command, *ptr_data, *ptr, data[SIZEBUFMAX + 1];
+uint8_t j;
+uint32_t u32tmp;
+
+// Prints a 32-bit integer in hex.
+void put_uint32(uint32_t n) {
+    char buff[8];
+    writeNum(buff, n, true);
+    cdc_write_buf(buff, 8);
+}
+
+/**
+ * \brief This function starts the SAM-BA monitor.
+ */
+void sam_ba_monitor_run(void) {
+    ptr_data = NULL;
+    command = 'z';
+
+    // Start waiting some cmd
+    while (1) {
+        process_msc();
+        length = cdc_read_buf(data, SIZEBUFMAX);
+        data[length] = 0;
+        if (length) {
+            logwrite("SERIAL:");
+            logmsg(data);
+            led_signal();
+        }
+        ptr = data;
+        for (i = 0; i < length; i++) {
+            if (*ptr != 0xff) {
+                if (*ptr == '#') {
+#if USE_CDC_TERMINAL
+                    if (b_terminal_mode) {
+                        cdc_write_buf("\n\r", 2);
+                    }
+#endif
+                    if (command == 'S') {
+                        // Check if some data are remaining in the "data" buffer
+                        if (length > i) {
+                            // Move current indexes to next avail data
+                            // (currently ptr points to "#")
+                            ptr++;
+                            i++;
+                            // We need to add first the remaining data of the
+                            // current buffer already read from usb
+                            // read a maximum of "current_number" bytes
+                            u32tmp = (length - i) < current_number ? (length - i) : current_number;
+                            memcpy(ptr_data, ptr, u32tmp);
+                            i += u32tmp;
+                            ptr += u32tmp;
+                            j = u32tmp;
+                        }
+                        // update i with the data read from the buffer
+                        i--;
+                        ptr--;
+                        // Do we expect more data ?
+                        if (j < current_number)
+                            cdc_read_buf_xmd(ptr_data, current_number - j);
+
+                        __asm("nop");
+                    } else if (command == 'R') {
+                        cdc_write_buf_xmd(ptr_data, current_number);
+                    } else if (command == 'O') {
+                        *ptr_data = (char)current_number;
+                    } else if (command == 'H') {
+                        *((uint16_t *)(void *)ptr_data) = (uint16_t)current_number;
+                    } else if (command == 'W') {
+                        // detect BOSSA resetting us
+                        if ((uint32_t)ptr_data == 0xE000ED0C)
+                            RGBLED_set_color(COLOR_LEAVE);
+                        *((int *)(void *)ptr_data) = current_number;
+                    } else if (command == 'o') {
+                        sam_ba_putdata_term(ptr_data, 1);
+                    } else if (command == 'h') {
+                        current_number = *((uint16_t *)(void *)ptr_data);
+                        sam_ba_putdata_term((uint8_t *)&current_number, 2);
+                    } else if (command == 'w') {
+                        current_number = *((uint32_t *)(void *)ptr_data);
+                        sam_ba_putdata_term((uint8_t *)&current_number, 4);
+                    } else if (command == 'G') {
+                        call_applet(current_number);
+                        if (b_sam_ba_interface_usart) {
+                            cdc_write_buf("\x06", 1);
+                        }
+                    } else if (command == 'T') {
+#if USE_CDC_TERMINAL
+                        b_terminal_mode = 1;
+                        cdc_write_buf("\n\r", 2);
+#endif
+                    } else if (command == 'N') {
+#if USE_CDC_TERMINAL
+                        if (b_terminal_mode == 0) {
+                            cdc_write_buf("\n\r", 2);
+                        }
+                        b_terminal_mode = 0;
+#endif
+                    } else if (command == 'V') {
+                        cdc_write_buf(fullVersion, sizeof(fullVersion));
+                    } else if (command == 'X') {
+                        // Syntax: X[ADDR]#
+                        // Erase the flash memory starting from ADDR to the end
+                        // of flash.
+
+                        flash_erase_to_end((uint32_t *) current_number);
+
+                        // Notify command completed
+                        cdc_write_buf("X\n\r", 3);
+                    } else if (command == 'Y') {
+                        // This command writes the content of a buffer in SRAM
+                        // into flash memory.
+
+                        // Syntax: Y[ADDR],0#
+                        // Set the starting address of the SRAM buffer.
+
+                        // Syntax: Y[ROM_ADDR],[SIZE]#
+                        // Write the first SIZE bytes from the SRAM buffer
+                        // (previously set) into
+                        // flash memory starting from address ROM_ADDR
+
+                        static uint32_t *src_buff_addr = NULL;
+
+                        if (current_number == 0) {
+                            // Set buffer address
+                            src_buff_addr = (void *)ptr_data;
+
+                        } else {
+                            flash_write_words((void *)ptr_data, src_buff_addr, current_number / 4);
+                        }
+
+                        // Notify command completed
+                        cdc_write_buf("Y\n\r", 3);
+                    } else if (command == 'Z') {
+                        // This command calculate CRC for a given area of
+                        // memory.
+                        // It's useful to quickly check if a transfer has been
+                        // done
+                        // successfully.
+
+                        // Syntax: Z[START_ADDR],[SIZE]#
+                        // Returns: Z[CRC]#
+
+                        uint8_t *data = (uint8_t *)ptr_data;
+                        uint32_t size = current_number;
+                        uint16_t crc = 0;
+                        uint32_t i = 0;
+                        for (i = 0; i < size; i++)
+                            crc = add_crc(*data++, crc);
+
+                        // Send response
+                        cdc_write_buf("Z", 1);
+                        put_uint32(crc);
+                        cdc_write_buf("#\n\r", 3);
+                    }
+
+                    command = 'z';
+                    current_number = 0;
+#if USE_CDC_TERMINAL
+                    if (b_terminal_mode) {
+                        cdc_write_buf(">", 1);
+                    }
+#endif
+                } else {
+                    if (('0' <= *ptr) && (*ptr <= '9')) {
+                        current_number = (current_number << 4) | (*ptr - '0');
+
+                    } else if (('A' <= *ptr) && (*ptr <= 'F')) {
+                        current_number = (current_number << 4) | (*ptr - 'A' + 0xa);
+
+                    } else if (('a' <= *ptr) && (*ptr <= 'f')) {
+                        current_number = (current_number << 4) | (*ptr - 'a' + 0xa);
+
+                    } else if (*ptr == ',') {
+                        ptr_data = (uint8_t *)current_number;
+                        current_number = 0;
+
+                    } else {
+                        command = *ptr;
+                        current_number = 0;
+                    }
+                }
+                ptr++;
+            }
+        }
+    }
+}
diff --git a/uf2-samdx1/src/screen.c b/uf2-samdx1/src/screen.c
new file mode 100644
index 00000000..13806d2e
--- /dev/null
+++ b/uf2-samdx1/src/screen.c
@@ -0,0 +1,467 @@
+#include "uf2.h"
+
+#if USE_SCREEN
+
+#include <string.h>
+
+#define DISPLAY_WIDTH 160
+#define DISPLAY_HEIGHT 128
+
+// Overlap 4x chars by this much.
+#define CHAR4_KERNING 2
+// Width of a single 4x char, adjusted by kerning
+#define CHAR4_KERNED_WIDTH  (6 * 4 - CHAR4_KERNING)
+
+#define ST7735_NOP 0x00
+#define ST7735_SWRESET 0x01
+#define ST7735_RDDID 0x04
+#define ST7735_RDDST 0x09
+
+#define ST7735_SLPIN 0x10
+#define ST7735_SLPOUT 0x11
+#define ST7735_PTLON 0x12
+#define ST7735_NORON 0x13
+
+#define ST7735_INVOFF 0x20
+#define ST7735_INVON 0x21
+#define ST7735_DISPOFF 0x28
+#define ST7735_DISPON 0x29
+#define ST7735_CASET 0x2A
+#define ST7735_RASET 0x2B
+#define ST7735_RAMWR 0x2C
+#define ST7735_RAMRD 0x2E
+
+#define ST7735_PTLAR 0x30
+#define ST7735_COLMOD 0x3A
+#define ST7735_MADCTL 0x36
+
+#define ST7735_FRMCTR1 0xB1
+#define ST7735_FRMCTR2 0xB2
+#define ST7735_FRMCTR3 0xB3
+#define ST7735_INVCTR 0xB4
+#define ST7735_DISSET5 0xB6
+
+#define ST7735_PWCTR1 0xC0
+#define ST7735_PWCTR2 0xC1
+#define ST7735_PWCTR3 0xC2
+#define ST7735_PWCTR4 0xC3
+#define ST7735_PWCTR5 0xC4
+#define ST7735_VMCTR1 0xC5
+
+#define ST7735_RDID1 0xDA
+#define ST7735_RDID2 0xDB
+#define ST7735_RDID3 0xDC
+#define ST7735_RDID4 0xDD
+
+#define ST7735_PWCTR6 0xFC
+
+#define ST7735_GMCTRP1 0xE0
+#define ST7735_GMCTRN1 0xE1
+
+uint32_t lookupCfg(uint32_t key, uint32_t defl);
+#define CFG(v) lookupCfg(CFG_##v, 0x42)
+
+uint32_t lookupCfg(uint32_t key, uint32_t defl) {
+    const uint32_t *ptr = UF2_BINFO->config_data;
+    if (!ptr || (((uint32_t)ptr) & 3) || *ptr != CFG_MAGIC0) {
+        // no config data!
+    } else {
+        ptr += 4;
+        while (*ptr) {
+            if (*ptr == key)
+                return ptr[1];
+            ptr += 2;
+        }
+    }
+    if (defl == 0x42)
+        while (1)
+            ;
+    return defl;
+}
+
+void pin_set(int pincfg, int v) {
+    int pin = lookupCfg(pincfg, -1);
+    if (pin < 0)
+        return;
+    if (v) {
+        PINOP(pin, OUTSET);
+    } else {
+        PINOP(pin, OUTCLR);
+    }
+}
+
+void setup_output_pin(int pincfg) {
+    int pin = lookupCfg(pincfg, -1);
+    if (pin < 0)
+        return;
+    PINOP(pin, DIRSET);
+    PINOP(pin, OUTCLR);
+}
+
+#define PINPORT(pin) PORT->Group[(pin) / 32]
+#define pinmask(pin) (1 << (pin & 0x1f))
+
+void transfer(uint8_t *ptr, uint32_t len) {
+    int mosi = CFG(PIN_DISPLAY_MOSI);
+    int sck = CFG(PIN_DISPLAY_SCK);
+
+    volatile uint32_t *mosi_set = &PINPORT(mosi).OUTSET.reg;
+    volatile uint32_t *mosi_clr = &PINPORT(mosi).OUTCLR.reg;
+    volatile uint32_t *sck_tgl = &PINPORT(sck).OUTTGL.reg;
+
+    uint32_t mosi_mask = pinmask(mosi);
+    uint32_t sck_mask = pinmask(sck);
+
+    PINOP(sck, OUTCLR);
+
+    uint8_t mask = 0, b;
+    for (;;) {
+        if (!mask) {
+            if (!len--)
+                break;
+            mask = 0x80;
+            b = *ptr++;
+        }
+        if (b & mask)
+            *mosi_set = mosi_mask;
+        else
+            *mosi_clr = mosi_mask;
+        *sck_tgl = sck_mask;
+        mask >>= 1;
+        *sck_tgl = sck_mask;
+    }
+}
+
+#define DELAY 0x80
+
+// clang-format off
+static const uint8_t initCmds[] = {
+    ST7735_SWRESET,   DELAY,  //  1: Software reset, 0 args, w/delay
+      120,                    //     150 ms delay
+    ST7735_SLPOUT ,   DELAY,  //  2: Out of sleep mode, 0 args, w/delay
+      120,                    //     500 ms delay
+    ST7735_INVOFF , 0      ,  // 13: Don't invert display, no args, no delay
+    ST7735_COLMOD , 1      ,  // 15: set color mode, 1 arg, no delay:
+      0x05,                  //     16-bit color
+    ST7735_GMCTRP1, 16      , //  1: Magical unicorn dust, 16 args, no delay:
+      0x02, 0x1c, 0x07, 0x12,
+      0x37, 0x32, 0x29, 0x2d,
+      0x29, 0x25, 0x2B, 0x39,
+      0x00, 0x01, 0x03, 0x10,
+    ST7735_NORON  ,    DELAY, //  3: Normal display on, no args, w/delay
+      10,                     //     10 ms delay
+    ST7735_DISPON ,    DELAY, //  4: Main screen turn on, no args w/delay
+      10,
+    0, 0 // END
+};
+// clang-format on
+
+static uint8_t cmdBuf[20];
+
+#define SET_DC(v) pin_set(CFG_PIN_DISPLAY_DC, v)
+#define SET_CS(v) pin_set(CFG_PIN_DISPLAY_CS, v)
+
+static void scr_delay(unsigned msec) {
+    int k = msec * 15000;
+    while (k--)
+        asm("nop");
+}
+
+static void sendCmd(uint8_t *buf, int len) {
+    // make sure cmd isn't on stack
+    if (buf != cmdBuf)
+        memcpy(cmdBuf, buf, len);
+    buf = cmdBuf;
+
+    SET_DC(0);
+    SET_CS(0);
+
+    transfer(buf, 1);
+
+    SET_DC(1);
+
+    len--;
+    buf++;
+    if (len > 0)
+        transfer(buf, len);
+
+    SET_CS(1);
+}
+
+static void sendCmdSeq(const uint8_t *buf) {
+    while (*buf) {
+        cmdBuf[0] = *buf++;
+        int v = *buf++;
+        int len = v & ~DELAY;
+        // note that we have to copy to RAM
+        memcpy(cmdBuf + 1, buf, len);
+        sendCmd(cmdBuf, len + 1);
+        buf += len;
+        if (v & DELAY) {
+            scr_delay(*buf++);
+        }
+    }
+}
+
+static uint32_t palXOR;
+
+static void setAddrWindow(int x, int y, int w, int h) {
+    uint8_t cmd0[] = {ST7735_RASET, 0, (uint8_t)x, 0, (uint8_t)(x + w - 1)};
+    uint8_t cmd1[] = {ST7735_CASET, 0, (uint8_t)y, 0, (uint8_t)(y + h - 1)};
+    sendCmd(cmd1, sizeof(cmd1));
+    sendCmd(cmd0, sizeof(cmd0));
+}
+
+static void configure(uint8_t madctl, uint32_t frmctr1) {
+    uint8_t cmd0[] = {ST7735_MADCTL, madctl};
+    uint8_t cmd1[] = {ST7735_FRMCTR1, (uint8_t)(frmctr1 >> 16), (uint8_t)(frmctr1 >> 8),
+                      (uint8_t)frmctr1};
+    sendCmd(cmd0, sizeof(cmd0));
+    sendCmd(cmd1, cmd1[3] == 0xff ? 3 : 4);
+}
+
+#define COL0(r, g, b) ((((r) >> 3) << 11) | (((g) >> 2) << 5) | ((b) >> 3))
+#define COL(c) COL0((c >> 16) & 0xff, (c >> 8) & 0xff, c & 0xff)
+
+const uint16_t palette[] = {
+    COL(0x000000), // 0
+    COL(0xffffff), // 1
+    COL(0xff2121), // 2
+    COL(0xff93c4), // 3
+    COL(0xff8135), // 4
+    COL(0xfff609), // 5
+    COL(0x249ca3), // 6
+    COL(0x78dc52), // 7
+    COL(0x003fad), // 8
+    COL(0x87f2ff), // 9
+    COL(0x8e2ec4), // 10
+    COL(0xa4839f), // 11
+    COL(0x5c406c), // 12
+    COL(0xe5cdc4), // 13
+    COL(0x91463d), // 14
+    COL(0x000000), // 15
+};
+
+uint8_t fb[168 * 128];
+extern const uint8_t font8[];
+extern const uint8_t fileLogo[];
+extern const uint8_t pendriveLogo[];
+extern const uint8_t arrowLogo[];
+
+static void printch(int x, int y, int col, const uint8_t *fnt) {
+    for (int i = 0; i < 6; ++i) {
+        uint8_t *p = fb + (x + i) * DISPLAY_HEIGHT + y;
+        uint8_t mask = 0x01;
+        for (int j = 0; j < 8; ++j) {
+            if (*fnt & mask)
+                *p = col;
+            p++;
+            mask <<= 1;
+        }
+        fnt++;
+    }
+}
+
+static void printch4(int x, int y, int col, const uint8_t *fnt) {
+    for (int i = 0; i < 6 * 4; ++i) {
+        uint8_t *p = fb + (x + i) * DISPLAY_HEIGHT + y;
+        uint8_t mask = 0x01;
+        for (int j = 0; j < 8; ++j) {
+            for (int k = 0; k < 4; ++k) {
+                if (*fnt & mask)
+                    *p = col;
+                p++;
+            }
+            mask <<= 1;
+        }
+        if ((i & 3) == 3)
+            fnt++;
+    }
+}
+
+void printicon(int x, int y, int col, const uint8_t *icon) {
+    int w = *icon++;
+    int h = *icon++;
+    int sz = *icon++;
+
+    uint8_t mask = 0x80;
+    int runlen = 0;
+    int runbit = 0;
+    uint8_t lastb = 0x00;
+
+    for (int i = 0; i < w; ++i) {
+        uint8_t *p = fb + (x + i) * DISPLAY_HEIGHT + y;
+        for (int j = 0; j < h; ++j) {
+            int c = 0;
+            if (mask != 0x80) {
+                if (lastb & mask)
+                    c = 1;
+                mask <<= 1;
+            } else if (runlen) {
+                if (runbit)
+                    c = 1;
+                runlen--;
+            } else {
+                if (sz-- <= 0)
+                    panic(10);
+                lastb = *icon++;
+                if (lastb & 0x80) {
+                    runlen = lastb & 63;
+                    runbit = lastb & 0x40;
+                } else {
+                    mask = 0x01;
+                }
+                --j;
+                continue; // restart
+            }
+            if (c)
+                *p = col;
+            p++;
+        }
+    }
+}
+
+void print(int x, int y, int col, const char *text) {
+    int x0 = x;
+    while (*text) {
+        char c = *text++;
+        if (c == '\r')
+            continue;
+        if (c == '\n') {
+            x = x0;
+            y += 10;
+            continue;
+        }
+        /*
+        if (x + 8 > DISPLAY_WIDTH) {
+            x = x0;
+            y += 10;
+        }
+        */
+        if (c < ' ')
+            c = '?';
+        if (c >= 0x7f)
+            c = '?';
+        c -= ' ';
+        printch(x, y, col, &font8[c * 6]);
+        x += 6;
+    }
+}
+
+void print4(int x, int y, int col, const char *text) {
+    while (*text) {
+        char c = *text++;
+        c -= ' ';
+        printch4(x, y, col, &font8[c * 6]);
+        x += CHAR4_KERNED_WIDTH;
+        if (x + CHAR4_KERNED_WIDTH > DISPLAY_WIDTH) {
+            // Next char won't fit.
+            return;
+        }
+    }
+}
+
+void draw_screen() {
+    if (lookupCfg(CFG_PIN_DISPLAY_SCK, 1000) == 1000)
+        return;
+
+    cmdBuf[0] = ST7735_RAMWR;
+    sendCmd(cmdBuf, 1);
+
+    SET_DC(1);
+    SET_CS(0);
+
+    uint8_t *p = fb;
+    for (int i = 0; i < DISPLAY_WIDTH; ++i) {
+        uint8_t cc[DISPLAY_HEIGHT * 2];
+        uint32_t dst = 0;
+        for (int j = 0; j < DISPLAY_HEIGHT; ++j) {
+            uint16_t color = palette[*p++ & 0xf];
+            cc[dst++] = color >> 8;
+            cc[dst++] = color & 0xff;
+        }
+        transfer(cc, sizeof(cc));
+    }
+
+    SET_CS(1);
+}
+
+void drawBar(int y, int h, int c) {
+    for (int x = 0; x < DISPLAY_WIDTH; ++x) {
+        memset(fb + x * DISPLAY_HEIGHT + y, c, h);
+    }
+}
+
+void draw_hf2() {
+    print4(20, 22, 5, "<-->");
+    print(40, 110, 7, "flashing...");
+    draw_screen();
+}
+
+void draw_drag() {
+    drawBar(0, 52, 7);
+    drawBar(52, 55, 8);
+    drawBar(107, 14, 4);
+
+    // Center PRODUCT_NAME and UF2_VERSION_BASE.
+    int name_x = (DISPLAY_WIDTH - (6 * 4 - CHAR4_KERNING) * (int) strlen(PRODUCT_NAME)) / 2;
+    print4(name_x >= 0 ? name_x : 0, 5, 1, PRODUCT_NAME);
+    int version_x = (DISPLAY_WIDTH - 6 * (int) strlen(UF2_VERSION_BASE)) / 2;
+    print(version_x >= 0 ? version_x : 0, 40, 6, UF2_VERSION_BASE);
+    print(23, 110, 1, "arcade.makecode.com");
+
+#define DRAG 70
+#define DRAGX 10
+    printicon(DRAGX + 20, DRAG + 5, 1, fileLogo);
+    printicon(DRAGX + 66, DRAG, 1, arrowLogo);
+    printicon(DRAGX + 108, DRAG, 1, pendriveLogo);
+    print(10, DRAG - 12, 1, "arcade.uf2");
+    print(90, DRAG - 12, 1, VOLUME_LABEL);
+
+    draw_screen();
+}
+
+void screen_early_init() {
+    setup_output_pin(CFG_PIN_DISPLAY_BL);
+}
+
+void screen_init() {
+    if (lookupCfg(CFG_PIN_DISPLAY_SCK, 1000) == 1000)
+        return;
+
+    setup_output_pin(CFG_PIN_DISPLAY_SCK);
+    setup_output_pin(CFG_PIN_DISPLAY_MOSI);
+    setup_output_pin(CFG_PIN_DISPLAY_BL);
+    setup_output_pin(CFG_PIN_DISPLAY_DC);
+    setup_output_pin(CFG_PIN_DISPLAY_RST);
+    setup_output_pin(CFG_PIN_DISPLAY_CS);
+
+    SET_CS(1);
+    SET_DC(1);
+
+    pin_set(CFG_PIN_DISPLAY_BL, 1);
+
+    pin_set(CFG_PIN_DISPLAY_RST, 0);
+    scr_delay(20);
+    pin_set(CFG_PIN_DISPLAY_RST, 1);
+    scr_delay(20);
+
+    sendCmdSeq(initCmds);
+
+    uint32_t cfg0 = CFG(DISPLAY_CFG0);
+    //uint32_t cfg2 = CFG(DISPLAY_CFG2);
+    uint32_t frmctr1 = CFG(DISPLAY_CFG1);
+    palXOR = (cfg0 & 0x1000000) ? 0xffffff : 0x000000;
+    uint32_t madctl = cfg0 & 0xff;
+    uint32_t offX = (cfg0 >> 8) & 0xff;
+    uint32_t offY = (cfg0 >> 16) & 0xff;
+    //uint32_t freq = (cfg2 & 0xff);
+
+    // DMESG("configure screen: FRMCTR1=%p MADCTL=%p SPI at %dMHz", frmctr1, madctl, freq);
+    configure(madctl, frmctr1);
+    setAddrWindow(offX, offY, CFG(DISPLAY_WIDTH), CFG(DISPLAY_HEIGHT));
+
+    memset(fb, 0, sizeof(fb));
+}
+
+#endif
diff --git a/uf2-samdx1/src/selfmain.c b/uf2-samdx1/src/selfmain.c
new file mode 100644
index 00000000..91496d96
--- /dev/null
+++ b/uf2-samdx1/src/selfmain.c
@@ -0,0 +1,210 @@
+#include "uf2.h"
+
+#include "sam.h"
+
+#if defined(SAMD21)
+#define BOOTLOADER_K 8
+#elif defined(SAMD51)
+#define BOOTLOADER_K 16
+#endif
+
+extern const uint8_t bootloader[];
+extern const uint16_t bootloader_crcs[];
+
+uint8_t bootloader_page_buf[FLASH_ROW_SIZE];
+
+#if defined(SAMD21)
+#define NVM_FUSE_ADDR ((uint32_t *)NVMCTRL_AUX0_ADDRESS)
+#elif defined(SAMD51)
+#define NVM_FUSE_ADDR ((uint32_t *)NVMCTRL_FUSES_BOOTPROT_ADDR)
+#endif
+
+static inline void nvmctrl_wait_ready(void) {
+#if defined(SAMD21)
+    while (NVMCTRL->INTFLAG.bit.READY == 0) { }
+#elif defined(SAMD51)
+    while (NVMCTRL->STATUS.bit.READY == 0) { }
+#endif
+}
+
+static inline void nvmctrl_set_addr(const uint32_t *addr) {
+#if defined(SAMD21)
+    NVMCTRL->ADDR.reg = (uint32_t)addr / 2;
+#elif defined(SAMD51)
+    NVMCTRL->ADDR.reg = (uint32_t)addr;
+#endif
+}
+
+static inline void nvmctrl_exec_cmd(uint32_t cmd) {
+#if defined(SAMD21)
+    NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;  // Clear error status bits.
+    NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | cmd;
+    nvmctrl_wait_ready();
+#elif defined(SAMD51)
+    NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMDEX_KEY | cmd;
+#endif
+    nvmctrl_wait_ready();
+}
+
+void set_fuses_and_bootprot(uint32_t new_bootprot) {
+#if defined(SAMD21)
+    uint32_t fuses[2];
+#elif defined(SAMD51)
+    uint32_t fuses[128];    // 512 bytes (whole user page)
+#endif
+    nvmctrl_wait_ready();
+
+    memcpy(fuses, (uint32_t *)NVM_FUSE_ADDR, sizeof(fuses));
+
+    // If it appears the fuses page was erased (all ones), replace fuses with reasonable values.
+
+#if defined(SAMD21)
+    bool repair_fuses = (fuses[0] == 0xffffffff ||
+                         fuses[1] == 0xffffffff);
+#elif defined(SAMD51)
+    bool repair_fuses = (fuses[0] == 0xffffffff ||
+                         fuses[1] == 0xffffffff ||
+                         fuses[4] == 0xffffffff);
+#endif
+
+    if (repair_fuses) {
+        // These canonical fuse values taken from working Adafruit boards.
+        // BOOTPROT is set to nothing in these values.
+#if defined(SAMD21)
+        fuses[0] = 0xD8E0C7FF;
+        fuses[1] = 0xFFFFFC5D;
+#elif defined(SAMD51)
+        fuses[0] = 0xFE9A9239;
+        fuses[1] = 0xAEECFF80;
+        fuses[2] = 0xFFFFFFFF;
+        // fuses[3] is for user use, so we don't change it.
+        fuses[4] = 0x00804010;
+#endif
+    }
+
+    uint32_t current_bootprot = (fuses[0] & NVMCTRL_FUSES_BOOTPROT_Msk) >> NVMCTRL_FUSES_BOOTPROT_Pos;
+
+    logval("repair_fuses", repair_fuses);
+    logval("current_bootprot", current_bootprot);
+    logval("new_bootprot", new_bootprot);
+
+    // Don't write if nothing will be changed.
+    if (current_bootprot == new_bootprot && !repair_fuses) {
+        return;
+    }
+
+    // Update fuses BOOTPROT value with desired value.
+    fuses[0] = (fuses[0] & ~NVMCTRL_FUSES_BOOTPROT_Msk) | (new_bootprot << NVMCTRL_FUSES_BOOTPROT_Pos);
+
+    // Write the fuses.
+
+#if defined(SAMD21)
+    NVMCTRL->CTRLB.reg = NVMCTRL->CTRLB.reg | NVMCTRL_CTRLB_CACHEDIS | NVMCTRL_CTRLB_MANW;
+    nvmctrl_set_addr(NVM_FUSE_ADDR);  // Set address to auxiliary row (fuses).
+    nvmctrl_exec_cmd(NVMCTRL_CTRLA_CMD_EAR);  // Erase auxiliary row.
+    nvmctrl_exec_cmd(NVMCTRL_CTRLA_CMD_PBC);  // Clear page buffer (64 bytes).
+    // Writes must be 16 or 32 bits at a time.
+    NVM_FUSE_ADDR[0] = fuses[0];
+    NVM_FUSE_ADDR[1] = fuses[1];
+    nvmctrl_exec_cmd(NVMCTRL_CTRLA_CMD_WAP);
+#elif defined(SAMD51)
+    NVMCTRL->CTRLA.bit.WMODE = NVMCTRL_CTRLA_WMODE_MAN;
+    nvmctrl_set_addr(NVM_FUSE_ADDR);  // Set address to user page.
+    nvmctrl_exec_cmd(NVMCTRL_CTRLB_CMD_EP);   // Erase user page.
+    nvmctrl_exec_cmd(NVMCTRL_CTRLB_CMD_PBC);  // Clear page buffer.
+    for (size_t i = 0; i < sizeof(fuses) / sizeof(uint32_t); i += 4) {
+        // Copy a quadword, one 32-bit word at a time. Writes to page
+        // buffer must be 16 or 32 bits at a time, so we use explicit
+        // word writes
+        NVM_FUSE_ADDR[i + 0] = fuses[i + 0];
+        NVM_FUSE_ADDR[i + 1] = fuses[i + 1];
+        NVM_FUSE_ADDR[i + 2] = fuses[i + 2];
+        NVM_FUSE_ADDR[i + 3] = fuses[i + 3];
+        nvmctrl_set_addr(&NVM_FUSE_ADDR[i]); // Set write address to the current quad word.
+	nvmctrl_exec_cmd(NVMCTRL_CTRLB_CMD_WQW); // Write quad word.
+    }
+#endif
+
+    resetIntoApp();
+}
+
+int main(void) {
+    led_init();
+
+    logmsg("Start");
+
+    assert((8 << NVMCTRL->PARAM.bit.PSZ) == FLASH_PAGE_SIZE);
+    // assert(FLASH_PAGE_SIZE * NVMCTRL->PARAM.bit.NVMP == FLASH_SIZE);
+
+    /* We have determined we should stay in the monitor. */
+    /* System initialization */
+    system_init();
+    __disable_irq();
+    __DMB();
+
+    logmsg("Before main loop");
+
+#ifdef SAMD21
+    // Disable BOOTPROT while updating bootloader.
+    set_fuses_and_bootprot(7); // 0k - See "Table 22-2 Boot Loader Size" in datasheet.
+#endif
+#ifdef SAMD51
+    // set_fuses_and_bootprot() will cause a reset and not return if
+    // the fuses are changed. We'll reenter main() and run this again,
+    // and it will do nothing the second time and fall hrough.
+    set_fuses_and_bootprot(13); // 16k. See "Table 25-10 Boot Loader Size" in datasheet.
+
+    // We only need to set the BOOTPROT once on the SAMD51. For updates, we can
+    // temporarily turn the protection off instead.
+    nvmctrl_exec_cmd(NVMCTRL_CTRLB_CMD_SBPDIS);
+    // Disable NVM caches, per errata.
+    NVMCTRL->CTRLA.bit.CACHEDIS0 = true;
+    NVMCTRL->CTRLA.bit.CACHEDIS1 = true;
+#endif
+
+#ifdef SAMD21
+    const uint8_t *ptr = bootloader;
+    for (uint32_t i = 0; i < BOOTLOADER_K; ++i) {
+        int crc = 0;
+        for (uint32_t j = 0; j < 1024; ++j) {
+            crc = add_crc(*ptr++, crc);
+        }
+        if (bootloader_crcs[i] != crc) {
+            logmsg("Invalid checksum. Aborting.");
+            panic(1);
+        }
+    }
+#endif
+
+    for (uint32_t i = 0; i < BOOTLOADER_K * 1024; i += FLASH_ROW_SIZE) {
+        memcpy(bootloader_page_buf, &bootloader[i], FLASH_ROW_SIZE);
+        flash_write_row((void *)i, (void *)bootloader_page_buf);
+    }
+
+    logmsg("Update successful!");
+
+    // re-base int vector back to bootloader, so that the flash erase
+    // below doesn't write over the vectors.
+    SCB->VTOR = 0;
+
+    // Write zeros to the stack location and reset handler location so the
+    // bootloader doesn't run us a second time. We don't need to erase to write
+    // zeros. The remainder of the write unit will be set to 1s which should
+    // preserve the existing values but its not critical.
+    uint32_t zeros[2] = {0, 0};
+    flash_write_words((void *)(BOOTLOADER_K * 1024), zeros, 2);
+
+#ifdef SAMD21
+    // Re-enable BOOTPROT
+    set_fuses_and_bootprot(2); // 8k
+#endif
+    // For the SAMD51, the boot protection will automatically be re-enabled on
+    // reset.
+
+    LED_MSC_OFF();
+    resetIntoBootloader();
+
+    // We should not reach here normally.
+    while (1) {
+    }
+}
diff --git a/uf2-samdx1/src/sketch.cpp b/uf2-samdx1/src/sketch.cpp
new file mode 100644
index 00000000..5c12e368
--- /dev/null
+++ b/uf2-samdx1/src/sketch.cpp
@@ -0,0 +1,192 @@
+#if defined(__SAMD51__)
+#error "update_bootloader*.ino is not available for SAMD51 boards"
+#endif
+
+#define BOOTLOADER_K 8
+
+// Error indications:
+// 2 quick flashes repeated forever: Flash page size wrong
+// 3: checksum error
+// 4: write verify failed
+//
+// Success: 5 slower flashes, then switch to BOOT drive
+
+static uint16_t crcCache[256];
+
+#define CRC16POLY 0x1021
+
+#define FLASH_ROW_SIZE (FLASH_PAGE_SIZE * 4)
+
+uint16_t add_crc(uint8_t ch, unsigned short crc0) {
+    if (!crcCache[1]) {
+        for (int ptr = 0; ptr < 256; ptr++) {
+            uint16_t crc = (int)ptr << 8;
+            for (uint16_t cmpt = 0; cmpt < 8; cmpt++) {
+                if (crc & 0x8000)
+                    crc = crc << 1 ^ CRC16POLY;
+                else
+                    crc = crc << 1;
+            }
+            crcCache[ptr] = crc;
+        }
+    }
+
+    return ((crc0 << 8) ^ crcCache[((crc0 >> 8) ^ ch) & 0xff]) & 0xffff;
+}
+
+#define NVM_USER_MEMORY ((volatile uint16_t *)NVMCTRL_USER)
+
+static inline void wait_ready(void) {
+    while (NVMCTRL->INTFLAG.bit.READY == 0) {
+    }
+}
+
+void exec_cmd(uint32_t cmd, const uint32_t *addr) {
+    NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+    NVMCTRL->ADDR.reg = (uint32_t)addr / 2;
+    NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | cmd;
+    wait_ready();
+}
+
+void flash_erase_row(uint32_t *dst) {
+    wait_ready();
+    // Execute "ER" Erase Row
+    exec_cmd(NVMCTRL_CTRLA_CMD_ER, dst);
+}
+
+void flash_write_words(uint32_t *dst, uint32_t *src, uint32_t n_words) {
+    while (n_words > 0) {
+        uint32_t len = min(FLASH_PAGE_SIZE >> 2, n_words);
+        n_words -= len;
+
+        // Execute "PBC" Page Buffer Clear
+        const uint32_t* dst_start = dst;
+        exec_cmd(NVMCTRL_CTRLA_CMD_PBC, dst);
+
+        // Write data to page buffer.
+        while (len--) {
+            *dst++ = *src++;
+        }
+
+        // Execute "WP" Write Page
+        exec_cmd(NVMCTRL_CTRLA_CMD_WP, dst_start);
+    }
+}
+
+void flash_write_row(uint32_t *dst, uint32_t *src) {
+    flash_erase_row(dst);
+    flash_write_words(dst, src, FLASH_ROW_SIZE / 4);
+}
+
+void setBootProt(int v) {
+    uint32_t *NVM_FUSES = (uint32_t *)NVMCTRL_AUX0_ADDRESS;
+
+    uint32_t fuses[2];
+
+    fuses[0] = NVM_FUSES[0];
+    fuses[1] = NVM_FUSES[1];
+
+    uint32_t bootprot = (fuses[0] & NVMCTRL_FUSES_BOOTPROT_Msk) >> NVMCTRL_FUSES_BOOTPROT_Pos;
+
+    if (bootprot == v) {
+        return;
+    }
+
+    fuses[0] = (fuses[0] & ~NVMCTRL_FUSES_BOOTPROT_Msk) | (v << NVMCTRL_FUSES_BOOTPROT_Pos);
+
+    wait_ready();
+    exec_cmd(NVMCTRL_CTRLA_CMD_EAR, (uint32_t *)NVMCTRL_USER);
+    exec_cmd(NVMCTRL_CTRLA_CMD_PBC, (uint32_t *)NVMCTRL_USER);
+
+    NVM_FUSES[0] = fuses[0];
+    NVM_FUSES[1] = fuses[1];
+
+    exec_cmd(NVMCTRL_CTRLA_CMD_WAP, (uint32_t *)NVMCTRL_USER);
+
+    NVIC_SystemReset();
+}
+
+// We can't use regular loop_delay() because it uses interrupts, which we turn off.
+void loop_delay(int ms) {
+    ms <<= 13;
+    while (ms--) {
+        asm("nop");
+    }
+}
+
+void blink_n(int n, int interval) {
+    // Start out off.
+    digitalWrite(LED_BUILTIN, LOW);
+    loop_delay(interval);
+    for (int i = 0; i < n; ++i) {
+        digitalWrite(LED_BUILTIN, HIGH);
+        loop_delay(interval);
+        digitalWrite(LED_BUILTIN, LOW);
+        loop_delay(interval);
+    }
+}
+
+void blink_n_forever(int n, int interval) {
+    while(1) {
+        blink_n(n, interval);
+        loop_delay(interval*5);
+    }
+}
+
+void setup() {
+    pinMode(LED_BUILTIN, OUTPUT);
+    digitalWrite(LED_BUILTIN, HIGH);
+
+    if (8 << NVMCTRL->PARAM.bit.PSZ != FLASH_PAGE_SIZE) {
+        blink_n_forever(2, 200);
+    }
+
+    NVMCTRL->CTRLB.bit.MANW = 1;
+    NVMCTRL->CTRLB.bit.CACHEDIS = 1;
+
+    __disable_irq();
+
+    // This will cause a reset and re-enter the program if a change was necessary.
+    // If no change was necessary we'll fall through.
+    setBootProt(7); // 0kB; disable BOOTPROT while writing.
+
+    const uint8_t *ptr = bootloader;
+
+    for (int i = 0; i < BOOTLOADER_K; ++i) {
+        int crc = 0;
+        for (int j = 0; j < 1024; ++j) {
+            crc = add_crc(*ptr++, crc);
+        }
+        if (bootloader_crcs[i] != crc) {
+            blink_n_forever(3, 200);
+        }
+    }
+
+    // Writing starts at 0x0, so flash_addr can be used as an index into bootloader[].
+    for (int flash_addr = 0; flash_addr < BOOTLOADER_K * 1024; flash_addr += FLASH_ROW_SIZE) {
+        flash_write_row((uint32_t *)flash_addr, (uint32_t *)&bootloader[flash_addr]);
+        if (memcmp((const void *)flash_addr, &bootloader[flash_addr], FLASH_ROW_SIZE) != 0) {
+            // Write verify failed.
+            blink_n_forever(4, 200);
+        }
+    }
+
+    // re-base int vector back to bootloader, so that the flash erase below doesn't write over the
+    // vectors
+    SCB->VTOR = 0;
+
+    blink_n(5, 750);
+
+    // Write zeros to the stack location and reset handler location so the
+    // bootloader doesn't run us a second time. We don't need to erase to write
+    // zeros. The remainder of the write unit will be set to 1s which should
+    // preserve the existing values but it's not critical.
+    uint32_t zeros[2] = {0, 0};
+    flash_write_words((uint32_t *)(BOOTLOADER_K * 1024), zeros, 2);
+
+    setBootProt(2); // 8kB
+
+}
+
+void loop() {
+}
diff --git a/uf2-samdx1/src/startup_samd21.c b/uf2-samdx1/src/startup_samd21.c
new file mode 100644
index 00000000..71958534
--- /dev/null
+++ b/uf2-samdx1/src/startup_samd21.c
@@ -0,0 +1,289 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD21
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "board_config.h"
+#include "samd21.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+//void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_USB
+void USB_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void EVSYS_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SERCOM4
+void SERCOM4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_ADC
+void ADC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_DAC
+void DAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PTC
+void PTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC1
+void AC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&_estack),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNMI_Handler         = (void*) NMI_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pvReservedM12          = (void*) (0UL), /* Reserved */
+        .pvReservedM11          = (void*) (0UL), /* Reserved */
+        .pvReservedM10          = (void*) (0UL), /* Reserved */
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVC_Handler         = (void*) SVC_Handler,
+        .pvReservedM4           = (void*) (0UL), /* Reserved */
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnSYSCTRL_Handler     = (void*) SYSCTRL_Handler,        /*  1 System Control */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /*  2 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /*  3 Real-Time Counter */
+        .pfnEIC_Handler         = (void*) EIC_Handler,            /*  4 External Interrupt Controller */
+        .pfnNVMCTRL_Handler     = (void*) NVMCTRL_Handler,        /*  5 Non-Volatile Memory Controller */
+        .pfnDMAC_Handler        = (void*) DMAC_Handler,           /*  6 Direct Memory Access Controller */
+#ifdef ID_USB
+        .pfnUSB_Handler         = (void*) USB_Handler,            /*  7 Universal Serial Bus */
+#else
+        .pvReserved7            = (void*) (0UL),                  /*  7 Reserved */
+#endif
+        .pfnEVSYS_Handler       = (void*) EVSYS_Handler,          /*  8 Event System Interface */
+        .pfnSERCOM0_Handler     = (void*) SERCOM0_Handler,        /*  9 Serial Communication Interface 0 */
+        .pfnSERCOM1_Handler     = (void*) SERCOM1_Handler,        /* 10 Serial Communication Interface 1 */
+        .pfnSERCOM2_Handler     = (void*) SERCOM2_Handler,        /* 11 Serial Communication Interface 2 */
+        .pfnSERCOM3_Handler     = (void*) SERCOM3_Handler,        /* 12 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_Handler     = (void*) SERCOM4_Handler,        /* 13 Serial Communication Interface 4 */
+#else
+        .pvReserved13           = (void*) (0UL),                  /* 13 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_Handler     = (void*) SERCOM5_Handler,        /* 14 Serial Communication Interface 5 */
+#else
+        .pvReserved14           = (void*) (0UL),                  /* 14 Reserved */
+#endif
+        .pfnTCC0_Handler        = (void*) TCC0_Handler,           /* 15 Timer Counter Control 0 */
+        .pfnTCC1_Handler        = (void*) TCC1_Handler,           /* 16 Timer Counter Control 1 */
+        .pfnTCC2_Handler        = (void*) TCC2_Handler,           /* 17 Timer Counter Control 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 18 Basic Timer Counter 0 */
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 19 Basic Timer Counter 1 */
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 20 Basic Timer Counter 2 */
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 21 Basic Timer Counter 3 */
+#else
+        .pvReserved21           = (void*) (0UL),                  /* 21 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 22 Basic Timer Counter 4 */
+#else
+        .pvReserved22           = (void*) (0UL),                  /* 22 Reserved */
+#endif
+#ifdef ID_ADC
+        .pfnADC_Handler         = (void*) ADC_Handler,            /* 23 Analog Digital Converter */
+#else
+        .pvReserved23           = (void*) (0UL),                  /* 23 Reserved */
+#endif
+#ifdef ID_AC
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 24 Analog Comparators 0 */
+#else
+        .pvReserved24           = (void*) (0UL),                  /* 24 Reserved */
+#endif
+#ifdef ID_DAC
+        .pfnDAC_Handler         = (void*) DAC_Handler,            /* 25 Digital Analog Converter */
+#else
+        .pvReserved25           = (void*) (0UL),                  /* 25 Reserved */
+#endif
+#ifdef ID_PTC
+        .pfnPTC_Handler         = (void*) PTC_Handler,            /* 26 Peripheral Touch Controller */
+#else
+        .pvReserved26           = (void*) (0UL),                  /* 26 Reserved */
+#endif
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 27 Inter-IC Sound Interface */
+#else
+        .pvReserved27           = (void*) (0UL),                  /* 27 Reserved */
+#endif
+#ifdef ID_AC1
+        .pfnAC1_Handler         = (void*) AC1_Handler             /* 28 Analog Comparators 1 */
+#else
+        .pvReserved28           = (void*) (0UL)                   /* 28 Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+        uint32_t *pSrc, *pDest;
+
+        /* Initialize the relocate segment */
+        pSrc = &_etext;
+        pDest = &_srelocate;
+
+        if (pSrc != pDest) {
+                for (; pDest < &_erelocate;) {
+                        *pDest++ = *pSrc++;
+                }
+        }
+
+        /* Clear the zero segment */
+        for (pDest = &_szero; pDest < &_ezero;) {
+                *pDest++ = 0;
+        }
+
+        /* Set the vector table base address */
+        pSrc = (uint32_t *) & _sfixed;
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+        /* Change default QOS values to have the best performance and correct USB behaviour */
+        SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+#if defined(ID_USB)
+        USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+        USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+#endif
+        DMAC->QOSCTRL.bit.DQOS = 2;
+        DMAC->QOSCTRL.bit.FQOS = 2;
+        DMAC->QOSCTRL.bit.WRBQOS = 2;
+
+        /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+        NVMCTRL->CTRLB.bit.MANW = 1;
+
+        /* Initialize the C library */
+        //__libc_init_array();
+
+        /* Branch to main function */
+        main();
+
+        /* Infinite loop */
+        while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
+
+void HardFault_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/uf2-samdx1/src/startup_samd51.c b/uf2-samdx1/src/startup_samd51.c
new file mode 100644
index 00000000..35e7b86a
--- /dev/null
+++ b/uf2-samdx1/src/startup_samd51.c
@@ -0,0 +1,567 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD51
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "sam.h"
+#include "component-version.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NMI_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TAL_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TAL_BRK */
+void TAL_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TAL_IPS_0, TAL_IPS_1 */
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&_estack),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+#if COMPONENT_VERSION >= 10001
+        .pfnNonMaskableInt_Handler = (void*) NMI_Handler,
+#else
+        .pfnNMI_Handler         = (void*) NMI_Handler,
+#endif
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+#if COMPONENT_VERSION >= 10001
+        .pfnMemManagement_Handler = (void*) MemManage_Handler,
+#else
+        .pfnMemManage_Handler   = (void*) MemManage_Handler,
+#endif
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+#if COMPONENT_VERSION >= 10001
+        .pfnSVCall_Handler      = (void*) SVC_Handler,
+        .pfnDebugMonitor_Handler    = (void*) DebugMon_Handler,
+#else
+        .pfnSVC_Handler         = (void*) SVC_Handler,
+        .pfnDebugMon_Handler    = (void*) DebugMon_Handler,
+#endif
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+#if COMPONENT_VERSION >= 10001
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+#else
+        .pfnTAL_0_Handler       = (void*) TAL_0_Handler,          /* 42 TAL_BRK */
+        .pfnTAL_1_Handler       = (void*) TAL_1_Handler,          /* 43 TAL_IPS_0, TAL_IPS_1 */
+#endif
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+        uint32_t *pSrc, *pDest;
+
+        /* Initialize the relocate segment */
+        pSrc = &_etext;
+        pDest = &_srelocate;
+
+        if (pSrc != pDest) {
+                for (; pDest < &_erelocate;) {
+                        *pDest++ = *pSrc++;
+                }
+        }
+
+        /* Clear the zero segment */
+        for (pDest = &_szero; pDest < &_ezero;) {
+                *pDest++ = 0;
+        }
+
+        /* Set the vector table base address */
+        pSrc = (uint32_t *) & _sfixed;
+        SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+#if __FPU_USED
+        /* Enable FPU */
+        SCB->CPACR |=  (0xFu << 20);
+        __DSB();
+        __ISB();
+#endif
+
+        /* Initialize the C library */
+        //__libc_init_array();
+
+        /* Branch to main function */
+        main();
+
+        /* Infinite loop */
+        while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/uf2-samdx1/src/uart_driver.c b/uf2-samdx1/src/uart_driver.c
new file mode 100644
index 00000000..f04dd58d
--- /dev/null
+++ b/uf2-samdx1/src/uart_driver.c
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "board_config.h"
+#include "uart_driver.h"
+
+bool uart_drv_error_flag = false;
+
+uint32_t uart_get_sercom_index(Sercom *sercom_instance) {
+    /* Save all available SERCOM instances for compare. */
+    Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+
+    /* Find index for sercom instance. */
+    for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+        if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
+            return i;
+        }
+    }
+
+    return 0;
+}
+
+void uart_basic_init(Sercom *sercom, uint16_t baud_val, enum uart_pad_settings pad_conf) {
+    /* Wait for synchronization */
+    while (sercom->USART.SYNCBUSY.bit.ENABLE)
+        ;
+    /* Disable the SERCOM UART module */
+    sercom->USART.CTRLA.bit.ENABLE = 0;
+    /* Wait for synchronization */
+    while (sercom->USART.SYNCBUSY.bit.SWRST)
+        ;
+    /* Perform a software reset */
+    sercom->USART.CTRLA.bit.SWRST = 1;
+    /* Wait for synchronization */
+    while (sercom->USART.CTRLA.bit.SWRST)
+        ;
+    /* Wait for synchronization */
+    while (sercom->USART.SYNCBUSY.bit.SWRST || sercom->USART.SYNCBUSY.bit.ENABLE)
+        ;
+    /* Update the UART pad settings, mode and data order settings */
+    sercom->USART.CTRLA.reg = pad_conf | SERCOM_USART_CTRLA_MODE(1) | SERCOM_USART_CTRLA_DORD;
+    /* Wait for synchronization */
+    while (sercom->USART.SYNCBUSY.bit.CTRLB)
+        ;
+    /* Enable transmit and receive and set data size to 8 bits */
+    sercom->USART.CTRLB.reg =
+        SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_CHSIZE(0);
+    /* Load the baud value */
+    sercom->USART.BAUD.reg = baud_val;
+    /* Wait for synchronization */
+    while (sercom->USART.SYNCBUSY.bit.ENABLE)
+        ;
+    /* Enable SERCOM UART */
+    sercom->USART.CTRLA.bit.ENABLE = 1;
+}
+
+void uart_disable(Sercom *sercom) {
+    /* Wait for synchronization */
+    while (sercom->USART.SYNCBUSY.bit.ENABLE)
+        ;
+    /* Disable SERCOM UART */
+    sercom->USART.CTRLA.bit.ENABLE = 0;
+}
+
+void uart_write_byte(Sercom *sercom, uint8_t data) {
+    /* Wait for Data Register Empty flag */
+    while (!sercom->USART.INTFLAG.bit.DRE)
+        ;
+    /* Write the data to DATA register */
+    sercom->USART.DATA.reg = (uint16_t)data;
+}
+
+uint8_t uart_read_byte(Sercom *sercom) {
+    /* Wait for Receive Complete flag */
+    while (!sercom->USART.INTFLAG.bit.RXC)
+        ;
+    /* Check for errors */
+    if (sercom->USART.STATUS.bit.PERR || sercom->USART.STATUS.bit.FERR ||
+        sercom->USART.STATUS.bit.BUFOVF)
+        /* Set the error flag */
+        uart_drv_error_flag = true;
+    /* Return the read data */
+    return ((uint8_t)sercom->USART.DATA.reg);
+}
+
+void uart_write_buffer_polled(Sercom *sercom, uint8_t *ptr, uint16_t length) {
+    /* Do the following for specified length */
+    do {
+        /* Wait for Data Register Empty flag */
+        while (!sercom->USART.INTFLAG.bit.DRE)
+            ;
+        /* Send data from the buffer */
+        sercom->USART.DATA.reg = (uint16_t)*ptr++;
+    } while (length--);
+}
+
+void uart_read_buffer_polled(Sercom *sercom, uint8_t *ptr, uint16_t length) {
+    /* Do the following for specified length */
+    do {
+        /* Wait for Receive Complete flag */
+        while (!sercom->USART.INTFLAG.bit.RXC)
+            ;
+        /* Check for errors */
+        if (sercom->USART.STATUS.bit.PERR || sercom->USART.STATUS.bit.FERR ||
+            sercom->USART.STATUS.bit.BUFOVF)
+            /* Set the error flag */
+            uart_drv_error_flag = true;
+        /* Store the read data to the buffer */
+        *ptr++ = (uint8_t)sercom->USART.DATA.reg;
+    } while (length--);
+}
\ No newline at end of file
diff --git a/uf2-samdx1/src/usart_sam_ba.c b/uf2-samdx1/src/usart_sam_ba.c
new file mode 100644
index 00000000..098c3c86
--- /dev/null
+++ b/uf2-samdx1/src/usart_sam_ba.c
@@ -0,0 +1,505 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "uf2.h"
+#include "uart_driver.h"
+
+/* Variable to let the main task select the appropriate communication interface
+ */
+volatile uint8_t b_sharp_received;
+
+/* RX and TX Buffers + rw pointers for each buffer */
+volatile uint8_t buffer_rx_usart[USART_BUFFER_SIZE];
+
+volatile uint8_t idx_rx_read;
+volatile uint8_t idx_rx_write;
+
+volatile uint8_t buffer_tx_usart[USART_BUFFER_SIZE];
+
+volatile uint8_t idx_tx_read;
+volatile uint8_t idx_tx_write;
+
+/* Test for timeout in AT91F_GetChar */
+uint8_t error_timeout;
+uint16_t size_of_data;
+uint8_t mode_of_transfer;
+
+#define BOOT_USART_PAD(n) BOOT_USART_PAD##n
+
+/**
+ * \brief Open the given USART
+ */
+void usart_open() {
+    uint32_t port;
+    uint8_t pin;
+
+    /* Configure the port pins for SERCOM_USART */
+    if (BOOT_USART_PAD0 != PINMUX_UNUSED) {
+        /* Mask 6th bit in pin number to check whether it is greater than 32
+         * i.e., PORTB pin */
+        port = (BOOT_USART_PAD0 & 0x200000) >> 21;
+        pin = BOOT_USART_PAD0 >> 16;
+        PORT->Group[port].PINCFG[(pin - (port * 32))].bit.PMUXEN = 1;
+        PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg &= ~(0xF << (4 * (pin & 0x01u)));
+        PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg |= (BOOT_USART_PAD0 & 0xFF)
+                                                               << (4 * (pin & 0x01u));
+    }
+    if (BOOT_USART_PAD1 != PINMUX_UNUSED) {
+        /* Mask 6th bit in pin number to check whether it is greater than 32
+         * i.e., PORTB pin */
+        port = (BOOT_USART_PAD1 & 0x200000) >> 21;
+        pin = BOOT_USART_PAD1 >> 16;
+        PORT->Group[port].PINCFG[(pin - (port * 32))].bit.PMUXEN = 1;
+        PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg &= ~(0xF << (4 * (pin & 0x01u)));
+        PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg |= (BOOT_USART_PAD1 & 0xFF)
+                                                               << (4 * (pin & 0x01u));
+    }
+    if (BOOT_USART_PAD2 != PINMUX_UNUSED) {
+        /* Mask 6th bit in pin number to check whether it is greater than 32
+         * i.e., PORTB pin */
+        port = (BOOT_USART_PAD2 & 0x200000) >> 21;
+        pin = BOOT_USART_PAD2 >> 16;
+        PORT->Group[port].PINCFG[(pin - (port * 32))].bit.PMUXEN = 1;
+        PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg &= ~(0xF << (4 * (pin & 0x01u)));
+        PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg |= (BOOT_USART_PAD2 & 0xFF)
+                                                               << (4 * (pin & 0x01u));
+    }
+    if (BOOT_USART_PAD3 != PINMUX_UNUSED) {
+        /* Mask 6th bit in pin number to check whether it is greater than 32
+         * i.e., PORTB pin */
+        port = (BOOT_USART_PAD3 & 0x200000) >> 21;
+        pin = BOOT_USART_PAD3 >> 16;
+        PORT->Group[port].PINCFG[(pin - (port * 32))].bit.PMUXEN = 1;
+        PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg &= ~(0xF << (4 * (pin & 0x01u)));
+        PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg |= (BOOT_USART_PAD3 & 0xFF)
+                                                               << (4 * (pin & 0x01u));
+    }
+
+    #ifdef SAMD21
+    uint32_t inst = uart_get_sercom_index(BOOT_USART_MODULE);
+    /* Enable clock for BOOT_USART_MODULE */
+    PM->APBCMASK.reg |= (1u << (inst + PM_APBCMASK_SERCOM0_Pos));
+
+    /* Set GCLK_GEN0 as source for GCLK_ID_SERCOMx_CORE */
+    GCLK_CLKCTRL_Type clkctrl = {0};
+    uint16_t temp;
+    GCLK->CLKCTRL.bit.ID = inst + GCLK_ID_SERCOM0_CORE;
+    temp = GCLK->CLKCTRL.reg;
+    clkctrl.bit.CLKEN = true;
+    clkctrl.bit.WRTLOCK = false;
+    clkctrl.bit.GEN = GCLK_CLKCTRL_GEN_GCLK0_Val;
+    GCLK->CLKCTRL.reg = (clkctrl.reg | temp);
+    /* Baud rate 115200 - clock 48MHz -> BAUD value-63018 */
+    uart_basic_init(BOOT_USART_MODULE, 63018, BOOT_USART_PAD_SETTINGS);
+    #endif
+
+    #ifdef SAMD51
+    GCLK->PCHCTRL[BOOT_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+    GCLK->PCHCTRL[BOOT_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+    MCLK->BOOT_USART_MASK.reg |= BOOT_USART_BUS_CLOCK_INDEX ;
+    /* Baud rate 115200 - clock 48MHz -> BAUD value-63018 */
+    uart_basic_init(BOOT_USART_MODULE, 63018, BOOT_USART_PAD_SETTINGS);
+    #endif
+
+
+
+    // Initialize flag
+    b_sharp_received = false;
+    idx_rx_read = 0;
+    idx_rx_write = 0;
+    idx_tx_read = 0;
+    idx_tx_write = 0;
+
+    error_timeout = 0;
+}
+
+/**
+ * \brief Configures communication line
+ *
+ */
+void usart_close(void) { uart_disable(BOOT_USART_MODULE); }
+
+/**
+ * \brief Puts a byte on usart line
+ * The type int is used to support printf redirection from compiler LIB.
+ *
+ * \param value      Value to put
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+int usart_putc(int value) {
+    uart_write_byte(BOOT_USART_MODULE, (uint8_t)value);
+    return 1;
+}
+
+int usart_getc(void) {
+    uint16_t retval;
+    retval = (uint16_t)uart_read_byte(BOOT_USART_MODULE);
+    // usart_read_wait(&usart_sam_ba, &retval);
+    return (int)retval;
+}
+
+int usart_sharp_received(void) {
+    if (usart_is_rx_ready()) {
+        if (usart_getc() == SHARP_CHARACTER)
+            return (true);
+    }
+    return (false);
+}
+
+bool usart_is_rx_ready(void) {
+    return (BOOT_USART_MODULE->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC);
+}
+
+int usart_readc(void) {
+    int retval;
+    retval = buffer_rx_usart[idx_rx_read];
+    idx_rx_read = (idx_rx_read + 1) & (USART_BUFFER_SIZE - 1);
+    return (retval);
+}
+
+// Send given data (polling)
+uint32_t usart_putdata(void const *data, uint32_t length) {
+    uint32_t i;
+    uint8_t *ptrdata;
+    ptrdata = (uint8_t *)data;
+    for (i = 0; i < length; i++) {
+        usart_putc(*ptrdata);
+        ptrdata++;
+    }
+    return (i);
+}
+
+// Get data from comm. device
+uint32_t usart_getdata(void *data, uint32_t length) {
+    uint8_t *ptrdata;
+    ptrdata = (uint8_t *)data;
+    *ptrdata = usart_getc();
+    return (1);
+}
+
+static uint16_t crcCache[256];
+
+//*----------------------------------------------------------------------------
+//* \fn    add_crc
+//* \brief Compute the CRC
+//*----------------------------------------------------------------------------
+uint16_t add_crc(uint8_t ch, unsigned short crc0) {
+    if (!crcCache[1]) {
+        for (int ptr = 0; ptr < 256; ptr++) {
+            uint16_t crc = (int)ptr << 8;
+            for (uint16_t cmpt = 0; cmpt < 8; cmpt++) {
+                if (crc & 0x8000)
+                    crc = crc << 1 ^ CRC16POLY;
+                else
+                    crc = crc << 1;
+            }
+            crcCache[ptr] = crc;
+        }
+    }
+
+    return ((crc0 << 8) ^ crcCache[((crc0 >> 8) ^ ch) & 0xff]) & 0xffff;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    getbytes
+//* \brief
+//*----------------------------------------------------------------------------
+static uint16_t getbytes(uint8_t *ptr_data, uint16_t length) {
+    uint16_t crc = 0;
+    uint16_t cpt;
+    uint8_t c;
+
+    for (cpt = 0; cpt < length; ++cpt) {
+        c = usart_getc();
+        if (error_timeout)
+            return 1;
+        crc = add_crc(c, crc);
+        // crc = (crc << 8) ^ xcrc16tab[(crc>>8) ^ c];
+        if (size_of_data || mode_of_transfer) {
+            *ptr_data++ = c;
+            if (length == PKTLEN_128)
+                size_of_data--;
+        }
+    }
+
+    return crc;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    putPacket
+//* \brief Used by Xup to send packets.
+//*----------------------------------------------------------------------------
+static int putPacket(uint8_t *tmppkt, uint8_t sno) {
+    uint32_t i;
+    uint16_t chksm;
+    uint8_t data;
+
+    chksm = 0;
+
+    usart_putc(SOH);
+
+    usart_putc(sno);
+    usart_putc((uint8_t) ~(sno));
+
+    for (i = 0; i < PKTLEN_128; i++) {
+        if (size_of_data || mode_of_transfer) {
+            data = *tmppkt++;
+            size_of_data--;
+        } else
+            data = 0x00;
+
+        usart_putc(data);
+
+        // chksm = (chksm<<8) ^ xcrc16tab[(chksm>>8)^data];
+        chksm = add_crc(data, chksm);
+    }
+
+    /* An "endian independent way to extract the CRC bytes. */
+    usart_putc((uint8_t)(chksm >> 8));
+    usart_putc((uint8_t)chksm);
+
+    return (usart_getc()); /* Wait for ack */
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    getPacket
+//* \brief Used by Xdown to retrieve packets.
+//*----------------------------------------------------------------------------
+uint8_t getPacket(uint8_t *ptr_data, uint8_t sno) {
+    uint8_t seq[2];
+    uint16_t crc, xcrc;
+
+    getbytes(seq, 2);
+    xcrc = getbytes(ptr_data, PKTLEN_128);
+    if (error_timeout)
+        return (false);
+
+    /* An "endian independent way to combine the CRC bytes. */
+    crc = (uint16_t)usart_getc() << 8;
+    crc += (uint16_t)usart_getc();
+
+    if (error_timeout == 1)
+        return (false);
+
+    if ((crc != xcrc) || (seq[0] != sno) || (seq[1] != (uint8_t)(~sno))) {
+        usart_putc(CAN);
+        return (false);
+    }
+
+    usart_putc(ACK);
+    return (true);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    Xup
+//* \brief Called when a transfer from target to host is being made (considered
+//*        an upload).
+//*----------------------------------------------------------------------------
+// static void Xup(char *ptr_data, uint16_t length)
+// Send given data (polling) using xmodem (if necessary)
+uint32_t usart_putdata_xmd(void const *data, uint32_t length) {
+    uint8_t c, sno = 1;
+    uint8_t done;
+    uint8_t *ptr_data = (uint8_t *)data;
+    error_timeout = 0;
+    if (!length)
+        mode_of_transfer = 1;
+    else {
+        size_of_data = length;
+        mode_of_transfer = 0;
+    }
+
+    if (length & (PKTLEN_128 - 1)) {
+        length += PKTLEN_128;
+        length &= ~(PKTLEN_128 - 1);
+    }
+
+    /* Startup synchronization... */
+    /* Wait to receive a NAK or 'C' from receiver. */
+    done = 0;
+    while (!done) {
+        c = (uint8_t)usart_getc();
+        if (error_timeout) { // Test for timeout in usart_getc
+            error_timeout = 0;
+            c = (uint8_t)usart_getc();
+            if (error_timeout) {
+                error_timeout = 0;
+                return (0);
+            }
+        }
+        switch (c) {
+        case NAK:
+            done = 1;
+            // ("CSM");
+            break;
+        case 'C':
+            done = 1;
+            // ("CRC");
+            break;
+        case 'q': /* ELS addition, not part of XMODEM spec. */
+            return (0);
+        default:
+            break;
+        }
+    }
+
+    done = 0;
+    sno = 1;
+    while (!done) {
+        c = (uint8_t)putPacket((uint8_t *)ptr_data, sno);
+        if (error_timeout) { // Test for timeout in usart_getc
+            error_timeout = 0;
+            return (0);
+        }
+        switch (c) {
+        case ACK:
+            ++sno;
+            length -= PKTLEN_128;
+            ptr_data += PKTLEN_128;
+            // ("A");
+            break;
+        case NAK:
+            // ("N");
+            break;
+        case CAN:
+        case EOT:
+        default:
+            done = 0;
+            break;
+        }
+        if (!length) {
+            usart_putc(EOT);
+            usart_getc(); /* Flush the ACK */
+            break;
+        }
+        // ("!");
+    }
+
+    mode_of_transfer = 0;
+    // ("Xup_done.");
+    return (1);
+    //    return(0);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    Xdown
+//* \brief Called when a transfer from host to target is being made (considered
+//*        an download).
+//*----------------------------------------------------------------------------
+// static void Xdown(char *ptr_data, uint16_t length)
+// Get data from comm. device using xmodem (if necessary)
+uint32_t usart_getdata_xmd(void *data, uint32_t length) {
+    uint32_t timeout;
+    char c;
+    uint8_t *ptr_data = (uint8_t *)data;
+    uint32_t b_run, nbr_of_timeout = 100;
+    uint8_t sno = 0x01;
+    uint32_t data_transfered = 0;
+    uint16_t crc = 0; 
+
+    for (int i =0; i < 128; i++)
+    {
+	    crc = add_crc(i, crc); // warm up crc function very slow on first run
+    }
+
+
+    // Copied from legacy source code ... might need some tweaking
+    uint32_t loops_per_second =
+        CPU_FREQUENCY / 10; /* system_clock_source_get_hz(BOOT_USART_GCLK_GEN_SOURCE) / 10; */
+
+    error_timeout = 0;
+
+    if (length == 0)
+        mode_of_transfer = 1;
+    else {
+        size_of_data = length;
+        mode_of_transfer = 0;
+    }
+
+    /* Startup synchronization... */
+    /* Continuously send NAK or 'C' until sender responds. */
+    // ("Xdown");
+    while (1) {
+        usart_putc('C');
+        timeout = loops_per_second;
+        while (!(usart_is_rx_ready()) && timeout)
+	{
+            timeout--;
+	    __asm__ volatile(""); //  How to prevent GCC from optimizing out a busy wait loop
+	}
+        if (timeout)
+            break;
+
+        if (!(--nbr_of_timeout))
+            return (0);
+        //            return -1;
+    }
+
+    b_run = true;
+    // ("Got response");
+    while (b_run != false) {
+        c = (char)usart_getc();
+        if (error_timeout) { // Test for timeout in usart_getc
+            error_timeout = 0;
+            return (0);
+            //            return (-1);
+        }
+        switch (c) {
+        case SOH: /* 128-byte incoming packet */
+            // ("O");
+            b_run = getPacket(ptr_data, sno);
+            if (error_timeout) { // Test for timeout in usart_getc
+                error_timeout = 0;
+                return (0);
+                //                return (-1);
+            }
+            if (b_run == true) {
+                ++sno;
+                ptr_data += PKTLEN_128;
+                data_transfered += PKTLEN_128;
+            }
+            break;
+        case EOT: // ("E");
+            usart_putc(ACK);
+            b_run = false;
+            break;
+        case CAN: // ("C");
+        case ESC: /* "X" User-invoked abort */
+        default:
+            b_run = false;
+            break;
+        }
+        // ("!");
+    }
+    mode_of_transfer = 0;
+    return (true);
+    //    return(b_run);
+}
diff --git a/uf2-samdx1/src/utils.c b/uf2-samdx1/src/utils.c
new file mode 100644
index 00000000..f1f3224a
--- /dev/null
+++ b/uf2-samdx1/src/utils.c
@@ -0,0 +1,263 @@
+#include "uf2.h"
+#include "neopixel.h"
+
+static uint32_t timerLow;
+uint32_t timerHigh, resetHorizon;
+
+void __attribute__ ((noinline)) delay(uint32_t ms) {
+    // These multipliers were determined empirically and are only approximate.
+    // After the pulsing LED is enabled (led_tick_on), the multipliers need to change
+    // due to the interrupt overhead of the pulsing.
+    // SAMD21 starts up at 1MHz by default.
+#ifdef SAMD21
+    uint32_t count = ms * (current_cpu_frequency_MHz) * (led_tick_on ? 149: 167);
+#endif
+#ifdef SAMD51
+    // SAMD51 starts up at 48MHz by default, and we set the clock to
+    // 48MHz, so we don't need to adjust for current_cpu_frequency_MHz.
+    uint32_t count = ms * (led_tick_on ? 6353 : 6826);
+#endif
+    for (uint32_t i = 1; i < count; ++i) {
+        asm volatile("");
+    }
+}
+
+// Useful for debugging.
+// PIN_PA19 is D12 on Metro M0, D11 on Metro M4
+#ifdef BLINK_DEBUG
+void blink_n(uint32_t pin, uint32_t n, uint32_t interval) {
+    // Start out off.
+    PINOP(pin, DIRSET);
+    PINOP(pin, OUTCLR);
+    delay(interval);
+    for (int i = 0; i < n; ++i) {
+        PINOP(pin, OUTSET);
+        delay(interval);
+        PINOP(pin, OUTCLR);
+        delay(interval);
+    }
+}
+
+void blink_n_forever(uint32_t pin, uint32_t n, uint32_t interval) {
+    while(1) {
+        blink_n(pin, n, interval);
+        delay(interval*5);
+    }
+}
+#endif
+
+void timerTick(void) {
+    if (timerLow-- == 0) {
+        timerLow = TIMER_STEP;
+        timerHigh++;
+        if (resetHorizon && timerHigh >= resetHorizon) {
+            resetHorizon = 0;
+            resetIntoApp();
+        }
+    }
+}
+
+void panic(int code) {
+    logval("PANIC", code);
+    while (1) {
+    }
+}
+
+int writeNum(char *buf, uint32_t n, bool full) {
+    int i = 0;
+    int sh = 28;
+    while (sh >= 0) {
+        int d = (n >> sh) & 0xf;
+        if (full || d || sh == 0 || i) {
+            buf[i++] = d > 9 ? 'A' + d - 10 : '0' + d;
+        }
+        sh -= 4;
+    }
+    return i;
+}
+
+void resetIntoApp() {
+    // reset without waiting for double tap (only works for one reset)
+    RGBLED_set_color(COLOR_LEAVE);
+    *DBL_TAP_PTR = DBL_TAP_MAGIC_QUICK_BOOT;
+    NVIC_SystemReset();
+}
+
+void resetIntoBootloader() {
+    // reset without waiting for double tap (only works for one reset)
+    *DBL_TAP_PTR = DBL_TAP_MAGIC;
+    NVIC_SystemReset();
+}
+
+#if USE_LOGS
+struct LogStore logStoreUF2;
+
+void logreset() {
+    logStoreUF2.ptr = 0;
+    logmsg("Reset logs.");
+}
+
+void logwritenum(uint32_t n) {
+    char buff[9];
+    buff[writeNum(buff, n, false)] = 0;
+    logwrite("0x");
+    logwrite(buff);
+}
+
+void logwrite(const char *msg) {
+    const int jump = sizeof(logStoreUF2.buffer) / 4;
+    if (logStoreUF2.ptr >= sizeof(logStoreUF2.buffer) - jump) {
+        logStoreUF2.ptr -= jump;
+        memmove(logStoreUF2.buffer, logStoreUF2.buffer + jump, logStoreUF2.ptr);
+    }
+    int l = strlen(msg);
+    if (l + logStoreUF2.ptr >= sizeof(logStoreUF2.buffer)) {
+        logwrite("TOO LONG!\n");
+        return;
+    }
+    memcpy(logStoreUF2.buffer + logStoreUF2.ptr, msg, l);
+    logStoreUF2.ptr += l;
+    logStoreUF2.buffer[logStoreUF2.ptr] = 0;
+}
+
+void logmsg(const char *msg) {
+    logwrite(msg);
+    logwrite("\n");
+}
+
+void logval(const char *lbl, uint32_t v) {
+    logwrite(lbl);
+    logwrite(": ");
+    logwritenum(v);
+    logwrite("\n");
+}
+#endif
+
+static uint32_t now;
+static uint32_t signal_end;
+int8_t led_tick_step = 1;
+volatile bool led_tick_on = false;
+static uint8_t limit = 200;
+
+void led_tick() {
+    led_tick_on = true;
+    now++;
+    if (signal_end) {
+        if (now == signal_end - 1000) {
+            LED_MSC_ON();
+        }
+        if (now == signal_end) {
+            signal_end = 0;
+        }
+    } else {
+        uint8_t curr = now & 0xff;
+        if (curr == 0) {
+            LED_MSC_ON();
+            if (limit < 10 || limit > 250) {
+                led_tick_step = -led_tick_step;
+            }
+            limit += led_tick_step;
+        } else if (curr == limit) {
+            LED_MSC_OFF();
+        }
+    }
+}
+
+void led_signal() {
+    if (signal_end < now) {
+        signal_end = now + 2000;
+        LED_MSC_OFF();
+    }
+}
+
+void led_init() {
+#if defined(LED_PIN)
+    PINOP(LED_PIN, DIRSET);
+#endif
+    LED_MSC_ON();
+
+#if defined(BOARD_RGBLED_CLOCK_PIN)
+    // using APA102, set pins to outputs
+    PINOP(BOARD_RGBLED_CLOCK_PIN, DIRSET);
+    PINOP(BOARD_RGBLED_DATA_PIN, DIRSET);
+
+    // This won't work for neopixel, because we're running at 1MHz or thereabouts...
+    RGBLED_set_color(COLOR_LEAVE);
+#endif
+
+#if USE_SCREEN
+    // turn display backlight
+    screen_early_init();
+#endif
+
+#if defined(LED_TX_PIN)
+    PINOP(LED_TX_PIN, DIRSET);
+    LED_TX_OFF();
+#endif
+
+#if defined(LED_RX_PIN)
+    PINOP(LED_RX_PIN, DIRSET);
+    LED_RX_OFF();
+#endif
+
+#if defined(BOARD_NEOPIXEL_POWERPIN)
+    PINOP(BOARD_NEOPIXEL_POWERPIN, DIRSET);
+    PINOP(BOARD_NEOPIXEL_POWERPIN, OUTSET);
+#endif
+}
+
+#if defined(BOARD_RGBLED_CLOCK_PIN)
+void write_apa_byte(uint8_t x) {
+    for (uint8_t i = 0x80; i != 0; i >>= 1) {
+        if (x & i)
+            PINOP(BOARD_RGBLED_DATA_PIN, OUTSET);
+        else
+            PINOP(BOARD_RGBLED_DATA_PIN, OUTCLR);
+
+        PINOP(BOARD_RGBLED_CLOCK_PIN, OUTSET);
+        // for (uint8_t j=0; j<25; j++) /* 0.1ms */
+        //  __asm__ __volatile__("");
+
+        PINOP(BOARD_RGBLED_CLOCK_PIN, OUTCLR);
+        // for (uint8_t j=0; j<25; j++) /* 0.1ms */
+        //  __asm__ __volatile__("");
+    }
+}
+#endif
+
+void RGBLED_set_color(uint32_t color) {
+#if defined(BOARD_RGBLED_CLOCK_PIN)
+    write_apa_byte(0x0);
+    write_apa_byte(0x0);
+    write_apa_byte(0x0);
+    write_apa_byte(0x0);
+
+    write_apa_byte(0xFF);
+    write_apa_byte(color >> 16);
+    write_apa_byte(color >> 8);
+    write_apa_byte(color);
+
+    write_apa_byte(0xFF);
+    write_apa_byte(0xFF);
+    write_apa_byte(0xFF);
+    write_apa_byte(0xFF);
+
+    // set clock port low for ~10ms
+    delay(50);
+#elif defined(BOARD_NEOPIXEL_PIN)
+    uint8_t buf[BOARD_NEOPIXEL_COUNT * 3];
+#if 0
+    memset(buf, 0, sizeof(buf));
+    buf[0] = color >> 8;
+    buf[1] = color >> 16;
+    buf[2] = color;
+#else
+    for (int i = 0; i < BOARD_NEOPIXEL_COUNT * 3; i += 3) {
+        buf[i + 0] = color >> 8;
+        buf[i + 1] = color >> 16;
+        buf[i + 2] = color;
+    }
+#endif
+    neopixel_send_buffer(buf, BOARD_NEOPIXEL_COUNT * 3);
+#endif
+}

From 9748c6a7e2f557730b9462d7d2082d84bbd7ea39 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sat, 30 May 2026 17:06:36 -0400
Subject: [PATCH 51/59] Fix UF2 conversion and artifact upload for SAMD build

- Switch convert_firmware_to_uf2 post-action from .bin to .elf target:
  SCons does not track .bin as a build node so AddPostAction on it never fired
- Generate .bin via objcopy in the callback if the platform hasn't created it yet
- Add if-no-files-found: warn to SAMD artifact upload so missing files are
  reported rather than silently dropped

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 .github/workflows/build_platformio.yml    |  1 +
 firmware/targets/samd/build_bootloader.py | 15 ++++++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/build_platformio.yml b/.github/workflows/build_platformio.yml
index c00e3b31..36a2ae0d 100644
--- a/.github/workflows/build_platformio.yml
+++ b/.github/workflows/build_platformio.yml
@@ -98,6 +98,7 @@ jobs:
       uses: actions/upload-artifact@v6
       with:
         name: ${{ matrix.env }}
+        if-no-files-found: warn
         path: |
           .pio/build/${{ matrix.env }}/firmware.bin
           .pio/build/${{ matrix.env }}/firmware.uf2
diff --git a/firmware/targets/samd/build_bootloader.py b/firmware/targets/samd/build_bootloader.py
index a76a97a1..9d3562c4 100644
--- a/firmware/targets/samd/build_bootloader.py
+++ b/firmware/targets/samd/build_bootloader.py
@@ -217,6 +217,7 @@ def build_bootloader(source, target, env):
 def convert_firmware_to_uf2(source, target, env):
     build_dir = Path(env.subst("$BUILD_DIR"))
     prog_name = env.subst("$PROGNAME")
+    elf_path = build_dir / f"{prog_name}.elf"
     bin_path = build_dir / f"{prog_name}.bin"
     uf2_path = build_dir / f"{prog_name}.uf2"
 
@@ -227,6 +228,16 @@ def convert_firmware_to_uf2(source, target, env):
         print(f"WARNING: uf2conv.py not found at {uf2conv}, skipping UF2 conversion")
         return
 
+    # The .bin is produced by the platform as a side-effect of the .elf build and
+    # may not exist yet when this post-action fires.  Generate it ourselves if needed.
+    if not bin_path.exists():
+        objcopy = Path(env.subst("$CC")).parent / "arm-none-eabi-objcopy"
+        try:
+            _run([str(objcopy), "-O", "binary", str(elf_path), str(bin_path)])
+        except RuntimeError:
+            print("WARNING: objcopy failed, cannot produce .bin or .uf2")
+            return
+
     print(f"\n--- Converting firmware to UF2 ---")
     try:
         # -b 0x2000 : application base address (after 8 KB SAMD21 bootloader)
@@ -246,4 +257,6 @@ def convert_firmware_to_uf2(source, target, env):
 
 
 env.AddPreAction("$BUILD_DIR/${PROGNAME}.elf", build_bootloader)
-env.AddPostAction("$BUILD_DIR/${PROGNAME}.bin", convert_firmware_to_uf2)
+# Hook into the ELF (a real SCons target), not the .bin (a side-effect artifact
+# that SCons does not track and therefore never triggers AddPostAction).
+env.AddPostAction("$BUILD_DIR/${PROGNAME}.elf", convert_firmware_to_uf2)

From 9c826781d3d7d12e5783106d51007fef7a8389c8 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sat, 30 May 2026 17:36:33 -0400
Subject: [PATCH 52/59] Update OpenEVSE NXT USB VID/PID to Microchip/OpenEVSE
 values

Change VID from 0x1B4F (SparkFun) to 0x04D8 (Microchip)
Change PID from 0x0D22 to 0xE437

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 uf2-samdx1/boards/OpenEVSE_NXT/board_config.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/uf2-samdx1/boards/OpenEVSE_NXT/board_config.h b/uf2-samdx1/boards/OpenEVSE_NXT/board_config.h
index a8f4dbed..18fd5700 100644
--- a/uf2-samdx1/boards/OpenEVSE_NXT/board_config.h
+++ b/uf2-samdx1/boards/OpenEVSE_NXT/board_config.h
@@ -7,8 +7,8 @@
 #define INDEX_URL "https://www.openevse.com"
 #define BOARD_ID "SAMD21G18A-OpenEVSE-NXT"
 
-#define USB_VID 0x1B4F
-#define USB_PID 0x0D22
+#define USB_VID 0x04D8
+#define USB_PID 0xE437
 
 #define LED_PIN PIN_PA17
 

From 3721aadad3a0f6c90fcbeeea4c74e69c0b440056 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sun, 7 Jun 2026 19:20:23 -0400
Subject: [PATCH 53/59] Add relay wear protection: ZC switching, current-zero
 check, frequency measurement
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

- Add RELAY_ZC_SWITCH feature: close relay at voltage ZC (CGMI hardware),
  open relay at voltage ZC (all hardware with valid AC signal)
- Add waitCurrentZero(): block until ammeter drops below 100 mA before
  opening relay; called from chargingOff() non-emergency path (#ifdef AMMETER)
- Add measureAcFreq(): three-path implementation —
    SAMD: ADC sign-change on GMI_LINE (PA09)
    m328p CGMI: midpoint of pinAC2 HIGH off-period pulses
    m328p non-CGMI: alternating rising edges on pinAC1/pinAC2 half-wave
      channels; diode threshold offset cancels in the interval measurement
- GFI trip calls chargingOff(1) — emergency flag bypasses ZC wait and
  waitCurrentZero() for minimum-latency fault response
- Add $FF Z RAPI command to enable/disable ZC relay switching (persisted)
- Add $GZ RAPI command to read measured AC frequency × 100
- Non-CGMI boards: frequency updated on relay open only (AC pins are
  load-side on older non-V6 boards; no valid signal at relay close)
- Enable RELAY_ZC_SWITCH in common platformio.ini build flags

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 firmware/open_evse/J1772EvseController.cpp | 153 ++++++++++++++++++++-
 firmware/open_evse/J1772EvseController.h   |  25 +++-
 firmware/open_evse/open_evse.h             |   8 ++
 firmware/open_evse/rapi_proc.cpp           |  16 ++-
 firmware/open_evse/rapi_proc.h             |  14 +-
 firmware/targets/samd/pindefs.h            |   4 +
 platformio.ini                             |   3 +-
 prepare-release.sh                         |   2 +-
 8 files changed, 215 insertions(+), 10 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 129775c5..b57f014d 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -114,6 +114,136 @@ void J1772EVSEController::readAmmeter()
   WDT_RESET();
 }
 
+#ifdef RELAY_ZC_SWITCH
+// Block until AC current amplitude drops below CURRENT_ZERO_THRESHOLD_MA (0.1 A).
+// Polls readAmmeter() indefinitely. WDT_RESET() called each iteration.
+// Emergency opens (chargingOff(1)) bypass this entirely.
+void J1772EVSEController::waitCurrentZero()
+{
+  do {
+    WDT_RESET();
+    readAmmeter();
+    int32_t ma = (int32_t)m_AmmeterReading * m_CurrentScaleFactor - m_AmmeterCurrentOffset;
+    if (ma < (int32_t)CURRENT_ZERO_THRESHOLD_MA) return;
+  } while (1);
+}
+
+// Measure AC frequency.  Stores the result (×100) in m_AcFreqX100 and sets
+// *zcTimeMsOut to the millis() timestamp of the second detected crossing.
+// Returns the half-period in µs, or 0 (with *zcTimeMsOut = 0) on failure.
+//
+// Detection method depends on hardware:
+//   SAMD:        ADC sign-change on GMI_LINE (adcGmi, PA09).
+//   m328p CGMI:  digital off-period pulses on pinAC2 — HIGH = near voltage ZC.
+//   m328p non-CGMI: each AC channel drives one diode half-wave (pinAC1 and
+//                pinAC2).  Rising edges alternate between channels every
+//                half-period; threshold offset cancels because both diodes
+//                have the same forward drop.
+uint32_t J1772EVSEController::measureAcFreq(unsigned long *zcTimeMsOut)
+{
+  *zcTimeMsOut = 0;
+  uint32_t zcUs[2] = {0, 0};
+  uint8_t count = 0;
+
+#if defined(TARGET_SAMD)
+  // ADC sign-change detection on GMI_LINE
+  uint8_t isFirst = 1;
+  uint16_t lastSample = 0;
+  for (uint32_t start = micros(); (micros() - start) < (ZC_DETECT_TIMEOUT_MS * 3000UL); ) {
+    uint16_t sample = (uint16_t)adcGmi.read();
+    if (!isFirst && ((lastSample > ADC_HALF) != (sample > ADC_HALF))) {
+      uint32_t now_us = micros();
+      // debounce: require at least 4 ms between accepted crossings
+      if (!count || (now_us - zcUs[0]) > 4000UL) {
+        zcUs[count++] = now_us;
+        if (count == 2) break;
+      }
+    }
+    isFirst = 0;
+    lastSample = sample;
+  }
+#else
+  if (hasCGMI()) {
+    // m328p CGMI: digital off-period pulses on pinAC2.
+    // Pin HIGH = AC voltage below detection threshold = near zero crossing.
+    // Use midpoint of each HIGH pulse as the ZC timestamp.
+    uint8_t inHigh = 0;
+    uint32_t risingUs = 0;
+    for (uint32_t start = micros(); (micros() - start) < (ZC_DETECT_TIMEOUT_MS * 3000UL); ) {
+      uint8_t pinState = pinAC2.read();
+      if (!inHigh && pinState) {
+        risingUs = micros();
+        inHigh = 1;
+      } else if (inHigh && !pinState) {
+        zcUs[count++] = risingUs + (micros() - risingUs) / 2;
+        inHigh = 0;
+        if (count == 2) break;
+      }
+    }
+  }
+#if defined(ACLINE1_REG) && defined(ACLINE2_REG)
+  else {
+    // Non-CGMI m328p: pinAC1 and pinAC2 are complementary diode half-wave
+    // channels — each is LOW for a full half-cycle (its non-conducting half).
+    // A rising edge on either channel marks the start of its half-cycle, which
+    // is a proxy for the zero crossing.  Alternating rising edges on opposite
+    // channels are one half-period apart; the diode threshold offset is the
+    // same on both channels so it cancels out in the interval measurement.
+    uint8_t lastAC1 = pinAC1.read(), lastAC2 = pinAC2.read();
+    uint8_t lastEdgePin = 0; // 1 = AC1, 2 = AC2
+    for (uint32_t start = micros(); (micros() - start) < (ZC_DETECT_TIMEOUT_MS * 3000UL); ) {
+      uint8_t ac1 = pinAC1.read(), ac2 = pinAC2.read();
+      uint8_t edgePin = 0;
+      if (!lastAC1 && ac1) edgePin = 1;
+      else if (!lastAC2 && ac2) edgePin = 2;
+      if (edgePin && edgePin != lastEdgePin) {
+        uint32_t now_us = micros();
+        if (!count || (now_us - zcUs[count - 1]) > 4000UL) {
+          zcUs[count++] = now_us;
+          lastEdgePin = edgePin;
+          if (count == 2) break;
+        }
+      }
+      lastAC1 = ac1;
+      lastAC2 = ac2;
+    }
+  }
+#endif // ACLINE1_REG && ACLINE2_REG
+#endif // TARGET_SAMD
+
+  if (count < 2) return 0;
+
+  uint32_t halfPeriodUs = zcUs[1] - zcUs[0];
+  if (halfPeriodUs < 5000UL || halfPeriodUs > 15000UL) return 0;  // 33–100 Hz sanity
+
+  m_AcFreqX100 = (uint16_t)(100000000UL / (2UL * halfPeriodUs));
+  *zcTimeMsOut = millis() - (uint32_t)((micros() - zcUs[1]) / 1000UL);
+  return halfPeriodUs;
+}
+
+// Shared timing core for relay close and open.  Detects a voltage ZC via the
+// GMI line (updating m_AcFreqX100 as a side effect), then delays so the relay
+// coil is energized/de-energized advanceMs before the next predicted ZC.
+// Falls through immediately if no ZC is detected.
+void J1772EVSEController::zcWaitRelay(uint8_t advanceMs)
+{
+  unsigned long zcTimeMs = 0;
+  uint32_t halfPeriodUs = measureAcFreq(&zcTimeMs);
+
+  if (!zcTimeMs) return;
+
+  uint8_t halfPeriodMs = (uint8_t)((halfPeriodUs + 500UL) / 1000UL);
+  uint8_t n = 1;
+  while ((uint16_t)(n * halfPeriodMs) < advanceMs) n++;
+  uint32_t switchAt = zcTimeMs + (uint32_t)n * halfPeriodMs - advanceMs;
+  unsigned long now = millis();
+  if (switchAt > now) delay(switchAt - now);
+}
+
+void J1772EVSEController::zcWaitRelayClose() { zcWaitRelay(RELAY_CLOSE_ADVANCE_MS); }
+void J1772EVSEController::zcWaitRelayOpen()  { zcWaitRelay(RELAY_OPEN_ADVANCE_MS); }
+#endif // RELAY_ZC_SWITCH
+
 #define MA_PTS 32 // # points in moving average MUST BE power of 2
 #define MA_BITS 5 // log2(MA_PTS)
 /*
@@ -163,10 +293,16 @@ J1772EVSEController::J1772EVSEController() :
 #ifdef VOLTMETER_PIN
   , adcVoltMeter(VOLTMETER_PIN)
 #endif
+#if defined(RELAY_ZC_SWITCH) && defined(TARGET_SAMD)
+  , adcGmi(GMI_ADC_PIN)
+#endif
 {
 #ifdef STATE_TRANSITION_REQ_FUNC
   m_StateTransitionReqFunc = NULL;
-#endif // STATE_TRANSITION_REQ_FUNC
+#endif
+#ifdef RELAY_ZC_SWITCH
+  m_AcFreqX100 = 0;
+#endif
 }
 
 void J1772EVSEController::SaveSettings()
@@ -282,6 +418,9 @@ void J1772EVSEController::ShowDisabledTests()
 
 void J1772EVSEController::chargingOn()
 {
+#ifdef RELAY_ZC_SWITCH
+  if (hasCGMI() && RelayZCSwitchEnabled()) zcWaitRelayClose();
+#endif
   // turn on charging current
 #ifdef OEV6
   if (isV6()) {
@@ -329,8 +468,16 @@ void J1772EVSEController::chargingOn()
   m_ChargeOnTimeMS = millis();
 }
 
-void J1772EVSEController::chargingOff()
+void J1772EVSEController::chargingOff(uint8_t emergency)
 {
+#ifdef RELAY_ZC_SWITCH
+  if (!emergency && chargingIsOn() && RelayZCSwitchEnabled()) {
+#ifdef AMMETER
+    waitCurrentZero();
+#endif
+    zcWaitRelayOpen();
+  }
+#endif
  // turn off charging current
 #ifdef OEV6
   if (isV6()) {
@@ -427,7 +574,7 @@ void J1772EVSEController::SetGfiTripped()
 
   // this is repeated in Update(), but we want to keep latency as low as possible
   // for safety so we do it here first anyway
-  chargingOff(); // turn off charging current
+  chargingOff(1); // GFI: emergency open — no zero-crossing wait
   // turn off the PWM
   m_Pilot.SetState(PILOT_STATE_P12);
 
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index f49fd3b7..97a9a7ed 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -89,6 +89,7 @@ typedef uint8_t (*EvseStateTransitionReqFunc)(uint8_t prevPilotState,uint8_t cur
 #define ECF_BOOT_LOCK_DISABLED 0x2000 // boot lock
 #define ECF_OVERCURRENT_DISABLED 0x0400 // disable overcurrent check
 #define ECF_BUTTON_DISABLED    0x8000 // front panel button disabled
+#define ECF_RELAY_ZC_DISABLED  0x0800 // disable zero-crossing relay switching
 #define ECF_DEFAULT            0x0000
 
 // J1772EVSEController volatile m_wVFlags bits - not saved to EEPROM
@@ -149,6 +150,9 @@ class J1772EVSEController {
 #ifdef VOLTMETER_PIN
   AdcPin adcVoltMeter;
 #endif
+#if defined(RELAY_ZC_SWITCH) && defined(TARGET_SAMD)
+  AdcPin adcGmi;  // GMI_LINE (PA09) analog signal for voltage ZC detection
+#endif
 
 #ifdef CHARGING_REG
   DigitalPin pinCharging;
@@ -182,6 +186,9 @@ class J1772EVSEController {
   uint8_t m_relayCloseMs; // #ms for DC pulse to close relay
   uint8_t m_relayHoldPwm; // PWM duty cycle to hold relay closed
 #endif // RELAY_PWM
+#ifdef RELAY_ZC_SWITCH
+  uint16_t m_AcFreqX100; // measured AC frequency × 100 (e.g. 6012 = 60.12 Hz); 0 = not yet measured
+#endif
   uint16_t m_wFlags; // ECF_xxx
   uint16_t m_wVFlags; // ECVF_xxx
   static THRESH_DATA m_ThreshData;
@@ -253,7 +260,14 @@ class J1772EVSEController {
   uint8_t doPost();
 #endif // ADVPWR
   void chargingOn();
-  void chargingOff();
+  void chargingOff(uint8_t emergency = 0);
+#ifdef RELAY_ZC_SWITCH
+  void zcWaitRelay(uint8_t advanceMs);
+  void zcWaitRelayClose();
+  void zcWaitRelayOpen();
+  void waitCurrentZero();
+  uint32_t measureAcFreq(unsigned long *zcTimeMsOut);
+#endif
   uint8_t chargingIsOn() { return vFlagIsSet(ECVF_CHARGING_ON); }
 
 #ifdef TIME_LIMIT
@@ -329,6 +343,15 @@ class J1772EVSEController {
   void ClrHardFault() { clrVFlags(ECVF_HARD_FAULT); }
   int8_t InHardFault() { return vFlagIsSet(ECVF_HARD_FAULT); }
   int8_t hasCGMI() { return flagIsSet(ECF_CGMI); }
+#ifdef RELAY_ZC_SWITCH
+  uint8_t RelayZCSwitchEnabled() { return !flagIsSet(ECF_RELAY_ZC_DISABLED); }
+  void EnableRelayZCSwitch(uint8_t tf) {
+    if (!tf) setFlags(ECF_RELAY_ZC_DISABLED);
+    else clrFlags(ECF_RELAY_ZC_DISABLED);
+    SaveEvseFlags();
+  }
+  uint16_t GetAcFreqX100() { return m_AcFreqX100; }
+#endif // RELAY_ZC_SWITCH
   int8_t BootLockIsEnabled() { return !flagIsSet(ECF_BOOT_LOCK_DISABLED); }
   void EnableBootLock(uint8_t tf) {
     if (!tf) setFlags(ECF_BOOT_LOCK_DISABLED); 
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index 8246c3c5..12c99b34 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -342,6 +342,14 @@ extern AutoCurrentCapacityController g_ACCController;
 // PWM parameters written to/loaded from EEPROM
 #define RELAY_HOLD_DELAY_TUNING // enable Z0
 
+#ifdef RELAY_ZC_SWITCH
+#define RELAY_CLOSE_ADVANCE_MS     20  // ms before voltage ZC to energize relay coil
+#define RELAY_OPEN_ADVANCE_MS       2  // ms before voltage ZC to de-energize relay coil
+#define ZC_DETECT_TIMEOUT_MS       35  // > one full AC cycle (50 Hz = 20 ms)
+#define AC_ZC_HALF_PERIOD_MS        8  // conservative half-period (works 50 & 60 Hz)
+#define CURRENT_ZERO_THRESHOLD_MA 100  // mA; current below this = safe to open relay (0.1 A)
+#endif // RELAY_ZC_SWITCH
+
 // OEV6 w/ CGMI - when power is loss, temporarily triggers NO GROUND fault
 // delay recording of NO GROUND fault to avoid recording this spurious fault
 #ifndef NO_GND_RECORD_DELAY
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index c3f424f2..da62fb29 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -352,6 +352,11 @@ int EvseRapiProcessor::processCmd()
 	  case 'V': // vent required check
 	    g_EvseController.EnableVentReq(u1.u8);
 	    break;
+#ifdef RELAY_ZC_SWITCH
+	  case 'Z': // zero-crossing relay switch
+	    g_EvseController.EnableRelayZCSwitch(u1.u8);
+	    break;
+#endif // RELAY_ZC_SWITCH
 	  default: // unknown
 	    rc = -1;
 	  }
@@ -843,11 +848,18 @@ int EvseRapiProcessor::processCmd()
 #ifdef HEARTBEAT_SUPERVISION
     case 'Y': // HEARTBEAT SUPERVISION
 	  sprintf(buffer,"%d %d %d", g_EvseController.GetHearbeatInterval(), g_EvseController.GetHearbeatCurrent(), g_EvseController.GetHearbeatTrigger());
-      bufCnt = 1; 
+      bufCnt = 1;
 	  rc = 0;
       break;
 #endif //HEARTBEAT_SUPERVISION
-	   
+#ifdef RELAY_ZC_SWITCH
+    case 'Z': // get AC frequency
+      sprintf(buffer,"%u", g_EvseController.GetAcFreqX100());
+      bufCnt = 1;
+      rc = 0;
+      break;
+#endif // RELAY_ZC_SWITCH
+
     }
     break;
 
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index ca512cb2..e8068ad5 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -151,6 +151,7 @@ FF - enable/disable feature
   R = stuck Relay check
   T = temperature monitoring
   V = Vent required check
+  Z = zero-cross detection for relay switching
  $FF D 0 - disable diode check
  $FF G 1 - enable ground check
 
@@ -364,11 +365,20 @@ T0 amps - set fake charging current
  
 GY - Get Hearbeat Supervision Status
  Response includes heartbeatinterval hearbeatcurrentlimit hearbeattrigger
- hearbeattrigger: 0 - There has never been a missed pulse, 
+ hearbeattrigger: 0 - There has never been a missed pulse,
  2 - there is a missed pulse, and HS is still in current limit
- 1 - There was a missed pulse once, but it has since been acknkoledged. Ampacity has been successfully restored to max permitted 
+ 1 - There was a missed pulse once, but it has since been acknkoledged. Ampacity has been successfully restored to max permitted
  See SY above for worked expamples.
 
+GZ - get AC line frequency (requires RELAY_ZC_SWITCH)
+ response: $OK freqx100
+ freqx100(decimal): measured AC frequency * 100, e.g. 6012 = 60.12 Hz
+ 0 = frequency not yet measured (no relay operation has occurred since boot)
+ CGMI hardware: updated on relay close (zcWaitRelayClose) and open (zcWaitRelayOpen)
+ non-CGMI hardware: updated on relay open only (zcWaitRelayOpen); AC pins are
+   load-side on older non-V6 boards so no valid signal is available at relay close
+ $GZ^38
+
 Z0 FOR TESTING RELAY_AUTO_PWM_PIN ONLY
 Z0 closems holdpwm
    closems(dec) = # ms to apply DC to relay pin
diff --git a/firmware/targets/samd/pindefs.h b/firmware/targets/samd/pindefs.h
index ea976592..15bd8e5f 100644
--- a/firmware/targets/samd/pindefs.h
+++ b/firmware/targets/samd/pindefs.h
@@ -27,6 +27,10 @@
 
 
 
+#ifdef RELAY_ZC_SWITCH
+#define GMI_ADC_PIN ZERO_PA09  // GMI_LINE — ADC-capable, for voltage ZC detection
+#endif
+
 // dummies - unused
 #define PILOT_IDX 0
 #define CHARGING_IDX 0
diff --git a/platformio.ini b/platformio.ini
index 29ed8fd1..9f3e7aa0 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -38,4 +38,5 @@ build_flags =
   -D OVERCURRENT_THRESHOLD=5
   -D OVERCURRENT_TIMEOUT=10000UL
   -D PERIODIC_LCD_REFRESH_MS=120000UL
-  -D NO_GROUND_RECORD_DELAY=2000
\ No newline at end of file
+  -D NO_GROUND_RECORD_DELAY=2000
+  -D RELAY_ZC_SWITCH
\ No newline at end of file
diff --git a/prepare-release.sh b/prepare-release.sh
index b778c035..8211b745 100755
--- a/prepare-release.sh
+++ b/prepare-release.sh
@@ -5,7 +5,7 @@
 mkdir -p firmware/targets
 
 pio run -e m328p_noWiFi_RTC_BTN_LCD
-cp .pio/build/m328p_noWiFi_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_noWiFi.hex
+cp .pio/build/m328p_noWiFi_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_noWiFi..hex
 
 pio run -e m328p_TFT_WIFI
 cp .pio/build/m328p_TFT_WIFI/firmware.hex firmware/targets/m328p_openevse.hex

From 9c95cd445379ffb2f3b645681ea62458c39cfe69 Mon Sep 17 00:00:00 2001
From: Chris Howell <chris1howell@msn.com>
Date: Sun, 7 Jun 2026 19:21:55 -0400
Subject: [PATCH 54/59] Fix typo in firmware target file name

---
 prepare-release.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/prepare-release.sh b/prepare-release.sh
index 8211b745..b778c035 100755
--- a/prepare-release.sh
+++ b/prepare-release.sh
@@ -5,7 +5,7 @@
 mkdir -p firmware/targets
 
 pio run -e m328p_noWiFi_RTC_BTN_LCD
-cp .pio/build/m328p_noWiFi_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_noWiFi..hex
+cp .pio/build/m328p_noWiFi_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_noWiFi.hex
 
 pio run -e m328p_TFT_WIFI
 cp .pio/build/m328p_TFT_WIFI/firmware.hex firmware/targets/m328p_openevse.hex

From b4ef511bf8abeda26503963b3bd602d447ecee24 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Sun, 7 Jun 2026 19:26:49 -0400
Subject: [PATCH 55/59] Move RELAY_ZC_SWITCH to per-target platformio.ini

Removes RELAY_ZC_SWITCH from the shared EU common flags in the root
platformio.ini and adds it explicitly to the m328p and samd target
configs, keeping target-specific features out of the common section.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 firmware/targets/m328p/platformio.ini | 1 +
 firmware/targets/samd/platformio.ini  | 1 +
 platformio.ini                        | 1 -
 3 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/firmware/targets/m328p/platformio.ini b/firmware/targets/m328p/platformio.ini
index 55b27e13..33d31b77 100644
--- a/firmware/targets/m328p/platformio.ini
+++ b/firmware/targets/m328p/platformio.ini
@@ -29,6 +29,7 @@ build_src_flags=
   ${m328p.build_src_flags}
   # RGBLCD Minimal code for legacy LCD support, not used for TFT Removing can save 4Kb builds but needed for some shared code
   -D RGBLCD 
+  -D RELAY_ZC_SWITCH
   -D 'VERSION="${common.version}"'
 
 
diff --git a/firmware/targets/samd/platformio.ini b/firmware/targets/samd/platformio.ini
index aa1e7731..82bccce6 100644
--- a/firmware/targets/samd/platformio.ini
+++ b/firmware/targets/samd/platformio.ini
@@ -27,6 +27,7 @@ build_src_filter =
 build_src_flags=
   ${samd.build_src_flags}
   ${common.build_flags}
+  -D RELAY_ZC_SWITCH
   -D 'VERSION="${common.version}.SAMD"'
 
 # SAMD OpenEVSE NXT (Atmel-ICE upload/programming)
diff --git a/platformio.ini b/platformio.ini
index 9f3e7aa0..5f245dd4 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -39,4 +39,3 @@ build_flags =
   -D OVERCURRENT_TIMEOUT=10000UL
   -D PERIODIC_LCD_REFRESH_MS=120000UL
   -D NO_GROUND_RECORD_DELAY=2000
-  -D RELAY_ZC_SWITCH
\ No newline at end of file

From 8b844622f734fd18c0426d83f922dceadd88ca09 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Tue, 9 Jun 2026 15:01:18 -0400
Subject: [PATCH 56/59] Add per-relay enable/disable control via RAPI ($SR/$GR
 commands)

Allows individual DC1, DC2, and AC relay outputs to be enabled or
disabled at runtime via new $SR and $GR RAPI commands. Settings are
persisted to EEPROM (offset 39) and applied on boot.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 firmware/open_evse/J1772EvseController.cpp | 23 +++++++++-------
 firmware/open_evse/J1772EvseController.h   | 16 +++++++++++
 firmware/open_evse/open_evse.h             |  1 +
 firmware/open_evse/rapi_proc.cpp           | 31 +++++++++++++++++++++-
 firmware/open_evse/rapi_proc.h             | 17 ++++++++++--
 5 files changed, 76 insertions(+), 12 deletions(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index b57f014d..583e7a39 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -428,30 +428,30 @@ void J1772EVSEController::chargingOn()
 //    Serial.print("\nrelayCloseMs: ");Serial.println(m_relayCloseMs);
 //    Serial.print("relayHoldPwm: ");Serial.println(m_relayHoldPwm);
     // turn on charging pin to close relay
-    digitalWrite(V6_CHARGING_PIN,HIGH);
-    digitalWrite(V6_CHARGING_PIN2,HIGH);
+    if (RelayDC1Enabled()) digitalWrite(V6_CHARGING_PIN,HIGH);
+    if (RelayDC2Enabled()) digitalWrite(V6_CHARGING_PIN2,HIGH);
     delay(m_relayCloseMs);
     // switch to PWM to hold closed
-    analogWrite(V6_CHARGING_PIN,m_relayHoldPwm);
-    analogWrite(V6_CHARGING_PIN2,m_relayHoldPwm);
+    if (RelayDC1Enabled()) analogWrite(V6_CHARGING_PIN,m_relayHoldPwm);
+    if (RelayDC2Enabled()) analogWrite(V6_CHARGING_PIN2,m_relayHoldPwm);
 #else // !RELAY_PWM
-    digitalWrite(V6_CHARGING_PIN,HIGH);
-    digitalWrite(V6_CHARGING_PIN2,HIGH);
+    if (RelayDC1Enabled()) digitalWrite(V6_CHARGING_PIN,HIGH);
+    if (RelayDC2Enabled()) digitalWrite(V6_CHARGING_PIN2,HIGH);
 #endif // RELAY_PWM
   }
   else {
 #endif // OEV6
 #ifdef CHARGING_REG
-    pinCharging.write(1);
+    if (RelayDC1Enabled()) pinCharging.write(1);
 #endif
 #ifdef CHARGING2_REG
-    pinCharging2.write(1);
+    if (RelayDC2Enabled()) pinCharging2.write(1);
 #endif // CHARGING2_REG
 #ifdef OEV6
   }
 #endif // OEV6
 #ifdef CHARGINGAC_REG
-  pinChargingAC.write(1);
+  if (RelayACEnabled()) pinChargingAC.write(1);
 #endif
 
   setVFlags(ECVF_CHARGING_ON);
@@ -1146,6 +1146,11 @@ void J1772EVSEController::Init()
 //  Serial.print("relayHoldPwm: ");Serial.println(m_relayHoldPwm);
 #endif // RELAY_PWM
 
+  m_relayFlags = eeprom_read_byte((uint8_t*)EOFS_RELAY_FLAGS);
+  if (m_relayFlags == 0xff) { // uninitialized EEPROM
+    m_relayFlags = ERELAYF_DEFAULT;
+  }
+
 
 #ifdef OEV6
   if (isV6()) {
diff --git a/firmware/open_evse/J1772EvseController.h b/firmware/open_evse/J1772EvseController.h
index 97a9a7ed..30e7d822 100644
--- a/firmware/open_evse/J1772EvseController.h
+++ b/firmware/open_evse/J1772EvseController.h
@@ -92,6 +92,12 @@ typedef uint8_t (*EvseStateTransitionReqFunc)(uint8_t prevPilotState,uint8_t cur
 #define ECF_RELAY_ZC_DISABLED  0x0800 // disable zero-crossing relay switching
 #define ECF_DEFAULT            0x0000
 
+// relay enable/disable flags - saved to EEPROM at EOFS_RELAY_FLAGS
+#define ERELAYF_DC1_DISABLED 0x01 // DC relay 1 disabled
+#define ERELAYF_DC2_DISABLED 0x02 // DC relay 2 disabled
+#define ERELAYF_AC_DISABLED  0x04 // AC relay disabled
+#define ERELAYF_DEFAULT      0x00 // all relays enabled
+
 // J1772EVSEController volatile m_wVFlags bits - not saved to EEPROM
 #define ECVF_AUTOSVCLVL_SKIPPED 0x0001 // auto svc level test skipped during post
 #define ECVF_HARD_FAULT         0x0002 // in non-autoresettable fault
@@ -186,6 +192,7 @@ class J1772EVSEController {
   uint8_t m_relayCloseMs; // #ms for DC pulse to close relay
   uint8_t m_relayHoldPwm; // PWM duty cycle to hold relay closed
 #endif // RELAY_PWM
+  uint8_t m_relayFlags; // ERELAYF_xxx - relay enable/disable bitmask
 #ifdef RELAY_ZC_SWITCH
   uint16_t m_AcFreqX100; // measured AC frequency × 100 (e.g. 6012 = 60.12 Hz); 0 = not yet measured
 #endif
@@ -339,6 +346,15 @@ class J1772EVSEController {
   }
 #endif // RELAY_PWM
 
+  uint8_t GetRelayFlags() { return m_relayFlags; }
+  void SetRelayFlags(uint8_t flags) {
+    m_relayFlags = flags;
+    eeprom_write_byte((uint8_t*)EOFS_RELAY_FLAGS, m_relayFlags);
+  }
+  uint8_t RelayDC1Enabled() { return !(m_relayFlags & ERELAYF_DC1_DISABLED); }
+  uint8_t RelayDC2Enabled() { return !(m_relayFlags & ERELAYF_DC2_DISABLED); }
+  uint8_t RelayACEnabled()  { return !(m_relayFlags & ERELAYF_AC_DISABLED); }
+
   void SetHardFault() { setVFlags(ECVF_HARD_FAULT); }
   void ClrHardFault() { clrVFlags(ECVF_HARD_FAULT); }
   int8_t InHardFault() { return vFlagIsSet(ECVF_HARD_FAULT); }
diff --git a/firmware/open_evse/open_evse.h b/firmware/open_evse/open_evse.h
index 12c99b34..307b50f6 100644
--- a/firmware/open_evse/open_evse.h
+++ b/firmware/open_evse/open_evse.h
@@ -519,6 +519,7 @@ extern AutoCurrentCapacityController g_ACCController;
 
 #define EOFS_RELAY_CLOSE_MS 37 // 1 byte
 #define EOFS_RELAY_HOLD_PWM 38 // 1 byte
+#define EOFS_RELAY_FLAGS    39 // 1 byte - relay enable/disable bitmask (ERELAYF_xxx)
 
 #define EOFS_MAX_HW_CURRENT_CAPACITY 511 // 1 byte
 
diff --git a/firmware/open_evse/rapi_proc.cpp b/firmware/open_evse/rapi_proc.cpp
index da62fb29..7e4098bd 100644
--- a/firmware/open_evse/rapi_proc.cpp
+++ b/firmware/open_evse/rapi_proc.cpp
@@ -624,10 +624,30 @@ int EvseRapiProcessor::processCmd()
         rc = 1; //Invalid number of tokens
       }
       sprintf(buffer,"%d %d %d", g_EvseController.GetHearbeatInterval(), g_EvseController.GetHearbeatCurrent(), g_EvseController.GetHearbeatTrigger());
-      bufCnt = 1; 
+      bufCnt = 1;
       break;
 #endif //HEARTBEAT_SUPERVISION
 
+    case 'R': // relay enable/disable  $SR n 0|1
+      if (tokenCnt == 3) {
+        u1.u8 = (uint8_t)dtoi32(tokens[1]); // relay number 1=DC1 2=DC2 3=AC
+        u2.u8 = (*tokens[2] != '0') ? 1 : 0; // 1=enable 0=disable
+        switch (u1.u8) {
+        case 1: u3.u8 = ERELAYF_DC1_DISABLED; break;
+        case 2: u3.u8 = ERELAYF_DC2_DISABLED; break;
+        case 3: u3.u8 = ERELAYF_AC_DISABLED;  break;
+        default: u3.u8 = 0; break;
+        }
+        if (u3.u8) {
+          u4.u8 = g_EvseController.GetRelayFlags();
+          if (u2.u8) u4.u8 &= ~u3.u8;
+          else       u4.u8 |=  u3.u8;
+          g_EvseController.SetRelayFlags(u4.u8);
+          rc = 0;
+        }
+      }
+      break;
+
     }
     break;
 
@@ -860,6 +880,15 @@ int EvseRapiProcessor::processCmd()
       break;
 #endif // RELAY_ZC_SWITCH
 
+    case 'R': // get relay enable status  $GR
+      sprintf(buffer,"%d %d %d",
+        (int)g_EvseController.RelayDC1Enabled(),
+        (int)g_EvseController.RelayDC2Enabled(),
+        (int)g_EvseController.RelayACEnabled());
+      bufCnt = 1;
+      rc = 0;
+      break;
+
     }
     break;
 
diff --git a/firmware/open_evse/rapi_proc.h b/firmware/open_evse/rapi_proc.h
index e8068ad5..3d3a2fd7 100644
--- a/firmware/open_evse/rapi_proc.h
+++ b/firmware/open_evse/rapi_proc.h
@@ -228,14 +228,22 @@ SY heartbeatinterval heartbeatcurrentlimit
  heartbeatinterval - seconds. 0 to disable
  heartbeatcurrentlimit - max current when no heartbeat within heartbeatinterval
  Response includes heartbeatinterval hearbeatcurrentlimit hearbeattrigger
- hearbeattrigger: 0 - There has never been a missed pulse, 
+ hearbeattrigger: 0 - There has never been a missed pulse,
  2 - there is a missed pulse, and HS is still in current limit
- 1 - There was a missed pulse once, but it has since been acknowledged. Ampacity has been successfully restored to max permitted 
+ 1 - There was a missed pulse once, but it has since been acknowledged. Ampacity has been successfully restored to max permitted
  $SY 100 6  //If no pulse for 100 seconds, set EVE ampacity limit to 6A until missed pulse is acknowledged
  $SY        //This is a heartbeat supervision pulse.  Need one every heartbeatinterval seconds.
  $SY 165    //This is an acknowledgement of a missed pulse.  Magic Cookie = 165 (=0XA5)
  When you send a pulse, an NK response indicates that a previous pulse was missed and has not yet been acked
 
+SR n 0|1 - enable/disable relay output (saved to EEPROM, applied at boot)
+ n: 1=DC relay 1, 2=DC relay 2, 3=AC relay
+ 0=disable 1=enable (all relays enabled by default)
+ $SR 1 0 - disable DC relay 1
+ $SR 2 0 - disable DC relay 2
+ $SR 3 0 - disable AC relay
+ $SR 1 1 - re-enable DC relay 1
+
 G0 - get EV connect state
  response: $OK connectstate
  connectstate: 0=not connected, 1=connected, 2=unknown
@@ -303,6 +311,11 @@ GH - get cHarge limit
  kWh = 0 = no charge limit
  $GH^2B
 
+GR - get relay enable status
+ response: $OK dc1 dc2 ac
+ dc1/dc2/ac: 1=enabled 0=disabled
+ $GR
+
 GI - get MCU ID - requires MCU_ID_LEN to be defined
  response: $OK mcuid
  mcuid: MCU serial number

From 1a2e9fda1eb0e25148928ed678f7d47718ac0500 Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Tue, 9 Jun 2026 20:52:24 -0400
Subject: [PATCH 57/59] Fix PP_AUTO_AMPACITY runtime-disabled bug causing 6A
 current clamp
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When PP_AUTO_AMPACITY is compiled in but the ECF_PP_AUTO_AMPACITY EEPROM
flag is not set (default), the ACCController is disabled and ppMaxAmps
is never initialized — it stays 0 from global zero-init.
GetMaxCurrentCapacity() was reading this stale zero via GetPPMaxAmps()
without checking IsEnabled(), causing ampacity to clamp to
MIN_CURRENT_CAPACITY_J1772 (6A) during STATE_B/C.

Any nosave=1 SetCurrentCapacity call (e.g. heartbeat supervision
fallback) would then cap the pilot to 6A instead of the intended value.

Fix: guard the PP cache read with g_ACCController.IsEnabled().

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 firmware/open_evse/J1772EvseController.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/firmware/open_evse/J1772EvseController.cpp b/firmware/open_evse/J1772EvseController.cpp
index 583e7a39..5045b63f 100644
--- a/firmware/open_evse/J1772EvseController.cpp
+++ b/firmware/open_evse/J1772EvseController.cpp
@@ -798,7 +798,8 @@ uint8_t J1772EVSEController::GetMaxCurrentCapacity()
   }
 
 #ifdef PP_AUTO_AMPACITY
-  if ((m_EvseState >= EVSE_STATE_B) && (m_EvseState <= EVSE_STATE_C)) {
+  if (g_ACCController.IsEnabled() &&
+      (m_EvseState >= EVSE_STATE_B) && (m_EvseState <= EVSE_STATE_C)) {
     uint8_t ppamps =  g_ACCController.GetPPMaxAmps();
     if (ppamps < ampacity) {
       ampacity = ppamps;

From 292d1bcc09abac3dbfb7d5c8d638175784b109aa Mon Sep 17 00:00:00 2001
From: chris1howell <chris1howell83@gmail.com>
Date: Tue, 9 Jun 2026 21:08:00 -0400
Subject: [PATCH 58/59] Fix 4-build config errors after rename of
 m328p_TFT_WIFI -> m328p_core

- platformio.ini: m328p_noWiFi extends env:m328p_TFT_WIFI (stale after
  rename); update to extends env:m328p_core
- prepare-release.sh: SAMD copy path was .pio/build/samd_us/ (old name);
  correct to .pio/build/samd/
- build_platformio.yml: m328p_noWiFi matrix entry missing python: 3.x;
  add to match other AVR entries and avoid empty version in setup-python

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
---
 .github/workflows/build_platformio.yml |  9 +++++++--
 firmware/targets/m328p/platformio.ini  | 26 ++++++++++++++++++++------
 prepare-release.sh                     | 13 ++++++++-----
 3 files changed, 35 insertions(+), 13 deletions(-)

diff --git a/.github/workflows/build_platformio.yml b/.github/workflows/build_platformio.yml
index 36a2ae0d..040f232b 100644
--- a/.github/workflows/build_platformio.yml
+++ b/.github/workflows/build_platformio.yml
@@ -12,12 +12,17 @@ jobs:
       fail-fast: false
       matrix:
         include:
-          - env: m328p_TFT_WIFI
+          - env: m328p_core
             python: 3.x
             platformio: 6.1.5
             arch: avr
             artifact: firmware.hex
-          - env: m328p_noWiFi_RTC_BTN_LCD
+          - env: m328p_LCD_WIFI
+            python: 3.x
+            platformio: 6.1.5
+            arch: avr
+            artifact: firmware.hex
+          - env: m328p_noWiFi
             python: 3.x
             platformio: 6.1.5
             arch: avr
diff --git a/firmware/targets/m328p/platformio.ini b/firmware/targets/m328p/platformio.ini
index 33d31b77..1c424c1d 100644
--- a/firmware/targets/m328p/platformio.ini
+++ b/firmware/targets/m328p/platformio.ini
@@ -16,7 +16,22 @@ build_src_filter =
   +<../targets/m328p>
 
  # WiFi with TFT
-[env:m328p_TFT_WIFI]
+[env:m328p_core]
+platform = atmelavr@3.4.0
+board = openevse
+framework = arduino
+upload_protocol = ${m328p.upload_protocol}
+upload_flags = ${m328p.upload_flags}
+lib_deps = ${m328p.lib_deps}
+build_src_filter =
+  ${m328p.build_src_filter}
+build_src_flags=
+  ${m328p.build_src_flags}
+  -D RELAY_ZC_SWITCH
+  -D 'VERSION="${common.version}.core"'
+
+ # WiFi with Text LCD Support
+[env:m328p_LCD_WIFI]
 platform = atmelavr@3.4.0
 board = openevse
 framework = arduino
@@ -30,12 +45,11 @@ build_src_flags=
   # RGBLCD Minimal code for legacy LCD support, not used for TFT Removing can save 4Kb builds but needed for some shared code
   -D RGBLCD 
   -D RELAY_ZC_SWITCH
-  -D 'VERSION="${common.version}"'
-
+  -D 'VERSION="${common.version}.legacy"'
 
- # legacy RTC LCD BTN no WiFi
-[env:m328p_noWiFi_RTC_BTN_LCD]
-extends = env:m328p_TFT_WIFI
+ # legacy no WiFi
+[env:m328p_noWiFi]
+extends = env:m328p_core
 platform = atmelavr@3.4.0
 board = openevse
 framework = arduino
diff --git a/prepare-release.sh b/prepare-release.sh
index b778c035..4e045d66 100755
--- a/prepare-release.sh
+++ b/prepare-release.sh
@@ -4,14 +4,17 @@
 
 mkdir -p firmware/targets
 
-pio run -e m328p_noWiFi_RTC_BTN_LCD
-cp .pio/build/m328p_noWiFi_RTC_BTN_LCD/firmware.hex firmware/targets/m328p_openevse_noWiFi.hex
+pio run -e m328p_core
+cp .pio/build/m328p_core/firmware.hex firmware/targets/openevse_core.hex
 
-pio run -e m328p_TFT_WIFI
-cp .pio/build/m328p_TFT_WIFI/firmware.hex firmware/targets/m328p_openevse.hex
+pio run -e m328p_noWiFi
+cp .pio/build/m328p_noWiFi/firmware.hex firmware/targets/openevse_noWiFi.hex
+
+pio run -e m328p_LCD_WIFI
+cp .pio/build/m328p_LCD_WIFI/firmware.hex firmware/targets/openevse_legacy.hex
 
 pio run -e samd
-cp .pio/build/samd_us/firmware.bin firmware/targets/arm_samd_openevse_nxt.bin
+cp .pio/build/samd/firmware.bin firmware/targets/arm_samd_openevse_nxt.bin
 
 ls firmware/targets/
 

From afba7cd06b7a63962547979ea7a7f8c2a3988620 Mon Sep 17 00:00:00 2001
From: Chris Howell <chris1howell@msn.com>
Date: Sat, 20 Jun 2026 11:26:40 -0400
Subject: [PATCH 59/59] Fix version format in platformio.ini

---
 platformio.ini | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/platformio.ini b/platformio.ini
index 5f245dd4..b52fc3b0 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -16,7 +16,7 @@ extra_configs =
 
 [common]
 lib_deps =
-version = D9.0.0
+version = 9.0.0
 build_src_filter =
    +<*.cpp>
 build_flags =